./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 03:16:32,412 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 03:16:32,479 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 03:16:32,483 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 03:16:32,484 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 03:16:32,508 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 03:16:32,509 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 03:16:32,509 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 03:16:32,510 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 03:16:32,510 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 03:16:32,511 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 03:16:32,512 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 03:16:32,512 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 03:16:32,513 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 03:16:32,513 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 03:16:32,514 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 03:16:32,514 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 03:16:32,515 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 03:16:32,515 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 03:16:32,516 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 03:16:32,516 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 03:16:32,517 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 03:16:32,517 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 03:16:32,518 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 03:16:32,518 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 03:16:32,519 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 03:16:32,519 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 03:16:32,520 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 03:16:32,520 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 03:16:32,521 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 03:16:32,521 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 03:16:32,521 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 03:16:32,522 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 03:16:32,522 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 03:16:32,522 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 03:16:32,523 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 03:16:32,523 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 03:16:32,523 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 03:16:32,524 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2023-11-29 03:16:32,760 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 03:16:32,782 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 03:16:32,785 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 03:16:32,786 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 03:16:32,787 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 03:16:32,788 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/transmitter.11.cil.c [2023-11-29 03:16:35,659 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 03:16:35,855 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 03:16:35,856 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/sv-benchmarks/c/systemc/transmitter.11.cil.c [2023-11-29 03:16:35,872 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/data/387eae526/04d60eb7e49f475191d52a6ff2c79aa0/FLAG26958df5a [2023-11-29 03:16:35,886 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/data/387eae526/04d60eb7e49f475191d52a6ff2c79aa0 [2023-11-29 03:16:35,888 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 03:16:35,890 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 03:16:35,891 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 03:16:35,892 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 03:16:35,896 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 03:16:35,897 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 03:16:35" (1/1) ... [2023-11-29 03:16:35,897 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@b3338ec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:35, skipping insertion in model container [2023-11-29 03:16:35,898 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 03:16:35" (1/1) ... [2023-11-29 03:16:35,956 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 03:16:36,215 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 03:16:36,229 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 03:16:36,290 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 03:16:36,312 INFO L206 MainTranslator]: Completed translation [2023-11-29 03:16:36,312 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36 WrapperNode [2023-11-29 03:16:36,312 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 03:16:36,314 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 03:16:36,314 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 03:16:36,314 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 03:16:36,322 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,336 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,425 INFO L138 Inliner]: procedures = 50, calls = 64, calls flagged for inlining = 59, calls inlined = 225, statements flattened = 3461 [2023-11-29 03:16:36,425 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 03:16:36,426 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 03:16:36,426 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 03:16:36,426 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 03:16:36,438 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,438 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,448 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,487 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 03:16:36,488 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,488 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,528 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,564 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,571 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,583 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,618 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 03:16:36,619 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 03:16:36,620 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 03:16:36,620 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 03:16:36,621 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (1/1) ... [2023-11-29 03:16:36,626 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:16:36,637 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:16:36,649 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:16:36,660 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 03:16:36,686 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 03:16:36,686 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 03:16:36,686 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 03:16:36,687 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 03:16:36,808 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 03:16:36,810 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 03:16:38,520 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 03:16:38,557 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 03:16:38,557 INFO L309 CfgBuilder]: Removed 15 assume(true) statements. [2023-11-29 03:16:38,559 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 03:16:38 BoogieIcfgContainer [2023-11-29 03:16:38,560 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 03:16:38,561 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 03:16:38,561 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 03:16:38,564 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 03:16:38,565 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 03:16:38,566 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 03:16:35" (1/3) ... [2023-11-29 03:16:38,567 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3809f9ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 03:16:38, skipping insertion in model container [2023-11-29 03:16:38,567 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 03:16:38,567 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:16:36" (2/3) ... [2023-11-29 03:16:38,567 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3809f9ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 03:16:38, skipping insertion in model container [2023-11-29 03:16:38,567 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 03:16:38,567 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 03:16:38" (3/3) ... [2023-11-29 03:16:38,569 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2023-11-29 03:16:38,646 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 03:16:38,646 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 03:16:38,646 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 03:16:38,646 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 03:16:38,647 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 03:16:38,647 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 03:16:38,647 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 03:16:38,647 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 03:16:38,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:38,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1343 [2023-11-29 03:16:38,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:38,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:38,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:38,733 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:38,733 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 03:16:38,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:38,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1343 [2023-11-29 03:16:38,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:38,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:38,761 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:38,761 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:38,772 INFO L748 eck$LassoCheckResult]: Stem: 227#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1380#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1124#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1376#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 510#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 528#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 424#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 355#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 197#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1480#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 39#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 657#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 621#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 665#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1359#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 255#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1175#L1090true assume !(0 == ~M_E~0); 280#L1090-2true assume !(0 == ~T1_E~0); 1333#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 801#L1100-1true assume !(0 == ~T3_E~0); 828#L1105-1true assume !(0 == ~T4_E~0); 151#L1110-1true assume !(0 == ~T5_E~0); 375#L1115-1true assume !(0 == ~T6_E~0); 601#L1120-1true assume !(0 == ~T7_E~0); 1368#L1125-1true assume !(0 == ~T8_E~0); 1360#L1130-1true assume !(0 == ~T9_E~0); 826#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 258#L1140-1true assume !(0 == ~T11_E~0); 757#L1145-1true assume !(0 == ~E_1~0); 796#L1150-1true assume !(0 == ~E_2~0); 364#L1155-1true assume !(0 == ~E_3~0); 1344#L1160-1true assume !(0 == ~E_4~0); 429#L1165-1true assume !(0 == ~E_5~0); 1097#L1170-1true assume !(0 == ~E_6~0); 1285#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 481#L1180-1true assume !(0 == ~E_8~0); 914#L1185-1true assume !(0 == ~E_9~0); 256#L1190-1true assume !(0 == ~E_10~0); 491#L1195-1true assume !(0 == ~E_11~0); 1041#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371#L525true assume !(1 == ~m_pc~0); 60#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1035#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 925#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 894#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 248#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 532#L544true assume 1 == ~t1_pc~0; 410#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 754#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 578#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1030#L563true assume !(1 == ~t2_pc~0); 744#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 69#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 362#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 643#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 755#L582true assume 1 == ~t3_pc~0; 136#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1246#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1108#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 103#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1404#L601true assume !(1 == ~t4_pc~0); 847#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 376#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 765#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1411#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1218#L620true assume 1 == ~t5_pc~0; 83#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 662#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 932#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1479#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1274#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1372#L639true assume !(1 == ~t6_pc~0); 599#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 315#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 347#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1269#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 379#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 961#L658true assume 1 == ~t7_pc~0; 600#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1293#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1396#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 704#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 251#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 383#L677true assume 1 == ~t8_pc~0; 883#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 849#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 292#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 884#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 996#L696true assume !(1 == ~t9_pc~0); 588#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 672#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 416#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 605#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 805#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1152#L715true assume 1 == ~t10_pc~0; 814#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 690#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 520#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 781#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 477#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 141#L734true assume !(1 == ~t11_pc~0); 430#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 483#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 711#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 663#L1438-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1214#L1213true assume !(1 == ~M_E~0); 475#L1213-2true assume !(1 == ~T1_E~0); 981#L1218-1true assume !(1 == ~T2_E~0); 29#L1223-1true assume !(1 == ~T3_E~0); 459#L1228-1true assume !(1 == ~T4_E~0); 1275#L1233-1true assume !(1 == ~T5_E~0); 1460#L1238-1true assume !(1 == ~T6_E~0); 764#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1418#L1248-1true assume !(1 == ~T8_E~0); 811#L1253-1true assume !(1 == ~T9_E~0); 1112#L1258-1true assume !(1 == ~T10_E~0); 789#L1263-1true assume !(1 == ~T11_E~0); 1160#L1268-1true assume !(1 == ~E_1~0); 617#L1273-1true assume !(1 == ~E_2~0); 1256#L1278-1true assume !(1 == ~E_3~0); 314#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1306#L1288-1true assume !(1 == ~E_5~0); 939#L1293-1true assume !(1 == ~E_6~0); 890#L1298-1true assume !(1 == ~E_7~0); 647#L1303-1true assume !(1 == ~E_8~0); 321#L1308-1true assume !(1 == ~E_9~0); 260#L1313-1true assume !(1 == ~E_10~0); 1385#L1318-1true assume !(1 == ~E_11~0); 265#L1323-1true assume { :end_inline_reset_delta_events } true; 1165#L1644-2true [2023-11-29 03:16:38,776 INFO L750 eck$LassoCheckResult]: Loop: 1165#L1644-2true assume !false; 702#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 208#L1065-1true assume !true; 857#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 543#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 966#L1090-3true assume !(0 == ~M_E~0); 1054#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1388#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 999#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1267#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 193#L1110-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1102#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 356#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 762#L1125-3true assume !(0 == ~T8_E~0); 1140#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1305#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 308#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 43#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 497#L1150-3true assume 0 == ~E_2~0;~E_2~0 := 1; 104#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1440#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 299#L1165-3true assume !(0 == ~E_5~0); 1494#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 573#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 250#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 117#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1308#L1190-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1117#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1492#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446#L525-36true assume 1 == ~m_pc~0; 1121#L526-12true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 168#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1127#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 329#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 572#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282#L544-36true assume !(1 == ~t1_pc~0); 936#L544-38true is_transmit1_triggered_~__retres1~1#1 := 0; 679#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1125#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1286#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1093#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 927#L563-36true assume !(1 == ~t2_pc~0); 974#L563-38true is_transmit2_triggered_~__retres1~2#1 := 0; 41#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 904#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1284#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 457#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1387#L582-36true assume 1 == ~t3_pc~0; 350#L583-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 509#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 411#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 670#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 482#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 443#L601-36true assume 1 == ~t4_pc~0; 368#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1475#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1064#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1208#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 911#L620-36true assume !(1 == ~t5_pc~0); 1472#L620-38true is_transmit5_triggered_~__retres1~5#1 := 0; 747#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1075#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 382#L1390-36true assume !(0 != activate_threads_~tmp___4~0#1); 174#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65#L639-36true assume !(1 == ~t6_pc~0); 1429#L639-38true is_transmit6_triggered_~__retres1~6#1 := 0; 85#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 387#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 203#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 603#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1207#L658-36true assume 1 == ~t7_pc~0; 123#L659-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1032#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1038#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61#L1406-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 733#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 950#L677-36true assume 1 == ~t8_pc~0; 1110#L678-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 644#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 645#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1205#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 558#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1114#L696-36true assume !(1 == ~t9_pc~0); 1330#L696-38true is_transmit9_triggered_~__retres1~9#1 := 0; 846#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 436#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1033#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 574#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1281#L715-36true assume !(1 == ~t10_pc~0); 545#L715-38true is_transmit10_triggered_~__retres1~10#1 := 0; 13#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 320#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1079#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 200#L734-36true assume !(1 == ~t11_pc~0); 49#L734-38true is_transmit11_triggered_~__retres1~11#1 := 0; 209#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1331#is_transmit11_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 625#L1438-38true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1119#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 361#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 730#L1218-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 225#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 770#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 332#L1233-3true assume !(1 == ~T5_E~0); 1295#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 507#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1063#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1423#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1070#L1258-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 216#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1015#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1040#L1273-3true assume !(1 == ~E_2~0); 1473#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1043#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 428#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1316#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 328#L1298-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1167#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 699#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 326#L1313-3true assume !(1 == ~E_10~0); 1066#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 217#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1450#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 439#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 316#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1451#L1663true assume !(0 == start_simulation_~tmp~3#1); 1355#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 602#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 526#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 76#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 254#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 560#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1194#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1165#L1644-2true [2023-11-29 03:16:38,784 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:38,785 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2023-11-29 03:16:38,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:38,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965512476] [2023-11-29 03:16:38,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:38,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:38,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:39,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:39,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:39,123 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965512476] [2023-11-29 03:16:39,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965512476] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:39,124 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:39,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:39,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088724196] [2023-11-29 03:16:39,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:39,131 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:39,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:39,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1163004199, now seen corresponding path program 1 times [2023-11-29 03:16:39,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:39,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166121198] [2023-11-29 03:16:39,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:39,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:39,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:39,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:39,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:39,209 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166121198] [2023-11-29 03:16:39,209 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166121198] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:39,209 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:39,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:39,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870284154] [2023-11-29 03:16:39,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:39,212 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:39,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:39,243 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-29 03:16:39,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-29 03:16:39,249 INFO L87 Difference]: Start difference. First operand has 1496 states, 1495 states have (on average 1.5010033444816053) internal successors, (2244), 1495 states have internal predecessors, (2244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:39,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:39,303 INFO L93 Difference]: Finished difference Result 1494 states and 2211 transitions. [2023-11-29 03:16:39,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1494 states and 2211 transitions. [2023-11-29 03:16:39,318 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:39,335 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1494 states to 1488 states and 2205 transitions. [2023-11-29 03:16:39,337 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:39,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:39,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2205 transitions. [2023-11-29 03:16:39,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:39,347 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-29 03:16:39,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2205 transitions. [2023-11-29 03:16:39,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:39,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4818548387096775) internal successors, (2205), 1487 states have internal predecessors, (2205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:39,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2205 transitions. [2023-11-29 03:16:39,432 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-29 03:16:39,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-29 03:16:39,437 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2205 transitions. [2023-11-29 03:16:39,437 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 03:16:39,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2205 transitions. [2023-11-29 03:16:39,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:39,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:39,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:39,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:39,452 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:39,452 INFO L748 eck$LassoCheckResult]: Stem: 3441#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3891#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3892#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3763#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3656#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3385#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3033#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3034#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3078#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3079#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4023#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4024#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4066#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3482#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3483#L1090 assume !(0 == ~M_E~0); 3528#L1090-2 assume !(0 == ~T1_E~0); 3529#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4214#L1100-1 assume !(0 == ~T3_E~0); 4215#L1105-1 assume !(0 == ~T4_E~0); 3306#L1110-1 assume !(0 == ~T5_E~0); 3307#L1115-1 assume !(0 == ~T6_E~0); 3692#L1120-1 assume !(0 == ~T7_E~0); 4000#L1125-1 assume !(0 == ~T8_E~0); 4472#L1130-1 assume !(0 == ~T9_E~0); 4235#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3487#L1140-1 assume !(0 == ~T11_E~0); 3488#L1145-1 assume !(0 == ~E_1~0); 4169#L1150-1 assume !(0 == ~E_2~0); 3669#L1155-1 assume !(0 == ~E_3~0); 3670#L1160-1 assume !(0 == ~E_4~0); 3768#L1165-1 assume !(0 == ~E_5~0); 3769#L1170-1 assume !(0 == ~E_6~0); 4407#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3849#L1180-1 assume !(0 == ~E_8~0); 3850#L1185-1 assume !(0 == ~E_9~0); 3484#L1190-1 assume !(0 == ~E_10~0); 3485#L1195-1 assume !(0 == ~E_11~0); 3865#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3689#L525 assume !(1 == ~m_pc~0); 3123#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3124#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4309#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4284#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3474#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3475#L544 assume 1 == ~t1_pc~0; 3744#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3691#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3103#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3329#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3969#L563 assume !(1 == ~t2_pc~0); 4155#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3142#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3143#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3556#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3557#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4047#L582 assume 1 == ~t3_pc~0; 3275#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3276#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3025#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3026#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3211#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3212#L601 assume !(1 == ~t4_pc~0); 4181#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3693#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3226#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4176#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4448#L620 assume 1 == ~t5_pc~0; 3174#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3175#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4063#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4315#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4457#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4458#L639 assume !(1 == ~t6_pc~0); 3998#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3593#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3642#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3699#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3700#L658 assume 1 == ~t7_pc~0; 3999#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3916#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4463#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4116#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3477#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3478#L677 assume 1 == ~t8_pc~0; 3707#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3288#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3289#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3549#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3550#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4276#L696 assume !(1 == ~t9_pc~0); 3983#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3984#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3754#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3755#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4005#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4218#L715 assume 1 == ~t10_pc~0; 4225#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4097#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3903#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3904#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3843#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3282#L734 assume !(1 == ~t11_pc~0); 3283#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3770#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3854#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3023#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3024#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4064#L1213 assume !(1 == ~M_E~0); 3841#L1213-2 assume !(1 == ~T1_E~0); 3842#L1218-1 assume !(1 == ~T2_E~0); 3056#L1223-1 assume !(1 == ~T3_E~0); 3057#L1228-1 assume !(1 == ~T4_E~0); 3816#L1233-1 assume !(1 == ~T5_E~0); 4459#L1238-1 assume !(1 == ~T6_E~0); 4174#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4175#L1248-1 assume !(1 == ~T8_E~0); 4221#L1253-1 assume !(1 == ~T9_E~0); 4222#L1258-1 assume !(1 == ~T10_E~0); 4197#L1263-1 assume !(1 == ~T11_E~0); 4198#L1268-1 assume !(1 == ~E_1~0); 4018#L1273-1 assume !(1 == ~E_2~0); 4019#L1278-1 assume !(1 == ~E_3~0); 3589#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3590#L1288-1 assume !(1 == ~E_5~0); 4320#L1293-1 assume !(1 == ~E_6~0); 4280#L1298-1 assume !(1 == ~E_7~0); 4051#L1303-1 assume !(1 == ~E_8~0); 3599#L1308-1 assume !(1 == ~E_9~0); 3491#L1313-1 assume !(1 == ~E_10~0); 3492#L1318-1 assume !(1 == ~E_11~0); 3502#L1323-1 assume { :end_inline_reset_delta_events } true; 3503#L1644-2 [2023-11-29 03:16:39,454 INFO L750 eck$LassoCheckResult]: Loop: 3503#L1644-2 assume !false; 4113#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3407#L1065-1 assume !false; 3408#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4455#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3138#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3715#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3604#L906 assume !(0 != eval_~tmp~0#1); 3606#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3926#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3927#L1090-3 assume !(0 == ~M_E~0); 4335#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4392#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4357#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4358#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3380#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3381#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3657#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3658#L1125-3 assume !(0 == ~T8_E~0); 4173#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4430#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3581#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3090#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3091#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3214#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3215#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3562#L1165-3 assume !(0 == ~E_5~0); 3563#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3962#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3476#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3240#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3241#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4418#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4419#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3797#L525-36 assume !(1 == ~m_pc~0); 3798#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3338#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3339#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3614#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3525#L544-36 assume 1 == ~t1_pc~0; 3526#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4085#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4086#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4423#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4405#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4310#L563-36 assume !(1 == ~t2_pc~0); 3328#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3086#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3087#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3813#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3814#L582-36 assume !(1 == ~t3_pc~0); 3648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3745#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3746#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3851#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3791#L601-36 assume 1 == ~t4_pc~0; 3677#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3678#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3943#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3944#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4396#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4297#L620-36 assume 1 == ~t5_pc~0; 3728#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3729#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4158#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3704#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 3347#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3134#L639-36 assume !(1 == ~t6_pc~0); 3136#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3172#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3173#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3397#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3398#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4003#L658-36 assume !(1 == ~t7_pc~0); 3147#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3148#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4382#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3125#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3126#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4147#L677-36 assume 1 == ~t8_pc~0; 4324#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3919#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4048#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4049#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3945#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3946#L696-36 assume 1 == ~t9_pc~0; 3837#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3838#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3779#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3780#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3963#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3964#L715-36 assume !(1 == ~t10_pc~0); 3925#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3021#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3022#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2999#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3000#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3390#L734-36 assume !(1 == ~t11_pc~0); 3100#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 3101#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3406#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3015#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3016#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4027#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3663#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3664#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3438#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3439#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3618#L1233-3 assume !(1 == ~T5_E~0); 3619#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3888#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3889#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4395#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4397#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3420#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3421#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L1273-3 assume !(1 == ~E_2~0); 4385#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4387#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3766#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3767#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3612#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3613#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4109#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3609#L1313-3 assume !(1 == ~E_10~0); 3610#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3422#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3423#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3365#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3591#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3592#L1663 assume !(0 == start_simulation_~tmp~3#1); 3263#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4001#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3209#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3092#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3093#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3158#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3481#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3947#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3503#L1644-2 [2023-11-29 03:16:39,455 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:39,455 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2023-11-29 03:16:39,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:39,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369718987] [2023-11-29 03:16:39,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:39,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:39,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:39,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:39,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:39,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369718987] [2023-11-29 03:16:39,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369718987] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:39,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:39,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:39,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491378138] [2023-11-29 03:16:39,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:39,548 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:39,548 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:39,549 INFO L85 PathProgramCache]: Analyzing trace with hash -825746646, now seen corresponding path program 1 times [2023-11-29 03:16:39,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:39,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688525122] [2023-11-29 03:16:39,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:39,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:39,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:39,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:39,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:39,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688525122] [2023-11-29 03:16:39,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688525122] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:39,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:39,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:39,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607245847] [2023-11-29 03:16:39,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:39,656 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:39,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:39,657 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:39,657 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:39,657 INFO L87 Difference]: Start difference. First operand 1488 states and 2205 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:39,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:39,729 INFO L93 Difference]: Finished difference Result 1488 states and 2204 transitions. [2023-11-29 03:16:39,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2204 transitions. [2023-11-29 03:16:39,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:39,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2204 transitions. [2023-11-29 03:16:39,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:39,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:39,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2204 transitions. [2023-11-29 03:16:39,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:39,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-29 03:16:39,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2204 transitions. [2023-11-29 03:16:39,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:39,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4811827956989247) internal successors, (2204), 1487 states have internal predecessors, (2204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:39,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2204 transitions. [2023-11-29 03:16:39,805 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-29 03:16:39,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:39,806 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2204 transitions. [2023-11-29 03:16:39,807 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 03:16:39,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2204 transitions. [2023-11-29 03:16:39,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:39,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:39,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:39,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:39,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:39,822 INFO L748 eck$LassoCheckResult]: Stem: 6424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 6425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7406#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7407#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6874#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6875#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6746#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6639#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6368#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6016#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6017#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6061#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6062#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7004#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7005#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7049#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6465#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6466#L1090 assume !(0 == ~M_E~0); 6508#L1090-2 assume !(0 == ~T1_E~0); 6509#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7196#L1100-1 assume !(0 == ~T3_E~0); 7197#L1105-1 assume !(0 == ~T4_E~0); 6288#L1110-1 assume !(0 == ~T5_E~0); 6289#L1115-1 assume !(0 == ~T6_E~0); 6675#L1120-1 assume !(0 == ~T7_E~0); 6983#L1125-1 assume !(0 == ~T8_E~0); 7455#L1130-1 assume !(0 == ~T9_E~0); 7218#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6470#L1140-1 assume !(0 == ~T11_E~0); 6471#L1145-1 assume !(0 == ~E_1~0); 7152#L1150-1 assume !(0 == ~E_2~0); 6652#L1155-1 assume !(0 == ~E_3~0); 6653#L1160-1 assume !(0 == ~E_4~0); 6751#L1165-1 assume !(0 == ~E_5~0); 6752#L1170-1 assume !(0 == ~E_6~0); 7390#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6832#L1180-1 assume !(0 == ~E_8~0); 6833#L1185-1 assume !(0 == ~E_9~0); 6467#L1190-1 assume !(0 == ~E_10~0); 6468#L1195-1 assume !(0 == ~E_11~0); 6848#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6667#L525 assume !(1 == ~m_pc~0); 6106#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6107#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7292#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7265#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6457#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6458#L544 assume 1 == ~t1_pc~0; 6727#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6674#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6081#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6312#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6952#L563 assume !(1 == ~t2_pc~0); 7138#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6125#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6126#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6536#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6537#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7030#L582 assume 1 == ~t3_pc~0; 6256#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6257#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6009#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6194#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6195#L601 assume !(1 == ~t4_pc~0); 7164#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6676#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6205#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7159#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7431#L620 assume 1 == ~t5_pc~0; 6153#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6154#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7046#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7297#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7440#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7441#L639 assume !(1 == ~t6_pc~0); 6981#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6574#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6575#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6625#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6682#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6683#L658 assume 1 == ~t7_pc~0; 6982#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6898#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7446#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7098#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6460#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6461#L677 assume 1 == ~t8_pc~0; 6688#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6271#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6272#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6532#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6533#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7259#L696 assume !(1 == ~t9_pc~0); 6964#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6965#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6737#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6738#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6988#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7201#L715 assume 1 == ~t10_pc~0; 7208#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7080#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6886#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6887#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6826#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6265#L734 assume !(1 == ~t11_pc~0); 6266#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6753#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6835#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6004#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 6005#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7047#L1213 assume !(1 == ~M_E~0); 6823#L1213-2 assume !(1 == ~T1_E~0); 6824#L1218-1 assume !(1 == ~T2_E~0); 6039#L1223-1 assume !(1 == ~T3_E~0); 6040#L1228-1 assume !(1 == ~T4_E~0); 6799#L1233-1 assume !(1 == ~T5_E~0); 7442#L1238-1 assume !(1 == ~T6_E~0); 7157#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7158#L1248-1 assume !(1 == ~T8_E~0); 7204#L1253-1 assume !(1 == ~T9_E~0); 7205#L1258-1 assume !(1 == ~T10_E~0); 7180#L1263-1 assume !(1 == ~T11_E~0); 7181#L1268-1 assume !(1 == ~E_1~0); 7001#L1273-1 assume !(1 == ~E_2~0); 7002#L1278-1 assume !(1 == ~E_3~0); 6572#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6573#L1288-1 assume !(1 == ~E_5~0); 7303#L1293-1 assume !(1 == ~E_6~0); 7263#L1298-1 assume !(1 == ~E_7~0); 7034#L1303-1 assume !(1 == ~E_8~0); 6582#L1308-1 assume !(1 == ~E_9~0); 6474#L1313-1 assume !(1 == ~E_10~0); 6475#L1318-1 assume !(1 == ~E_11~0); 6482#L1323-1 assume { :end_inline_reset_delta_events } true; 6483#L1644-2 [2023-11-29 03:16:39,822 INFO L750 eck$LassoCheckResult]: Loop: 6483#L1644-2 assume !false; 7096#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6389#L1065-1 assume !false; 6390#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7438#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6121#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6698#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6587#L906 assume !(0 != eval_~tmp~0#1); 6589#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6909#L1090-3 assume !(0 == ~M_E~0); 7318#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7375#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7340#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7341#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6363#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6364#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6640#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6641#L1125-3 assume !(0 == ~T8_E~0); 7156#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7413#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6562#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6071#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6072#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6196#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6197#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6545#L1165-3 assume !(0 == ~E_5~0); 6546#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6945#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6459#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6220#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6221#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7401#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7402#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6780#L525-36 assume !(1 == ~m_pc~0); 6781#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6321#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6322#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6597#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6598#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6511#L544-36 assume 1 == ~t1_pc~0; 6512#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7068#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7069#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7408#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7388#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7293#L563-36 assume 1 == ~t2_pc~0; 6310#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6069#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6070#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7274#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6796#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6797#L582-36 assume 1 == ~t3_pc~0; 6629#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6630#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6728#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6729#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6834#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6774#L601-36 assume 1 == ~t4_pc~0; 6660#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6661#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6926#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6927#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7379#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7280#L620-36 assume 1 == ~t5_pc~0; 6713#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6714#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7141#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6687#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 6330#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6117#L639-36 assume 1 == ~t6_pc~0; 6118#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6158#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6159#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6380#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6381#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6986#L658-36 assume !(1 == ~t7_pc~0); 6130#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6131#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7365#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6108#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6109#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7130#L677-36 assume !(1 == ~t8_pc~0); 6901#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6902#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7031#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7032#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6928#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6929#L696-36 assume 1 == ~t9_pc~0; 6820#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6821#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6762#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6763#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6946#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6947#L715-36 assume 1 == ~t10_pc~0; 7091#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6006#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6007#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5982#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5983#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6373#L734-36 assume !(1 == ~t11_pc~0); 6085#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 6086#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6391#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5998#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5999#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7010#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6648#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6649#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6421#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6422#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6601#L1233-3 assume !(1 == ~T5_E~0); 6602#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6871#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6872#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7378#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7380#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6404#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6405#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7353#L1273-3 assume !(1 == ~E_2~0); 7368#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7370#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6749#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6750#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6595#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6596#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7092#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6592#L1313-3 assume !(1 == ~E_10~0); 6593#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6406#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6407#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6348#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6576#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6577#L1663 assume !(0 == start_simulation_~tmp~3#1); 6246#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6984#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6192#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6078#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6079#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6141#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6464#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6930#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6483#L1644-2 [2023-11-29 03:16:39,823 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:39,824 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2023-11-29 03:16:39,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:39,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871492351] [2023-11-29 03:16:39,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:39,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:39,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:39,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:39,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:39,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1871492351] [2023-11-29 03:16:39,895 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1871492351] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:39,895 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:39,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:39,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111054668] [2023-11-29 03:16:39,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:39,896 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:39,897 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:39,897 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 1 times [2023-11-29 03:16:39,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:39,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369935341] [2023-11-29 03:16:39,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:39,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:39,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:39,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:39,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:39,988 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369935341] [2023-11-29 03:16:39,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369935341] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:39,989 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:39,989 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:39,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623403649] [2023-11-29 03:16:39,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:39,990 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:39,990 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:39,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:39,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:39,991 INFO L87 Difference]: Start difference. First operand 1488 states and 2204 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:40,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:40,026 INFO L93 Difference]: Finished difference Result 1488 states and 2203 transitions. [2023-11-29 03:16:40,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2203 transitions. [2023-11-29 03:16:40,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:40,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2203 transitions. [2023-11-29 03:16:40,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:40,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:40,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2203 transitions. [2023-11-29 03:16:40,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:40,053 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-29 03:16:40,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2203 transitions. [2023-11-29 03:16:40,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:40,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.480510752688172) internal successors, (2203), 1487 states have internal predecessors, (2203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:40,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2203 transitions. [2023-11-29 03:16:40,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-29 03:16:40,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:40,089 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2203 transitions. [2023-11-29 03:16:40,089 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 03:16:40,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2203 transitions. [2023-11-29 03:16:40,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:40,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:40,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:40,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:40,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:40,102 INFO L748 eck$LassoCheckResult]: Stem: 9407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 9408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9857#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9858#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9729#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9622#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9351#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8999#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9000#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9044#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9045#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9987#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9988#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10032#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9448#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9449#L1090 assume !(0 == ~M_E~0); 9491#L1090-2 assume !(0 == ~T1_E~0); 9492#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10180#L1100-1 assume !(0 == ~T3_E~0); 10181#L1105-1 assume !(0 == ~T4_E~0); 9272#L1110-1 assume !(0 == ~T5_E~0); 9273#L1115-1 assume !(0 == ~T6_E~0); 9658#L1120-1 assume !(0 == ~T7_E~0); 9966#L1125-1 assume !(0 == ~T8_E~0); 10438#L1130-1 assume !(0 == ~T9_E~0); 10201#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9453#L1140-1 assume !(0 == ~T11_E~0); 9454#L1145-1 assume !(0 == ~E_1~0); 10135#L1150-1 assume !(0 == ~E_2~0); 9635#L1155-1 assume !(0 == ~E_3~0); 9636#L1160-1 assume !(0 == ~E_4~0); 9734#L1165-1 assume !(0 == ~E_5~0); 9735#L1170-1 assume !(0 == ~E_6~0); 10373#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9815#L1180-1 assume !(0 == ~E_8~0); 9816#L1185-1 assume !(0 == ~E_9~0); 9450#L1190-1 assume !(0 == ~E_10~0); 9451#L1195-1 assume !(0 == ~E_11~0); 9831#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9655#L525 assume !(1 == ~m_pc~0); 9089#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9090#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10275#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10250#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9440#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9441#L544 assume 1 == ~t1_pc~0; 9710#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9657#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9069#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9295#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9935#L563 assume !(1 == ~t2_pc~0); 10121#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9108#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9109#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9519#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9520#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10013#L582 assume 1 == ~t3_pc~0; 9241#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9242#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8991#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8992#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9177#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9178#L601 assume !(1 == ~t4_pc~0); 10147#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9659#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9191#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9192#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10142#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10414#L620 assume 1 == ~t5_pc~0; 9140#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9141#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10281#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10423#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10424#L639 assume !(1 == ~t6_pc~0); 9964#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9559#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9560#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9608#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9665#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9666#L658 assume 1 == ~t7_pc~0; 9965#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9882#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10429#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10082#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9443#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9444#L677 assume 1 == ~t8_pc~0; 9673#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9254#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9255#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9515#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9516#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10242#L696 assume !(1 == ~t9_pc~0); 9949#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9950#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9720#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9721#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9971#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10184#L715 assume 1 == ~t10_pc~0; 10191#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10063#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9869#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9870#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9809#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9248#L734 assume !(1 == ~t11_pc~0); 9249#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9736#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9818#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8989#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8990#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10030#L1213 assume !(1 == ~M_E~0); 9807#L1213-2 assume !(1 == ~T1_E~0); 9808#L1218-1 assume !(1 == ~T2_E~0); 9022#L1223-1 assume !(1 == ~T3_E~0); 9023#L1228-1 assume !(1 == ~T4_E~0); 9782#L1233-1 assume !(1 == ~T5_E~0); 10425#L1238-1 assume !(1 == ~T6_E~0); 10140#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10141#L1248-1 assume !(1 == ~T8_E~0); 10187#L1253-1 assume !(1 == ~T9_E~0); 10188#L1258-1 assume !(1 == ~T10_E~0); 10163#L1263-1 assume !(1 == ~T11_E~0); 10164#L1268-1 assume !(1 == ~E_1~0); 9984#L1273-1 assume !(1 == ~E_2~0); 9985#L1278-1 assume !(1 == ~E_3~0); 9555#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9556#L1288-1 assume !(1 == ~E_5~0); 10286#L1293-1 assume !(1 == ~E_6~0); 10246#L1298-1 assume !(1 == ~E_7~0); 10017#L1303-1 assume !(1 == ~E_8~0); 9565#L1308-1 assume !(1 == ~E_9~0); 9457#L1313-1 assume !(1 == ~E_10~0); 9458#L1318-1 assume !(1 == ~E_11~0); 9468#L1323-1 assume { :end_inline_reset_delta_events } true; 9469#L1644-2 [2023-11-29 03:16:40,102 INFO L750 eck$LassoCheckResult]: Loop: 9469#L1644-2 assume !false; 10079#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9373#L1065-1 assume !false; 9374#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10421#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9104#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9681#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9570#L906 assume !(0 != eval_~tmp~0#1); 9572#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9892#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9893#L1090-3 assume !(0 == ~M_E~0); 10301#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10358#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10323#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10324#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9346#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9347#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9623#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9624#L1125-3 assume !(0 == ~T8_E~0); 10139#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10396#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9547#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9056#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9057#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9180#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9181#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9528#L1165-3 assume !(0 == ~E_5~0); 9529#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9928#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9442#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9204#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9205#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10384#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10385#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9763#L525-36 assume !(1 == ~m_pc~0); 9764#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9309#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9310#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9580#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9581#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9494#L544-36 assume 1 == ~t1_pc~0; 9495#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10051#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10052#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10391#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10372#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10276#L563-36 assume 1 == ~t2_pc~0; 9293#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9049#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9050#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10257#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9779#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9780#L582-36 assume 1 == ~t3_pc~0; 9612#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9613#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9711#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9712#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9817#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9754#L601-36 assume 1 == ~t4_pc~0; 9643#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9644#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9909#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9910#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10362#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10263#L620-36 assume !(1 == ~t5_pc~0); 9696#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9695#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10124#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9670#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 9313#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9100#L639-36 assume 1 == ~t6_pc~0; 9101#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9138#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9139#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9363#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9364#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9969#L658-36 assume !(1 == ~t7_pc~0); 9113#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 9114#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10348#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9091#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9092#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10113#L677-36 assume 1 == ~t8_pc~0; 10290#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9885#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10014#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10015#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9911#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9912#L696-36 assume 1 == ~t9_pc~0; 9803#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9804#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9745#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9746#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9929#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9930#L715-36 assume !(1 == ~t10_pc~0); 9891#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8987#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8988#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8965#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8966#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9356#L734-36 assume !(1 == ~t11_pc~0); 9066#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 9067#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9372#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8981#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8982#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9993#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9629#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9630#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9404#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9405#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9584#L1233-3 assume !(1 == ~T5_E~0); 9585#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9854#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9855#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10361#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10363#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9386#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9387#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10336#L1273-3 assume !(1 == ~E_2~0); 10351#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10353#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9732#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9733#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9578#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9579#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10075#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9575#L1313-3 assume !(1 == ~E_10~0); 9576#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9388#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9389#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9331#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9557#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9558#L1663 assume !(0 == start_simulation_~tmp~3#1); 9224#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9967#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9175#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9058#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 9059#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9124#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9447#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9913#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9469#L1644-2 [2023-11-29 03:16:40,103 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:40,103 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2023-11-29 03:16:40,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:40,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069463749] [2023-11-29 03:16:40,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:40,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:40,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:40,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:40,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:40,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069463749] [2023-11-29 03:16:40,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2069463749] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:40,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:40,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:40,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289372246] [2023-11-29 03:16:40,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:40,159 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:40,160 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:40,160 INFO L85 PathProgramCache]: Analyzing trace with hash -1935633556, now seen corresponding path program 1 times [2023-11-29 03:16:40,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:40,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290903774] [2023-11-29 03:16:40,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:40,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:40,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:40,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:40,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:40,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290903774] [2023-11-29 03:16:40,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290903774] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:40,261 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:40,261 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:40,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555271000] [2023-11-29 03:16:40,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:40,262 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:40,262 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:40,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:40,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:40,263 INFO L87 Difference]: Start difference. First operand 1488 states and 2203 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:40,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:40,298 INFO L93 Difference]: Finished difference Result 1488 states and 2202 transitions. [2023-11-29 03:16:40,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2202 transitions. [2023-11-29 03:16:40,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:40,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2202 transitions. [2023-11-29 03:16:40,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:40,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:40,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2202 transitions. [2023-11-29 03:16:40,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:40,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-29 03:16:40,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2202 transitions. [2023-11-29 03:16:40,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:40,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4798387096774193) internal successors, (2202), 1487 states have internal predecessors, (2202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:40,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2202 transitions. [2023-11-29 03:16:40,362 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-29 03:16:40,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:40,364 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2202 transitions. [2023-11-29 03:16:40,364 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 03:16:40,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2202 transitions. [2023-11-29 03:16:40,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:40,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:40,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:40,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:40,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:40,376 INFO L748 eck$LassoCheckResult]: Stem: 12390#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12391#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13372#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13373#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12840#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12841#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12712#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12605#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12334#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11982#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11983#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12027#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12028#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12970#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12971#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13015#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12431#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12432#L1090 assume !(0 == ~M_E~0); 12474#L1090-2 assume !(0 == ~T1_E~0); 12475#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13162#L1100-1 assume !(0 == ~T3_E~0); 13163#L1105-1 assume !(0 == ~T4_E~0); 12254#L1110-1 assume !(0 == ~T5_E~0); 12255#L1115-1 assume !(0 == ~T6_E~0); 12641#L1120-1 assume !(0 == ~T7_E~0); 12949#L1125-1 assume !(0 == ~T8_E~0); 13421#L1130-1 assume !(0 == ~T9_E~0); 13184#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12436#L1140-1 assume !(0 == ~T11_E~0); 12437#L1145-1 assume !(0 == ~E_1~0); 13118#L1150-1 assume !(0 == ~E_2~0); 12618#L1155-1 assume !(0 == ~E_3~0); 12619#L1160-1 assume !(0 == ~E_4~0); 12717#L1165-1 assume !(0 == ~E_5~0); 12718#L1170-1 assume !(0 == ~E_6~0); 13356#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12798#L1180-1 assume !(0 == ~E_8~0); 12799#L1185-1 assume !(0 == ~E_9~0); 12433#L1190-1 assume !(0 == ~E_10~0); 12434#L1195-1 assume !(0 == ~E_11~0); 12814#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12633#L525 assume !(1 == ~m_pc~0); 12072#L525-2 is_master_triggered_~__retres1~0#1 := 0; 12073#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13258#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13231#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12423#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12424#L544 assume 1 == ~t1_pc~0; 12693#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12640#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12046#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12047#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12278#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12918#L563 assume !(1 == ~t2_pc~0); 13104#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12091#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12092#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12502#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12503#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12996#L582 assume 1 == ~t3_pc~0; 12222#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12223#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11974#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11975#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12160#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12161#L601 assume !(1 == ~t4_pc~0); 13130#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12642#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12170#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12171#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13125#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13397#L620 assume 1 == ~t5_pc~0; 12119#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12120#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13012#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13263#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13406#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13407#L639 assume !(1 == ~t6_pc~0); 12947#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12540#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12591#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12648#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12649#L658 assume 1 == ~t7_pc~0; 12948#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12864#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13412#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13064#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12426#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12427#L677 assume 1 == ~t8_pc~0; 12654#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12237#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12238#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12498#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12499#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13225#L696 assume !(1 == ~t9_pc~0); 12930#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12931#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12703#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12704#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12954#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13167#L715 assume 1 == ~t10_pc~0; 13174#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13046#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12852#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12853#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12792#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12231#L734 assume !(1 == ~t11_pc~0); 12232#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12719#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12801#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11970#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11971#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13013#L1213 assume !(1 == ~M_E~0); 12789#L1213-2 assume !(1 == ~T1_E~0); 12790#L1218-1 assume !(1 == ~T2_E~0); 12005#L1223-1 assume !(1 == ~T3_E~0); 12006#L1228-1 assume !(1 == ~T4_E~0); 12765#L1233-1 assume !(1 == ~T5_E~0); 13408#L1238-1 assume !(1 == ~T6_E~0); 13123#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13124#L1248-1 assume !(1 == ~T8_E~0); 13170#L1253-1 assume !(1 == ~T9_E~0); 13171#L1258-1 assume !(1 == ~T10_E~0); 13146#L1263-1 assume !(1 == ~T11_E~0); 13147#L1268-1 assume !(1 == ~E_1~0); 12967#L1273-1 assume !(1 == ~E_2~0); 12968#L1278-1 assume !(1 == ~E_3~0); 12538#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12539#L1288-1 assume !(1 == ~E_5~0); 13269#L1293-1 assume !(1 == ~E_6~0); 13229#L1298-1 assume !(1 == ~E_7~0); 13000#L1303-1 assume !(1 == ~E_8~0); 12548#L1308-1 assume !(1 == ~E_9~0); 12440#L1313-1 assume !(1 == ~E_10~0); 12441#L1318-1 assume !(1 == ~E_11~0); 12448#L1323-1 assume { :end_inline_reset_delta_events } true; 12449#L1644-2 [2023-11-29 03:16:40,377 INFO L750 eck$LassoCheckResult]: Loop: 12449#L1644-2 assume !false; 13062#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12355#L1065-1 assume !false; 12356#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13404#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12087#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12664#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12553#L906 assume !(0 != eval_~tmp~0#1); 12555#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12874#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12875#L1090-3 assume !(0 == ~M_E~0); 13284#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13341#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13306#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13307#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12329#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12330#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12606#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12607#L1125-3 assume !(0 == ~T8_E~0); 13122#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13379#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12528#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12037#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12038#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12162#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12163#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12511#L1165-3 assume !(0 == ~E_5~0); 12512#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12911#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12425#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12186#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12187#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13367#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13368#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12746#L525-36 assume !(1 == ~m_pc~0); 12747#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12287#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12288#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12563#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12564#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12477#L544-36 assume 1 == ~t1_pc~0; 12478#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13034#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13035#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13374#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13354#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13259#L563-36 assume 1 == ~t2_pc~0; 12276#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12035#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12036#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13240#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12762#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12763#L582-36 assume 1 == ~t3_pc~0; 12595#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12596#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12694#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12695#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12800#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12740#L601-36 assume 1 == ~t4_pc~0; 12626#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12627#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12892#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12893#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13345#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13246#L620-36 assume 1 == ~t5_pc~0; 12679#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12680#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13107#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12653#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 12296#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12083#L639-36 assume 1 == ~t6_pc~0; 12084#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12124#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12125#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12346#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12347#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12952#L658-36 assume !(1 == ~t7_pc~0); 12096#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 12097#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13331#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12074#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12075#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13096#L677-36 assume !(1 == ~t8_pc~0); 12867#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12868#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12997#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12998#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12894#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12895#L696-36 assume 1 == ~t9_pc~0; 12786#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12787#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12728#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12729#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12912#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12913#L715-36 assume 1 == ~t10_pc~0; 13057#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11972#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11973#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11948#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11949#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12339#L734-36 assume !(1 == ~t11_pc~0); 12051#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 12052#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12357#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11964#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11965#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12976#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12614#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12615#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12387#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12388#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12567#L1233-3 assume !(1 == ~T5_E~0); 12568#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12837#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12838#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13344#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13346#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12370#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12371#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13319#L1273-3 assume !(1 == ~E_2~0); 13334#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13336#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12715#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12716#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12561#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12562#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13058#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12558#L1313-3 assume !(1 == ~E_10~0); 12559#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12372#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12373#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12314#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12542#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 12543#L1663 assume !(0 == start_simulation_~tmp~3#1); 12212#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12950#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12158#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12044#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 12045#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12107#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12430#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 12896#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12449#L1644-2 [2023-11-29 03:16:40,377 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:40,378 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2023-11-29 03:16:40,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:40,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359395011] [2023-11-29 03:16:40,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:40,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:40,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:40,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:40,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:40,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359395011] [2023-11-29 03:16:40,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359395011] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:40,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:40,434 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:40,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [559363825] [2023-11-29 03:16:40,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:40,435 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:40,435 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:40,436 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 2 times [2023-11-29 03:16:40,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:40,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53172489] [2023-11-29 03:16:40,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:40,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:40,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:40,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:40,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:40,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53172489] [2023-11-29 03:16:40,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53172489] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:40,509 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:40,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:40,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269840531] [2023-11-29 03:16:40,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:40,510 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:40,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:40,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:40,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:40,511 INFO L87 Difference]: Start difference. First operand 1488 states and 2202 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:40,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:40,545 INFO L93 Difference]: Finished difference Result 1488 states and 2201 transitions. [2023-11-29 03:16:40,545 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2201 transitions. [2023-11-29 03:16:40,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:40,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2201 transitions. [2023-11-29 03:16:40,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:40,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:40,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2201 transitions. [2023-11-29 03:16:40,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:40,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-29 03:16:40,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2201 transitions. [2023-11-29 03:16:40,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:40,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4791666666666667) internal successors, (2201), 1487 states have internal predecessors, (2201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:40,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2201 transitions. [2023-11-29 03:16:40,607 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-29 03:16:40,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:40,608 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2201 transitions. [2023-11-29 03:16:40,608 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 03:16:40,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2201 transitions. [2023-11-29 03:16:40,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:40,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:40,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:40,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:40,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:40,621 INFO L748 eck$LassoCheckResult]: Stem: 15373#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15374#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15823#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15824#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15695#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15588#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15317#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14965#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14966#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15010#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15011#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15953#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15954#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15998#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15414#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15415#L1090 assume !(0 == ~M_E~0); 15457#L1090-2 assume !(0 == ~T1_E~0); 15458#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16146#L1100-1 assume !(0 == ~T3_E~0); 16147#L1105-1 assume !(0 == ~T4_E~0); 15238#L1110-1 assume !(0 == ~T5_E~0); 15239#L1115-1 assume !(0 == ~T6_E~0); 15624#L1120-1 assume !(0 == ~T7_E~0); 15932#L1125-1 assume !(0 == ~T8_E~0); 16404#L1130-1 assume !(0 == ~T9_E~0); 16167#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15419#L1140-1 assume !(0 == ~T11_E~0); 15420#L1145-1 assume !(0 == ~E_1~0); 16101#L1150-1 assume !(0 == ~E_2~0); 15601#L1155-1 assume !(0 == ~E_3~0); 15602#L1160-1 assume !(0 == ~E_4~0); 15700#L1165-1 assume !(0 == ~E_5~0); 15701#L1170-1 assume !(0 == ~E_6~0); 16339#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15781#L1180-1 assume !(0 == ~E_8~0); 15782#L1185-1 assume !(0 == ~E_9~0); 15416#L1190-1 assume !(0 == ~E_10~0); 15417#L1195-1 assume !(0 == ~E_11~0); 15797#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15621#L525 assume !(1 == ~m_pc~0); 15055#L525-2 is_master_triggered_~__retres1~0#1 := 0; 15056#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16241#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16216#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15406#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15407#L544 assume 1 == ~t1_pc~0; 15676#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15623#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15035#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15261#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15901#L563 assume !(1 == ~t2_pc~0); 16087#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15074#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15075#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15485#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15486#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15979#L582 assume 1 == ~t3_pc~0; 15207#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15208#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14958#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15143#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15144#L601 assume !(1 == ~t4_pc~0); 16113#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15625#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15157#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15158#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 16108#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16380#L620 assume 1 == ~t5_pc~0; 15104#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15105#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15995#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16247#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16389#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16390#L639 assume !(1 == ~t6_pc~0); 15930#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15525#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15526#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15574#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15631#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15632#L658 assume 1 == ~t7_pc~0; 15931#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15848#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16395#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16047#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15409#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15410#L677 assume 1 == ~t8_pc~0; 15639#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15220#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15481#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15482#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16208#L696 assume !(1 == ~t9_pc~0); 15915#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15916#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15686#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15687#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15937#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16150#L715 assume 1 == ~t10_pc~0; 16157#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16029#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15835#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15836#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15775#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15214#L734 assume !(1 == ~t11_pc~0); 15215#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15702#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15784#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14955#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14956#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15996#L1213 assume !(1 == ~M_E~0); 15773#L1213-2 assume !(1 == ~T1_E~0); 15774#L1218-1 assume !(1 == ~T2_E~0); 14988#L1223-1 assume !(1 == ~T3_E~0); 14989#L1228-1 assume !(1 == ~T4_E~0); 15748#L1233-1 assume !(1 == ~T5_E~0); 16391#L1238-1 assume !(1 == ~T6_E~0); 16106#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16107#L1248-1 assume !(1 == ~T8_E~0); 16153#L1253-1 assume !(1 == ~T9_E~0); 16154#L1258-1 assume !(1 == ~T10_E~0); 16129#L1263-1 assume !(1 == ~T11_E~0); 16130#L1268-1 assume !(1 == ~E_1~0); 15950#L1273-1 assume !(1 == ~E_2~0); 15951#L1278-1 assume !(1 == ~E_3~0); 15521#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15522#L1288-1 assume !(1 == ~E_5~0); 16252#L1293-1 assume !(1 == ~E_6~0); 16212#L1298-1 assume !(1 == ~E_7~0); 15983#L1303-1 assume !(1 == ~E_8~0); 15531#L1308-1 assume !(1 == ~E_9~0); 15423#L1313-1 assume !(1 == ~E_10~0); 15424#L1318-1 assume !(1 == ~E_11~0); 15434#L1323-1 assume { :end_inline_reset_delta_events } true; 15435#L1644-2 [2023-11-29 03:16:40,621 INFO L750 eck$LassoCheckResult]: Loop: 15435#L1644-2 assume !false; 16045#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15339#L1065-1 assume !false; 15340#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16387#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15070#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15647#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15536#L906 assume !(0 != eval_~tmp~0#1); 15538#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15858#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15859#L1090-3 assume !(0 == ~M_E~0); 16267#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16324#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16289#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16290#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15312#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15313#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15589#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15590#L1125-3 assume !(0 == ~T8_E~0); 16105#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16362#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15513#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15022#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15023#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15146#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15147#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15494#L1165-3 assume !(0 == ~E_5~0); 15495#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15894#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15408#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15170#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15171#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16350#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16351#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15729#L525-36 assume !(1 == ~m_pc~0); 15730#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15275#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15276#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15546#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15547#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15460#L544-36 assume 1 == ~t1_pc~0; 15461#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16017#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16018#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16357#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16338#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16242#L563-36 assume 1 == ~t2_pc~0; 15259#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15018#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15019#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16223#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15745#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15746#L582-36 assume 1 == ~t3_pc~0; 15578#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15579#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15677#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15678#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15783#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15723#L601-36 assume 1 == ~t4_pc~0; 15609#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15610#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15875#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15876#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16328#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16227#L620-36 assume 1 == ~t5_pc~0; 15660#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15661#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16090#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15636#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 15279#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15063#L639-36 assume 1 == ~t6_pc~0; 15064#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15102#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15103#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15329#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15330#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15935#L658-36 assume !(1 == ~t7_pc~0); 15079#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 15080#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16314#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15057#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15058#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16079#L677-36 assume 1 == ~t8_pc~0; 16256#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15851#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15980#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15981#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15877#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15878#L696-36 assume 1 == ~t9_pc~0; 15769#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15770#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15711#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15712#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15895#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15896#L715-36 assume !(1 == ~t10_pc~0); 15857#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14953#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14954#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14931#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14932#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15322#L734-36 assume !(1 == ~t11_pc~0); 15032#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 15033#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15338#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14947#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14948#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15959#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15595#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15596#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15370#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15371#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15550#L1233-3 assume !(1 == ~T5_E~0); 15551#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15820#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15821#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16327#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16329#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15352#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15353#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16302#L1273-3 assume !(1 == ~E_2~0); 16317#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16319#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15698#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15699#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15544#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15545#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16041#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15541#L1313-3 assume !(1 == ~E_10~0); 15542#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15354#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15355#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15297#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 15524#L1663 assume !(0 == start_simulation_~tmp~3#1); 15190#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15933#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15141#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 15025#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15087#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15413#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 15879#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15435#L1644-2 [2023-11-29 03:16:40,622 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:40,622 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2023-11-29 03:16:40,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:40,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1646177372] [2023-11-29 03:16:40,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:40,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:40,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:40,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:40,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:40,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1646177372] [2023-11-29 03:16:40,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1646177372] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:40,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:40,680 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:40,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545106884] [2023-11-29 03:16:40,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:40,681 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:40,681 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:40,682 INFO L85 PathProgramCache]: Analyzing trace with hash -658480883, now seen corresponding path program 1 times [2023-11-29 03:16:40,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:40,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272441159] [2023-11-29 03:16:40,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:40,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:40,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:40,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:40,768 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:40,768 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272441159] [2023-11-29 03:16:40,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272441159] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:40,768 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:40,768 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:40,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241953945] [2023-11-29 03:16:40,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:40,769 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:40,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:40,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:40,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:40,770 INFO L87 Difference]: Start difference. First operand 1488 states and 2201 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:40,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:40,804 INFO L93 Difference]: Finished difference Result 1488 states and 2200 transitions. [2023-11-29 03:16:40,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2200 transitions. [2023-11-29 03:16:40,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:40,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2200 transitions. [2023-11-29 03:16:40,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:40,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:40,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2200 transitions. [2023-11-29 03:16:40,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:40,830 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-29 03:16:40,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2200 transitions. [2023-11-29 03:16:40,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:40,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.478494623655914) internal successors, (2200), 1487 states have internal predecessors, (2200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:40,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2200 transitions. [2023-11-29 03:16:40,864 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-29 03:16:40,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:40,865 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2200 transitions. [2023-11-29 03:16:40,865 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 03:16:40,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2200 transitions. [2023-11-29 03:16:40,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:40,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:40,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:40,875 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:40,875 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:40,875 INFO L748 eck$LassoCheckResult]: Stem: 18356#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18357#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 19338#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19339#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18806#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18807#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18678#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18571#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18300#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17948#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17949#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17993#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17994#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18936#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18937#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18981#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18397#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18398#L1090 assume !(0 == ~M_E~0); 18440#L1090-2 assume !(0 == ~T1_E~0); 18441#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19128#L1100-1 assume !(0 == ~T3_E~0); 19129#L1105-1 assume !(0 == ~T4_E~0); 18220#L1110-1 assume !(0 == ~T5_E~0); 18221#L1115-1 assume !(0 == ~T6_E~0); 18607#L1120-1 assume !(0 == ~T7_E~0); 18915#L1125-1 assume !(0 == ~T8_E~0); 19387#L1130-1 assume !(0 == ~T9_E~0); 19150#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18402#L1140-1 assume !(0 == ~T11_E~0); 18403#L1145-1 assume !(0 == ~E_1~0); 19084#L1150-1 assume !(0 == ~E_2~0); 18584#L1155-1 assume !(0 == ~E_3~0); 18585#L1160-1 assume !(0 == ~E_4~0); 18683#L1165-1 assume !(0 == ~E_5~0); 18684#L1170-1 assume !(0 == ~E_6~0); 19322#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18764#L1180-1 assume !(0 == ~E_8~0); 18765#L1185-1 assume !(0 == ~E_9~0); 18399#L1190-1 assume !(0 == ~E_10~0); 18400#L1195-1 assume !(0 == ~E_11~0); 18780#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18599#L525 assume !(1 == ~m_pc~0); 18038#L525-2 is_master_triggered_~__retres1~0#1 := 0; 18039#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19224#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19197#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18389#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18390#L544 assume 1 == ~t1_pc~0; 18659#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18606#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18012#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18013#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18244#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18884#L563 assume !(1 == ~t2_pc~0); 19070#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18057#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18058#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18468#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18469#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18962#L582 assume 1 == ~t3_pc~0; 18188#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18189#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17940#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17941#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 18126#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18127#L601 assume !(1 == ~t4_pc~0); 19096#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18608#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18136#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18137#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 19091#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19363#L620 assume 1 == ~t5_pc~0; 18085#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18086#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19229#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19372#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19373#L639 assume !(1 == ~t6_pc~0); 18913#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18506#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18507#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18557#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18614#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18615#L658 assume 1 == ~t7_pc~0; 18914#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18830#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19378#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19030#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18392#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18393#L677 assume 1 == ~t8_pc~0; 18620#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18203#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18204#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18464#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18465#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19191#L696 assume !(1 == ~t9_pc~0); 18896#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18897#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18669#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18670#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18920#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19133#L715 assume 1 == ~t10_pc~0; 19140#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19012#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18818#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18819#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18758#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18197#L734 assume !(1 == ~t11_pc~0); 18198#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18685#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18767#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17936#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17937#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18979#L1213 assume !(1 == ~M_E~0); 18755#L1213-2 assume !(1 == ~T1_E~0); 18756#L1218-1 assume !(1 == ~T2_E~0); 17971#L1223-1 assume !(1 == ~T3_E~0); 17972#L1228-1 assume !(1 == ~T4_E~0); 18731#L1233-1 assume !(1 == ~T5_E~0); 19374#L1238-1 assume !(1 == ~T6_E~0); 19089#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19090#L1248-1 assume !(1 == ~T8_E~0); 19136#L1253-1 assume !(1 == ~T9_E~0); 19137#L1258-1 assume !(1 == ~T10_E~0); 19112#L1263-1 assume !(1 == ~T11_E~0); 19113#L1268-1 assume !(1 == ~E_1~0); 18933#L1273-1 assume !(1 == ~E_2~0); 18934#L1278-1 assume !(1 == ~E_3~0); 18504#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18505#L1288-1 assume !(1 == ~E_5~0); 19235#L1293-1 assume !(1 == ~E_6~0); 19195#L1298-1 assume !(1 == ~E_7~0); 18966#L1303-1 assume !(1 == ~E_8~0); 18514#L1308-1 assume !(1 == ~E_9~0); 18406#L1313-1 assume !(1 == ~E_10~0); 18407#L1318-1 assume !(1 == ~E_11~0); 18414#L1323-1 assume { :end_inline_reset_delta_events } true; 18415#L1644-2 [2023-11-29 03:16:40,876 INFO L750 eck$LassoCheckResult]: Loop: 18415#L1644-2 assume !false; 19028#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18321#L1065-1 assume !false; 18322#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19370#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18053#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18630#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18519#L906 assume !(0 != eval_~tmp~0#1); 18521#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18841#L1090-3 assume !(0 == ~M_E~0); 19250#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19307#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19272#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19273#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18295#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18296#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18572#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18573#L1125-3 assume !(0 == ~T8_E~0); 19088#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19345#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18494#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18003#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18004#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18128#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18129#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18477#L1165-3 assume !(0 == ~E_5~0); 18478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18877#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18391#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18152#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18153#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19333#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19334#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18712#L525-36 assume !(1 == ~m_pc~0); 18713#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18253#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18254#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18529#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18530#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18443#L544-36 assume 1 == ~t1_pc~0; 18444#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19000#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19001#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19340#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19320#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19225#L563-36 assume 1 == ~t2_pc~0; 18242#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18001#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18002#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19206#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18728#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18729#L582-36 assume 1 == ~t3_pc~0; 18561#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18562#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18660#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18661#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18766#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18706#L601-36 assume 1 == ~t4_pc~0; 18592#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18593#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18858#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18859#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19311#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19212#L620-36 assume 1 == ~t5_pc~0; 18645#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18646#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19073#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18619#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 18262#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18049#L639-36 assume 1 == ~t6_pc~0; 18050#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18090#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18091#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18312#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18313#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18918#L658-36 assume 1 == ~t7_pc~0; 18162#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18063#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19297#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18040#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18041#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19062#L677-36 assume !(1 == ~t8_pc~0); 18833#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 18834#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18963#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18964#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18860#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18861#L696-36 assume 1 == ~t9_pc~0; 18752#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18753#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18694#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18695#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18878#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18879#L715-36 assume !(1 == ~t10_pc~0); 18842#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 17938#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17939#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17914#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17915#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18305#L734-36 assume !(1 == ~t11_pc~0); 18017#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 18018#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18323#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17930#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17931#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18942#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18580#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18581#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18353#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18354#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18533#L1233-3 assume !(1 == ~T5_E~0); 18534#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18803#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18804#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19310#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19312#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18336#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18337#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19285#L1273-3 assume !(1 == ~E_2~0); 19300#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19302#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18681#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18682#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18527#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18528#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19024#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18524#L1313-3 assume !(1 == ~E_10~0); 18525#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18338#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18339#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18280#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18508#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 18509#L1663 assume !(0 == start_simulation_~tmp~3#1); 18178#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18916#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18124#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18010#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 18011#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18073#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18396#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 18862#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18415#L1644-2 [2023-11-29 03:16:40,876 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:40,877 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2023-11-29 03:16:40,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:40,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216147776] [2023-11-29 03:16:40,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:40,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:40,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:40,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:40,938 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:40,939 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216147776] [2023-11-29 03:16:40,939 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216147776] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:40,939 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:40,939 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:40,939 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [362160136] [2023-11-29 03:16:40,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:40,940 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:40,940 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:40,941 INFO L85 PathProgramCache]: Analyzing trace with hash -1386990515, now seen corresponding path program 1 times [2023-11-29 03:16:40,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:40,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328916776] [2023-11-29 03:16:40,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:40,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:40,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328916776] [2023-11-29 03:16:41,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328916776] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [85541353] [2023-11-29 03:16:41,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,013 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:41,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:41,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:41,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:41,014 INFO L87 Difference]: Start difference. First operand 1488 states and 2200 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:41,048 INFO L93 Difference]: Finished difference Result 1488 states and 2199 transitions. [2023-11-29 03:16:41,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2199 transitions. [2023-11-29 03:16:41,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2199 transitions. [2023-11-29 03:16:41,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:41,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:41,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2199 transitions. [2023-11-29 03:16:41,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:41,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-29 03:16:41,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2199 transitions. [2023-11-29 03:16:41,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:41,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4778225806451613) internal successors, (2199), 1487 states have internal predecessors, (2199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2199 transitions. [2023-11-29 03:16:41,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-29 03:16:41,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:41,109 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2199 transitions. [2023-11-29 03:16:41,109 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 03:16:41,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2199 transitions. [2023-11-29 03:16:41,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:41,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:41,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:41,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:41,119 INFO L748 eck$LassoCheckResult]: Stem: 21339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 22321#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22322#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21789#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21790#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21661#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21554#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21283#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20931#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20932#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20976#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20977#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21919#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21920#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21964#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21380#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21381#L1090 assume !(0 == ~M_E~0); 21423#L1090-2 assume !(0 == ~T1_E~0); 21424#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22112#L1100-1 assume !(0 == ~T3_E~0); 22113#L1105-1 assume !(0 == ~T4_E~0); 21203#L1110-1 assume !(0 == ~T5_E~0); 21204#L1115-1 assume !(0 == ~T6_E~0); 21590#L1120-1 assume !(0 == ~T7_E~0); 21898#L1125-1 assume !(0 == ~T8_E~0); 22370#L1130-1 assume !(0 == ~T9_E~0); 22133#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21385#L1140-1 assume !(0 == ~T11_E~0); 21386#L1145-1 assume !(0 == ~E_1~0); 22067#L1150-1 assume !(0 == ~E_2~0); 21567#L1155-1 assume !(0 == ~E_3~0); 21568#L1160-1 assume !(0 == ~E_4~0); 21666#L1165-1 assume !(0 == ~E_5~0); 21667#L1170-1 assume !(0 == ~E_6~0); 22305#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21747#L1180-1 assume !(0 == ~E_8~0); 21748#L1185-1 assume !(0 == ~E_9~0); 21382#L1190-1 assume !(0 == ~E_10~0); 21383#L1195-1 assume !(0 == ~E_11~0); 21763#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21587#L525 assume !(1 == ~m_pc~0); 21021#L525-2 is_master_triggered_~__retres1~0#1 := 0; 21022#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22207#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22180#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21372#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21373#L544 assume 1 == ~t1_pc~0; 21642#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21589#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21000#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21001#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21227#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21867#L563 assume !(1 == ~t2_pc~0); 22053#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21040#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21041#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21451#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21452#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21945#L582 assume 1 == ~t3_pc~0; 21173#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21174#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20923#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20924#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 21109#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21110#L601 assume !(1 == ~t4_pc~0); 22079#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21591#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21123#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21124#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 22074#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22346#L620 assume 1 == ~t5_pc~0; 21068#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21069#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22212#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22355#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22356#L639 assume !(1 == ~t6_pc~0); 21896#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21491#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21540#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21597#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21598#L658 assume 1 == ~t7_pc~0; 21897#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22361#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22013#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21375#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21376#L677 assume 1 == ~t8_pc~0; 21603#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21186#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21187#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21447#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21448#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22174#L696 assume !(1 == ~t9_pc~0); 21881#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21882#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21653#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21903#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22116#L715 assume 1 == ~t10_pc~0; 22123#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21995#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21801#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21802#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21741#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21180#L734 assume !(1 == ~t11_pc~0); 21181#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21668#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21750#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20921#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20922#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21962#L1213 assume !(1 == ~M_E~0); 21739#L1213-2 assume !(1 == ~T1_E~0); 21740#L1218-1 assume !(1 == ~T2_E~0); 20954#L1223-1 assume !(1 == ~T3_E~0); 20955#L1228-1 assume !(1 == ~T4_E~0); 21714#L1233-1 assume !(1 == ~T5_E~0); 22357#L1238-1 assume !(1 == ~T6_E~0); 22072#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22073#L1248-1 assume !(1 == ~T8_E~0); 22119#L1253-1 assume !(1 == ~T9_E~0); 22120#L1258-1 assume !(1 == ~T10_E~0); 22095#L1263-1 assume !(1 == ~T11_E~0); 22096#L1268-1 assume !(1 == ~E_1~0); 21916#L1273-1 assume !(1 == ~E_2~0); 21917#L1278-1 assume !(1 == ~E_3~0); 21487#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21488#L1288-1 assume !(1 == ~E_5~0); 22218#L1293-1 assume !(1 == ~E_6~0); 22178#L1298-1 assume !(1 == ~E_7~0); 21949#L1303-1 assume !(1 == ~E_8~0); 21497#L1308-1 assume !(1 == ~E_9~0); 21389#L1313-1 assume !(1 == ~E_10~0); 21390#L1318-1 assume !(1 == ~E_11~0); 21397#L1323-1 assume { :end_inline_reset_delta_events } true; 21398#L1644-2 [2023-11-29 03:16:41,120 INFO L750 eck$LassoCheckResult]: Loop: 21398#L1644-2 assume !false; 22011#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21305#L1065-1 assume !false; 21306#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22353#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21036#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21613#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21502#L906 assume !(0 != eval_~tmp~0#1); 21504#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21824#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21825#L1090-3 assume !(0 == ~M_E~0); 22233#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22290#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22255#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22256#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21278#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21279#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21555#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21556#L1125-3 assume !(0 == ~T8_E~0); 22071#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22328#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21477#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20988#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20989#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21112#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21113#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21460#L1165-3 assume !(0 == ~E_5~0); 21461#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21860#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21374#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21136#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21137#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22316#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22317#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21695#L525-36 assume !(1 == ~m_pc~0); 21696#L525-38 is_master_triggered_~__retres1~0#1 := 0; 21241#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21242#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21512#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21513#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21426#L544-36 assume 1 == ~t1_pc~0; 21427#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21983#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21984#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22323#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22304#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22208#L563-36 assume 1 == ~t2_pc~0; 21225#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20984#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20985#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22189#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21711#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21712#L582-36 assume 1 == ~t3_pc~0; 21544#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21545#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21643#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21644#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21749#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21689#L601-36 assume 1 == ~t4_pc~0; 21575#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21576#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21841#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21842#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22294#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22195#L620-36 assume !(1 == ~t5_pc~0); 21632#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 21631#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22060#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21602#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 21245#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21032#L639-36 assume 1 == ~t6_pc~0; 21033#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21073#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21074#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21293#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21294#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21901#L658-36 assume !(1 == ~t7_pc~0); 21042#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 21043#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22280#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21023#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21024#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22045#L677-36 assume !(1 == ~t8_pc~0); 21815#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 21816#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21946#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21947#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21843#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21844#L696-36 assume 1 == ~t9_pc~0; 21735#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21736#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21677#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21678#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21861#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21862#L715-36 assume 1 == ~t10_pc~0; 22006#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20919#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20920#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20897#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20898#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21288#L734-36 assume !(1 == ~t11_pc~0); 20998#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20999#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21304#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20913#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20914#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21925#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21561#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21562#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21336#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21337#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21516#L1233-3 assume !(1 == ~T5_E~0); 21517#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21786#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21787#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22293#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22295#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21318#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21319#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22268#L1273-3 assume !(1 == ~E_2~0); 22283#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22285#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21665#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21509#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21510#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22007#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21507#L1313-3 assume !(1 == ~E_10~0); 21508#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21320#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21321#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21263#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 21490#L1663 assume !(0 == start_simulation_~tmp~3#1); 21154#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21899#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21107#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20990#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20991#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21053#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21379#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 21845#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21398#L1644-2 [2023-11-29 03:16:41,120 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:41,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2023-11-29 03:16:41,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:41,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836243628] [2023-11-29 03:16:41,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:41,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:41,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836243628] [2023-11-29 03:16:41,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1836243628] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,172 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1914527869] [2023-11-29 03:16:41,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,173 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:41,173 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:41,173 INFO L85 PathProgramCache]: Analyzing trace with hash -979985172, now seen corresponding path program 1 times [2023-11-29 03:16:41,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:41,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486906986] [2023-11-29 03:16:41,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:41,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:41,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [486906986] [2023-11-29 03:16:41,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [486906986] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551741083] [2023-11-29 03:16:41,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,240 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:41,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:41,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:41,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:41,241 INFO L87 Difference]: Start difference. First operand 1488 states and 2199 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:41,300 INFO L93 Difference]: Finished difference Result 1488 states and 2198 transitions. [2023-11-29 03:16:41,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2198 transitions. [2023-11-29 03:16:41,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2198 transitions. [2023-11-29 03:16:41,314 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:41,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:41,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2198 transitions. [2023-11-29 03:16:41,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:41,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-29 03:16:41,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2198 transitions. [2023-11-29 03:16:41,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:41,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4771505376344085) internal successors, (2198), 1487 states have internal predecessors, (2198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2198 transitions. [2023-11-29 03:16:41,348 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-29 03:16:41,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:41,349 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2198 transitions. [2023-11-29 03:16:41,349 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 03:16:41,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2198 transitions. [2023-11-29 03:16:41,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:41,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:41,357 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:41,357 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:41,357 INFO L748 eck$LassoCheckResult]: Stem: 24322#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24323#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 25305#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25306#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24772#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24773#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24644#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24537#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24266#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23914#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23915#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23959#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23960#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24906#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24907#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24954#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24363#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24364#L1090 assume !(0 == ~M_E~0); 24410#L1090-2 assume !(0 == ~T1_E~0); 24411#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25095#L1100-1 assume !(0 == ~T3_E~0); 25096#L1105-1 assume !(0 == ~T4_E~0); 24187#L1110-1 assume !(0 == ~T5_E~0); 24188#L1115-1 assume !(0 == ~T6_E~0); 24576#L1120-1 assume !(0 == ~T7_E~0); 24881#L1125-1 assume !(0 == ~T8_E~0); 25353#L1130-1 assume !(0 == ~T9_E~0); 25116#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24368#L1140-1 assume !(0 == ~T11_E~0); 24369#L1145-1 assume !(0 == ~E_1~0); 25050#L1150-1 assume !(0 == ~E_2~0); 24550#L1155-1 assume !(0 == ~E_3~0); 24551#L1160-1 assume !(0 == ~E_4~0); 24649#L1165-1 assume !(0 == ~E_5~0); 24650#L1170-1 assume !(0 == ~E_6~0); 25288#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24730#L1180-1 assume !(0 == ~E_8~0); 24731#L1185-1 assume !(0 == ~E_9~0); 24365#L1190-1 assume !(0 == ~E_10~0); 24366#L1195-1 assume !(0 == ~E_11~0); 24746#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24570#L525 assume !(1 == ~m_pc~0); 24004#L525-2 is_master_triggered_~__retres1~0#1 := 0; 24005#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25190#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25165#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24355#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24356#L544 assume 1 == ~t1_pc~0; 24625#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24572#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23983#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23984#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24210#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24850#L563 assume !(1 == ~t2_pc~0); 25038#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24023#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24024#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24437#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24438#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24928#L582 assume 1 == ~t3_pc~0; 24156#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24157#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23906#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23907#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 24092#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24093#L601 assume !(1 == ~t4_pc~0); 25062#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24577#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24106#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24107#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 25057#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25329#L620 assume 1 == ~t5_pc~0; 24055#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24056#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24944#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25196#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25338#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25339#L639 assume !(1 == ~t6_pc~0); 24879#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24474#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24475#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24523#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24582#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24583#L658 assume 1 == ~t7_pc~0; 24880#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24797#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25344#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24997#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24358#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24359#L677 assume 1 == ~t8_pc~0; 24588#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24175#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24176#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24430#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24431#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25157#L696 assume !(1 == ~t9_pc~0); 24865#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24866#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24635#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24636#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24888#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25100#L715 assume 1 == ~t10_pc~0; 25106#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24978#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24784#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24785#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24724#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24163#L734 assume !(1 == ~t11_pc~0); 24164#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24652#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24735#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23904#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23905#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24945#L1213 assume !(1 == ~M_E~0); 24722#L1213-2 assume !(1 == ~T1_E~0); 24723#L1218-1 assume !(1 == ~T2_E~0); 23937#L1223-1 assume !(1 == ~T3_E~0); 23938#L1228-1 assume !(1 == ~T4_E~0); 24697#L1233-1 assume !(1 == ~T5_E~0); 25340#L1238-1 assume !(1 == ~T6_E~0); 25055#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25056#L1248-1 assume !(1 == ~T8_E~0); 25102#L1253-1 assume !(1 == ~T9_E~0); 25103#L1258-1 assume !(1 == ~T10_E~0); 25078#L1263-1 assume !(1 == ~T11_E~0); 25079#L1268-1 assume !(1 == ~E_1~0); 24899#L1273-1 assume !(1 == ~E_2~0); 24900#L1278-1 assume !(1 == ~E_3~0); 24470#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24471#L1288-1 assume !(1 == ~E_5~0); 25201#L1293-1 assume !(1 == ~E_6~0); 25161#L1298-1 assume !(1 == ~E_7~0); 24932#L1303-1 assume !(1 == ~E_8~0); 24480#L1308-1 assume !(1 == ~E_9~0); 24372#L1313-1 assume !(1 == ~E_10~0); 24373#L1318-1 assume !(1 == ~E_11~0); 24379#L1323-1 assume { :end_inline_reset_delta_events } true; 24380#L1644-2 [2023-11-29 03:16:41,358 INFO L750 eck$LassoCheckResult]: Loop: 24380#L1644-2 assume !false; 24994#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24287#L1065-1 assume !false; 24288#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25336#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24019#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24596#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24485#L906 assume !(0 != eval_~tmp~0#1); 24487#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24807#L1090-3 assume !(0 == ~M_E~0); 25216#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25273#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25238#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25239#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24261#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24262#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24538#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24539#L1125-3 assume !(0 == ~T8_E~0); 25054#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25311#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24460#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23969#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23970#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24094#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24095#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24443#L1165-3 assume !(0 == ~E_5~0); 24444#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24843#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24357#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24118#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24119#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25299#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25300#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24678#L525-36 assume !(1 == ~m_pc~0); 24679#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24219#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24220#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24495#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24496#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24407#L544-36 assume 1 == ~t1_pc~0; 24408#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24966#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24967#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25304#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25286#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25191#L563-36 assume 1 == ~t2_pc~0; 24208#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23967#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23968#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25172#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24694#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24695#L582-36 assume !(1 == ~t3_pc~0); 24529#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 24528#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24626#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24627#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24732#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24672#L601-36 assume !(1 == ~t4_pc~0); 24560#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 24559#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24824#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24825#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25277#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25178#L620-36 assume 1 == ~t5_pc~0; 24611#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24612#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25039#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24585#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 24228#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24015#L639-36 assume 1 == ~t6_pc~0; 24016#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24053#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24054#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24278#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24279#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24884#L658-36 assume 1 == ~t7_pc~0; 24128#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24029#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25263#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24006#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24007#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25028#L677-36 assume 1 == ~t8_pc~0; 25205#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24800#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24929#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24930#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24826#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24827#L696-36 assume !(1 == ~t9_pc~0); 24720#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24719#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24660#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24661#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24844#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24845#L715-36 assume !(1 == ~t10_pc~0); 24808#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23902#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23903#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23880#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23881#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24271#L734-36 assume 1 == ~t11_pc~0; 24272#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23982#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24289#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23896#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23897#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24908#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24546#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24547#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24319#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24320#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24499#L1233-3 assume !(1 == ~T5_E~0); 24500#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24769#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24770#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25276#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25278#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24302#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24303#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25251#L1273-3 assume !(1 == ~E_2~0); 25266#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25268#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24647#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24648#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24493#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24494#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24990#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24490#L1313-3 assume !(1 == ~E_10~0); 24491#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24304#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24305#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24246#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24472#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 24473#L1663 assume !(0 == start_simulation_~tmp~3#1); 24144#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24882#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24090#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23976#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23977#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24039#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24362#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 24828#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24380#L1644-2 [2023-11-29 03:16:41,358 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:41,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2023-11-29 03:16:41,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:41,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380110424] [2023-11-29 03:16:41,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:41,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:41,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380110424] [2023-11-29 03:16:41,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [380110424] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633392826] [2023-11-29 03:16:41,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,400 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:41,400 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:41,400 INFO L85 PathProgramCache]: Analyzing trace with hash -2009510740, now seen corresponding path program 1 times [2023-11-29 03:16:41,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:41,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232501592] [2023-11-29 03:16:41,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:41,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:41,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232501592] [2023-11-29 03:16:41,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232501592] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,458 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902228644] [2023-11-29 03:16:41,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,459 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:41,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:41,460 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:41,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:41,460 INFO L87 Difference]: Start difference. First operand 1488 states and 2198 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:41,486 INFO L93 Difference]: Finished difference Result 1488 states and 2197 transitions. [2023-11-29 03:16:41,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2197 transitions. [2023-11-29 03:16:41,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2197 transitions. [2023-11-29 03:16:41,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:41,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:41,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2197 transitions. [2023-11-29 03:16:41,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:41,504 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-29 03:16:41,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2197 transitions. [2023-11-29 03:16:41,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:41,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.476478494623656) internal successors, (2197), 1487 states have internal predecessors, (2197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2197 transitions. [2023-11-29 03:16:41,528 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-29 03:16:41,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:41,529 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2197 transitions. [2023-11-29 03:16:41,530 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 03:16:41,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2197 transitions. [2023-11-29 03:16:41,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:41,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:41,538 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:41,538 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:41,538 INFO L748 eck$LassoCheckResult]: Stem: 27305#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27306#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 28287#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28288#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27755#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27756#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27627#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27520#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27249#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26897#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26898#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26942#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26943#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27885#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27886#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27930#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27346#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27347#L1090 assume !(0 == ~M_E~0); 27389#L1090-2 assume !(0 == ~T1_E~0); 27390#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28077#L1100-1 assume !(0 == ~T3_E~0); 28078#L1105-1 assume !(0 == ~T4_E~0); 27169#L1110-1 assume !(0 == ~T5_E~0); 27170#L1115-1 assume !(0 == ~T6_E~0); 27556#L1120-1 assume !(0 == ~T7_E~0); 27864#L1125-1 assume !(0 == ~T8_E~0); 28336#L1130-1 assume !(0 == ~T9_E~0); 28099#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27351#L1140-1 assume !(0 == ~T11_E~0); 27352#L1145-1 assume !(0 == ~E_1~0); 28033#L1150-1 assume !(0 == ~E_2~0); 27533#L1155-1 assume !(0 == ~E_3~0); 27534#L1160-1 assume !(0 == ~E_4~0); 27632#L1165-1 assume !(0 == ~E_5~0); 27633#L1170-1 assume !(0 == ~E_6~0); 28271#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27713#L1180-1 assume !(0 == ~E_8~0); 27714#L1185-1 assume !(0 == ~E_9~0); 27348#L1190-1 assume !(0 == ~E_10~0); 27349#L1195-1 assume !(0 == ~E_11~0); 27729#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27548#L525 assume !(1 == ~m_pc~0); 26987#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26988#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28173#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28146#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27338#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27339#L544 assume 1 == ~t1_pc~0; 27608#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27555#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26963#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26964#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 27193#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27833#L563 assume !(1 == ~t2_pc~0); 28019#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27006#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27007#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27417#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27418#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27911#L582 assume 1 == ~t3_pc~0; 27137#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27138#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26889#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26890#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 27075#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27076#L601 assume !(1 == ~t4_pc~0); 28045#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27557#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27090#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 28040#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28312#L620 assume 1 == ~t5_pc~0; 27034#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27035#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28178#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28321#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28322#L639 assume !(1 == ~t6_pc~0); 27862#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27457#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27458#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27506#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27563#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27564#L658 assume 1 == ~t7_pc~0; 27863#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27779#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28327#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27979#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27341#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27342#L677 assume 1 == ~t8_pc~0; 27569#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27152#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27153#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27413#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27414#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28140#L696 assume !(1 == ~t9_pc~0); 27845#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27846#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27618#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27619#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27869#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28082#L715 assume 1 == ~t10_pc~0; 28089#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27961#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27767#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27768#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27707#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27146#L734 assume !(1 == ~t11_pc~0); 27147#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27634#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27716#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26887#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26888#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27928#L1213 assume !(1 == ~M_E~0); 27704#L1213-2 assume !(1 == ~T1_E~0); 27705#L1218-1 assume !(1 == ~T2_E~0); 26920#L1223-1 assume !(1 == ~T3_E~0); 26921#L1228-1 assume !(1 == ~T4_E~0); 27680#L1233-1 assume !(1 == ~T5_E~0); 28323#L1238-1 assume !(1 == ~T6_E~0); 28038#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28039#L1248-1 assume !(1 == ~T8_E~0); 28085#L1253-1 assume !(1 == ~T9_E~0); 28086#L1258-1 assume !(1 == ~T10_E~0); 28061#L1263-1 assume !(1 == ~T11_E~0); 28062#L1268-1 assume !(1 == ~E_1~0); 27882#L1273-1 assume !(1 == ~E_2~0); 27883#L1278-1 assume !(1 == ~E_3~0); 27453#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27454#L1288-1 assume !(1 == ~E_5~0); 28184#L1293-1 assume !(1 == ~E_6~0); 28144#L1298-1 assume !(1 == ~E_7~0); 27915#L1303-1 assume !(1 == ~E_8~0); 27463#L1308-1 assume !(1 == ~E_9~0); 27355#L1313-1 assume !(1 == ~E_10~0); 27356#L1318-1 assume !(1 == ~E_11~0); 27363#L1323-1 assume { :end_inline_reset_delta_events } true; 27364#L1644-2 [2023-11-29 03:16:41,539 INFO L750 eck$LassoCheckResult]: Loop: 27364#L1644-2 assume !false; 27977#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27271#L1065-1 assume !false; 27272#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28319#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27002#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27579#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27468#L906 assume !(0 != eval_~tmp~0#1); 27470#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27790#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27791#L1090-3 assume !(0 == ~M_E~0); 28199#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28256#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28221#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28222#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27244#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27245#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27521#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27522#L1125-3 assume !(0 == ~T8_E~0); 28037#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28294#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27443#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26952#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26953#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27078#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27079#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27426#L1165-3 assume !(0 == ~E_5~0); 27427#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27826#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27340#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27101#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27102#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28282#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28283#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27661#L525-36 assume !(1 == ~m_pc~0); 27662#L525-38 is_master_triggered_~__retres1~0#1 := 0; 27202#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27203#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27478#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27479#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27392#L544-36 assume 1 == ~t1_pc~0; 27393#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27949#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27950#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28289#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28270#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28174#L563-36 assume 1 == ~t2_pc~0; 27191#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26950#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26951#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28155#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27677#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27678#L582-36 assume 1 == ~t3_pc~0; 27510#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27511#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27609#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27610#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27715#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27655#L601-36 assume 1 == ~t4_pc~0; 27541#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27542#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27807#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27808#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28260#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28161#L620-36 assume 1 == ~t5_pc~0; 27596#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27597#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28024#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27568#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 27211#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26998#L639-36 assume 1 == ~t6_pc~0; 26999#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27039#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27040#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27261#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27262#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27867#L658-36 assume !(1 == ~t7_pc~0); 27011#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 27012#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28246#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26989#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26990#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28011#L677-36 assume !(1 == ~t8_pc~0); 27782#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 27783#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27912#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27913#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27809#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27810#L696-36 assume 1 == ~t9_pc~0; 27701#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27702#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27640#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27641#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27827#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27828#L715-36 assume 1 == ~t10_pc~0; 27972#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26885#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26886#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26863#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26864#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27251#L734-36 assume !(1 == ~t11_pc~0); 26961#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26962#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27270#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26879#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26880#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27891#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27527#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27528#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27302#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27303#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27482#L1233-3 assume !(1 == ~T5_E~0); 27483#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27752#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27753#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28259#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28261#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27284#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27285#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28234#L1273-3 assume !(1 == ~E_2~0); 28249#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28250#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27630#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27631#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27475#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27476#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27973#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27473#L1313-3 assume !(1 == ~E_10~0); 27474#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27286#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27287#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27229#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 27456#L1663 assume !(0 == start_simulation_~tmp~3#1); 27120#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27865#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27073#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26956#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26957#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27019#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27345#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 27811#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27364#L1644-2 [2023-11-29 03:16:41,539 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:41,539 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2023-11-29 03:16:41,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:41,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784707387] [2023-11-29 03:16:41,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:41,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:41,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784707387] [2023-11-29 03:16:41,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784707387] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,576 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1824991770] [2023-11-29 03:16:41,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,577 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:41,577 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:41,578 INFO L85 PathProgramCache]: Analyzing trace with hash 297167501, now seen corresponding path program 3 times [2023-11-29 03:16:41,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:41,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187242693] [2023-11-29 03:16:41,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:41,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:41,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,623 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187242693] [2023-11-29 03:16:41,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1187242693] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644994654] [2023-11-29 03:16:41,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,625 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:41,625 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:41,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:41,625 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:41,625 INFO L87 Difference]: Start difference. First operand 1488 states and 2197 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:41,652 INFO L93 Difference]: Finished difference Result 1488 states and 2196 transitions. [2023-11-29 03:16:41,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2196 transitions. [2023-11-29 03:16:41,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2196 transitions. [2023-11-29 03:16:41,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:41,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:41,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2196 transitions. [2023-11-29 03:16:41,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:41,671 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-29 03:16:41,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2196 transitions. [2023-11-29 03:16:41,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:41,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4758064516129032) internal successors, (2196), 1487 states have internal predecessors, (2196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2196 transitions. [2023-11-29 03:16:41,738 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-29 03:16:41,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:41,739 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2196 transitions. [2023-11-29 03:16:41,739 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 03:16:41,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2196 transitions. [2023-11-29 03:16:41,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:41,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:41,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:41,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:41,750 INFO L748 eck$LassoCheckResult]: Stem: 30288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 31271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30738#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30739#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30610#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30503#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30232#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29880#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29881#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29925#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29926#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30872#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30873#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30920#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30329#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30330#L1090 assume !(0 == ~M_E~0); 30376#L1090-2 assume !(0 == ~T1_E~0); 30377#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31061#L1100-1 assume !(0 == ~T3_E~0); 31062#L1105-1 assume !(0 == ~T4_E~0); 30153#L1110-1 assume !(0 == ~T5_E~0); 30154#L1115-1 assume !(0 == ~T6_E~0); 30542#L1120-1 assume !(0 == ~T7_E~0); 30847#L1125-1 assume !(0 == ~T8_E~0); 31319#L1130-1 assume !(0 == ~T9_E~0); 31082#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30334#L1140-1 assume !(0 == ~T11_E~0); 30335#L1145-1 assume !(0 == ~E_1~0); 31016#L1150-1 assume !(0 == ~E_2~0); 30516#L1155-1 assume !(0 == ~E_3~0); 30517#L1160-1 assume !(0 == ~E_4~0); 30615#L1165-1 assume !(0 == ~E_5~0); 30616#L1170-1 assume !(0 == ~E_6~0); 31254#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30696#L1180-1 assume !(0 == ~E_8~0); 30697#L1185-1 assume !(0 == ~E_9~0); 30331#L1190-1 assume !(0 == ~E_10~0); 30332#L1195-1 assume !(0 == ~E_11~0); 30712#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30536#L525 assume !(1 == ~m_pc~0); 29970#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29971#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31156#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31131#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30321#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30322#L544 assume 1 == ~t1_pc~0; 30591#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30538#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29949#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29950#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 30176#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30816#L563 assume !(1 == ~t2_pc~0); 31004#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29989#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30403#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30404#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30894#L582 assume 1 == ~t3_pc~0; 30122#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30123#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29872#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29873#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 30058#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30059#L601 assume !(1 == ~t4_pc~0); 31028#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30543#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30072#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30073#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 31023#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31295#L620 assume 1 == ~t5_pc~0; 30021#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30022#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30910#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31162#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31304#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31305#L639 assume !(1 == ~t6_pc~0); 30845#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30440#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30489#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30548#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30549#L658 assume 1 == ~t7_pc~0; 30846#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30763#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31310#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30963#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30324#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30325#L677 assume 1 == ~t8_pc~0; 30554#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30138#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30139#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30396#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30397#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31123#L696 assume !(1 == ~t9_pc~0); 30831#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30832#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30601#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30602#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30854#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31066#L715 assume 1 == ~t10_pc~0; 31072#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30944#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30750#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30751#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30690#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30129#L734 assume !(1 == ~t11_pc~0); 30130#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30617#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30701#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29870#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29871#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30911#L1213 assume !(1 == ~M_E~0); 30688#L1213-2 assume !(1 == ~T1_E~0); 30689#L1218-1 assume !(1 == ~T2_E~0); 29903#L1223-1 assume !(1 == ~T3_E~0); 29904#L1228-1 assume !(1 == ~T4_E~0); 30663#L1233-1 assume !(1 == ~T5_E~0); 31306#L1238-1 assume !(1 == ~T6_E~0); 31021#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31022#L1248-1 assume !(1 == ~T8_E~0); 31068#L1253-1 assume !(1 == ~T9_E~0); 31069#L1258-1 assume !(1 == ~T10_E~0); 31044#L1263-1 assume !(1 == ~T11_E~0); 31045#L1268-1 assume !(1 == ~E_1~0); 30865#L1273-1 assume !(1 == ~E_2~0); 30866#L1278-1 assume !(1 == ~E_3~0); 30436#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30437#L1288-1 assume !(1 == ~E_5~0); 31167#L1293-1 assume !(1 == ~E_6~0); 31127#L1298-1 assume !(1 == ~E_7~0); 30898#L1303-1 assume !(1 == ~E_8~0); 30446#L1308-1 assume !(1 == ~E_9~0); 30338#L1313-1 assume !(1 == ~E_10~0); 30339#L1318-1 assume !(1 == ~E_11~0); 30349#L1323-1 assume { :end_inline_reset_delta_events } true; 30350#L1644-2 [2023-11-29 03:16:41,751 INFO L750 eck$LassoCheckResult]: Loop: 30350#L1644-2 assume !false; 30960#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30254#L1065-1 assume !false; 30255#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31302#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29985#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30451#L906 assume !(0 != eval_~tmp~0#1); 30453#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30773#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30774#L1090-3 assume !(0 == ~M_E~0); 31182#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31239#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31204#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31205#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30227#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30228#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30504#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30505#L1125-3 assume !(0 == ~T8_E~0); 31020#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31277#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30426#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29935#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29936#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30060#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30061#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30409#L1165-3 assume !(0 == ~E_5~0); 30410#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30809#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30323#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30084#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30085#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31265#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31266#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30641#L525-36 assume !(1 == ~m_pc~0); 30642#L525-38 is_master_triggered_~__retres1~0#1 := 0; 30185#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30186#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30461#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30462#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30373#L544-36 assume 1 == ~t1_pc~0; 30374#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30932#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30933#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31270#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31252#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31157#L563-36 assume 1 == ~t2_pc~0; 30174#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29933#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29934#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31138#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30660#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30661#L582-36 assume 1 == ~t3_pc~0; 30493#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30494#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30592#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30593#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30698#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30638#L601-36 assume 1 == ~t4_pc~0; 30524#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30525#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30790#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30791#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31243#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31144#L620-36 assume 1 == ~t5_pc~0; 30577#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30578#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31005#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30551#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 30194#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29981#L639-36 assume 1 == ~t6_pc~0; 29982#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30019#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30020#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30244#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30245#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30850#L658-36 assume !(1 == ~t7_pc~0); 29994#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 29995#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31229#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29972#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29973#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30994#L677-36 assume 1 == ~t8_pc~0; 31171#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30766#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30895#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30896#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30792#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30793#L696-36 assume 1 == ~t9_pc~0; 30684#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30685#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30626#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30627#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30810#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30811#L715-36 assume !(1 == ~t10_pc~0); 30772#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29868#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29869#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29846#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29847#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30237#L734-36 assume !(1 == ~t11_pc~0); 29947#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 29948#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30253#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29862#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29863#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30874#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30510#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30511#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30285#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30286#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30465#L1233-3 assume !(1 == ~T5_E~0); 30466#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30735#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30736#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31242#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31244#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30267#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30268#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31217#L1273-3 assume !(1 == ~E_2~0); 31232#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31234#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30613#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30614#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30459#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30460#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30956#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30456#L1313-3 assume !(1 == ~E_10~0); 30457#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30269#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30270#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 30212#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30438#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30439#L1663 assume !(0 == start_simulation_~tmp~3#1); 30110#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30848#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 30056#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29939#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29940#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30005#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30328#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30794#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30350#L1644-2 [2023-11-29 03:16:41,751 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:41,752 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2023-11-29 03:16:41,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:41,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059496948] [2023-11-29 03:16:41,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:41,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:41,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1059496948] [2023-11-29 03:16:41,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1059496948] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,814 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,814 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473880646] [2023-11-29 03:16:41,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,815 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:41,815 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:41,815 INFO L85 PathProgramCache]: Analyzing trace with hash -658480883, now seen corresponding path program 2 times [2023-11-29 03:16:41,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:41,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090471642] [2023-11-29 03:16:41,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:41,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:41,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:41,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:41,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:41,893 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090471642] [2023-11-29 03:16:41,893 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090471642] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:41,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:41,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:41,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489459495] [2023-11-29 03:16:41,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:41,895 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:41,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:41,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:41,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:41,896 INFO L87 Difference]: Start difference. First operand 1488 states and 2196 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:41,935 INFO L93 Difference]: Finished difference Result 1488 states and 2195 transitions. [2023-11-29 03:16:41,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2195 transitions. [2023-11-29 03:16:41,942 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2195 transitions. [2023-11-29 03:16:41,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:41,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:41,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2195 transitions. [2023-11-29 03:16:41,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:41,957 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-29 03:16:41,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2195 transitions. [2023-11-29 03:16:41,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:41,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4751344086021505) internal successors, (2195), 1487 states have internal predecessors, (2195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:41,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2195 transitions. [2023-11-29 03:16:41,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-29 03:16:41,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:41,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2195 transitions. [2023-11-29 03:16:41,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 03:16:41,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2195 transitions. [2023-11-29 03:16:41,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:41,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:41,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:42,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:42,000 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:42,001 INFO L748 eck$LassoCheckResult]: Stem: 33271#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 34253#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34254#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33721#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33722#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33593#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33486#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33215#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32863#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32864#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32908#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32909#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33851#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33852#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33896#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33312#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33313#L1090 assume !(0 == ~M_E~0); 33355#L1090-2 assume !(0 == ~T1_E~0); 33356#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34043#L1100-1 assume !(0 == ~T3_E~0); 34044#L1105-1 assume !(0 == ~T4_E~0); 33135#L1110-1 assume !(0 == ~T5_E~0); 33136#L1115-1 assume !(0 == ~T6_E~0); 33522#L1120-1 assume !(0 == ~T7_E~0); 33830#L1125-1 assume !(0 == ~T8_E~0); 34302#L1130-1 assume !(0 == ~T9_E~0); 34065#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33317#L1140-1 assume !(0 == ~T11_E~0); 33318#L1145-1 assume !(0 == ~E_1~0); 33999#L1150-1 assume !(0 == ~E_2~0); 33499#L1155-1 assume !(0 == ~E_3~0); 33500#L1160-1 assume !(0 == ~E_4~0); 33598#L1165-1 assume !(0 == ~E_5~0); 33599#L1170-1 assume !(0 == ~E_6~0); 34237#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33679#L1180-1 assume !(0 == ~E_8~0); 33680#L1185-1 assume !(0 == ~E_9~0); 33314#L1190-1 assume !(0 == ~E_10~0); 33315#L1195-1 assume !(0 == ~E_11~0); 33695#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33514#L525 assume !(1 == ~m_pc~0); 32953#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32954#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34139#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34112#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33304#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33305#L544 assume 1 == ~t1_pc~0; 33574#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33521#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32927#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32928#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 33159#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33799#L563 assume !(1 == ~t2_pc~0); 33985#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32972#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32973#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33383#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33384#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33877#L582 assume 1 == ~t3_pc~0; 33103#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33104#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32855#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32856#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 33041#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33042#L601 assume !(1 == ~t4_pc~0); 34011#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33523#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33053#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33054#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 34006#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34278#L620 assume 1 == ~t5_pc~0; 33000#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33001#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33893#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34144#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34287#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34288#L639 assume !(1 == ~t6_pc~0); 33828#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33421#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33422#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33472#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33529#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33530#L658 assume 1 == ~t7_pc~0; 33829#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33745#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34293#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33945#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33307#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33308#L677 assume 1 == ~t8_pc~0; 33535#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33118#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33119#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33379#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33380#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34106#L696 assume !(1 == ~t9_pc~0); 33811#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33812#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33584#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33585#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33835#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34048#L715 assume 1 == ~t10_pc~0; 34055#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33927#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33733#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33734#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33673#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33112#L734 assume !(1 == ~t11_pc~0); 33113#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33600#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33682#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32851#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32852#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33894#L1213 assume !(1 == ~M_E~0); 33670#L1213-2 assume !(1 == ~T1_E~0); 33671#L1218-1 assume !(1 == ~T2_E~0); 32886#L1223-1 assume !(1 == ~T3_E~0); 32887#L1228-1 assume !(1 == ~T4_E~0); 33646#L1233-1 assume !(1 == ~T5_E~0); 34289#L1238-1 assume !(1 == ~T6_E~0); 34004#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34005#L1248-1 assume !(1 == ~T8_E~0); 34051#L1253-1 assume !(1 == ~T9_E~0); 34052#L1258-1 assume !(1 == ~T10_E~0); 34027#L1263-1 assume !(1 == ~T11_E~0); 34028#L1268-1 assume !(1 == ~E_1~0); 33848#L1273-1 assume !(1 == ~E_2~0); 33849#L1278-1 assume !(1 == ~E_3~0); 33419#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33420#L1288-1 assume !(1 == ~E_5~0); 34150#L1293-1 assume !(1 == ~E_6~0); 34110#L1298-1 assume !(1 == ~E_7~0); 33881#L1303-1 assume !(1 == ~E_8~0); 33429#L1308-1 assume !(1 == ~E_9~0); 33321#L1313-1 assume !(1 == ~E_10~0); 33322#L1318-1 assume !(1 == ~E_11~0); 33329#L1323-1 assume { :end_inline_reset_delta_events } true; 33330#L1644-2 [2023-11-29 03:16:42,001 INFO L750 eck$LassoCheckResult]: Loop: 33330#L1644-2 assume !false; 33943#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33236#L1065-1 assume !false; 33237#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34285#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32968#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33545#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33434#L906 assume !(0 != eval_~tmp~0#1); 33436#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33756#L1090-3 assume !(0 == ~M_E~0); 34165#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34222#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34187#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34188#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33210#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33211#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33487#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33488#L1125-3 assume !(0 == ~T8_E~0); 34003#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34260#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33409#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32918#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32919#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33043#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33044#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33392#L1165-3 assume !(0 == ~E_5~0); 33393#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33792#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33306#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33067#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33068#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34248#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34249#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33627#L525-36 assume !(1 == ~m_pc~0); 33628#L525-38 is_master_triggered_~__retres1~0#1 := 0; 33168#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33169#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33444#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33445#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33358#L544-36 assume !(1 == ~t1_pc~0); 33360#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 33915#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33916#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34255#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34235#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34140#L563-36 assume 1 == ~t2_pc~0; 33157#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32916#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32917#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34121#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33643#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33644#L582-36 assume 1 == ~t3_pc~0; 33476#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33477#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33575#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33576#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33681#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33621#L601-36 assume 1 == ~t4_pc~0; 33507#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33508#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33773#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33774#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34226#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34127#L620-36 assume 1 == ~t5_pc~0; 33560#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33561#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33988#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33534#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 33177#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32964#L639-36 assume 1 == ~t6_pc~0; 32965#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33005#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33006#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33227#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33228#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33833#L658-36 assume !(1 == ~t7_pc~0); 32977#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 32978#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34212#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32955#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32956#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33977#L677-36 assume !(1 == ~t8_pc~0); 33748#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 33749#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33878#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33879#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33775#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33776#L696-36 assume 1 == ~t9_pc~0; 33667#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33668#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33609#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33610#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33793#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33794#L715-36 assume 1 == ~t10_pc~0; 33938#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32853#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32854#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32829#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32830#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33220#L734-36 assume !(1 == ~t11_pc~0); 32932#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 32933#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33238#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32845#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32846#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33857#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33495#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33496#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33268#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33269#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33448#L1233-3 assume !(1 == ~T5_E~0); 33449#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33718#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33719#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34225#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34227#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33251#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33252#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34200#L1273-3 assume !(1 == ~E_2~0); 34215#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34217#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33596#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33597#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33442#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33443#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33939#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33439#L1313-3 assume !(1 == ~E_10~0); 33440#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33253#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33254#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 33195#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33423#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 33424#L1663 assume !(0 == start_simulation_~tmp~3#1); 33086#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33831#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 33039#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 32926#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32988#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33311#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 33777#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33330#L1644-2 [2023-11-29 03:16:42,001 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:42,001 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2023-11-29 03:16:42,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:42,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050327945] [2023-11-29 03:16:42,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:42,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:42,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:42,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:42,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:42,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050327945] [2023-11-29 03:16:42,080 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050327945] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:42,080 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:42,080 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:42,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150097307] [2023-11-29 03:16:42,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:42,081 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:42,081 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:42,081 INFO L85 PathProgramCache]: Analyzing trace with hash -1567805460, now seen corresponding path program 1 times [2023-11-29 03:16:42,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:42,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902264134] [2023-11-29 03:16:42,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:42,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:42,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:42,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:42,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:42,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902264134] [2023-11-29 03:16:42,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902264134] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:42,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:42,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:42,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618122817] [2023-11-29 03:16:42,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:42,145 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:42,145 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:42,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:42,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:42,146 INFO L87 Difference]: Start difference. First operand 1488 states and 2195 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:42,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:42,185 INFO L93 Difference]: Finished difference Result 1488 states and 2190 transitions. [2023-11-29 03:16:42,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2190 transitions. [2023-11-29 03:16:42,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:42,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2190 transitions. [2023-11-29 03:16:42,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:42,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:42,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2190 transitions. [2023-11-29 03:16:42,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:42,207 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-29 03:16:42,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2190 transitions. [2023-11-29 03:16:42,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:42,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.471774193548387) internal successors, (2190), 1487 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:42,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2190 transitions. [2023-11-29 03:16:42,241 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-29 03:16:42,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:42,242 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2190 transitions. [2023-11-29 03:16:42,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 03:16:42,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2190 transitions. [2023-11-29 03:16:42,249 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:42,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:42,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:42,252 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:42,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:42,252 INFO L748 eck$LassoCheckResult]: Stem: 36254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 36255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 37237#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37238#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36704#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 36705#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36576#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36469#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36198#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35846#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35847#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35891#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35892#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36836#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36837#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36882#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36295#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36296#L1090 assume !(0 == ~M_E~0); 36341#L1090-2 assume !(0 == ~T1_E~0); 36342#L1095-1 assume !(0 == ~T2_E~0); 37027#L1100-1 assume !(0 == ~T3_E~0); 37028#L1105-1 assume !(0 == ~T4_E~0); 36119#L1110-1 assume !(0 == ~T5_E~0); 36120#L1115-1 assume !(0 == ~T6_E~0); 36505#L1120-1 assume !(0 == ~T7_E~0); 36813#L1125-1 assume !(0 == ~T8_E~0); 37285#L1130-1 assume !(0 == ~T9_E~0); 37048#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36300#L1140-1 assume !(0 == ~T11_E~0); 36301#L1145-1 assume !(0 == ~E_1~0); 36982#L1150-1 assume !(0 == ~E_2~0); 36482#L1155-1 assume !(0 == ~E_3~0); 36483#L1160-1 assume !(0 == ~E_4~0); 36581#L1165-1 assume !(0 == ~E_5~0); 36582#L1170-1 assume !(0 == ~E_6~0); 37220#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36662#L1180-1 assume !(0 == ~E_8~0); 36663#L1185-1 assume !(0 == ~E_9~0); 36297#L1190-1 assume !(0 == ~E_10~0); 36298#L1195-1 assume !(0 == ~E_11~0); 36678#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36502#L525 assume !(1 == ~m_pc~0); 35936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 35937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37122#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37097#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36287#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36288#L544 assume 1 == ~t1_pc~0; 36557#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36504#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35915#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35916#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 36142#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36782#L563 assume !(1 == ~t2_pc~0); 36968#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35955#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36369#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 36370#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36860#L582 assume 1 == ~t3_pc~0; 36088#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36089#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35838#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35839#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 36024#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36025#L601 assume !(1 == ~t4_pc~0); 36994#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36506#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36039#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 36989#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37261#L620 assume 1 == ~t5_pc~0; 35987#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35988#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36876#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37128#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 37270#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37271#L639 assume !(1 == ~t6_pc~0); 36811#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36406#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36407#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36455#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 36512#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36513#L658 assume 1 == ~t7_pc~0; 36812#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36729#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37276#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36929#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 36290#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36291#L677 assume 1 == ~t8_pc~0; 36520#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36101#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36102#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36362#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 36363#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37089#L696 assume !(1 == ~t9_pc~0); 36796#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36797#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36567#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36568#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36820#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37031#L715 assume 1 == ~t10_pc~0; 37038#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36910#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36716#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36717#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 36656#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36095#L734 assume !(1 == ~t11_pc~0); 36096#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 36583#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36667#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35836#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 35837#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36877#L1213 assume !(1 == ~M_E~0); 36654#L1213-2 assume !(1 == ~T1_E~0); 36655#L1218-1 assume !(1 == ~T2_E~0); 35869#L1223-1 assume !(1 == ~T3_E~0); 35870#L1228-1 assume !(1 == ~T4_E~0); 36629#L1233-1 assume !(1 == ~T5_E~0); 37272#L1238-1 assume !(1 == ~T6_E~0); 36987#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36988#L1248-1 assume !(1 == ~T8_E~0); 37034#L1253-1 assume !(1 == ~T9_E~0); 37035#L1258-1 assume !(1 == ~T10_E~0); 37010#L1263-1 assume !(1 == ~T11_E~0); 37011#L1268-1 assume !(1 == ~E_1~0); 36831#L1273-1 assume !(1 == ~E_2~0); 36832#L1278-1 assume !(1 == ~E_3~0); 36402#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36403#L1288-1 assume !(1 == ~E_5~0); 37133#L1293-1 assume !(1 == ~E_6~0); 37093#L1298-1 assume !(1 == ~E_7~0); 36864#L1303-1 assume !(1 == ~E_8~0); 36412#L1308-1 assume !(1 == ~E_9~0); 36304#L1313-1 assume !(1 == ~E_10~0); 36305#L1318-1 assume !(1 == ~E_11~0); 36315#L1323-1 assume { :end_inline_reset_delta_events } true; 36316#L1644-2 [2023-11-29 03:16:42,253 INFO L750 eck$LassoCheckResult]: Loop: 36316#L1644-2 assume !false; 36926#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36220#L1065-1 assume !false; 36221#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 37268#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35951#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36528#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36417#L906 assume !(0 != eval_~tmp~0#1); 36419#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36739#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36740#L1090-3 assume !(0 == ~M_E~0); 37148#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37205#L1095-3 assume !(0 == ~T2_E~0); 37170#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37171#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36193#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36194#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36470#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36471#L1125-3 assume !(0 == ~T8_E~0); 36986#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37243#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36394#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35903#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35904#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36027#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36028#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36375#L1165-3 assume !(0 == ~E_5~0); 36376#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36775#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36289#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36053#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36054#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37231#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 37232#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36605#L525-36 assume !(1 == ~m_pc~0); 36606#L525-38 is_master_triggered_~__retres1~0#1 := 0; 36151#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36152#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36427#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36428#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36338#L544-36 assume 1 == ~t1_pc~0; 36339#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36898#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36899#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37236#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37218#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37123#L563-36 assume 1 == ~t2_pc~0; 36140#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35899#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35900#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37104#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36626#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36627#L582-36 assume 1 == ~t3_pc~0; 36459#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36460#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36558#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36559#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36664#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36604#L601-36 assume 1 == ~t4_pc~0; 36490#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36491#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36756#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36757#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37209#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37110#L620-36 assume 1 == ~t5_pc~0; 36541#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36542#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36971#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36517#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 36160#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35947#L639-36 assume 1 == ~t6_pc~0; 35948#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35985#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35986#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36210#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36211#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36816#L658-36 assume !(1 == ~t7_pc~0); 35960#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 35961#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37195#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35938#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36960#L677-36 assume 1 == ~t8_pc~0; 37137#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36732#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36861#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36862#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36758#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36759#L696-36 assume 1 == ~t9_pc~0; 36650#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36651#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36592#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36593#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36776#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36777#L715-36 assume !(1 == ~t10_pc~0); 36738#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 35834#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35835#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36203#L734-36 assume !(1 == ~t11_pc~0); 35913#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 35914#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36219#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35828#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35829#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36840#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36476#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36477#L1218-3 assume !(1 == ~T2_E~0); 36251#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36252#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36431#L1233-3 assume !(1 == ~T5_E~0); 36432#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36701#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36702#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37208#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37210#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36233#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36234#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37183#L1273-3 assume !(1 == ~E_2~0); 37198#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37200#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36579#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36580#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36425#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36426#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36922#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36422#L1313-3 assume !(1 == ~E_10~0); 36423#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36235#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36236#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36178#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36405#L1663 assume !(0 == start_simulation_~tmp~3#1); 36076#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36814#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36022#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35905#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 35906#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35971#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36294#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 36760#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 36316#L1644-2 [2023-11-29 03:16:42,253 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:42,253 INFO L85 PathProgramCache]: Analyzing trace with hash 1863040740, now seen corresponding path program 1 times [2023-11-29 03:16:42,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:42,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055493096] [2023-11-29 03:16:42,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:42,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:42,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:42,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:42,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:42,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055493096] [2023-11-29 03:16:42,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055493096] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:42,353 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:42,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:42,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1253185065] [2023-11-29 03:16:42,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:42,354 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:42,354 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:42,354 INFO L85 PathProgramCache]: Analyzing trace with hash 2067663241, now seen corresponding path program 1 times [2023-11-29 03:16:42,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:42,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372335519] [2023-11-29 03:16:42,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:42,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:42,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:42,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:42,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:42,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372335519] [2023-11-29 03:16:42,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372335519] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:42,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:42,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:42,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654634692] [2023-11-29 03:16:42,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:42,415 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:42,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:42,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:16:42,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:16:42,416 INFO L87 Difference]: Start difference. First operand 1488 states and 2190 transitions. cyclomatic complexity: 703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:42,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:42,574 INFO L93 Difference]: Finished difference Result 2840 states and 4171 transitions. [2023-11-29 03:16:42,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2840 states and 4171 transitions. [2023-11-29 03:16:42,588 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2678 [2023-11-29 03:16:42,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2840 states to 2840 states and 4171 transitions. [2023-11-29 03:16:42,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2840 [2023-11-29 03:16:42,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2840 [2023-11-29 03:16:42,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2840 states and 4171 transitions. [2023-11-29 03:16:42,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:42,614 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2840 states and 4171 transitions. [2023-11-29 03:16:42,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2840 states and 4171 transitions. [2023-11-29 03:16:42,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2840 to 1488. [2023-11-29 03:16:42,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4704301075268817) internal successors, (2188), 1487 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:42,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2188 transitions. [2023-11-29 03:16:42,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2188 transitions. [2023-11-29 03:16:42,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:16:42,655 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2188 transitions. [2023-11-29 03:16:42,655 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 03:16:42,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2188 transitions. [2023-11-29 03:16:42,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:42,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:42,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:42,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:42,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:42,664 INFO L748 eck$LassoCheckResult]: Stem: 40592#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 40593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 41574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41042#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 41043#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40914#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40807#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40536#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40184#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40185#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40229#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40230#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41172#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41173#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41217#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40633#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40634#L1090 assume !(0 == ~M_E~0); 40676#L1090-2 assume !(0 == ~T1_E~0); 40677#L1095-1 assume !(0 == ~T2_E~0); 41364#L1100-1 assume !(0 == ~T3_E~0); 41365#L1105-1 assume !(0 == ~T4_E~0); 40456#L1110-1 assume !(0 == ~T5_E~0); 40457#L1115-1 assume !(0 == ~T6_E~0); 40843#L1120-1 assume !(0 == ~T7_E~0); 41151#L1125-1 assume !(0 == ~T8_E~0); 41623#L1130-1 assume !(0 == ~T9_E~0); 41386#L1135-1 assume !(0 == ~T10_E~0); 40638#L1140-1 assume !(0 == ~T11_E~0); 40639#L1145-1 assume !(0 == ~E_1~0); 41320#L1150-1 assume !(0 == ~E_2~0); 40820#L1155-1 assume !(0 == ~E_3~0); 40821#L1160-1 assume !(0 == ~E_4~0); 40919#L1165-1 assume !(0 == ~E_5~0); 40920#L1170-1 assume !(0 == ~E_6~0); 41558#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 41000#L1180-1 assume !(0 == ~E_8~0); 41001#L1185-1 assume !(0 == ~E_9~0); 40635#L1190-1 assume !(0 == ~E_10~0); 40636#L1195-1 assume !(0 == ~E_11~0); 41016#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40835#L525 assume !(1 == ~m_pc~0); 40274#L525-2 is_master_triggered_~__retres1~0#1 := 0; 40275#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41460#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41433#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40625#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40626#L544 assume 1 == ~t1_pc~0; 40895#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40842#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40249#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 40480#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41120#L563 assume !(1 == ~t2_pc~0); 41306#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40293#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40294#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40704#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 40705#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41198#L582 assume 1 == ~t3_pc~0; 40424#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40425#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40176#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40177#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 40362#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40363#L601 assume !(1 == ~t4_pc~0); 41332#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40844#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40372#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40373#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 41327#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41599#L620 assume 1 == ~t5_pc~0; 40321#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40322#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41214#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41465#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 41608#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41609#L639 assume !(1 == ~t6_pc~0); 41149#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40742#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40743#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40793#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 40850#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40851#L658 assume 1 == ~t7_pc~0; 41150#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41066#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41614#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41266#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 40628#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40629#L677 assume 1 == ~t8_pc~0; 40856#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40439#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40440#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40700#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 40701#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41427#L696 assume !(1 == ~t9_pc~0); 41132#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 41133#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40905#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40906#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41156#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41369#L715 assume 1 == ~t10_pc~0; 41376#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41248#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41054#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41055#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 40994#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40433#L734 assume !(1 == ~t11_pc~0); 40434#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 40921#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41003#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40172#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 40173#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41215#L1213 assume !(1 == ~M_E~0); 40991#L1213-2 assume !(1 == ~T1_E~0); 40992#L1218-1 assume !(1 == ~T2_E~0); 40207#L1223-1 assume !(1 == ~T3_E~0); 40208#L1228-1 assume !(1 == ~T4_E~0); 40967#L1233-1 assume !(1 == ~T5_E~0); 41610#L1238-1 assume !(1 == ~T6_E~0); 41325#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41326#L1248-1 assume !(1 == ~T8_E~0); 41372#L1253-1 assume !(1 == ~T9_E~0); 41373#L1258-1 assume !(1 == ~T10_E~0); 41348#L1263-1 assume !(1 == ~T11_E~0); 41349#L1268-1 assume !(1 == ~E_1~0); 41169#L1273-1 assume !(1 == ~E_2~0); 41170#L1278-1 assume !(1 == ~E_3~0); 40740#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40741#L1288-1 assume !(1 == ~E_5~0); 41471#L1293-1 assume !(1 == ~E_6~0); 41431#L1298-1 assume !(1 == ~E_7~0); 41202#L1303-1 assume !(1 == ~E_8~0); 40750#L1308-1 assume !(1 == ~E_9~0); 40642#L1313-1 assume !(1 == ~E_10~0); 40643#L1318-1 assume !(1 == ~E_11~0); 40650#L1323-1 assume { :end_inline_reset_delta_events } true; 40651#L1644-2 [2023-11-29 03:16:42,664 INFO L750 eck$LassoCheckResult]: Loop: 40651#L1644-2 assume !false; 41264#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40557#L1065-1 assume !false; 40558#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41606#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40289#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40866#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40755#L906 assume !(0 != eval_~tmp~0#1); 40757#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41076#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41077#L1090-3 assume !(0 == ~M_E~0); 41486#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41543#L1095-3 assume !(0 == ~T2_E~0); 41508#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41509#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40531#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40532#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40808#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40809#L1125-3 assume !(0 == ~T8_E~0); 41324#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41581#L1135-3 assume !(0 == ~T10_E~0); 40730#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40239#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40240#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40364#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40365#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40713#L1165-3 assume !(0 == ~E_5~0); 40714#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41113#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40627#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40388#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40389#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41569#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41570#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40948#L525-36 assume !(1 == ~m_pc~0); 40949#L525-38 is_master_triggered_~__retres1~0#1 := 0; 40489#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40490#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40765#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40766#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40679#L544-36 assume 1 == ~t1_pc~0; 40680#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41236#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41237#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41576#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41556#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41461#L563-36 assume 1 == ~t2_pc~0; 40478#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40237#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40238#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41442#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40964#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40965#L582-36 assume 1 == ~t3_pc~0; 40797#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40798#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40896#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40897#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41002#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40942#L601-36 assume 1 == ~t4_pc~0; 40828#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40829#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41094#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41095#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41547#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41448#L620-36 assume 1 == ~t5_pc~0; 40881#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40882#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41309#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40855#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 40498#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40285#L639-36 assume 1 == ~t6_pc~0; 40286#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40326#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40327#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40548#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40549#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41154#L658-36 assume !(1 == ~t7_pc~0); 40298#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 40299#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41533#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40276#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40277#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41298#L677-36 assume 1 == ~t8_pc~0; 41475#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41070#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41199#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41200#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41096#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41097#L696-36 assume 1 == ~t9_pc~0; 40988#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40989#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40930#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40931#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41114#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41115#L715-36 assume !(1 == ~t10_pc~0); 41078#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 40174#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40175#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40150#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40151#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40541#L734-36 assume !(1 == ~t11_pc~0); 40253#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 40254#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40559#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40166#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40167#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41178#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40816#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40817#L1218-3 assume !(1 == ~T2_E~0); 40589#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40590#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40769#L1233-3 assume !(1 == ~T5_E~0); 40770#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41039#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41040#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41546#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41548#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40572#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40573#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41521#L1273-3 assume !(1 == ~E_2~0); 41536#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41538#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40917#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40918#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40763#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40764#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41260#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40760#L1313-3 assume !(1 == ~E_10~0); 40761#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40574#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40575#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40516#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40744#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 40745#L1663 assume !(0 == start_simulation_~tmp~3#1); 40414#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41152#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40360#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40246#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 40247#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40309#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40632#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41098#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 40651#L1644-2 [2023-11-29 03:16:42,664 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:42,664 INFO L85 PathProgramCache]: Analyzing trace with hash -268309982, now seen corresponding path program 1 times [2023-11-29 03:16:42,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:42,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261144934] [2023-11-29 03:16:42,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:42,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:42,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:42,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:42,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:42,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [261144934] [2023-11-29 03:16:42,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [261144934] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:42,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:42,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:42,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778834385] [2023-11-29 03:16:42,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:42,729 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:42,729 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:42,729 INFO L85 PathProgramCache]: Analyzing trace with hash 17254343, now seen corresponding path program 1 times [2023-11-29 03:16:42,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:42,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687819117] [2023-11-29 03:16:42,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:42,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:42,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:42,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:42,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:42,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687819117] [2023-11-29 03:16:42,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687819117] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:42,788 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:42,789 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:42,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512525453] [2023-11-29 03:16:42,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:42,789 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:42,790 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:42,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:42,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:42,790 INFO L87 Difference]: Start difference. First operand 1488 states and 2188 transitions. cyclomatic complexity: 701 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:42,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:42,857 INFO L93 Difference]: Finished difference Result 1488 states and 2170 transitions. [2023-11-29 03:16:42,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2170 transitions. [2023-11-29 03:16:42,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:42,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2170 transitions. [2023-11-29 03:16:42,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-29 03:16:42,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-29 03:16:42,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2170 transitions. [2023-11-29 03:16:42,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:42,875 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-29 03:16:42,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2170 transitions. [2023-11-29 03:16:42,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1488. [2023-11-29 03:16:42,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1488 states, 1488 states have (on average 1.4583333333333333) internal successors, (2170), 1487 states have internal predecessors, (2170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:42,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2170 transitions. [2023-11-29 03:16:42,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-29 03:16:42,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:42,905 INFO L428 stractBuchiCegarLoop]: Abstraction has 1488 states and 2170 transitions. [2023-11-29 03:16:42,906 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 03:16:42,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2170 transitions. [2023-11-29 03:16:42,911 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1339 [2023-11-29 03:16:42,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:42,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:42,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:42,913 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:42,914 INFO L748 eck$LassoCheckResult]: Stem: 43575#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 43576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 44557#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44558#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44024#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 44025#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43897#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43790#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43519#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43167#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43168#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43212#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43213#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44155#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44156#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44200#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43616#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43617#L1090 assume !(0 == ~M_E~0); 43659#L1090-2 assume !(0 == ~T1_E~0); 43660#L1095-1 assume !(0 == ~T2_E~0); 44347#L1100-1 assume !(0 == ~T3_E~0); 44348#L1105-1 assume !(0 == ~T4_E~0); 43439#L1110-1 assume !(0 == ~T5_E~0); 43440#L1115-1 assume !(0 == ~T6_E~0); 43826#L1120-1 assume !(0 == ~T7_E~0); 44133#L1125-1 assume !(0 == ~T8_E~0); 44606#L1130-1 assume !(0 == ~T9_E~0); 44369#L1135-1 assume !(0 == ~T10_E~0); 43621#L1140-1 assume !(0 == ~T11_E~0); 43622#L1145-1 assume !(0 == ~E_1~0); 44303#L1150-1 assume !(0 == ~E_2~0); 43803#L1155-1 assume !(0 == ~E_3~0); 43804#L1160-1 assume !(0 == ~E_4~0); 43902#L1165-1 assume !(0 == ~E_5~0); 43903#L1170-1 assume !(0 == ~E_6~0); 44541#L1175-1 assume !(0 == ~E_7~0); 43982#L1180-1 assume !(0 == ~E_8~0); 43983#L1185-1 assume !(0 == ~E_9~0); 43618#L1190-1 assume !(0 == ~E_10~0); 43619#L1195-1 assume !(0 == ~E_11~0); 43998#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43818#L525 assume !(1 == ~m_pc~0); 43257#L525-2 is_master_triggered_~__retres1~0#1 := 0; 43258#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44443#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44416#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43608#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43609#L544 assume 1 == ~t1_pc~0; 43878#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43825#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43231#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43232#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 43463#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44102#L563 assume !(1 == ~t2_pc~0); 44289#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43276#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43277#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43687#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 43688#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44181#L582 assume 1 == ~t3_pc~0; 43407#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43408#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43159#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43160#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 43345#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43346#L601 assume !(1 == ~t4_pc~0); 44315#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43827#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43357#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43358#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 44310#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44582#L620 assume 1 == ~t5_pc~0; 43304#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43305#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44197#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44448#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 44591#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44592#L639 assume !(1 == ~t6_pc~0); 44131#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 43725#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43726#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43776#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 43833#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43834#L658 assume !(1 == ~t7_pc~0); 44047#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 44048#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44249#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 43611#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43612#L677 assume 1 == ~t8_pc~0; 43839#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43422#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43423#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43683#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 43684#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44410#L696 assume !(1 == ~t9_pc~0); 44114#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 44115#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43888#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43889#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44138#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44352#L715 assume 1 == ~t10_pc~0; 44359#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44231#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44036#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44037#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 43976#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43416#L734 assume !(1 == ~t11_pc~0); 43417#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 43904#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43985#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43155#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 43156#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44198#L1213 assume !(1 == ~M_E~0); 43973#L1213-2 assume !(1 == ~T1_E~0); 43974#L1218-1 assume !(1 == ~T2_E~0); 43190#L1223-1 assume !(1 == ~T3_E~0); 43191#L1228-1 assume !(1 == ~T4_E~0); 43949#L1233-1 assume !(1 == ~T5_E~0); 44593#L1238-1 assume !(1 == ~T6_E~0); 44308#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44309#L1248-1 assume !(1 == ~T8_E~0); 44355#L1253-1 assume !(1 == ~T9_E~0); 44356#L1258-1 assume !(1 == ~T10_E~0); 44331#L1263-1 assume !(1 == ~T11_E~0); 44332#L1268-1 assume !(1 == ~E_1~0); 44152#L1273-1 assume !(1 == ~E_2~0); 44153#L1278-1 assume !(1 == ~E_3~0); 43723#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43724#L1288-1 assume !(1 == ~E_5~0); 44454#L1293-1 assume !(1 == ~E_6~0); 44414#L1298-1 assume !(1 == ~E_7~0); 44185#L1303-1 assume !(1 == ~E_8~0); 43733#L1308-1 assume !(1 == ~E_9~0); 43625#L1313-1 assume !(1 == ~E_10~0); 43626#L1318-1 assume !(1 == ~E_11~0); 43633#L1323-1 assume { :end_inline_reset_delta_events } true; 43634#L1644-2 [2023-11-29 03:16:42,914 INFO L750 eck$LassoCheckResult]: Loop: 43634#L1644-2 assume !false; 44247#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43540#L1065-1 assume !false; 43541#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44589#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43272#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43849#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43738#L906 assume !(0 != eval_~tmp~0#1); 43740#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44058#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44059#L1090-3 assume !(0 == ~M_E~0); 44469#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44526#L1095-3 assume !(0 == ~T2_E~0); 44491#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44492#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43514#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43515#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43791#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43792#L1125-3 assume !(0 == ~T8_E~0); 44307#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44564#L1135-3 assume !(0 == ~T10_E~0); 43713#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43222#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43223#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43348#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43349#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43696#L1165-3 assume !(0 == ~E_5~0); 43697#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44095#L1175-3 assume !(0 == ~E_7~0); 43610#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43371#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43372#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44552#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44553#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43930#L525-36 assume !(1 == ~m_pc~0); 43931#L525-38 is_master_triggered_~__retres1~0#1 := 0; 43472#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43473#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43748#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43749#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43662#L544-36 assume !(1 == ~t1_pc~0); 43664#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 44219#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44220#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44559#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44539#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44444#L563-36 assume 1 == ~t2_pc~0; 43461#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43220#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43221#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44425#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43946#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43947#L582-36 assume 1 == ~t3_pc~0; 43780#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43781#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43879#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43880#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43984#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43924#L601-36 assume 1 == ~t4_pc~0; 43811#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43812#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44076#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44077#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44530#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44431#L620-36 assume 1 == ~t5_pc~0; 43864#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43865#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44292#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43838#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 43481#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43268#L639-36 assume 1 == ~t6_pc~0; 43269#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43309#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43310#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43531#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43532#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44136#L658-36 assume !(1 == ~t7_pc~0); 43281#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 43282#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44516#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43259#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43260#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44281#L677-36 assume !(1 == ~t8_pc~0); 44051#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 44052#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44182#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44183#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44078#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44079#L696-36 assume 1 == ~t9_pc~0; 43970#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43971#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43913#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43914#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44096#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44097#L715-36 assume 1 == ~t10_pc~0; 44242#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43157#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43158#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43135#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43136#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43524#L734-36 assume !(1 == ~t11_pc~0); 43236#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 43237#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43542#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43149#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43150#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44161#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43799#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43800#L1218-3 assume !(1 == ~T2_E~0); 43572#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43573#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43752#L1233-3 assume !(1 == ~T5_E~0); 43753#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44021#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44022#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44529#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44531#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43555#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43556#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44504#L1273-3 assume !(1 == ~E_2~0); 44519#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44521#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43900#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43901#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43746#L1298-3 assume !(1 == ~E_7~0); 43747#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44243#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43743#L1313-3 assume !(1 == ~E_10~0); 43744#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43557#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 43558#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43499#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43727#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 43728#L1663 assume !(0 == start_simulation_~tmp~3#1); 43390#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44134#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43343#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43226#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 43227#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43289#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43615#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 44080#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 43634#L1644-2 [2023-11-29 03:16:42,914 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:42,914 INFO L85 PathProgramCache]: Analyzing trace with hash -2032217409, now seen corresponding path program 1 times [2023-11-29 03:16:42,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:42,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627766482] [2023-11-29 03:16:42,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:42,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:42,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:43,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:43,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:43,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627766482] [2023-11-29 03:16:43,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627766482] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:43,007 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:43,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:16:43,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885836547] [2023-11-29 03:16:43,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:43,008 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:43,009 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:43,009 INFO L85 PathProgramCache]: Analyzing trace with hash -884328670, now seen corresponding path program 1 times [2023-11-29 03:16:43,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:43,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320804259] [2023-11-29 03:16:43,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:43,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:43,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:43,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:43,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:43,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320804259] [2023-11-29 03:16:43,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320804259] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:43,067 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:43,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:43,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137761329] [2023-11-29 03:16:43,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:43,068 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:43,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:43,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:16:43,068 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:16:43,069 INFO L87 Difference]: Start difference. First operand 1488 states and 2170 transitions. cyclomatic complexity: 683 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:43,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:43,443 INFO L93 Difference]: Finished difference Result 3985 states and 5734 transitions. [2023-11-29 03:16:43,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3985 states and 5734 transitions. [2023-11-29 03:16:43,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3653 [2023-11-29 03:16:43,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3985 states to 3985 states and 5734 transitions. [2023-11-29 03:16:43,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3985 [2023-11-29 03:16:43,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3985 [2023-11-29 03:16:43,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3985 states and 5734 transitions. [2023-11-29 03:16:43,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:43,480 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3985 states and 5734 transitions. [2023-11-29 03:16:43,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3985 states and 5734 transitions. [2023-11-29 03:16:43,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3985 to 1530. [2023-11-29 03:16:43,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1530 states, 1530 states have (on average 1.445751633986928) internal successors, (2212), 1529 states have internal predecessors, (2212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:43,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1530 states to 1530 states and 2212 transitions. [2023-11-29 03:16:43,527 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2023-11-29 03:16:43,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:16:43,531 INFO L428 stractBuchiCegarLoop]: Abstraction has 1530 states and 2212 transitions. [2023-11-29 03:16:43,531 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 03:16:43,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1530 states and 2212 transitions. [2023-11-29 03:16:43,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1378 [2023-11-29 03:16:43,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:43,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:43,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:43,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:43,539 INFO L748 eck$LassoCheckResult]: Stem: 49062#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 49063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 50070#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50071#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49517#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 49518#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49389#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49280#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49006#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48653#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48654#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48698#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48699#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49650#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49651#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49695#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49105#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49106#L1090 assume !(0 == ~M_E~0); 49148#L1090-2 assume !(0 == ~T1_E~0); 49149#L1095-1 assume !(0 == ~T2_E~0); 49846#L1100-1 assume !(0 == ~T3_E~0); 49847#L1105-1 assume !(0 == ~T4_E~0); 48925#L1110-1 assume !(0 == ~T5_E~0); 48926#L1115-1 assume !(0 == ~T6_E~0); 49316#L1120-1 assume !(0 == ~T7_E~0); 49628#L1125-1 assume !(0 == ~T8_E~0); 50129#L1130-1 assume !(0 == ~T9_E~0); 49869#L1135-1 assume !(0 == ~T10_E~0); 49110#L1140-1 assume !(0 == ~T11_E~0); 49111#L1145-1 assume !(0 == ~E_1~0); 49801#L1150-1 assume !(0 == ~E_2~0); 49293#L1155-1 assume !(0 == ~E_3~0); 49294#L1160-1 assume !(0 == ~E_4~0); 49394#L1165-1 assume !(0 == ~E_5~0); 49395#L1170-1 assume !(0 == ~E_6~0); 50053#L1175-1 assume !(0 == ~E_7~0); 49475#L1180-1 assume !(0 == ~E_8~0); 49476#L1185-1 assume !(0 == ~E_9~0); 49107#L1190-1 assume !(0 == ~E_10~0); 49108#L1195-1 assume !(0 == ~E_11~0); 49491#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49308#L525 assume !(1 == ~m_pc~0); 48743#L525-2 is_master_triggered_~__retres1~0#1 := 0; 48744#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50025#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49918#L1350 assume !(0 != activate_threads_~tmp~1#1); 49096#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49097#L544 assume 1 == ~t1_pc~0; 49368#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49315#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48717#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48718#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 48949#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49596#L563 assume !(1 == ~t2_pc~0); 49787#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48762#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49176#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 49177#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49676#L582 assume 1 == ~t3_pc~0; 48893#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48894#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48645#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48646#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 48831#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48832#L601 assume !(1 == ~t4_pc~0); 49813#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49317#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48841#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48842#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 49808#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50101#L620 assume 1 == ~t5_pc~0; 48790#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48791#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49692#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49952#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 50113#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50114#L639 assume !(1 == ~t6_pc~0); 49626#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49215#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49266#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 49323#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49324#L658 assume !(1 == ~t7_pc~0); 49540#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49541#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50119#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49746#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 49100#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49101#L677 assume 1 == ~t8_pc~0; 49329#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48908#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48909#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49172#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 49173#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49912#L696 assume !(1 == ~t9_pc~0); 49608#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 49609#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49378#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49379#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49633#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49851#L715 assume 1 == ~t10_pc~0; 49859#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49726#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49529#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49530#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 49469#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48902#L734 assume !(1 == ~t11_pc~0); 48903#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 49396#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49478#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48641#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 48642#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49693#L1213 assume !(1 == ~M_E~0); 49466#L1213-2 assume !(1 == ~T1_E~0); 49467#L1218-1 assume !(1 == ~T2_E~0); 48676#L1223-1 assume !(1 == ~T3_E~0); 48677#L1228-1 assume !(1 == ~T4_E~0); 49441#L1233-1 assume !(1 == ~T5_E~0); 50115#L1238-1 assume !(1 == ~T6_E~0); 49806#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49807#L1248-1 assume !(1 == ~T8_E~0); 49855#L1253-1 assume !(1 == ~T9_E~0); 49856#L1258-1 assume !(1 == ~T10_E~0); 49829#L1263-1 assume !(1 == ~T11_E~0); 49830#L1268-1 assume !(1 == ~E_1~0); 49647#L1273-1 assume !(1 == ~E_2~0); 49648#L1278-1 assume !(1 == ~E_3~0); 49213#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49214#L1288-1 assume !(1 == ~E_5~0); 49958#L1293-1 assume !(1 == ~E_6~0); 49916#L1298-1 assume !(1 == ~E_7~0); 49680#L1303-1 assume !(1 == ~E_8~0); 49223#L1308-1 assume !(1 == ~E_9~0); 49114#L1313-1 assume !(1 == ~E_10~0); 49115#L1318-1 assume !(1 == ~E_11~0); 49122#L1323-1 assume { :end_inline_reset_delta_events } true; 49123#L1644-2 [2023-11-29 03:16:43,540 INFO L750 eck$LassoCheckResult]: Loop: 49123#L1644-2 assume !false; 49744#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49027#L1065-1 assume !false; 49028#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 50111#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48758#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49339#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49228#L906 assume !(0 != eval_~tmp~0#1); 49230#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49551#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49552#L1090-3 assume !(0 == ~M_E~0); 49974#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50035#L1095-3 assume !(0 == ~T2_E~0); 49998#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49999#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49001#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49002#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49281#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49282#L1125-3 assume !(0 == ~T8_E~0); 49805#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50079#L1135-3 assume !(0 == ~T10_E~0); 49202#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48708#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48709#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48833#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48834#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49185#L1165-3 assume !(0 == ~E_5~0); 49186#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49589#L1175-3 assume !(0 == ~E_7~0); 49099#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48857#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 48858#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50064#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50065#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49422#L525-36 assume 1 == ~m_pc~0; 49424#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50067#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50074#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50075#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49239#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49151#L544-36 assume 1 == ~t1_pc~0; 49152#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49714#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49715#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50072#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50051#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49948#L563-36 assume 1 == ~t2_pc~0; 48947#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48706#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48707#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49927#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49438#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49439#L582-36 assume 1 == ~t3_pc~0; 49270#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49271#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49369#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49370#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49477#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49416#L601-36 assume 1 == ~t4_pc~0; 49301#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49302#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49569#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49570#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50040#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49934#L620-36 assume 1 == ~t5_pc~0; 49354#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49355#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49790#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49328#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 48968#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48754#L639-36 assume 1 == ~t6_pc~0; 48755#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48795#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48796#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49018#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49019#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49631#L658-36 assume !(1 == ~t7_pc~0); 48767#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 48768#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50024#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48745#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48746#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49779#L677-36 assume !(1 == ~t8_pc~0); 49544#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 49545#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49677#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49678#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49571#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49572#L696-36 assume 1 == ~t9_pc~0; 49463#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49464#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49405#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49406#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49590#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49591#L715-36 assume !(1 == ~t10_pc~0); 49553#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 48643#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48644#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48619#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48620#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49011#L734-36 assume !(1 == ~t11_pc~0); 48722#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 48723#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49029#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48635#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48636#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49656#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49289#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49290#L1218-3 assume !(1 == ~T2_E~0); 49059#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49060#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49242#L1233-3 assume !(1 == ~T5_E~0); 49243#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49514#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49515#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50039#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50041#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49042#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49043#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50011#L1273-3 assume !(1 == ~E_2~0); 50028#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50030#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49392#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49393#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49236#L1298-3 assume !(1 == ~E_7~0); 49237#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49739#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49233#L1313-3 assume !(1 == ~E_10~0); 49234#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49044#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49045#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48986#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49217#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 49218#L1663 assume !(0 == start_simulation_~tmp~3#1); 48883#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49629#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48829#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 48715#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 48716#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48778#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49104#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49574#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 49123#L1644-2 [2023-11-29 03:16:43,540 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:43,540 INFO L85 PathProgramCache]: Analyzing trace with hash -2060717699, now seen corresponding path program 1 times [2023-11-29 03:16:43,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:43,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907328743] [2023-11-29 03:16:43,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:43,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:43,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:43,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:43,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:43,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907328743] [2023-11-29 03:16:43,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1907328743] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:43,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:43,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:43,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283960674] [2023-11-29 03:16:43,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:43,590 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:43,590 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:43,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1434729917, now seen corresponding path program 1 times [2023-11-29 03:16:43,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:43,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241253282] [2023-11-29 03:16:43,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:43,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:43,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:43,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:43,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:43,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241253282] [2023-11-29 03:16:43,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241253282] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:43,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:43,634 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:43,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185225354] [2023-11-29 03:16:43,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:43,635 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:43,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:43,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:43,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:43,636 INFO L87 Difference]: Start difference. First operand 1530 states and 2212 transitions. cyclomatic complexity: 683 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:43,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:43,730 INFO L93 Difference]: Finished difference Result 2805 states and 4029 transitions. [2023-11-29 03:16:43,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2805 states and 4029 transitions. [2023-11-29 03:16:43,737 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2652 [2023-11-29 03:16:43,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2805 states to 2805 states and 4029 transitions. [2023-11-29 03:16:43,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2805 [2023-11-29 03:16:43,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2805 [2023-11-29 03:16:43,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2805 states and 4029 transitions. [2023-11-29 03:16:43,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:43,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2805 states and 4029 transitions. [2023-11-29 03:16:43,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2805 states and 4029 transitions. [2023-11-29 03:16:43,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2805 to 2803. [2023-11-29 03:16:43,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2803 states, 2803 states have (on average 1.4366749910809846) internal successors, (4027), 2802 states have internal predecessors, (4027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:43,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2803 states to 2803 states and 4027 transitions. [2023-11-29 03:16:43,819 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2803 states and 4027 transitions. [2023-11-29 03:16:43,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:43,819 INFO L428 stractBuchiCegarLoop]: Abstraction has 2803 states and 4027 transitions. [2023-11-29 03:16:43,819 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 03:16:43,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2803 states and 4027 transitions. [2023-11-29 03:16:43,825 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2650 [2023-11-29 03:16:43,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:43,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:43,827 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:43,827 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:43,828 INFO L748 eck$LassoCheckResult]: Stem: 53408#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 53409#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 54428#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54429#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53865#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 53866#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53736#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53627#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53349#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52995#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52996#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53040#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53041#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53999#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54000#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54044#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53450#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53451#L1090 assume !(0 == ~M_E~0); 53494#L1090-2 assume !(0 == ~T1_E~0); 53495#L1095-1 assume !(0 == ~T2_E~0); 54195#L1100-1 assume !(0 == ~T3_E~0); 54196#L1105-1 assume !(0 == ~T4_E~0); 53267#L1110-1 assume !(0 == ~T5_E~0); 53268#L1115-1 assume !(0 == ~T6_E~0); 53664#L1120-1 assume !(0 == ~T7_E~0); 53977#L1125-1 assume !(0 == ~T8_E~0); 54499#L1130-1 assume !(0 == ~T9_E~0); 54220#L1135-1 assume !(0 == ~T10_E~0); 53455#L1140-1 assume !(0 == ~T11_E~0); 53456#L1145-1 assume !(0 == ~E_1~0); 54149#L1150-1 assume !(0 == ~E_2~0); 53641#L1155-1 assume !(0 == ~E_3~0); 53642#L1160-1 assume !(0 == ~E_4~0); 53741#L1165-1 assume !(0 == ~E_5~0); 53742#L1170-1 assume !(0 == ~E_6~0); 54411#L1175-1 assume !(0 == ~E_7~0); 53823#L1180-1 assume !(0 == ~E_8~0); 53824#L1185-1 assume !(0 == ~E_9~0); 53452#L1190-1 assume !(0 == ~E_10~0); 53453#L1195-1 assume !(0 == ~E_11~0); 53839#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53656#L525 assume !(1 == ~m_pc~0); 53085#L525-2 is_master_triggered_~__retres1~0#1 := 0; 53086#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54301#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54273#L1350 assume !(0 != activate_threads_~tmp~1#1); 53442#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53443#L544 assume !(1 == ~t1_pc~0); 53662#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53663#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53060#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 53290#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53946#L563 assume !(1 == ~t2_pc~0); 54135#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53104#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53105#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53523#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 53524#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54025#L582 assume 1 == ~t3_pc~0; 53235#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53236#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52987#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52988#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 53173#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53174#L601 assume !(1 == ~t4_pc~0); 54162#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53665#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53183#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53184#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 54157#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54471#L620 assume 1 == ~t5_pc~0; 53132#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53133#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54041#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54307#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 54482#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54483#L639 assume !(1 == ~t6_pc~0); 53975#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53562#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53563#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53613#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 53670#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53671#L658 assume !(1 == ~t7_pc~0); 53889#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53890#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54488#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54093#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 53445#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53446#L677 assume 1 == ~t8_pc~0; 53677#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53250#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53251#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53519#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 53520#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54264#L696 assume !(1 == ~t9_pc~0); 53958#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 53959#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53726#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53727#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53982#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54200#L715 assume 1 == ~t10_pc~0; 54209#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54075#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53877#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53878#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 53816#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53244#L734 assume !(1 == ~t11_pc~0); 53245#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 53743#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53826#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52983#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 52984#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54042#L1213 assume !(1 == ~M_E~0); 53813#L1213-2 assume !(1 == ~T1_E~0); 53814#L1218-1 assume !(1 == ~T2_E~0); 53018#L1223-1 assume !(1 == ~T3_E~0); 53019#L1228-1 assume !(1 == ~T4_E~0); 53789#L1233-1 assume !(1 == ~T5_E~0); 54484#L1238-1 assume !(1 == ~T6_E~0); 54155#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54156#L1248-1 assume !(1 == ~T8_E~0); 54205#L1253-1 assume !(1 == ~T9_E~0); 54206#L1258-1 assume !(1 == ~T10_E~0); 54178#L1263-1 assume !(1 == ~T11_E~0); 54179#L1268-1 assume !(1 == ~E_1~0); 53996#L1273-1 assume !(1 == ~E_2~0); 53997#L1278-1 assume !(1 == ~E_3~0); 53560#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 53561#L1288-1 assume !(1 == ~E_5~0); 54315#L1293-1 assume !(1 == ~E_6~0); 54268#L1298-1 assume !(1 == ~E_7~0); 54029#L1303-1 assume !(1 == ~E_8~0); 53570#L1308-1 assume !(1 == ~E_9~0); 53459#L1313-1 assume !(1 == ~E_10~0); 53460#L1318-1 assume !(1 == ~E_11~0); 53467#L1323-1 assume { :end_inline_reset_delta_events } true; 53468#L1644-2 [2023-11-29 03:16:43,828 INFO L750 eck$LassoCheckResult]: Loop: 53468#L1644-2 assume !false; 54091#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53386#L1065-1 assume !false; 54975#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54823#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54809#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54806#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54803#L906 assume !(0 != eval_~tmp~0#1); 54804#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55665#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55664#L1090-3 assume !(0 == ~M_E~0); 55663#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55662#L1095-3 assume !(0 == ~T2_E~0); 55661#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55660#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55659#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55658#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55657#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55656#L1125-3 assume !(0 == ~T8_E~0); 55655#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55654#L1135-3 assume !(0 == ~T10_E~0); 55653#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55652#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55651#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55650#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55557#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55509#L1165-3 assume !(0 == ~E_5~0); 55508#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55507#L1175-3 assume !(0 == ~E_7~0); 55506#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 55505#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55504#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55503#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55500#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55499#L525-36 assume !(1 == ~m_pc~0); 55497#L525-38 is_master_triggered_~__retres1~0#1 := 0; 55495#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55493#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55492#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 53938#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53499#L544-36 assume !(1 == ~t1_pc~0); 53500#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 55598#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55597#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55596#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55595#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55594#L563-36 assume !(1 == ~t2_pc~0); 55592#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 55591#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55590#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55589#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55588#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55587#L582-36 assume 1 == ~t3_pc~0; 55585#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55584#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55583#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55582#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55581#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55580#L601-36 assume !(1 == ~t4_pc~0); 55578#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 55577#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55576#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55575#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55574#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55573#L620-36 assume 1 == ~t5_pc~0; 55571#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55570#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55569#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55568#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 55567#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53096#L639-36 assume 1 == ~t6_pc~0; 53097#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53137#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53138#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53361#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53362#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53980#L658-36 assume !(1 == ~t7_pc~0); 53109#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 53110#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54379#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53087#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53088#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54127#L677-36 assume !(1 == ~t8_pc~0); 53893#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 53894#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54026#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54027#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53920#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53921#L696-36 assume 1 == ~t9_pc~0; 53810#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53811#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53753#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53754#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53940#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53941#L715-36 assume 1 == ~t10_pc~0; 54086#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52985#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52986#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52961#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52962#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53356#L734-36 assume !(1 == ~t11_pc~0); 53064#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 53065#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53374#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52977#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52978#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54005#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53637#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53638#L1218-3 assume !(1 == ~T2_E~0); 53405#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53406#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53589#L1233-3 assume !(1 == ~T5_E~0); 53590#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53862#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53863#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54396#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54398#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53388#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53389#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54366#L1273-3 assume !(1 == ~E_2~0); 54384#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54386#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53739#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53740#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53583#L1298-3 assume !(1 == ~E_7~0); 53584#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54087#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53580#L1313-3 assume !(1 == ~E_10~0); 53581#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53390#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 53391#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 53328#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 53564#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 53565#L1663 assume !(0 == start_simulation_~tmp~3#1); 54516#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55524#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 55514#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 53057#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 53058#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53120#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53449#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 53923#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 53468#L1644-2 [2023-11-29 03:16:43,828 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:43,828 INFO L85 PathProgramCache]: Analyzing trace with hash -2098164388, now seen corresponding path program 1 times [2023-11-29 03:16:43,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:43,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099169177] [2023-11-29 03:16:43,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:43,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:43,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:43,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:43,874 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:43,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099169177] [2023-11-29 03:16:43,874 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099169177] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:43,875 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:43,875 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:43,875 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42793099] [2023-11-29 03:16:43,875 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:43,875 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:43,876 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:43,876 INFO L85 PathProgramCache]: Analyzing trace with hash 405655710, now seen corresponding path program 1 times [2023-11-29 03:16:43,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:43,876 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648558081] [2023-11-29 03:16:43,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:43,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:43,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:43,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:43,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:43,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648558081] [2023-11-29 03:16:43,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648558081] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:43,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:43,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:43,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693169878] [2023-11-29 03:16:43,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:43,915 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:43,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:43,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:43,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:43,916 INFO L87 Difference]: Start difference. First operand 2803 states and 4027 transitions. cyclomatic complexity: 1226 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:44,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:44,009 INFO L93 Difference]: Finished difference Result 5250 states and 7502 transitions. [2023-11-29 03:16:44,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5250 states and 7502 transitions. [2023-11-29 03:16:44,027 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5094 [2023-11-29 03:16:44,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5250 states to 5250 states and 7502 transitions. [2023-11-29 03:16:44,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5250 [2023-11-29 03:16:44,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5250 [2023-11-29 03:16:44,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5250 states and 7502 transitions. [2023-11-29 03:16:44,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:44,048 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5250 states and 7502 transitions. [2023-11-29 03:16:44,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5250 states and 7502 transitions. [2023-11-29 03:16:44,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5250 to 5246. [2023-11-29 03:16:44,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5246 states, 5246 states have (on average 1.4292794510102935) internal successors, (7498), 5245 states have internal predecessors, (7498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:44,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5246 states to 5246 states and 7498 transitions. [2023-11-29 03:16:44,114 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5246 states and 7498 transitions. [2023-11-29 03:16:44,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:44,115 INFO L428 stractBuchiCegarLoop]: Abstraction has 5246 states and 7498 transitions. [2023-11-29 03:16:44,115 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 03:16:44,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5246 states and 7498 transitions. [2023-11-29 03:16:44,125 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5090 [2023-11-29 03:16:44,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:44,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:44,127 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:44,127 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:44,127 INFO L748 eck$LassoCheckResult]: Stem: 61463#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 61464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 62497#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62498#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61917#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 61918#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61786#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61680#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61406#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61055#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 61056#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 61100#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61101#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62057#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62058#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62106#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 61504#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61505#L1090 assume !(0 == ~M_E~0); 61549#L1090-2 assume !(0 == ~T1_E~0); 61550#L1095-1 assume !(0 == ~T2_E~0); 62257#L1100-1 assume !(0 == ~T3_E~0); 62258#L1105-1 assume !(0 == ~T4_E~0); 61326#L1110-1 assume !(0 == ~T5_E~0); 61327#L1115-1 assume !(0 == ~T6_E~0); 61716#L1120-1 assume !(0 == ~T7_E~0); 62031#L1125-1 assume !(0 == ~T8_E~0); 62577#L1130-1 assume !(0 == ~T9_E~0); 62281#L1135-1 assume !(0 == ~T10_E~0); 61509#L1140-1 assume !(0 == ~T11_E~0); 61510#L1145-1 assume !(0 == ~E_1~0); 62211#L1150-1 assume !(0 == ~E_2~0); 61693#L1155-1 assume !(0 == ~E_3~0); 61694#L1160-1 assume !(0 == ~E_4~0); 61791#L1165-1 assume !(0 == ~E_5~0); 61792#L1170-1 assume !(0 == ~E_6~0); 62478#L1175-1 assume !(0 == ~E_7~0); 61874#L1180-1 assume !(0 == ~E_8~0); 61875#L1185-1 assume !(0 == ~E_9~0); 61506#L1190-1 assume !(0 == ~E_10~0); 61507#L1195-1 assume !(0 == ~E_11~0); 61890#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61713#L525 assume !(1 == ~m_pc~0); 61145#L525-2 is_master_triggered_~__retres1~0#1 := 0; 61146#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62364#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62336#L1350 assume !(0 != activate_threads_~tmp~1#1); 61496#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61497#L544 assume !(1 == ~t1_pc~0); 61714#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61715#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61125#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 61348#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61999#L563 assume !(1 == ~t2_pc~0); 62198#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61164#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61165#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61579#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 61580#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62081#L582 assume !(1 == ~t3_pc~0); 62210#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62544#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61047#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61048#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 61233#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61234#L601 assume !(1 == ~t4_pc~0); 62223#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61717#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61247#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61248#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 62218#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62537#L620 assume 1 == ~t5_pc~0; 61196#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61197#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62097#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62370#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 62555#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62556#L639 assume !(1 == ~t6_pc~0); 62029#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 61617#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61618#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61666#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 61722#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61723#L658 assume !(1 == ~t7_pc~0); 61941#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 61942#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62561#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62154#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 61499#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61500#L677 assume 1 == ~t8_pc~0; 61730#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61311#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61312#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61571#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 61572#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62327#L696 assume !(1 == ~t9_pc~0); 62013#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 62014#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61776#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61777#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62039#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62261#L715 assume 1 == ~t10_pc~0; 62271#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 62131#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61929#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61930#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 61867#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61302#L734 assume !(1 == ~t11_pc~0); 61303#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 61793#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61879#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61045#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 61046#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62098#L1213 assume !(1 == ~M_E~0); 61865#L1213-2 assume !(1 == ~T1_E~0); 61866#L1218-1 assume !(1 == ~T2_E~0); 61078#L1223-1 assume !(1 == ~T3_E~0); 61079#L1228-1 assume !(1 == ~T4_E~0); 61840#L1233-1 assume !(1 == ~T5_E~0); 62557#L1238-1 assume !(1 == ~T6_E~0); 62216#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62217#L1248-1 assume !(1 == ~T8_E~0); 62267#L1253-1 assume !(1 == ~T9_E~0); 62268#L1258-1 assume !(1 == ~T10_E~0); 62240#L1263-1 assume !(1 == ~T11_E~0); 62241#L1268-1 assume !(1 == ~E_1~0); 62052#L1273-1 assume !(1 == ~E_2~0); 62053#L1278-1 assume !(1 == ~E_3~0); 61613#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 61614#L1288-1 assume !(1 == ~E_5~0); 62377#L1293-1 assume !(1 == ~E_6~0); 62332#L1298-1 assume !(1 == ~E_7~0); 62085#L1303-1 assume !(1 == ~E_8~0); 61623#L1308-1 assume !(1 == ~E_9~0); 61513#L1313-1 assume !(1 == ~E_10~0); 61514#L1318-1 assume !(1 == ~E_11~0); 61524#L1323-1 assume { :end_inline_reset_delta_events } true; 61525#L1644-2 [2023-11-29 03:16:44,128 INFO L750 eck$LassoCheckResult]: Loop: 61525#L1644-2 assume !false; 63767#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63762#L1065-1 assume !false; 63760#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 63753#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 63742#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 63740#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 63738#L906 assume !(0 != eval_~tmp~0#1); 62306#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61952#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61953#L1090-3 assume !(0 == ~M_E~0); 62394#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62452#L1095-3 assume !(0 == ~T2_E~0); 62418#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62419#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61400#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61401#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61681#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61682#L1125-3 assume !(0 == ~T8_E~0); 62215#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62505#L1135-3 assume !(0 == ~T10_E~0); 61602#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 61110#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61111#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61235#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61236#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61585#L1165-3 assume !(0 == ~E_5~0); 61586#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61992#L1175-3 assume !(0 == ~E_7~0); 61498#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61261#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 61262#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62489#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62490#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61818#L525-36 assume !(1 == ~m_pc~0); 61819#L525-38 is_master_triggered_~__retres1~0#1 := 0; 61357#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61358#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61638#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 61639#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61547#L544-36 assume !(1 == ~t1_pc~0); 61548#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 62119#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62120#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62496#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62475#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62365#L563-36 assume 1 == ~t2_pc~0; 61346#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61108#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61109#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62345#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61837#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61838#L582-36 assume !(1 == ~t3_pc~0); 62383#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 61916#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61767#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61768#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61876#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61813#L601-36 assume 1 == ~t4_pc~0; 61814#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 66155#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66154#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66153#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66152#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66151#L620-36 assume 1 == ~t5_pc~0; 66149#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66148#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66147#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66146#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 66145#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66144#L639-36 assume !(1 == ~t6_pc~0); 66143#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 66141#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66140#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66139#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66138#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66137#L658-36 assume !(1 == ~t7_pc~0); 66135#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 66134#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66133#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66132#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66131#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66130#L677-36 assume !(1 == ~t8_pc~0); 66129#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 66127#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66126#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66125#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66124#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66123#L696-36 assume !(1 == ~t9_pc~0); 66121#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 66120#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66119#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66118#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66117#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66116#L715-36 assume !(1 == ~t10_pc~0); 66115#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 66113#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66112#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66111#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66110#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66109#L734-36 assume !(1 == ~t11_pc~0); 66107#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 66106#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66105#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66104#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66103#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62491#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61687#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61688#L1218-3 assume !(1 == ~T2_E~0); 61460#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61461#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61642#L1233-3 assume !(1 == ~T5_E~0); 61643#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61913#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61914#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62459#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62461#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61441#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61442#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62430#L1273-3 assume !(1 == ~E_2~0); 62445#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62447#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61789#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61790#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61636#L1298-3 assume !(1 == ~E_7~0); 61637#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62145#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 61633#L1313-3 assume !(1 == ~E_10~0); 61634#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61443#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 61444#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 61384#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 61615#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 61616#L1663 assume !(0 == start_simulation_~tmp~3#1); 61286#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 62574#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 63780#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 63778#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 63776#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63774#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63772#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 63770#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 61525#L1644-2 [2023-11-29 03:16:44,128 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:44,128 INFO L85 PathProgramCache]: Analyzing trace with hash 919650235, now seen corresponding path program 1 times [2023-11-29 03:16:44,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:44,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806448842] [2023-11-29 03:16:44,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:44,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:44,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:44,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:44,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:44,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806448842] [2023-11-29 03:16:44,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806448842] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:44,174 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:44,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:44,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994476154] [2023-11-29 03:16:44,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:44,175 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:44,175 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:44,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1517739100, now seen corresponding path program 1 times [2023-11-29 03:16:44,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:44,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239679374] [2023-11-29 03:16:44,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:44,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:44,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:44,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:44,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:44,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239679374] [2023-11-29 03:16:44,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239679374] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:44,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:44,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:44,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588129075] [2023-11-29 03:16:44,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:44,252 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:44,253 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:44,253 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:44,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:44,253 INFO L87 Difference]: Start difference. First operand 5246 states and 7498 transitions. cyclomatic complexity: 2256 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:44,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:44,379 INFO L93 Difference]: Finished difference Result 9941 states and 14145 transitions. [2023-11-29 03:16:44,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9941 states and 14145 transitions. [2023-11-29 03:16:44,414 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9772 [2023-11-29 03:16:44,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9941 states to 9941 states and 14145 transitions. [2023-11-29 03:16:44,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9941 [2023-11-29 03:16:44,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9941 [2023-11-29 03:16:44,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9941 states and 14145 transitions. [2023-11-29 03:16:44,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:44,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9941 states and 14145 transitions. [2023-11-29 03:16:44,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9941 states and 14145 transitions. [2023-11-29 03:16:44,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9941 to 9933. [2023-11-29 03:16:44,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9933 states, 9933 states have (on average 1.4232356790496326) internal successors, (14137), 9932 states have internal predecessors, (14137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:44,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9933 states to 9933 states and 14137 transitions. [2023-11-29 03:16:44,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9933 states and 14137 transitions. [2023-11-29 03:16:44,561 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:44,561 INFO L428 stractBuchiCegarLoop]: Abstraction has 9933 states and 14137 transitions. [2023-11-29 03:16:44,561 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 03:16:44,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9933 states and 14137 transitions. [2023-11-29 03:16:44,581 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9764 [2023-11-29 03:16:44,581 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:44,581 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:44,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:44,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:44,583 INFO L748 eck$LassoCheckResult]: Stem: 76655#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 76656#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 77733#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77734#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77122#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 77123#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76990#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76878#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76596#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76249#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76250#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76294#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76295#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77265#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77266#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77315#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76699#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76700#L1090 assume !(0 == ~M_E~0); 76745#L1090-2 assume !(0 == ~T1_E~0); 76746#L1095-1 assume !(0 == ~T2_E~0); 77480#L1100-1 assume !(0 == ~T3_E~0); 77481#L1105-1 assume !(0 == ~T4_E~0); 76515#L1110-1 assume !(0 == ~T5_E~0); 76516#L1115-1 assume !(0 == ~T6_E~0); 76915#L1120-1 assume !(0 == ~T7_E~0); 77238#L1125-1 assume !(0 == ~T8_E~0); 77835#L1130-1 assume !(0 == ~T9_E~0); 77508#L1135-1 assume !(0 == ~T10_E~0); 76706#L1140-1 assume !(0 == ~T11_E~0); 76707#L1145-1 assume !(0 == ~E_1~0); 77431#L1150-1 assume !(0 == ~E_2~0); 76891#L1155-1 assume !(0 == ~E_3~0); 76892#L1160-1 assume !(0 == ~E_4~0); 76995#L1165-1 assume !(0 == ~E_5~0); 76996#L1170-1 assume !(0 == ~E_6~0); 77715#L1175-1 assume !(0 == ~E_7~0); 77078#L1180-1 assume !(0 == ~E_8~0); 77079#L1185-1 assume !(0 == ~E_9~0); 76701#L1190-1 assume !(0 == ~E_10~0); 76702#L1195-1 assume !(0 == ~E_11~0); 77094#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76907#L525 assume !(1 == ~m_pc~0); 76337#L525-2 is_master_triggered_~__retres1~0#1 := 0; 76338#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77598#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 77566#L1350 assume !(0 != activate_threads_~tmp~1#1); 76691#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76692#L544 assume !(1 == ~t1_pc~0); 76913#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76914#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76312#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76313#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 76539#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77205#L563 assume !(1 == ~t2_pc~0); 77415#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76359#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76360#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76772#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 76773#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77295#L582 assume !(1 == ~t3_pc~0); 77430#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77790#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76241#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76242#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 76424#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76425#L601 assume !(1 == ~t4_pc~0); 77445#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76916#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76434#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76435#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 77438#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77785#L620 assume !(1 == ~t5_pc~0); 77254#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77255#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77312#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77607#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 77800#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77801#L639 assume !(1 == ~t6_pc~0); 77236#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76811#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76812#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76863#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 76922#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76923#L658 assume !(1 == ~t7_pc~0); 77147#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 77148#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77808#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77367#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 76694#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76695#L677 assume 1 == ~t8_pc~0; 76929#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76498#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76499#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76768#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 76769#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77556#L696 assume !(1 == ~t9_pc~0); 77218#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 77219#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76978#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76979#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77243#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77486#L715 assume 1 == ~t10_pc~0; 77496#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77348#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77136#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77137#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 77071#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76492#L734 assume !(1 == ~t11_pc~0); 76493#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 76997#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77081#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76237#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 76238#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77313#L1213 assume !(1 == ~M_E~0); 77068#L1213-2 assume !(1 == ~T1_E~0); 77069#L1218-1 assume !(1 == ~T2_E~0); 76272#L1223-1 assume !(1 == ~T3_E~0); 76273#L1228-1 assume !(1 == ~T4_E~0); 77045#L1233-1 assume !(1 == ~T5_E~0); 77802#L1238-1 assume !(1 == ~T6_E~0); 77436#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77437#L1248-1 assume !(1 == ~T8_E~0); 77492#L1253-1 assume !(1 == ~T9_E~0); 77493#L1258-1 assume !(1 == ~T10_E~0); 77463#L1263-1 assume !(1 == ~T11_E~0); 77464#L1268-1 assume !(1 == ~E_1~0); 77262#L1273-1 assume !(1 == ~E_2~0); 77263#L1278-1 assume !(1 == ~E_3~0); 76809#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 76810#L1288-1 assume !(1 == ~E_5~0); 77614#L1293-1 assume !(1 == ~E_6~0); 77561#L1298-1 assume !(1 == ~E_7~0); 77299#L1303-1 assume !(1 == ~E_8~0); 76819#L1308-1 assume !(1 == ~E_9~0); 76710#L1313-1 assume !(1 == ~E_10~0); 76711#L1318-1 assume !(1 == ~E_11~0); 76718#L1323-1 assume { :end_inline_reset_delta_events } true; 76719#L1644-2 [2023-11-29 03:16:44,583 INFO L750 eck$LassoCheckResult]: Loop: 76719#L1644-2 assume !false; 77365#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76618#L1065-1 assume !false; 76619#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77798#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76352#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76940#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 76824#L906 assume !(0 != eval_~tmp~0#1); 76826#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77159#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77160#L1090-3 assume !(0 == ~M_E~0); 77638#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77697#L1095-3 assume !(0 == ~T2_E~0); 77661#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77662#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76591#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76592#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76879#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76880#L1125-3 assume !(0 == ~T8_E~0); 77435#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77743#L1135-3 assume !(0 == ~T10_E~0); 76798#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76303#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76304#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76426#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76427#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76781#L1165-3 assume !(0 == ~E_5~0); 76782#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77198#L1175-3 assume !(0 == ~E_7~0); 76693#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 76450#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76451#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77727#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77728#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77876#L525-36 assume !(1 == ~m_pc~0); 85962#L525-38 is_master_triggered_~__retres1~0#1 := 0; 76548#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76549#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76834#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 76835#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76750#L544-36 assume !(1 == ~t1_pc~0); 76751#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 77335#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77336#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77735#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77713#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77601#L563-36 assume 1 == ~t2_pc~0; 77603#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86122#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86121#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 86119#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86117#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86115#L582-36 assume !(1 == ~t3_pc~0); 86113#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 86110#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86108#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86106#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86104#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86102#L601-36 assume 1 == ~t4_pc~0; 86099#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86096#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86094#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86092#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86075#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86074#L620-36 assume !(1 == ~t5_pc~0); 86072#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 86071#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86061#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86059#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 86057#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86054#L639-36 assume 1 == ~t6_pc~0; 86051#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86049#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86047#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86045#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86043#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86040#L658-36 assume !(1 == ~t7_pc~0); 86037#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 86036#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86012#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86011#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86010#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86009#L677-36 assume !(1 == ~t8_pc~0); 85981#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 85978#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85974#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85971#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85968#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85966#L696-36 assume !(1 == ~t9_pc~0); 85963#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 85961#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85960#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85959#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85957#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85954#L715-36 assume !(1 == ~t10_pc~0); 85952#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 85949#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85948#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85947#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85946#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85945#L734-36 assume !(1 == ~t11_pc~0); 76317#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 76318#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76620#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76231#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76232#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77271#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76887#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76888#L1218-3 assume !(1 == ~T2_E~0); 85858#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85857#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85856#L1233-3 assume !(1 == ~T5_E~0); 85855#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85854#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 85853#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 85852#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 85851#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 85850#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85557#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 85556#L1273-3 assume !(1 == ~E_2~0); 85555#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85554#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85553#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85552#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85551#L1298-3 assume !(1 == ~E_7~0); 85550#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85549#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 85548#L1313-3 assume !(1 == ~E_10~0); 85547#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85546#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77868#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76575#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76813#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 76814#L1663 assume !(0 == start_simulation_~tmp~3#1); 76476#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77239#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76422#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76310#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 76311#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76374#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76698#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 77182#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 76719#L1644-2 [2023-11-29 03:16:44,584 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:44,584 INFO L85 PathProgramCache]: Analyzing trace with hash -258324326, now seen corresponding path program 1 times [2023-11-29 03:16:44,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:44,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408574335] [2023-11-29 03:16:44,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:44,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:44,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:44,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:44,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:44,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408574335] [2023-11-29 03:16:44,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408574335] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:44,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:44,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:44,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466545872] [2023-11-29 03:16:44,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:44,629 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:44,629 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:44,629 INFO L85 PathProgramCache]: Analyzing trace with hash 726001948, now seen corresponding path program 1 times [2023-11-29 03:16:44,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:44,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405545262] [2023-11-29 03:16:44,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:44,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:44,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:44,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:44,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:44,669 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405545262] [2023-11-29 03:16:44,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405545262] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:44,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:44,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:44,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305087885] [2023-11-29 03:16:44,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:44,670 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:44,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:44,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:44,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:44,671 INFO L87 Difference]: Start difference. First operand 9933 states and 14137 transitions. cyclomatic complexity: 4212 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:44,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:44,853 INFO L93 Difference]: Finished difference Result 18924 states and 26826 transitions. [2023-11-29 03:16:44,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18924 states and 26826 transitions. [2023-11-29 03:16:44,904 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18720 [2023-11-29 03:16:44,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18924 states to 18924 states and 26826 transitions. [2023-11-29 03:16:44,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18924 [2023-11-29 03:16:44,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18924 [2023-11-29 03:16:44,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18924 states and 26826 transitions. [2023-11-29 03:16:44,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:44,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18924 states and 26826 transitions. [2023-11-29 03:16:44,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18924 states and 26826 transitions. [2023-11-29 03:16:45,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18924 to 18908. [2023-11-29 03:16:45,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18908 states, 18908 states have (on average 1.4179183414427756) internal successors, (26810), 18907 states have internal predecessors, (26810), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:45,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18908 states to 18908 states and 26810 transitions. [2023-11-29 03:16:45,174 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18908 states and 26810 transitions. [2023-11-29 03:16:45,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:45,174 INFO L428 stractBuchiCegarLoop]: Abstraction has 18908 states and 26810 transitions. [2023-11-29 03:16:45,175 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 03:16:45,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18908 states and 26810 transitions. [2023-11-29 03:16:45,223 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18704 [2023-11-29 03:16:45,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:45,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:45,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:45,272 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:45,272 INFO L748 eck$LassoCheckResult]: Stem: 105517#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 105518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 106576#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106577#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105971#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 105972#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105843#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105736#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105461#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105113#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105114#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 105158#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 105159#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 106117#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 106118#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 106162#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 105559#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105560#L1090 assume !(0 == ~M_E~0); 105604#L1090-2 assume !(0 == ~T1_E~0); 105605#L1095-1 assume !(0 == ~T2_E~0); 106322#L1100-1 assume !(0 == ~T3_E~0); 106323#L1105-1 assume !(0 == ~T4_E~0); 105381#L1110-1 assume !(0 == ~T5_E~0); 105382#L1115-1 assume !(0 == ~T6_E~0); 105774#L1120-1 assume !(0 == ~T7_E~0); 106091#L1125-1 assume !(0 == ~T8_E~0); 106670#L1130-1 assume !(0 == ~T9_E~0); 106343#L1135-1 assume !(0 == ~T10_E~0); 105565#L1140-1 assume !(0 == ~T11_E~0); 105566#L1145-1 assume !(0 == ~E_1~0); 106274#L1150-1 assume !(0 == ~E_2~0); 105750#L1155-1 assume !(0 == ~E_3~0); 105751#L1160-1 assume !(0 == ~E_4~0); 105848#L1165-1 assume !(0 == ~E_5~0); 105849#L1170-1 assume !(0 == ~E_6~0); 106556#L1175-1 assume !(0 == ~E_7~0); 105930#L1180-1 assume !(0 == ~E_8~0); 105931#L1185-1 assume !(0 == ~E_9~0); 105561#L1190-1 assume !(0 == ~E_10~0); 105562#L1195-1 assume !(0 == ~E_11~0); 105946#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105771#L525 assume !(1 == ~m_pc~0); 105202#L525-2 is_master_triggered_~__retres1~0#1 := 0; 105203#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106433#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106404#L1350 assume !(0 != activate_threads_~tmp~1#1); 105551#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105552#L544 assume !(1 == ~t1_pc~0); 105772#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105773#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105181#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 105182#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 105404#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106058#L563 assume !(1 == ~t2_pc~0); 106258#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105224#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 105633#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 105634#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106143#L582 assume !(1 == ~t3_pc~0); 106273#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 106630#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105105#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 105106#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 105289#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105290#L601 assume !(1 == ~t4_pc~0); 106288#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105775#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105303#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 105304#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 106283#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106619#L620 assume !(1 == ~t5_pc~0); 106107#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 106108#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106159#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 106441#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 106639#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106640#L639 assume !(1 == ~t6_pc~0); 106089#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 105674#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105675#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 105723#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 105780#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 105781#L658 assume !(1 == ~t7_pc~0); 105997#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 105998#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 106648#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106217#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 105554#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 105555#L677 assume !(1 == ~t8_pc~0); 105578#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 105363#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 105364#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 105629#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 105630#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106392#L696 assume !(1 == ~t9_pc~0); 106073#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 106074#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 105833#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 105834#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 106096#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 106326#L715 assume 1 == ~t10_pc~0; 106333#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 106193#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 105985#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 105986#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 105923#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 105357#L734 assume !(1 == ~t11_pc~0); 105358#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 105850#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 105933#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 105103#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 105104#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106160#L1213 assume !(1 == ~M_E~0); 105921#L1213-2 assume !(1 == ~T1_E~0); 105922#L1218-1 assume !(1 == ~T2_E~0); 105136#L1223-1 assume !(1 == ~T3_E~0); 105137#L1228-1 assume !(1 == ~T4_E~0); 105897#L1233-1 assume !(1 == ~T5_E~0); 106641#L1238-1 assume !(1 == ~T6_E~0); 106281#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 106282#L1248-1 assume !(1 == ~T8_E~0); 106329#L1253-1 assume !(1 == ~T9_E~0); 106330#L1258-1 assume !(1 == ~T10_E~0); 106305#L1263-1 assume !(1 == ~T11_E~0); 106306#L1268-1 assume !(1 == ~E_1~0); 106114#L1273-1 assume !(1 == ~E_2~0); 106115#L1278-1 assume !(1 == ~E_3~0); 105670#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 105671#L1288-1 assume !(1 == ~E_5~0); 106448#L1293-1 assume !(1 == ~E_6~0); 106397#L1298-1 assume !(1 == ~E_7~0); 106147#L1303-1 assume !(1 == ~E_8~0); 105680#L1308-1 assume !(1 == ~E_9~0); 105569#L1313-1 assume !(1 == ~E_10~0); 105570#L1318-1 assume !(1 == ~E_11~0); 105579#L1323-1 assume { :end_inline_reset_delta_events } true; 105580#L1644-2 [2023-11-29 03:16:45,273 INFO L750 eck$LassoCheckResult]: Loop: 105580#L1644-2 assume !false; 106213#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105483#L1065-1 assume !false; 105484#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 106637#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 105217#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 105796#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105685#L906 assume !(0 != eval_~tmp~0#1); 105687#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123146#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123145#L1090-3 assume !(0 == ~M_E~0); 123144#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 123143#L1095-3 assume !(0 == ~T2_E~0); 123142#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123141#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123140#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123139#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 123138#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 123137#L1125-3 assume !(0 == ~T8_E~0); 123136#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 123135#L1135-3 assume !(0 == ~T10_E~0); 123134#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 123133#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 123132#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123131#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123130#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 123129#L1165-3 assume !(0 == ~E_5~0); 123128#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123127#L1175-3 assume !(0 == ~E_7~0); 123126#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 123125#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 123124#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 123123#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 123122#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123121#L525-36 assume 1 == ~m_pc~0; 123120#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 123118#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123116#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123113#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123112#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123111#L544-36 assume !(1 == ~t1_pc~0); 123110#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 123109#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123108#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123107#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123106#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123105#L563-36 assume 1 == ~t2_pc~0; 123103#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 123101#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123100#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123099#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123095#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123093#L582-36 assume !(1 == ~t3_pc~0); 123091#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 123089#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123086#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123084#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123082#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123080#L601-36 assume !(1 == ~t4_pc~0); 123077#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 123075#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123073#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123071#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 123069#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123066#L620-36 assume !(1 == ~t5_pc~0); 123064#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 123062#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123060#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123058#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 123056#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123054#L639-36 assume 1 == ~t6_pc~0; 123051#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 123049#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123047#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 123045#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 123043#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 123040#L658-36 assume !(1 == ~t7_pc~0); 123037#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 123035#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123033#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 123031#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 123029#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 123027#L677-36 assume !(1 == ~t8_pc~0); 123025#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 123023#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 123021#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 123019#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 123017#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123014#L696-36 assume !(1 == ~t9_pc~0); 123011#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 123009#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123007#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123005#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 123002#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 123000#L715-36 assume 1 == ~t10_pc~0; 122997#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 122995#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 122993#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 122991#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 122989#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 122987#L734-36 assume 1 == ~t11_pc~0; 122985#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 122982#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 122980#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122978#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 122976#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122973#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 122971#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 122969#L1218-3 assume !(1 == ~T2_E~0); 122967#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122965#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 122963#L1233-3 assume !(1 == ~T5_E~0); 122960#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 122958#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 122956#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 122954#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 122952#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 122950#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 122949#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 122946#L1273-3 assume !(1 == ~E_2~0); 122944#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 122942#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 122940#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 122938#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 122936#L1298-3 assume !(1 == ~E_7~0); 122934#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 122932#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 122930#L1313-3 assume !(1 == ~E_10~0); 122928#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 122926#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 122905#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 122898#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 122896#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 122892#L1663 assume !(0 == start_simulation_~tmp~3#1); 122511#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 122345#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 122329#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 122323#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 122317#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 122315#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122311#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 122310#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 105580#L1644-2 [2023-11-29 03:16:45,273 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:45,273 INFO L85 PathProgramCache]: Analyzing trace with hash 1174510393, now seen corresponding path program 1 times [2023-11-29 03:16:45,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:45,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790616548] [2023-11-29 03:16:45,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:45,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:45,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:45,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:45,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:45,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790616548] [2023-11-29 03:16:45,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [790616548] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:45,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:45,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:16:45,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827749937] [2023-11-29 03:16:45,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:45,336 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:45,336 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:45,336 INFO L85 PathProgramCache]: Analyzing trace with hash 51239904, now seen corresponding path program 1 times [2023-11-29 03:16:45,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:45,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697359148] [2023-11-29 03:16:45,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:45,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:45,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:45,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:45,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:45,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697359148] [2023-11-29 03:16:45,386 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697359148] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:45,386 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:45,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:45,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240630187] [2023-11-29 03:16:45,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:45,387 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:45,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:45,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:16:45,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:16:45,388 INFO L87 Difference]: Start difference. First operand 18908 states and 26810 transitions. cyclomatic complexity: 7918 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:45,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:45,846 INFO L93 Difference]: Finished difference Result 39837 states and 56132 transitions. [2023-11-29 03:16:45,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39837 states and 56132 transitions. [2023-11-29 03:16:46,049 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 39520 [2023-11-29 03:16:46,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39837 states to 39837 states and 56132 transitions. [2023-11-29 03:16:46,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39837 [2023-11-29 03:16:46,220 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39837 [2023-11-29 03:16:46,220 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39837 states and 56132 transitions. [2023-11-29 03:16:46,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:46,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39837 states and 56132 transitions. [2023-11-29 03:16:46,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39837 states and 56132 transitions. [2023-11-29 03:16:46,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39837 to 19439. [2023-11-29 03:16:46,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19439 states, 19439 states have (on average 1.406502392098359) internal successors, (27341), 19438 states have internal predecessors, (27341), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:46,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19439 states to 19439 states and 27341 transitions. [2023-11-29 03:16:46,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19439 states and 27341 transitions. [2023-11-29 03:16:46,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:16:46,583 INFO L428 stractBuchiCegarLoop]: Abstraction has 19439 states and 27341 transitions. [2023-11-29 03:16:46,583 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 03:16:46,583 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19439 states and 27341 transitions. [2023-11-29 03:16:46,644 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19232 [2023-11-29 03:16:46,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:46,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:46,647 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:46,647 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:46,648 INFO L748 eck$LassoCheckResult]: Stem: 164273#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 164274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 165346#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 165347#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164739#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 164740#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164605#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164497#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164216#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163871#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 163872#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 163916#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 163917#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 164882#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164883#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 164934#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 164317#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164318#L1090 assume !(0 == ~M_E~0); 164367#L1090-2 assume !(0 == ~T1_E~0); 164368#L1095-1 assume !(0 == ~T2_E~0); 165088#L1100-1 assume !(0 == ~T3_E~0); 165089#L1105-1 assume !(0 == ~T4_E~0); 164137#L1110-1 assume !(0 == ~T5_E~0); 164138#L1115-1 assume !(0 == ~T6_E~0); 164536#L1120-1 assume !(0 == ~T7_E~0); 164850#L1125-1 assume !(0 == ~T8_E~0); 165439#L1130-1 assume !(0 == ~T9_E~0); 165112#L1135-1 assume !(0 == ~T10_E~0); 164323#L1140-1 assume !(0 == ~T11_E~0); 164324#L1145-1 assume !(0 == ~E_1~0); 165040#L1150-1 assume !(0 == ~E_2~0); 164511#L1155-1 assume !(0 == ~E_3~0); 164512#L1160-1 assume !(0 == ~E_4~0); 164612#L1165-1 assume !(0 == ~E_5~0); 164613#L1170-1 assume !(0 == ~E_6~0); 165320#L1175-1 assume !(0 == ~E_7~0); 164695#L1180-1 assume !(0 == ~E_8~0); 164696#L1185-1 assume !(0 == ~E_9~0); 164319#L1190-1 assume !(0 == ~E_10~0); 164320#L1195-1 assume !(0 == ~E_11~0); 164711#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164530#L525 assume !(1 == ~m_pc~0); 163960#L525-2 is_master_triggered_~__retres1~0#1 := 0; 163961#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165197#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 165168#L1350 assume !(0 != activate_threads_~tmp~1#1); 164309#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164310#L544 assume !(1 == ~t1_pc~0); 164531#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 164532#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163940#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163941#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 164159#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164818#L563 assume !(1 == ~t2_pc~0); 165026#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 163979#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163980#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 164393#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 164394#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164906#L582 assume !(1 == ~t3_pc~0); 165039#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 165399#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163863#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163864#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 164045#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164046#L601 assume !(1 == ~t4_pc~0); 165054#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 164537#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164059#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 164060#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 165049#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 165392#L620 assume !(1 == ~t5_pc~0); 164869#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 164870#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164924#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 165203#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 165408#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 165409#L639 assume !(1 == ~t6_pc~0); 164848#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 164431#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 164432#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 164481#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 164542#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 164543#L658 assume !(1 == ~t7_pc~0); 164763#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 164764#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 165417#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164980#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 164312#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164313#L677 assume !(1 == ~t8_pc~0); 164337#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 164125#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 164126#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 164386#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 164387#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 165159#L696 assume !(1 == ~t9_pc~0); 164833#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 164834#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 164941#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164858#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 164859#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 165093#L715 assume 1 == ~t10_pc~0; 165101#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 164960#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 164751#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 164752#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 164688#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 164113#L734 assume !(1 == ~t11_pc~0); 164114#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 164614#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 164700#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 163861#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 163862#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164925#L1213 assume !(1 == ~M_E~0); 164686#L1213-2 assume !(1 == ~T1_E~0); 164687#L1218-1 assume !(1 == ~T2_E~0); 163894#L1223-1 assume !(1 == ~T3_E~0); 163895#L1228-1 assume !(1 == ~T4_E~0); 164661#L1233-1 assume !(1 == ~T5_E~0); 165410#L1238-1 assume !(1 == ~T6_E~0); 165047#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 165048#L1248-1 assume !(1 == ~T8_E~0); 165097#L1253-1 assume !(1 == ~T9_E~0); 165098#L1258-1 assume !(1 == ~T10_E~0); 165071#L1263-1 assume !(1 == ~T11_E~0); 165072#L1268-1 assume !(1 == ~E_1~0); 164874#L1273-1 assume !(1 == ~E_2~0); 164875#L1278-1 assume !(1 == ~E_3~0); 164427#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 164428#L1288-1 assume !(1 == ~E_5~0); 165210#L1293-1 assume !(1 == ~E_6~0); 165164#L1298-1 assume !(1 == ~E_7~0); 164910#L1303-1 assume !(1 == ~E_8~0); 164438#L1308-1 assume !(1 == ~E_9~0); 164327#L1313-1 assume !(1 == ~E_10~0); 164328#L1318-1 assume !(1 == ~E_11~0); 164338#L1323-1 assume { :end_inline_reset_delta_events } true; 164339#L1644-2 [2023-11-29 03:16:46,648 INFO L750 eck$LassoCheckResult]: Loop: 164339#L1644-2 assume !false; 169562#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 169557#L1065-1 assume !false; 169554#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 169542#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 169527#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 169522#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 169514#L906 assume !(0 != eval_~tmp~0#1); 169515#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 172326#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 172325#L1090-3 assume !(0 == ~M_E~0); 172324#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 172323#L1095-3 assume !(0 == ~T2_E~0); 172322#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 172321#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 172320#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 172319#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 172318#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 172317#L1125-3 assume !(0 == ~T8_E~0); 172316#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 172315#L1135-3 assume !(0 == ~T10_E~0); 172314#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 172313#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 172312#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 172311#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 172310#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 172309#L1165-3 assume !(0 == ~E_5~0); 172308#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 172307#L1175-3 assume !(0 == ~E_7~0); 172306#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 172305#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 172304#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 172303#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 172302#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172301#L525-36 assume 1 == ~m_pc~0; 172299#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 172297#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 172295#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172293#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 172292#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 172291#L544-36 assume !(1 == ~t1_pc~0); 172290#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 172289#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 172288#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 172287#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 172286#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172285#L563-36 assume !(1 == ~t2_pc~0); 172283#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 172282#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172281#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 172280#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 172279#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172278#L582-36 assume !(1 == ~t3_pc~0); 172277#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 172276#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172275#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 172274#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 172273#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172272#L601-36 assume !(1 == ~t4_pc~0); 172270#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 172269#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172268#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 172267#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 172266#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172265#L620-36 assume !(1 == ~t5_pc~0); 172264#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 172263#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172262#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 172261#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 172260#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 172259#L639-36 assume !(1 == ~t6_pc~0); 172258#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 172256#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 172255#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 172254#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 172253#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 172252#L658-36 assume !(1 == ~t7_pc~0); 172250#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 172249#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 172248#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 172247#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 172246#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 172245#L677-36 assume !(1 == ~t8_pc~0); 172244#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 172243#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172242#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 172241#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 172240#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 172239#L696-36 assume !(1 == ~t9_pc~0); 172238#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 172236#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 172234#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 172232#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 169789#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 169787#L715-36 assume 1 == ~t10_pc~0; 169784#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 169781#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 169779#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 169777#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 169775#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 169773#L734-36 assume !(1 == ~t11_pc~0); 169770#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 169767#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 169765#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 169763#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 169761#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169760#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 169759#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 169758#L1218-3 assume !(1 == ~T2_E~0); 169757#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169756#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 169755#L1233-3 assume !(1 == ~T5_E~0); 169754#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 169752#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 169749#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 169746#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 169743#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 169740#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 169738#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 169736#L1273-3 assume !(1 == ~E_2~0); 169734#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 169732#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 169730#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 169727#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 169724#L1298-3 assume !(1 == ~E_7~0); 169721#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 169717#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 169714#L1313-3 assume !(1 == ~E_10~0); 169711#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 169709#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 169678#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 169670#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 169667#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 169655#L1663 assume !(0 == start_simulation_~tmp~3#1); 169653#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 169642#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 169625#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 169617#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 169605#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 169594#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 169586#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 169576#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 164339#L1644-2 [2023-11-29 03:16:46,649 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:46,649 INFO L85 PathProgramCache]: Analyzing trace with hash 145151095, now seen corresponding path program 1 times [2023-11-29 03:16:46,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:46,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235828006] [2023-11-29 03:16:46,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:46,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:46,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:46,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:46,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:46,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235828006] [2023-11-29 03:16:46,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235828006] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:46,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:46,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:46,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654300358] [2023-11-29 03:16:46,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:46,822 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:46,823 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:46,823 INFO L85 PathProgramCache]: Analyzing trace with hash 1579793467, now seen corresponding path program 1 times [2023-11-29 03:16:46,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:46,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59024341] [2023-11-29 03:16:46,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:46,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:46,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:46,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:46,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:46,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59024341] [2023-11-29 03:16:46,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [59024341] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:46,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:46,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:46,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [229248477] [2023-11-29 03:16:46,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:46,866 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:46,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:46,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:46,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:46,867 INFO L87 Difference]: Start difference. First operand 19439 states and 27341 transitions. cyclomatic complexity: 7918 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:47,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:47,032 INFO L93 Difference]: Finished difference Result 37110 states and 52010 transitions. [2023-11-29 03:16:47,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37110 states and 52010 transitions. [2023-11-29 03:16:47,226 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36816 [2023-11-29 03:16:47,318 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37110 states to 37110 states and 52010 transitions. [2023-11-29 03:16:47,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37110 [2023-11-29 03:16:47,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37110 [2023-11-29 03:16:47,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37110 states and 52010 transitions. [2023-11-29 03:16:47,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:47,380 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37110 states and 52010 transitions. [2023-11-29 03:16:47,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37110 states and 52010 transitions. [2023-11-29 03:16:47,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37110 to 37078. [2023-11-29 03:16:47,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.4018555477641728) internal successors, (51978), 37077 states have internal predecessors, (51978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:47,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51978 transitions. [2023-11-29 03:16:47,832 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51978 transitions. [2023-11-29 03:16:47,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:47,833 INFO L428 stractBuchiCegarLoop]: Abstraction has 37078 states and 51978 transitions. [2023-11-29 03:16:47,833 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 03:16:47,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51978 transitions. [2023-11-29 03:16:48,001 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-29 03:16:48,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:48,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:48,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:48,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:48,021 INFO L748 eck$LassoCheckResult]: Stem: 220831#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 220832#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 221902#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221903#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221298#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 221299#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221163#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 221054#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 220775#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 220427#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 220428#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 220473#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 220474#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 221452#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 221453#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 221501#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 220875#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 220876#L1090 assume !(0 == ~M_E~0); 220923#L1090-2 assume !(0 == ~T1_E~0); 220924#L1095-1 assume !(0 == ~T2_E~0); 221659#L1100-1 assume !(0 == ~T3_E~0); 221660#L1105-1 assume !(0 == ~T4_E~0); 220697#L1110-1 assume !(0 == ~T5_E~0); 220698#L1115-1 assume !(0 == ~T6_E~0); 221094#L1120-1 assume !(0 == ~T7_E~0); 221420#L1125-1 assume !(0 == ~T8_E~0); 221986#L1130-1 assume !(0 == ~T9_E~0); 221678#L1135-1 assume !(0 == ~T10_E~0); 220881#L1140-1 assume !(0 == ~T11_E~0); 220882#L1145-1 assume !(0 == ~E_1~0); 221608#L1150-1 assume !(0 == ~E_2~0); 221069#L1155-1 assume !(0 == ~E_3~0); 221070#L1160-1 assume !(0 == ~E_4~0); 221168#L1165-1 assume !(0 == ~E_5~0); 221169#L1170-1 assume !(0 == ~E_6~0); 221882#L1175-1 assume !(0 == ~E_7~0); 221253#L1180-1 assume !(0 == ~E_8~0); 221254#L1185-1 assume !(0 == ~E_9~0); 220877#L1190-1 assume !(0 == ~E_10~0); 220878#L1195-1 assume !(0 == ~E_11~0); 221269#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221088#L525 assume !(1 == ~m_pc~0); 220517#L525-2 is_master_triggered_~__retres1~0#1 := 0; 220518#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221852#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221739#L1350 assume !(0 != activate_threads_~tmp~1#1); 220867#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220868#L544 assume !(1 == ~t1_pc~0); 221089#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 221090#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220497#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220498#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 220720#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221385#L563 assume !(1 == ~t2_pc~0); 221596#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 220536#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220537#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 220949#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 220950#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221474#L582 assume !(1 == ~t3_pc~0); 221607#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221946#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220419#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220420#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 220602#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220603#L601 assume !(1 == ~t4_pc~0); 221623#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 221095#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220616#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220617#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 221617#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221941#L620 assume !(1 == ~t5_pc~0); 221436#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 221437#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221493#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 221773#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 221954#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221955#L639 assume !(1 == ~t6_pc~0); 221418#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 220989#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220990#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221039#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 221098#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221099#L658 assume !(1 == ~t7_pc~0); 221324#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 221325#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221963#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221550#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 220870#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220871#L677 assume !(1 == ~t8_pc~0); 220894#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 220681#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 220682#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220942#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 220943#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 221730#L696 assume !(1 == ~t9_pc~0); 221403#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 221404#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221153#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221154#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 221429#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 221663#L715 assume !(1 == ~t10_pc~0); 221919#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 221528#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 221310#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 221311#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 221247#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 220672#L734 assume !(1 == ~t11_pc~0); 220673#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 221170#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 221258#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 220417#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 220418#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221494#L1213 assume !(1 == ~M_E~0); 221245#L1213-2 assume !(1 == ~T1_E~0); 221246#L1218-1 assume !(1 == ~T2_E~0); 220450#L1223-1 assume !(1 == ~T3_E~0); 220451#L1228-1 assume !(1 == ~T4_E~0); 221217#L1233-1 assume !(1 == ~T5_E~0); 221956#L1238-1 assume !(1 == ~T6_E~0); 221615#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 221616#L1248-1 assume !(1 == ~T8_E~0); 221666#L1253-1 assume !(1 == ~T9_E~0); 221667#L1258-1 assume !(1 == ~T10_E~0); 221642#L1263-1 assume !(1 == ~T11_E~0); 221643#L1268-1 assume !(1 == ~E_1~0); 221444#L1273-1 assume !(1 == ~E_2~0); 221445#L1278-1 assume !(1 == ~E_3~0); 220985#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 220986#L1288-1 assume !(1 == ~E_5~0); 221777#L1293-1 assume !(1 == ~E_6~0); 221735#L1298-1 assume !(1 == ~E_7~0); 221478#L1303-1 assume !(1 == ~E_8~0); 220995#L1308-1 assume !(1 == ~E_9~0); 220885#L1313-1 assume !(1 == ~E_10~0); 220886#L1318-1 assume !(1 == ~E_11~0); 220895#L1323-1 assume { :end_inline_reset_delta_events } true; 220896#L1644-2 [2023-11-29 03:16:48,022 INFO L750 eck$LassoCheckResult]: Loop: 220896#L1644-2 assume !false; 244497#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 244491#L1065-1 assume !false; 244486#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 244237#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 244216#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 244208#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 244197#L906 assume !(0 != eval_~tmp~0#1); 244198#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 247367#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 247365#L1090-3 assume !(0 == ~M_E~0); 247363#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 247361#L1095-3 assume !(0 == ~T2_E~0); 247359#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 247357#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 247355#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 247352#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 247350#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 247348#L1125-3 assume !(0 == ~T8_E~0); 247346#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 247345#L1135-3 assume !(0 == ~T10_E~0); 247341#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 247339#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 247337#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 247334#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 247333#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 247332#L1165-3 assume !(0 == ~E_5~0); 247320#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 247310#L1175-3 assume !(0 == ~E_7~0); 247309#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 247308#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 247295#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 247286#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 247279#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247210#L525-36 assume 1 == ~m_pc~0; 247193#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 247187#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247179#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247115#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 247113#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247111#L544-36 assume !(1 == ~t1_pc~0); 247109#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 247107#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247105#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247102#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 247100#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247098#L563-36 assume !(1 == ~t2_pc~0); 247095#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 247093#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247091#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 247088#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 247086#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247084#L582-36 assume !(1 == ~t3_pc~0); 247080#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 247068#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247058#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247049#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247042#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247035#L601-36 assume 1 == ~t4_pc~0; 247030#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 247023#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247015#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247009#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 247002#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 246995#L620-36 assume !(1 == ~t5_pc~0); 246988#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 246979#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245378#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 245365#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 245363#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245361#L639-36 assume !(1 == ~t6_pc~0); 245359#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 245356#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 245354#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 245352#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 245350#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 245345#L658-36 assume !(1 == ~t7_pc~0); 245342#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 245340#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 245339#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 245338#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 245337#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 245318#L677-36 assume !(1 == ~t8_pc~0); 245311#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 245305#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 245276#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 245270#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 245264#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 244972#L696-36 assume !(1 == ~t9_pc~0); 244970#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 244968#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 244966#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 244964#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 244961#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 244959#L715-36 assume !(1 == ~t10_pc~0); 244957#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 244955#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 244953#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 244951#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 244947#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 244945#L734-36 assume 1 == ~t11_pc~0; 244942#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 244938#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 244936#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 244934#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 244932#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 244930#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 244928#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 244926#L1218-3 assume !(1 == ~T2_E~0); 244924#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 244922#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 244919#L1233-3 assume !(1 == ~T5_E~0); 244917#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 244915#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 244913#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 244911#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 244910#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 244909#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 244894#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 244884#L1273-3 assume !(1 == ~E_2~0); 244883#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 244882#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 244881#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 244879#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 244878#L1298-3 assume !(1 == ~E_7~0); 244845#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 244829#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 244820#L1313-3 assume !(1 == ~E_10~0); 244814#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 244810#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 244669#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 244656#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 244648#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 244638#L1663 assume !(0 == start_simulation_~tmp~3#1); 244633#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 244559#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 244544#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 244539#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 244532#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 244527#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 244521#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 244512#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 220896#L1644-2 [2023-11-29 03:16:48,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:48,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2023-11-29 03:16:48,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:48,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020359896] [2023-11-29 03:16:48,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:48,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:48,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:48,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:48,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:48,130 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020359896] [2023-11-29 03:16:48,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020359896] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:48,131 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:48,131 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:48,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931831581] [2023-11-29 03:16:48,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:48,132 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:48,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:48,132 INFO L85 PathProgramCache]: Analyzing trace with hash 1328081372, now seen corresponding path program 1 times [2023-11-29 03:16:48,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:48,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311869856] [2023-11-29 03:16:48,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:48,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:48,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:48,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:48,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:48,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311869856] [2023-11-29 03:16:48,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1311869856] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:48,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:48,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:48,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [816917107] [2023-11-29 03:16:48,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:48,208 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:48,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:48,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:16:48,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:16:48,209 INFO L87 Difference]: Start difference. First operand 37078 states and 51978 transitions. cyclomatic complexity: 14932 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:48,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:48,548 INFO L93 Difference]: Finished difference Result 77699 states and 108961 transitions. [2023-11-29 03:16:48,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77699 states and 108961 transitions. [2023-11-29 03:16:48,929 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 77136 [2023-11-29 03:16:49,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77699 states to 77699 states and 108961 transitions. [2023-11-29 03:16:49,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77699 [2023-11-29 03:16:49,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77699 [2023-11-29 03:16:49,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77699 states and 108961 transitions. [2023-11-29 03:16:49,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:49,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77699 states and 108961 transitions. [2023-11-29 03:16:49,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77699 states and 108961 transitions. [2023-11-29 03:16:49,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77699 to 40755. [2023-11-29 03:16:49,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40755 states, 40755 states have (on average 1.404367562262299) internal successors, (57235), 40754 states have internal predecessors, (57235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:49,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40755 states to 40755 states and 57235 transitions. [2023-11-29 03:16:49,923 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40755 states and 57235 transitions. [2023-11-29 03:16:49,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:16:49,923 INFO L428 stractBuchiCegarLoop]: Abstraction has 40755 states and 57235 transitions. [2023-11-29 03:16:49,924 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 03:16:49,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40755 states and 57235 transitions. [2023-11-29 03:16:50,066 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40352 [2023-11-29 03:16:50,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:50,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:50,070 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:50,070 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:50,070 INFO L748 eck$LassoCheckResult]: Stem: 335625#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 335626#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 336724#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 336725#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 336090#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 336091#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 335958#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 335847#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 335567#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 335214#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 335215#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 335259#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 335260#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 336247#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 336248#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 336299#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 335666#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 335667#L1090 assume !(0 == ~M_E~0); 335716#L1090-2 assume !(0 == ~T1_E~0); 335717#L1095-1 assume !(0 == ~T2_E~0); 336466#L1100-1 assume !(0 == ~T3_E~0); 336467#L1105-1 assume !(0 == ~T4_E~0); 335484#L1110-1 assume !(0 == ~T5_E~0); 335485#L1115-1 assume !(0 == ~T6_E~0); 335888#L1120-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 336215#L1125-1 assume !(0 == ~T8_E~0); 336833#L1130-1 assume !(0 == ~T9_E~0); 336489#L1135-1 assume !(0 == ~T10_E~0); 335672#L1140-1 assume !(0 == ~T11_E~0); 335673#L1145-1 assume !(0 == ~E_1~0); 336933#L1150-1 assume !(0 == ~E_2~0); 335864#L1155-1 assume !(0 == ~E_3~0); 335865#L1160-1 assume !(0 == ~E_4~0); 336932#L1165-1 assume !(0 == ~E_5~0); 336701#L1170-1 assume !(0 == ~E_6~0); 336702#L1175-1 assume !(0 == ~E_7~0); 336931#L1180-1 assume !(0 == ~E_8~0); 336930#L1185-1 assume !(0 == ~E_9~0); 336929#L1190-1 assume !(0 == ~E_10~0); 336928#L1195-1 assume !(0 == ~E_11~0); 336670#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 336671#L525 assume !(1 == ~m_pc~0); 336926#L525-2 is_master_triggered_~__retres1~0#1 := 0; 336924#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 336922#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 336920#L1350 assume !(0 != activate_threads_~tmp~1#1); 336919#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 336121#L544 assume !(1 == ~t1_pc~0); 336122#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 336410#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 335282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 335283#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 336179#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 336180#L563 assume !(1 == ~t2_pc~0); 336397#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 336398#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 335861#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 336269#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336270#L582 assume !(1 == ~t3_pc~0); 336835#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 336836#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 336914#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 336711#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 335391#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 335392#L601 assume !(1 == ~t4_pc~0); 336911#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 336910#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 336909#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 336908#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 336858#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336859#L620 assume !(1 == ~t5_pc~0); 336235#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 336236#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 336907#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 336876#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 336877#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 336838#L639 assume !(1 == ~t6_pc~0); 336839#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 335780#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 335781#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 336789#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 335894#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 335895#L658 assume !(1 == ~t7_pc~0); 336214#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 336803#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 336804#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 336347#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 335661#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 335662#L677 assume !(1 == ~t8_pc~0); 335900#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 335471#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 335472#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 336508#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 336900#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 336899#L696 assume !(1 == ~t9_pc~0); 336195#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 336196#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 336938#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 336224#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 336225#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 336472#L715 assume !(1 == ~t10_pc~0); 336818#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 336819#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 336106#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 336107#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 336037#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 336038#L734 assume !(1 == ~t11_pc~0); 336888#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 336887#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 336357#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 336358#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 336289#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336290#L1213 assume !(1 == ~M_E~0); 336886#L1213-2 assume !(1 == ~T1_E~0); 336885#L1218-1 assume !(1 == ~T2_E~0); 336884#L1223-1 assume !(1 == ~T3_E~0); 336883#L1228-1 assume !(1 == ~T4_E~0); 336793#L1233-1 assume !(1 == ~T5_E~0); 336794#L1238-1 assume !(1 == ~T6_E~0); 336882#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 336422#L1248-1 assume !(1 == ~T8_E~0); 336477#L1253-1 assume !(1 == ~T9_E~0); 336478#L1258-1 assume !(1 == ~T10_E~0); 336447#L1263-1 assume !(1 == ~T11_E~0); 336448#L1268-1 assume !(1 == ~E_1~0); 336240#L1273-1 assume !(1 == ~E_2~0); 336241#L1278-1 assume !(1 == ~E_3~0); 335776#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 335777#L1288-1 assume !(1 == ~E_5~0); 336588#L1293-1 assume !(1 == ~E_6~0); 336543#L1298-1 assume !(1 == ~E_7~0); 336274#L1303-1 assume !(1 == ~E_8~0); 335787#L1308-1 assume !(1 == ~E_9~0); 335676#L1313-1 assume !(1 == ~E_10~0); 335677#L1318-1 assume !(1 == ~E_11~0); 335688#L1323-1 assume { :end_inline_reset_delta_events } true; 335689#L1644-2 [2023-11-29 03:16:50,071 INFO L750 eck$LassoCheckResult]: Loop: 335689#L1644-2 assume !false; 343116#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 343111#L1065-1 assume !false; 343109#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 343092#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 343081#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 343079#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 343076#L906 assume !(0 != eval_~tmp~0#1); 343077#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 343442#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 343441#L1090-3 assume !(0 == ~M_E~0); 343440#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 343439#L1095-3 assume !(0 == ~T2_E~0); 343438#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 343437#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 343436#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 343435#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 343433#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 343432#L1125-3 assume !(0 == ~T8_E~0); 343431#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 343430#L1135-3 assume !(0 == ~T10_E~0); 343429#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 343428#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 343427#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 343426#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 343425#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 343424#L1165-3 assume !(0 == ~E_5~0); 343423#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 343422#L1175-3 assume !(0 == ~E_7~0); 343421#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 343420#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 343419#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 343418#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 343417#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 343416#L525-36 assume !(1 == ~m_pc~0); 343415#L525-38 is_master_triggered_~__retres1~0#1 := 0; 343413#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343411#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 343409#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 343407#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343406#L544-36 assume !(1 == ~t1_pc~0); 343405#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 343404#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 343403#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 343402#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 343401#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 343400#L563-36 assume 1 == ~t2_pc~0; 343399#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 343397#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 343396#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 343395#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 343394#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 343393#L582-36 assume !(1 == ~t3_pc~0); 343392#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 343391#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343390#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 343389#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 343388#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343387#L601-36 assume !(1 == ~t4_pc~0); 343385#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 343384#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 343383#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 343382#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 343381#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 343380#L620-36 assume !(1 == ~t5_pc~0); 343379#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 343378#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 343377#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 343376#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 343375#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 343374#L639-36 assume !(1 == ~t6_pc~0); 343373#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 343371#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 343370#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 343369#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 343368#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 343367#L658-36 assume !(1 == ~t7_pc~0); 343365#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 343364#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 343363#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 343362#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 343361#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 343360#L677-36 assume !(1 == ~t8_pc~0); 343359#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 343358#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 343357#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 343356#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 343355#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 343354#L696-36 assume !(1 == ~t9_pc~0); 343353#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 343351#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 343349#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 343347#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 343345#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 343344#L715-36 assume !(1 == ~t10_pc~0); 343343#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 343342#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 343341#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 343340#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 343339#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 343338#L734-36 assume 1 == ~t11_pc~0; 343337#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 343335#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 343334#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 343333#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 343332#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 343331#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 343330#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 343329#L1218-3 assume !(1 == ~T2_E~0); 343328#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 343327#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 343326#L1233-3 assume !(1 == ~T5_E~0); 343325#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 343323#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 343321#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 343318#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 343316#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 343314#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 343312#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 343310#L1273-3 assume !(1 == ~E_2~0); 343308#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 343306#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 343304#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 343302#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 343300#L1298-3 assume !(1 == ~E_7~0); 343298#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 343296#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 343293#L1313-3 assume !(1 == ~E_10~0); 343291#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 343289#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 343274#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 343267#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 343264#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 343152#L1663 assume !(0 == start_simulation_~tmp~3#1); 343149#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 343140#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 343129#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 343127#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 343125#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 343123#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 343121#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 343119#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 335689#L1644-2 [2023-11-29 03:16:50,071 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:50,071 INFO L85 PathProgramCache]: Analyzing trace with hash 948156820, now seen corresponding path program 1 times [2023-11-29 03:16:50,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:50,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771565171] [2023-11-29 03:16:50,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:50,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:50,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:50,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:50,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:50,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771565171] [2023-11-29 03:16:50,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771565171] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:50,156 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:50,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:50,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981646672] [2023-11-29 03:16:50,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:50,157 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:50,157 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:50,158 INFO L85 PathProgramCache]: Analyzing trace with hash 1460114489, now seen corresponding path program 1 times [2023-11-29 03:16:50,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:50,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481303257] [2023-11-29 03:16:50,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:50,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:50,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:50,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:50,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:50,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481303257] [2023-11-29 03:16:50,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481303257] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:50,224 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:50,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:50,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830467897] [2023-11-29 03:16:50,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:50,225 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:50,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:50,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:16:50,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:16:50,227 INFO L87 Difference]: Start difference. First operand 40755 states and 57235 transitions. cyclomatic complexity: 16512 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:50,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:50,499 INFO L93 Difference]: Finished difference Result 37078 states and 51880 transitions. [2023-11-29 03:16:50,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37078 states and 51880 transitions. [2023-11-29 03:16:50,622 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-29 03:16:50,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37078 states to 37078 states and 51880 transitions. [2023-11-29 03:16:50,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37078 [2023-11-29 03:16:50,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37078 [2023-11-29 03:16:50,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37078 states and 51880 transitions. [2023-11-29 03:16:50,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:50,847 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2023-11-29 03:16:50,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37078 states and 51880 transitions. [2023-11-29 03:16:51,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37078 to 37078. [2023-11-29 03:16:51,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3992124710070661) internal successors, (51880), 37077 states have internal predecessors, (51880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:51,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 51880 transitions. [2023-11-29 03:16:51,127 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2023-11-29 03:16:51,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:51,128 INFO L428 stractBuchiCegarLoop]: Abstraction has 37078 states and 51880 transitions. [2023-11-29 03:16:51,128 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 03:16:51,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 51880 transitions. [2023-11-29 03:16:51,298 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-29 03:16:51,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:51,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:51,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:51,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:51,302 INFO L748 eck$LassoCheckResult]: Stem: 413465#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 413466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 414562#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 414563#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 413926#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 413927#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 413793#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 413685#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 413408#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 413057#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 413058#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 413102#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 413103#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 414073#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 414074#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 414120#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 413507#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 413508#L1090 assume !(0 == ~M_E~0); 413554#L1090-2 assume !(0 == ~T1_E~0); 413555#L1095-1 assume !(0 == ~T2_E~0); 414293#L1100-1 assume !(0 == ~T3_E~0); 414294#L1105-1 assume !(0 == ~T4_E~0); 413328#L1110-1 assume !(0 == ~T5_E~0); 413329#L1115-1 assume !(0 == ~T6_E~0); 413721#L1120-1 assume !(0 == ~T7_E~0); 414047#L1125-1 assume !(0 == ~T8_E~0); 414693#L1130-1 assume !(0 == ~T9_E~0); 414317#L1135-1 assume !(0 == ~T10_E~0); 413513#L1140-1 assume !(0 == ~T11_E~0); 413514#L1145-1 assume !(0 == ~E_1~0); 414234#L1150-1 assume !(0 == ~E_2~0); 413699#L1155-1 assume !(0 == ~E_3~0); 413700#L1160-1 assume !(0 == ~E_4~0); 413798#L1165-1 assume !(0 == ~E_5~0); 413799#L1170-1 assume !(0 == ~E_6~0); 414533#L1175-1 assume !(0 == ~E_7~0); 413882#L1180-1 assume !(0 == ~E_8~0); 413883#L1185-1 assume !(0 == ~E_9~0); 413509#L1190-1 assume !(0 == ~E_10~0); 413510#L1195-1 assume !(0 == ~E_11~0); 413898#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 413718#L525 assume !(1 == ~m_pc~0); 413147#L525-2 is_master_triggered_~__retres1~0#1 := 0; 413148#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 414500#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 414377#L1350 assume !(0 != activate_threads_~tmp~1#1); 413498#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 413499#L544 assume !(1 == ~t1_pc~0); 413719#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 413720#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 413125#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 413126#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 413352#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 414012#L563 assume !(1 == ~t2_pc~0); 414218#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 413169#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 413170#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 413582#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 413583#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 414100#L582 assume !(1 == ~t3_pc~0); 414233#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 414636#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 413049#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 413050#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 413234#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 413235#L601 assume !(1 == ~t4_pc~0); 414249#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 413722#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 413248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 413249#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 414244#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 414627#L620 assume !(1 == ~t5_pc~0); 414061#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 414062#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 414117#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 414412#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 414648#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 414649#L639 assume !(1 == ~t6_pc~0); 414045#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 413620#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 413621#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 413670#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 413727#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 413728#L658 assume !(1 == ~t7_pc~0); 413955#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 413956#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 414661#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 414172#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 413502#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 413503#L677 assume !(1 == ~t8_pc~0); 413526#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 413309#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 413310#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 413575#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 413576#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 414365#L696 assume !(1 == ~t9_pc~0); 414028#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 414029#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 413783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 413784#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 414052#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 414297#L715 assume !(1 == ~t10_pc~0); 414585#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 414152#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 413942#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 413943#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 413875#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 413303#L734 assume !(1 == ~t11_pc~0); 413304#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 413800#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 413887#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 413047#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 413048#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 414118#L1213 assume !(1 == ~M_E~0); 413873#L1213-2 assume !(1 == ~T1_E~0); 413874#L1218-1 assume !(1 == ~T2_E~0); 413080#L1223-1 assume !(1 == ~T3_E~0); 413081#L1228-1 assume !(1 == ~T4_E~0); 413846#L1233-1 assume !(1 == ~T5_E~0); 414650#L1238-1 assume !(1 == ~T6_E~0); 414242#L1243-1 assume !(1 == ~T7_E~0); 414243#L1248-1 assume !(1 == ~T8_E~0); 414302#L1253-1 assume !(1 == ~T9_E~0); 414303#L1258-1 assume !(1 == ~T10_E~0); 414270#L1263-1 assume !(1 == ~T11_E~0); 414271#L1268-1 assume !(1 == ~E_1~0); 414069#L1273-1 assume !(1 == ~E_2~0); 414070#L1278-1 assume !(1 == ~E_3~0); 413616#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 413617#L1288-1 assume !(1 == ~E_5~0); 414419#L1293-1 assume !(1 == ~E_6~0); 414370#L1298-1 assume !(1 == ~E_7~0); 414104#L1303-1 assume !(1 == ~E_8~0); 413626#L1308-1 assume !(1 == ~E_9~0); 413517#L1313-1 assume !(1 == ~E_10~0); 413518#L1318-1 assume !(1 == ~E_11~0); 413527#L1323-1 assume { :end_inline_reset_delta_events } true; 413528#L1644-2 WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [2023-11-29 03:16:58,593 INFO L750 eck$LassoCheckResult]: Loop: 886574#L1644-2 assume !false; 906339#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 906334#L1065-1 assume !false; 906331#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 906320#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 906309#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 906306#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 906304#L906 assume !(0 != eval_~tmp~0#1); 906305#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 906889#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 906888#L1090-3 assume !(0 == ~M_E~0); 906886#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 906884#L1095-3 assume !(0 == ~T2_E~0); 906882#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 906880#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 906878#L1110-3 assume !(0 == ~T5_E~0); 906876#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 906874#L1120-3 assume !(0 == ~T7_E~0); 906872#L1125-3 assume !(0 == ~T8_E~0); 906870#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 906868#L1135-3 assume !(0 == ~T10_E~0); 906865#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 906863#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 906856#L1150-3 assume !(0 == ~E_2~0); 906857#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 906887#L1160-3 assume !(0 == ~E_4~0); 906885#L1165-3 assume !(0 == ~E_5~0); 906883#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 906881#L1175-3 assume !(0 == ~E_7~0); 906879#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 906877#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 906875#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 906873#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 906871#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 906869#L525-36 assume !(1 == ~m_pc~0); 906867#L525-38 is_master_triggered_~__retres1~0#1 := 0; 914065#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 911210#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 906860#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 906855#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 906853#L544-36 assume !(1 == ~t1_pc~0); 906851#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 906849#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 906847#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 906845#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 906843#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 906839#L563-36 assume 1 == ~t2_pc~0; 906840#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 906800#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 906798#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 906796#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 906794#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 906792#L582-36 assume !(1 == ~t3_pc~0); 906790#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 906788#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 906786#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 906783#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 906781#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 906779#L601-36 assume !(1 == ~t4_pc~0); 906776#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 906774#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 906771#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 906769#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 906767#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 906765#L620-36 assume !(1 == ~t5_pc~0); 906763#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 906761#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 906759#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 906757#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 906755#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 906753#L639-36 assume !(1 == ~t6_pc~0); 906751#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 906748#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 906747#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 906743#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 906741#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 906739#L658-36 assume !(1 == ~t7_pc~0); 906736#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 906733#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 906731#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 906729#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 906727#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 906725#L677-36 assume !(1 == ~t8_pc~0); 906723#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 906721#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 906719#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 906717#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 906714#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 906709#L696-36 assume 1 == ~t9_pc~0; 906710#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 906711#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 906892#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 906700#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 906698#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 906696#L715-36 assume !(1 == ~t10_pc~0); 906694#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 906692#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 906690#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 906688#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 906686#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 906684#L734-36 assume !(1 == ~t11_pc~0); 906681#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 906679#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 906677#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 906676#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 906675#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 906673#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 906672#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 906671#L1218-3 assume !(1 == ~T2_E~0); 906670#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 906666#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 906664#L1233-3 assume !(1 == ~T5_E~0); 906662#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 906660#L1243-3 assume !(1 == ~T7_E~0); 906657#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 906655#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 906653#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 906651#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 906649#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 906647#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 906644#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 906642#L1283-3 assume !(1 == ~E_4~0); 906640#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 906637#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 906635#L1298-3 assume !(1 == ~E_7~0); 906633#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 906631#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 906629#L1313-3 assume !(1 == ~E_10~0); 906627#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 906625#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 906608#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 906601#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 906599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 906385#L1663 assume !(0 == start_simulation_~tmp~3#1); 906383#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 906364#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 906352#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 906350#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 906348#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 906346#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 906344#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 906342#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 886574#L1644-2 [2023-11-29 03:16:58,593 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:58,593 INFO L85 PathProgramCache]: Analyzing trace with hash -1087159146, now seen corresponding path program 1 times [2023-11-29 03:16:58,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:58,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246830426] [2023-11-29 03:16:58,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:58,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:58,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:58,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:58,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:58,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246830426] [2023-11-29 03:16:58,629 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246830426] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:58,629 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:58,629 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:16:58,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367112491] [2023-11-29 03:16:58,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:58,630 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:16:58,630 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:58,630 INFO L85 PathProgramCache]: Analyzing trace with hash -848054523, now seen corresponding path program 1 times [2023-11-29 03:16:58,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:58,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581951705] [2023-11-29 03:16:58,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:58,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:58,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:58,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:58,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:58,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581951705] [2023-11-29 03:16:58,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581951705] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:58,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:58,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:58,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221816463] [2023-11-29 03:16:58,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:58,670 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:58,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:58,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:58,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:58,671 INFO L87 Difference]: Start difference. First operand 70227 states and 96392 transitions. cyclomatic complexity: 26197 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:58,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:16:58,797 INFO L93 Difference]: Finished difference Result 37078 states and 50928 transitions. [2023-11-29 03:16:58,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37078 states and 50928 transitions. [2023-11-29 03:16:58,902 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-29 03:16:58,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37078 states to 37078 states and 50928 transitions. [2023-11-29 03:16:58,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37078 [2023-11-29 03:16:58,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37078 [2023-11-29 03:16:58,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37078 states and 50928 transitions. [2023-11-29 03:16:58,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:16:58,994 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2023-11-29 03:16:59,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37078 states and 50928 transitions. [2023-11-29 03:16:59,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37078 to 37078. [2023-11-29 03:16:59,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37078 states, 37078 states have (on average 1.3735368682237445) internal successors, (50928), 37077 states have internal predecessors, (50928), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:16:59,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37078 states to 37078 states and 50928 transitions. [2023-11-29 03:16:59,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2023-11-29 03:16:59,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:16:59,512 INFO L428 stractBuchiCegarLoop]: Abstraction has 37078 states and 50928 transitions. [2023-11-29 03:16:59,512 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 03:16:59,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37078 states and 50928 transitions. [2023-11-29 03:16:59,609 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36784 [2023-11-29 03:16:59,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:16:59,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:16:59,611 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:59,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:16:59,612 INFO L748 eck$LassoCheckResult]: Stem: 993825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 993826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 994888#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 994889#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 994282#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 994283#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 994151#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 994046#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 993768#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 993419#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 993420#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 993463#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 993464#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 994423#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 994424#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 994471#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 993868#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 993869#L1090 assume !(0 == ~M_E~0); 993913#L1090-2 assume !(0 == ~T1_E~0); 993914#L1095-1 assume !(0 == ~T2_E~0); 994631#L1100-1 assume !(0 == ~T3_E~0); 994632#L1105-1 assume !(0 == ~T4_E~0); 993687#L1110-1 assume !(0 == ~T5_E~0); 993688#L1115-1 assume !(0 == ~T6_E~0); 994081#L1120-1 assume !(0 == ~T7_E~0); 994397#L1125-1 assume !(0 == ~T8_E~0); 995010#L1130-1 assume !(0 == ~T9_E~0); 994651#L1135-1 assume !(0 == ~T10_E~0); 993874#L1140-1 assume !(0 == ~T11_E~0); 993875#L1145-1 assume !(0 == ~E_1~0); 994581#L1150-1 assume !(0 == ~E_2~0); 994060#L1155-1 assume !(0 == ~E_3~0); 994061#L1160-1 assume !(0 == ~E_4~0); 994156#L1165-1 assume !(0 == ~E_5~0); 994157#L1170-1 assume !(0 == ~E_6~0); 994868#L1175-1 assume !(0 == ~E_7~0); 994237#L1180-1 assume !(0 == ~E_8~0); 994238#L1185-1 assume !(0 == ~E_9~0); 993870#L1190-1 assume !(0 == ~E_10~0); 993871#L1195-1 assume !(0 == ~E_11~0); 994253#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 994078#L525 assume !(1 == ~m_pc~0); 993506#L525-2 is_master_triggered_~__retres1~0#1 := 0; 993507#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 994832#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 994711#L1350 assume !(0 != activate_threads_~tmp~1#1); 993860#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 993861#L544 assume !(1 == ~t1_pc~0); 994079#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 994080#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 993486#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 993487#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 993710#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 994365#L563 assume !(1 == ~t2_pc~0); 994566#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 993528#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 993529#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 993940#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 993941#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 994449#L582 assume !(1 == ~t3_pc~0); 994580#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 994953#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 993411#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 993412#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 993593#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 993594#L601 assume !(1 == ~t4_pc~0); 994596#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 994082#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 993607#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 993608#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 994590#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 994943#L620 assume !(1 == ~t5_pc~0); 994412#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 994413#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 994468#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 994753#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 994966#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 994967#L639 assume !(1 == ~t6_pc~0); 994396#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 993981#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 993982#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 994031#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 994087#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 994088#L658 assume !(1 == ~t7_pc~0); 994309#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 994310#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 994980#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 994521#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 993863#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 993864#L677 assume !(1 == ~t8_pc~0); 993887#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 993670#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 993671#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 993936#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 993937#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 994702#L696 assume !(1 == ~t9_pc~0); 994379#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 994380#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 994141#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 994142#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 994402#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 994635#L715 assume !(1 == ~t10_pc~0); 994909#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 994502#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 994296#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 994297#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 994230#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 993664#L734 assume !(1 == ~t11_pc~0); 993665#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 994158#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 994240#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 993409#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 993410#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 994469#L1213 assume !(1 == ~M_E~0); 994228#L1213-2 assume !(1 == ~T1_E~0); 994229#L1218-1 assume !(1 == ~T2_E~0); 993442#L1223-1 assume !(1 == ~T3_E~0); 993443#L1228-1 assume !(1 == ~T4_E~0); 994204#L1233-1 assume !(1 == ~T5_E~0); 994968#L1238-1 assume !(1 == ~T6_E~0); 994588#L1243-1 assume !(1 == ~T7_E~0); 994589#L1248-1 assume !(1 == ~T8_E~0); 994638#L1253-1 assume !(1 == ~T9_E~0); 994639#L1258-1 assume !(1 == ~T10_E~0); 994614#L1263-1 assume !(1 == ~T11_E~0); 994615#L1268-1 assume !(1 == ~E_1~0); 994420#L1273-1 assume !(1 == ~E_2~0); 994421#L1278-1 assume !(1 == ~E_3~0); 993977#L1283-1 assume !(1 == ~E_4~0); 993978#L1288-1 assume !(1 == ~E_5~0); 994757#L1293-1 assume !(1 == ~E_6~0); 994706#L1298-1 assume !(1 == ~E_7~0); 994453#L1303-1 assume !(1 == ~E_8~0); 993987#L1308-1 assume !(1 == ~E_9~0); 993878#L1313-1 assume !(1 == ~E_10~0); 993879#L1318-1 assume !(1 == ~E_11~0); 993888#L1323-1 assume { :end_inline_reset_delta_events } true; 993889#L1644-2 [2023-11-29 03:16:59,613 INFO L750 eck$LassoCheckResult]: Loop: 993889#L1644-2 assume !false; 1006555#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1006550#L1065-1 assume !false; 1006548#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1006540#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1006529#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1006520#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1006513#L906 assume !(0 != eval_~tmp~0#1); 1006514#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1006962#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1006960#L1090-3 assume !(0 == ~M_E~0); 1006958#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1006956#L1095-3 assume !(0 == ~T2_E~0); 1006954#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1006951#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1006949#L1110-3 assume !(0 == ~T5_E~0); 1006947#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1006945#L1120-3 assume !(0 == ~T7_E~0); 1006943#L1125-3 assume !(0 == ~T8_E~0); 1006941#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1006939#L1135-3 assume !(0 == ~T10_E~0); 1006937#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1006935#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1006933#L1150-3 assume !(0 == ~E_2~0); 1006931#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1006929#L1160-3 assume !(0 == ~E_4~0); 1006927#L1165-3 assume !(0 == ~E_5~0); 1006924#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1006922#L1175-3 assume !(0 == ~E_7~0); 1006920#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1006918#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1006916#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1006913#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1006911#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1006909#L525-36 assume 1 == ~m_pc~0; 1006907#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1006908#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006970#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1006898#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1006896#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1006894#L544-36 assume !(1 == ~t1_pc~0); 1006892#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1006890#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1006888#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1006884#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1006882#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1006878#L563-36 assume !(1 == ~t2_pc~0); 1006875#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1006873#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1006871#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1006869#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1006867#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1006865#L582-36 assume !(1 == ~t3_pc~0); 1006863#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1006861#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1006859#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1006856#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1006854#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1006852#L601-36 assume !(1 == ~t4_pc~0); 1006849#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1006847#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1006846#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1006842#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1006840#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1006838#L620-36 assume !(1 == ~t5_pc~0); 1006835#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1006834#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1006833#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1006830#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1006826#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1006825#L639-36 assume !(1 == ~t6_pc~0); 1006824#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1006822#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1006821#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1006820#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1006819#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1006818#L658-36 assume !(1 == ~t7_pc~0); 1006816#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1006815#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1006814#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1006813#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1006812#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1006811#L677-36 assume !(1 == ~t8_pc~0); 1006810#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1006809#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1006808#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1006807#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1006806#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1006804#L696-36 assume 1 == ~t9_pc~0; 1006805#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1006803#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1006801#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1006797#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1006795#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1006794#L715-36 assume !(1 == ~t10_pc~0); 1006793#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1006792#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1006788#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1006786#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1006784#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1006782#L734-36 assume 1 == ~t11_pc~0; 1006779#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1006776#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1006774#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1006772#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1006770#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1006768#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1006766#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1006764#L1218-3 assume !(1 == ~T2_E~0); 1006761#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1006759#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1006757#L1233-3 assume !(1 == ~T5_E~0); 1006755#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1006753#L1243-3 assume !(1 == ~T7_E~0); 1006751#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1006749#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1006747#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1006745#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1006743#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1006741#L1273-3 assume !(1 == ~E_2~0); 1006739#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1006736#L1283-3 assume !(1 == ~E_4~0); 1006734#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1006732#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1006730#L1298-3 assume !(1 == ~E_7~0); 1006728#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1006726#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1006724#L1313-3 assume !(1 == ~E_10~0); 1006722#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1006720#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1006701#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1006694#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1006692#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1006591#L1663 assume !(0 == start_simulation_~tmp~3#1); 1006588#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1006579#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1006568#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1006566#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1006564#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1006562#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1006560#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1006558#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 993889#L1644-2 [2023-11-29 03:16:59,613 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:59,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 3 times [2023-11-29 03:16:59,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:59,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371695201] [2023-11-29 03:16:59,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:59,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:59,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:16:59,631 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:16:59,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:16:59,679 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:16:59,680 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:16:59,680 INFO L85 PathProgramCache]: Analyzing trace with hash -1084917654, now seen corresponding path program 1 times [2023-11-29 03:16:59,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:16:59,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392675038] [2023-11-29 03:16:59,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:16:59,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:16:59,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:16:59,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:16:59,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:16:59,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392675038] [2023-11-29 03:16:59,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392675038] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:16:59,742 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:16:59,743 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:16:59,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899763248] [2023-11-29 03:16:59,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:16:59,743 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:16:59,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:16:59,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:16:59,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:16:59,744 INFO L87 Difference]: Start difference. First operand 37078 states and 50928 transitions. cyclomatic complexity: 13882 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:00,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:00,048 INFO L93 Difference]: Finished difference Result 54939 states and 75292 transitions. [2023-11-29 03:17:00,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54939 states and 75292 transitions. [2023-11-29 03:17:00,285 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54480 [2023-11-29 03:17:00,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54939 states to 54939 states and 75292 transitions. [2023-11-29 03:17:00,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54939 [2023-11-29 03:17:00,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54939 [2023-11-29 03:17:00,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54939 states and 75292 transitions. [2023-11-29 03:17:00,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:00,498 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54939 states and 75292 transitions. [2023-11-29 03:17:00,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54939 states and 75292 transitions. [2023-11-29 03:17:01,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54939 to 54923. [2023-11-29 03:17:01,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54923 states, 54923 states have (on average 1.3705733481419442) internal successors, (75276), 54922 states have internal predecessors, (75276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:01,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54923 states to 54923 states and 75276 transitions. [2023-11-29 03:17:01,218 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54923 states and 75276 transitions. [2023-11-29 03:17:01,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:17:01,219 INFO L428 stractBuchiCegarLoop]: Abstraction has 54923 states and 75276 transitions. [2023-11-29 03:17:01,219 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 03:17:01,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54923 states and 75276 transitions. [2023-11-29 03:17:01,347 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54464 [2023-11-29 03:17:01,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:01,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:01,349 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:01,349 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:01,349 INFO L748 eck$LassoCheckResult]: Stem: 1085845#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1085846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1086959#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1086960#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1086312#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1086313#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1086180#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1086070#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1085788#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1085442#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1085443#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1085487#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1085488#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1086469#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1086470#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1086520#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1085886#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1085887#L1090 assume !(0 == ~M_E~0); 1085940#L1090-2 assume !(0 == ~T1_E~0); 1085941#L1095-1 assume !(0 == ~T2_E~0); 1086689#L1100-1 assume !(0 == ~T3_E~0); 1086690#L1105-1 assume !(0 == ~T4_E~0); 1085707#L1110-1 assume !(0 == ~T5_E~0); 1085708#L1115-1 assume !(0 == ~T6_E~0); 1086109#L1120-1 assume !(0 == ~T7_E~0); 1086437#L1125-1 assume !(0 == ~T8_E~0); 1087070#L1130-1 assume !(0 == ~T9_E~0); 1086709#L1135-1 assume !(0 == ~T10_E~0); 1085893#L1140-1 assume !(0 == ~T11_E~0); 1085894#L1145-1 assume !(0 == ~E_1~0); 1086641#L1150-1 assume !(0 == ~E_2~0); 1086086#L1155-1 assume !(0 == ~E_3~0); 1086087#L1160-1 assume !(0 == ~E_4~0); 1086185#L1165-1 assume !(0 == ~E_5~0); 1086186#L1170-1 assume !(0 == ~E_6~0); 1086936#L1175-1 assume !(0 == ~E_7~0); 1086268#L1180-1 assume !(0 == ~E_8~0); 1086269#L1185-1 assume !(0 == ~E_9~0); 1085888#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 1085889#L1195-1 assume !(0 == ~E_11~0); 1086906#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1086907#L525 assume !(1 == ~m_pc~0); 1087177#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1087175#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1087173#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1087170#L1350 assume !(0 != activate_threads_~tmp~1#1); 1087169#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1086341#L544 assume !(1 == ~t1_pc~0); 1086342#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1086638#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1085511#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1085512#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1086400#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1086401#L563 assume !(1 == ~t2_pc~0); 1086658#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1085551#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1085552#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1085964#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1085965#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1086639#L582 assume !(1 == ~t3_pc~0); 1086640#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1087011#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1085434#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1085435#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1087164#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1087093#L601 assume !(1 == ~t4_pc~0); 1086654#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1086729#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1087161#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1087160#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1087097#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1087098#L620 assume !(1 == ~t5_pc~0); 1086456#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1086457#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1087159#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1087122#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1087123#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1087073#L639 assume !(1 == ~t6_pc~0); 1087074#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1086002#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1086003#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1087023#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1086113#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1086114#L658 assume !(1 == ~t7_pc~0); 1086436#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1087037#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1087038#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1086572#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1085881#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1085882#L677 assume !(1 == ~t8_pc~0); 1086121#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1085695#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1085696#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1086732#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1087152#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1087151#L696 assume !(1 == ~t9_pc~0); 1086416#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1086417#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1087172#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1086446#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1086447#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1086694#L715 assume !(1 == ~t10_pc~0); 1087054#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1087055#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1086325#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1086326#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1086261#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1086262#L734 assume !(1 == ~t11_pc~0); 1087140#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1087139#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1087138#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1085432#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1085433#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1086512#L1213 assume !(1 == ~M_E~0); 1087136#L1213-2 assume !(1 == ~T1_E~0); 1087135#L1218-1 assume !(1 == ~T2_E~0); 1087134#L1223-1 assume !(1 == ~T3_E~0); 1087133#L1228-1 assume !(1 == ~T4_E~0); 1087027#L1233-1 assume !(1 == ~T5_E~0); 1087028#L1238-1 assume !(1 == ~T6_E~0); 1086646#L1243-1 assume !(1 == ~T7_E~0); 1086647#L1248-1 assume !(1 == ~T8_E~0); 1087130#L1253-1 assume !(1 == ~T9_E~0); 1086947#L1258-1 assume !(1 == ~T10_E~0); 1086672#L1263-1 assume !(1 == ~T11_E~0); 1086673#L1268-1 assume !(1 == ~E_1~0); 1086461#L1273-1 assume !(1 == ~E_2~0); 1086462#L1278-1 assume !(1 == ~E_3~0); 1085998#L1283-1 assume !(1 == ~E_4~0); 1085999#L1288-1 assume !(1 == ~E_5~0); 1087128#L1293-1 assume !(1 == ~E_6~0); 1087127#L1298-1 assume !(1 == ~E_7~0); 1086496#L1303-1 assume !(1 == ~E_8~0); 1086009#L1308-1 assume !(1 == ~E_9~0); 1085897#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1085898#L1318-1 assume !(1 == ~E_11~0); 1085909#L1323-1 assume { :end_inline_reset_delta_events } true; 1085910#L1644-2 [2023-11-29 03:17:01,349 INFO L750 eck$LassoCheckResult]: Loop: 1085910#L1644-2 assume !false; 1096012#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1096007#L1065-1 assume !false; 1096005#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1095993#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1095982#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1095980#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1095976#L906 assume !(0 != eval_~tmp~0#1); 1095977#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1096472#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1096471#L1090-3 assume !(0 == ~M_E~0); 1096470#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1096469#L1095-3 assume !(0 == ~T2_E~0); 1096467#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1096463#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1096461#L1110-3 assume !(0 == ~T5_E~0); 1096459#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1096457#L1120-3 assume !(0 == ~T7_E~0); 1096454#L1125-3 assume !(0 == ~T8_E~0); 1096452#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1096450#L1135-3 assume !(0 == ~T10_E~0); 1096448#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1096446#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1096444#L1150-3 assume !(0 == ~E_2~0); 1096442#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1096440#L1160-3 assume !(0 == ~E_4~0); 1096439#L1165-3 assume !(0 == ~E_5~0); 1096436#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1096434#L1175-3 assume !(0 == ~E_7~0); 1096432#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1096430#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1096427#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1096425#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1096423#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1096421#L525-36 assume !(1 == ~m_pc~0); 1096417#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1096415#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1096413#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1096411#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1096407#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1096405#L544-36 assume !(1 == ~t1_pc~0); 1096403#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1096401#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1096399#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1096397#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1096395#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1096391#L563-36 assume !(1 == ~t2_pc~0); 1096389#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1096387#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1096385#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1096383#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1096380#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1096378#L582-36 assume !(1 == ~t3_pc~0); 1096376#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1096374#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1096372#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1096369#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1096367#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1096365#L601-36 assume !(1 == ~t4_pc~0); 1096362#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1096360#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1096358#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1096356#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1096354#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1096352#L620-36 assume !(1 == ~t5_pc~0); 1096350#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1096348#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1096346#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1096345#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1096341#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1096339#L639-36 assume 1 == ~t6_pc~0; 1096336#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1096334#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1096331#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1096329#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1096327#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1096325#L658-36 assume !(1 == ~t7_pc~0); 1096322#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1096320#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1096318#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1096316#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1096314#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1096311#L677-36 assume !(1 == ~t8_pc~0); 1096309#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1096307#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1096305#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1096303#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1096301#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1096296#L696-36 assume !(1 == ~t9_pc~0); 1096294#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1096292#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1096290#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1096288#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1096285#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1096283#L715-36 assume !(1 == ~t10_pc~0); 1096281#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1096279#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1096277#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1096275#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1096273#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1096271#L734-36 assume !(1 == ~t11_pc~0); 1096268#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1096266#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1096264#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1096262#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1096260#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1096258#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1096257#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1096256#L1218-3 assume !(1 == ~T2_E~0); 1096255#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1096253#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1096252#L1233-3 assume !(1 == ~T5_E~0); 1096251#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1096250#L1243-3 assume !(1 == ~T7_E~0); 1096246#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1096244#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1096242#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1096240#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1096237#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1096235#L1273-3 assume !(1 == ~E_2~0); 1096233#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1096231#L1283-3 assume !(1 == ~E_4~0); 1096229#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1096227#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1096225#L1298-3 assume !(1 == ~E_7~0); 1096223#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1096220#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1096218#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1096215#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1096213#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1096198#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1096190#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1096188#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1096049#L1663 assume !(0 == start_simulation_~tmp~3#1); 1096047#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1096037#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1096026#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1096023#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1096021#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1096019#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1096017#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1096015#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1085910#L1644-2 [2023-11-29 03:17:01,350 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:01,350 INFO L85 PathProgramCache]: Analyzing trace with hash 735969430, now seen corresponding path program 1 times [2023-11-29 03:17:01,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:01,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091171687] [2023-11-29 03:17:01,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:01,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:01,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:01,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:01,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:01,401 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091171687] [2023-11-29 03:17:01,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091171687] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:01,401 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:01,401 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:17:01,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422868054] [2023-11-29 03:17:01,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:01,402 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:17:01,402 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:01,402 INFO L85 PathProgramCache]: Analyzing trace with hash -910896222, now seen corresponding path program 1 times [2023-11-29 03:17:01,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:01,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78451097] [2023-11-29 03:17:01,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:01,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:01,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:01,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:01,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:01,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78451097] [2023-11-29 03:17:01,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78451097] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:01,450 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:01,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:01,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709626281] [2023-11-29 03:17:01,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:01,450 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:01,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:01,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:17:01,451 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:17:01,451 INFO L87 Difference]: Start difference. First operand 54923 states and 75276 transitions. cyclomatic complexity: 20385 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:02,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:02,048 INFO L93 Difference]: Finished difference Result 103096 states and 141346 transitions. [2023-11-29 03:17:02,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103096 states and 141346 transitions. [2023-11-29 03:17:02,365 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 99808 [2023-11-29 03:17:02,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103096 states to 103096 states and 141346 transitions. [2023-11-29 03:17:02,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103096 [2023-11-29 03:17:02,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103096 [2023-11-29 03:17:02,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103096 states and 141346 transitions. [2023-11-29 03:17:02,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:02,644 INFO L218 hiAutomatonCegarLoop]: Abstraction has 103096 states and 141346 transitions. [2023-11-29 03:17:02,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103096 states and 141346 transitions. [2023-11-29 03:17:03,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103096 to 53038. [2023-11-29 03:17:03,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53038 states, 53038 states have (on average 1.3694143821411064) internal successors, (72631), 53037 states have internal predecessors, (72631), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:03,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53038 states to 53038 states and 72631 transitions. [2023-11-29 03:17:03,456 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53038 states and 72631 transitions. [2023-11-29 03:17:03,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:17:03,456 INFO L428 stractBuchiCegarLoop]: Abstraction has 53038 states and 72631 transitions. [2023-11-29 03:17:03,456 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 03:17:03,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53038 states and 72631 transitions. [2023-11-29 03:17:03,582 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52688 [2023-11-29 03:17:03,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:03,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:03,584 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:03,584 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:03,584 INFO L748 eck$LassoCheckResult]: Stem: 1243878#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1243879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1244956#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1244957#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1244339#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1244340#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1244209#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1244105#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1243821#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1243473#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1243474#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1243517#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1243518#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1244481#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1244482#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1244529#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1243925#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1243926#L1090 assume !(0 == ~M_E~0); 1243970#L1090-2 assume !(0 == ~T1_E~0); 1243971#L1095-1 assume !(0 == ~T2_E~0); 1244695#L1100-1 assume !(0 == ~T3_E~0); 1244696#L1105-1 assume !(0 == ~T4_E~0); 1243737#L1110-1 assume !(0 == ~T5_E~0); 1243738#L1115-1 assume !(0 == ~T6_E~0); 1244140#L1120-1 assume !(0 == ~T7_E~0); 1244454#L1125-1 assume !(0 == ~T8_E~0); 1245069#L1130-1 assume !(0 == ~T9_E~0); 1244720#L1135-1 assume !(0 == ~T10_E~0); 1243929#L1140-1 assume !(0 == ~T11_E~0); 1243930#L1145-1 assume !(0 == ~E_1~0); 1244647#L1150-1 assume !(0 == ~E_2~0); 1244119#L1155-1 assume !(0 == ~E_3~0); 1244120#L1160-1 assume !(0 == ~E_4~0); 1244214#L1165-1 assume !(0 == ~E_5~0); 1244215#L1170-1 assume !(0 == ~E_6~0); 1244933#L1175-1 assume !(0 == ~E_7~0); 1244299#L1180-1 assume !(0 == ~E_8~0); 1244300#L1185-1 assume !(0 == ~E_9~0); 1243923#L1190-1 assume !(0 == ~E_10~0); 1243924#L1195-1 assume !(0 == ~E_11~0); 1244315#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1244133#L525 assume !(1 == ~m_pc~0); 1243561#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1243562#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1244897#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1244784#L1350 assume !(0 != activate_threads_~tmp~1#1); 1243915#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1243916#L544 assume !(1 == ~t1_pc~0); 1244138#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1244139#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1243535#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1243536#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1243762#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1244423#L563 assume !(1 == ~t2_pc~0); 1244632#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1243581#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1243582#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1243996#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1243997#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1244507#L582 assume !(1 == ~t3_pc~0); 1244646#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1245022#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1243465#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1243466#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1243645#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1243646#L601 assume !(1 == ~t4_pc~0); 1244661#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1244141#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1243655#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1243656#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1244656#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1245008#L620 assume !(1 == ~t5_pc~0); 1244469#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1244470#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1244526#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1244817#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1245036#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1245037#L639 assume !(1 == ~t6_pc~0); 1244453#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1244036#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1244037#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1244088#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1244146#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1244147#L658 assume !(1 == ~t7_pc~0); 1244363#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1244364#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1245046#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1244583#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1243918#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1243919#L677 assume !(1 == ~t8_pc~0); 1243941#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1243721#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1243722#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1243992#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1243993#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1244775#L696 assume !(1 == ~t9_pc~0); 1244435#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1244436#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1244199#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1244200#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1244459#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1244701#L715 assume !(1 == ~t10_pc~0); 1244974#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1244562#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1244352#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1244353#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1244292#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1243715#L734 assume !(1 == ~t11_pc~0); 1243716#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1244216#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1244302#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1243461#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1243462#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1244527#L1213 assume !(1 == ~M_E~0); 1244288#L1213-2 assume !(1 == ~T1_E~0); 1244289#L1218-1 assume !(1 == ~T2_E~0); 1243496#L1223-1 assume !(1 == ~T3_E~0); 1243497#L1228-1 assume !(1 == ~T4_E~0); 1244261#L1233-1 assume !(1 == ~T5_E~0); 1245038#L1238-1 assume !(1 == ~T6_E~0); 1244654#L1243-1 assume !(1 == ~T7_E~0); 1244655#L1248-1 assume !(1 == ~T8_E~0); 1244707#L1253-1 assume !(1 == ~T9_E~0); 1244708#L1258-1 assume !(1 == ~T10_E~0); 1244678#L1263-1 assume !(1 == ~T11_E~0); 1244679#L1268-1 assume !(1 == ~E_1~0); 1244477#L1273-1 assume !(1 == ~E_2~0); 1244478#L1278-1 assume !(1 == ~E_3~0); 1244034#L1283-1 assume !(1 == ~E_4~0); 1244035#L1288-1 assume !(1 == ~E_5~0); 1244823#L1293-1 assume !(1 == ~E_6~0); 1244779#L1298-1 assume !(1 == ~E_7~0); 1244511#L1303-1 assume !(1 == ~E_8~0); 1244044#L1308-1 assume !(1 == ~E_9~0); 1243933#L1313-1 assume !(1 == ~E_10~0); 1243934#L1318-1 assume !(1 == ~E_11~0); 1243942#L1323-1 assume { :end_inline_reset_delta_events } true; 1243943#L1644-2 [2023-11-29 03:17:03,585 INFO L750 eck$LassoCheckResult]: Loop: 1243943#L1644-2 assume !false; 1251136#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1251131#L1065-1 assume !false; 1251129#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1251121#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1251110#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1251108#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1251105#L906 assume !(0 != eval_~tmp~0#1); 1251106#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1251428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1251427#L1090-3 assume !(0 == ~M_E~0); 1251426#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1251424#L1095-3 assume !(0 == ~T2_E~0); 1251423#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1251422#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1251421#L1110-3 assume !(0 == ~T5_E~0); 1251420#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1251419#L1120-3 assume !(0 == ~T7_E~0); 1251418#L1125-3 assume !(0 == ~T8_E~0); 1251417#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1251416#L1135-3 assume !(0 == ~T10_E~0); 1251415#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1251414#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1251413#L1150-3 assume !(0 == ~E_2~0); 1251412#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1251411#L1160-3 assume !(0 == ~E_4~0); 1251409#L1165-3 assume !(0 == ~E_5~0); 1251408#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1251407#L1175-3 assume !(0 == ~E_7~0); 1251406#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1251405#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1251403#L1190-3 assume !(0 == ~E_10~0); 1251402#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1251401#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1251400#L525-36 assume 1 == ~m_pc~0; 1251399#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1251397#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1251395#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1251392#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1251391#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1251390#L544-36 assume !(1 == ~t1_pc~0); 1251389#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1251388#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1251387#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1251385#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1251384#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1251382#L563-36 assume !(1 == ~t2_pc~0); 1251381#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1251377#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1251375#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1251373#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1251371#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1251368#L582-36 assume !(1 == ~t3_pc~0); 1251366#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1251364#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1251362#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1251360#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1251358#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1251356#L601-36 assume !(1 == ~t4_pc~0); 1251353#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1251350#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1251348#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1251346#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1251344#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1251342#L620-36 assume !(1 == ~t5_pc~0); 1251340#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1251338#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1251336#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1251334#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1251332#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1251330#L639-36 assume !(1 == ~t6_pc~0); 1251328#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1251324#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1251322#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1251320#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1251318#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1251316#L658-36 assume !(1 == ~t7_pc~0); 1251313#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1251311#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1251309#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1251307#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1251305#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1251303#L677-36 assume !(1 == ~t8_pc~0); 1251301#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1251299#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1251296#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1251294#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1251292#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1251285#L696-36 assume !(1 == ~t9_pc~0); 1251283#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1251281#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1251279#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1251277#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1251274#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1251272#L715-36 assume !(1 == ~t10_pc~0); 1251270#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1251268#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1251266#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1251264#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1251262#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1251258#L734-36 assume !(1 == ~t11_pc~0); 1251255#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1251253#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1251251#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1251248#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1251246#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1251244#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1251242#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1251240#L1218-3 assume !(1 == ~T2_E~0); 1251238#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1251236#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1251234#L1233-3 assume !(1 == ~T5_E~0); 1251232#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1251229#L1243-3 assume !(1 == ~T7_E~0); 1251227#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1251225#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1251223#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1251221#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1251219#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1251217#L1273-3 assume !(1 == ~E_2~0); 1251215#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1251213#L1283-3 assume !(1 == ~E_4~0); 1251211#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1251209#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1251207#L1298-3 assume !(1 == ~E_7~0); 1251205#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1251203#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1251201#L1313-3 assume !(1 == ~E_10~0); 1251199#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1251197#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1251182#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1251175#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1251173#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1251169#L1663 assume !(0 == start_simulation_~tmp~3#1); 1251168#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1251161#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1251150#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1251148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1251145#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1251143#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1251141#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1251139#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1243943#L1644-2 [2023-11-29 03:17:03,585 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:03,585 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 4 times [2023-11-29 03:17:03,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:03,585 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235638003] [2023-11-29 03:17:03,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:03,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:03,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:03,597 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:03,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:03,631 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:03,631 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:03,632 INFO L85 PathProgramCache]: Analyzing trace with hash -971106712, now seen corresponding path program 1 times [2023-11-29 03:17:03,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:03,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009923767] [2023-11-29 03:17:03,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:03,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:03,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:03,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:03,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:03,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009923767] [2023-11-29 03:17:03,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2009923767] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:03,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:03,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:03,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [177595413] [2023-11-29 03:17:03,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:03,679 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:03,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:03,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:03,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:03,679 INFO L87 Difference]: Start difference. First operand 53038 states and 72631 transitions. cyclomatic complexity: 19625 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:04,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:04,078 INFO L93 Difference]: Finished difference Result 98838 states and 134303 transitions. [2023-11-29 03:17:04,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98838 states and 134303 transitions. [2023-11-29 03:17:04,712 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98288 [2023-11-29 03:17:04,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98838 states to 98838 states and 134303 transitions. [2023-11-29 03:17:04,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98838 [2023-11-29 03:17:04,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98838 [2023-11-29 03:17:04,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98838 states and 134303 transitions. [2023-11-29 03:17:05,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:05,020 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98838 states and 134303 transitions. [2023-11-29 03:17:05,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98838 states and 134303 transitions. [2023-11-29 03:17:05,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98838 to 53182. [2023-11-29 03:17:05,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53182 states, 53182 states have (on average 1.3684141250799142) internal successors, (72775), 53181 states have internal predecessors, (72775), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:05,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53182 states to 53182 states and 72775 transitions. [2023-11-29 03:17:05,758 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53182 states and 72775 transitions. [2023-11-29 03:17:05,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 03:17:05,759 INFO L428 stractBuchiCegarLoop]: Abstraction has 53182 states and 72775 transitions. [2023-11-29 03:17:05,759 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-29 03:17:05,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53182 states and 72775 transitions. [2023-11-29 03:17:05,926 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52832 [2023-11-29 03:17:05,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:05,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:05,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:05,929 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:05,929 INFO L748 eck$LassoCheckResult]: Stem: 1395777#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1395778#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1396892#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1396893#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1396242#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1396243#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1396115#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1396002#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1395715#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1395366#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1395367#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1395411#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1395412#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1396398#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1396399#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1396449#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1395823#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1395824#L1090 assume !(0 == ~M_E~0); 1395873#L1090-2 assume !(0 == ~T1_E~0); 1395874#L1095-1 assume !(0 == ~T2_E~0); 1396614#L1100-1 assume !(0 == ~T3_E~0); 1396615#L1105-1 assume !(0 == ~T4_E~0); 1395634#L1110-1 assume !(0 == ~T5_E~0); 1395635#L1115-1 assume !(0 == ~T6_E~0); 1396039#L1120-1 assume !(0 == ~T7_E~0); 1396366#L1125-1 assume !(0 == ~T8_E~0); 1397021#L1130-1 assume !(0 == ~T9_E~0); 1396640#L1135-1 assume !(0 == ~T10_E~0); 1395829#L1140-1 assume !(0 == ~T11_E~0); 1395830#L1145-1 assume !(0 == ~E_1~0); 1396560#L1150-1 assume !(0 == ~E_2~0); 1396017#L1155-1 assume !(0 == ~E_3~0); 1396018#L1160-1 assume !(0 == ~E_4~0); 1396120#L1165-1 assume !(0 == ~E_5~0); 1396121#L1170-1 assume !(0 == ~E_6~0); 1396870#L1175-1 assume !(0 == ~E_7~0); 1396202#L1180-1 assume !(0 == ~E_8~0); 1396203#L1185-1 assume !(0 == ~E_9~0); 1395825#L1190-1 assume !(0 == ~E_10~0); 1395826#L1195-1 assume !(0 == ~E_11~0); 1396218#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1396034#L525 assume !(1 == ~m_pc~0); 1395455#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1395456#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1396832#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1396707#L1350 assume !(0 != activate_threads_~tmp~1#1); 1395815#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1395816#L544 assume !(1 == ~t1_pc~0); 1396035#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1396036#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1395435#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1395436#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1395657#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1396334#L563 assume !(1 == ~t2_pc~0); 1396547#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1395474#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1395475#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1395898#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1395899#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1396421#L582 assume !(1 == ~t3_pc~0); 1396559#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1396962#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1395358#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1395359#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1395539#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1395540#L601 assume !(1 == ~t4_pc~0); 1396577#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1396040#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1395553#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1395554#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1396570#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1396952#L620 assume !(1 == ~t5_pc~0); 1396385#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1396386#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1396441#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1396744#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1396973#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1396974#L639 assume !(1 == ~t6_pc~0); 1396364#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1395938#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1395939#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1395987#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1396045#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1396046#L658 assume !(1 == ~t7_pc~0); 1396269#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1396270#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1396989#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1396498#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1395818#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1395819#L677 assume !(1 == ~t8_pc~0); 1395842#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1395620#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1395621#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1395891#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1395892#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1396694#L696 assume !(1 == ~t9_pc~0); 1396350#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1396351#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1396102#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1396103#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1396374#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1396620#L715 assume !(1 == ~t10_pc~0); 1396913#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1396476#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1396255#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1396256#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1396195#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1395609#L734 assume !(1 == ~t11_pc~0); 1395610#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1396123#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1396207#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1395356#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1395357#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1396442#L1213 assume !(1 == ~M_E~0); 1396193#L1213-2 assume !(1 == ~T1_E~0); 1396194#L1218-1 assume !(1 == ~T2_E~0); 1395389#L1223-1 assume !(1 == ~T3_E~0); 1395390#L1228-1 assume !(1 == ~T4_E~0); 1396165#L1233-1 assume !(1 == ~T5_E~0); 1396975#L1238-1 assume !(1 == ~T6_E~0); 1396568#L1243-1 assume !(1 == ~T7_E~0); 1396569#L1248-1 assume !(1 == ~T8_E~0); 1396625#L1253-1 assume !(1 == ~T9_E~0); 1396626#L1258-1 assume !(1 == ~T10_E~0); 1396597#L1263-1 assume !(1 == ~T11_E~0); 1396598#L1268-1 assume !(1 == ~E_1~0); 1396390#L1273-1 assume !(1 == ~E_2~0); 1396391#L1278-1 assume !(1 == ~E_3~0); 1395934#L1283-1 assume !(1 == ~E_4~0); 1395935#L1288-1 assume !(1 == ~E_5~0); 1396751#L1293-1 assume !(1 == ~E_6~0); 1396703#L1298-1 assume !(1 == ~E_7~0); 1396425#L1303-1 assume !(1 == ~E_8~0); 1395944#L1308-1 assume !(1 == ~E_9~0); 1395833#L1313-1 assume !(1 == ~E_10~0); 1395834#L1318-1 assume !(1 == ~E_11~0); 1395843#L1323-1 assume { :end_inline_reset_delta_events } true; 1395844#L1644-2 [2023-11-29 03:17:05,930 INFO L750 eck$LassoCheckResult]: Loop: 1395844#L1644-2 assume !false; 1406062#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1406058#L1065-1 assume !false; 1406057#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1406054#L829 assume !(0 == ~m_st~0); 1406055#L833 assume !(0 == ~t1_st~0); 1406044#L837 assume !(0 == ~t2_st~0); 1406046#L841 assume !(0 == ~t3_st~0); 1406049#L845 assume !(0 == ~t4_st~0); 1406051#L849 assume !(0 == ~t5_st~0); 1406052#L853 assume !(0 == ~t6_st~0); 1406053#L857 assume !(0 == ~t7_st~0); 1406056#L861 assume !(0 == ~t8_st~0); 1406047#L865 assume !(0 == ~t9_st~0); 1406048#L869 assume !(0 == ~t10_st~0); 1406050#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 1405655#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1404626#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1404627#L906 assume !(0 != eval_~tmp~0#1); 1406379#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1406378#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1406377#L1090-3 assume !(0 == ~M_E~0); 1406376#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1406375#L1095-3 assume !(0 == ~T2_E~0); 1406374#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1406373#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1406372#L1110-3 assume !(0 == ~T5_E~0); 1406371#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1406370#L1120-3 assume !(0 == ~T7_E~0); 1406369#L1125-3 assume !(0 == ~T8_E~0); 1406368#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1406367#L1135-3 assume !(0 == ~T10_E~0); 1406366#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1406365#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1406364#L1150-3 assume !(0 == ~E_2~0); 1406363#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1406362#L1160-3 assume !(0 == ~E_4~0); 1406361#L1165-3 assume !(0 == ~E_5~0); 1406360#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1406359#L1175-3 assume !(0 == ~E_7~0); 1406358#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1406357#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1406356#L1190-3 assume !(0 == ~E_10~0); 1406355#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1406354#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1406353#L525-36 assume !(1 == ~m_pc~0); 1406352#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1406350#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1406348#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1406346#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1406344#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1406343#L544-36 assume !(1 == ~t1_pc~0); 1406342#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1406341#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1406340#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1406339#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1406338#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1406336#L563-36 assume !(1 == ~t2_pc~0); 1406335#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1406334#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1406333#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1406332#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1406331#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1406330#L582-36 assume !(1 == ~t3_pc~0); 1406329#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1406328#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1406327#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1406326#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1406325#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1406324#L601-36 assume !(1 == ~t4_pc~0); 1406322#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1406321#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1406320#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1406319#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1406318#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1406317#L620-36 assume !(1 == ~t5_pc~0); 1406316#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1406315#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1406314#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1406313#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1406312#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1406311#L639-36 assume 1 == ~t6_pc~0; 1406309#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1406308#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1406307#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1406306#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1406305#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1406304#L658-36 assume !(1 == ~t7_pc~0); 1406302#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1406301#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1406300#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1406299#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1406298#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1406297#L677-36 assume !(1 == ~t8_pc~0); 1406296#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1406295#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1406294#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1406293#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1406292#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1406291#L696-36 assume 1 == ~t9_pc~0; 1406289#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1406287#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1406285#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1406283#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1406282#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1406281#L715-36 assume !(1 == ~t10_pc~0); 1406280#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1406279#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1406278#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1406277#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1406276#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1406275#L734-36 assume !(1 == ~t11_pc~0); 1406273#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1406272#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1406271#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1406270#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1406269#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1406268#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1406267#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1406266#L1218-3 assume !(1 == ~T2_E~0); 1406265#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1406264#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1406263#L1233-3 assume !(1 == ~T5_E~0); 1406262#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1406261#L1243-3 assume !(1 == ~T7_E~0); 1406260#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1406259#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1406258#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1406257#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1406256#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1406255#L1273-3 assume !(1 == ~E_2~0); 1406254#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1406253#L1283-3 assume !(1 == ~E_4~0); 1406252#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1406251#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1406250#L1298-3 assume !(1 == ~E_7~0); 1406249#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1406248#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1406247#L1313-3 assume !(1 == ~E_10~0); 1406246#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1406245#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1406238#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1406229#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1406145#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1406136#L1663 assume !(0 == start_simulation_~tmp~3#1); 1406135#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1406132#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1406112#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1406104#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1406094#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1406087#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1406080#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1406073#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1395844#L1644-2 [2023-11-29 03:17:05,930 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:05,931 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 5 times [2023-11-29 03:17:05,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:05,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527117209] [2023-11-29 03:17:05,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:05,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:05,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:05,946 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:05,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:05,989 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:05,990 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:05,990 INFO L85 PathProgramCache]: Analyzing trace with hash 1843232279, now seen corresponding path program 1 times [2023-11-29 03:17:05,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:05,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885392987] [2023-11-29 03:17:05,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:05,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:06,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:06,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:06,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:06,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885392987] [2023-11-29 03:17:06,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885392987] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:06,051 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:06,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:17:06,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051037471] [2023-11-29 03:17:06,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:06,052 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:06,052 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:06,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:17:06,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:17:06,053 INFO L87 Difference]: Start difference. First operand 53182 states and 72775 transitions. cyclomatic complexity: 19625 Second operand has 3 states, 3 states have (on average 51.0) internal successors, (153), 3 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:06,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:06,686 INFO L93 Difference]: Finished difference Result 102438 states and 138975 transitions. [2023-11-29 03:17:06,686 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102438 states and 138975 transitions. [2023-11-29 03:17:07,056 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101888 [2023-11-29 03:17:07,272 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102438 states to 102438 states and 138975 transitions. [2023-11-29 03:17:07,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102438 [2023-11-29 03:17:07,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102438 [2023-11-29 03:17:07,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102438 states and 138975 transitions. [2023-11-29 03:17:07,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:07,355 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102438 states and 138975 transitions. [2023-11-29 03:17:07,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102438 states and 138975 transitions. [2023-11-29 03:17:08,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102438 to 98518. [2023-11-29 03:17:08,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98518 states, 98518 states have (on average 1.3586857224060578) internal successors, (133855), 98517 states have internal predecessors, (133855), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:08,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98518 states to 98518 states and 133855 transitions. [2023-11-29 03:17:08,446 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98518 states and 133855 transitions. [2023-11-29 03:17:08,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:17:08,446 INFO L428 stractBuchiCegarLoop]: Abstraction has 98518 states and 133855 transitions. [2023-11-29 03:17:08,446 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-29 03:17:08,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98518 states and 133855 transitions. [2023-11-29 03:17:08,692 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 97968 [2023-11-29 03:17:08,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:08,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:08,694 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:08,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:08,694 INFO L748 eck$LassoCheckResult]: Stem: 1551406#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1551407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1552581#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1552582#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1551878#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1551879#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1551743#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1551634#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1551347#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1550992#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1550993#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1551037#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1551038#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1552038#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1552039#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1552088#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1551453#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1551454#L1090 assume !(0 == ~M_E~0); 1551500#L1090-2 assume !(0 == ~T1_E~0); 1551501#L1095-1 assume !(0 == ~T2_E~0); 1552276#L1100-1 assume !(0 == ~T3_E~0); 1552277#L1105-1 assume !(0 == ~T4_E~0); 1551263#L1110-1 assume !(0 == ~T5_E~0); 1551264#L1115-1 assume !(0 == ~T6_E~0); 1551669#L1120-1 assume !(0 == ~T7_E~0); 1552010#L1125-1 assume !(0 == ~T8_E~0); 1552736#L1130-1 assume !(0 == ~T9_E~0); 1552303#L1135-1 assume !(0 == ~T10_E~0); 1551459#L1140-1 assume !(0 == ~T11_E~0); 1551460#L1145-1 assume !(0 == ~E_1~0); 1552216#L1150-1 assume !(0 == ~E_2~0); 1551649#L1155-1 assume !(0 == ~E_3~0); 1551650#L1160-1 assume !(0 == ~E_4~0); 1551750#L1165-1 assume !(0 == ~E_5~0); 1551751#L1170-1 assume !(0 == ~E_6~0); 1552559#L1175-1 assume !(0 == ~E_7~0); 1551832#L1180-1 assume !(0 == ~E_8~0); 1551833#L1185-1 assume !(0 == ~E_9~0); 1551455#L1190-1 assume !(0 == ~E_10~0); 1551456#L1195-1 assume !(0 == ~E_11~0); 1551848#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1551662#L525 assume !(1 == ~m_pc~0); 1551081#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1551082#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1552507#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1552366#L1350 assume !(0 != activate_threads_~tmp~1#1); 1551444#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1551445#L544 assume !(1 == ~t1_pc~0); 1551667#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1551668#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1551055#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1551056#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1551288#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1551973#L563 assume !(1 == ~t2_pc~0); 1552199#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1551103#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1551104#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1551524#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1551525#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1552066#L582 assume !(1 == ~t3_pc~0); 1552215#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1552654#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1550984#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1550985#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1551169#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1551170#L601 assume !(1 == ~t4_pc~0); 1552237#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1551670#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1551179#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1551180#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1552227#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1552645#L620 assume !(1 == ~t5_pc~0); 1552027#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1552028#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1552085#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1552411#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1552670#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1552671#L639 assume !(1 == ~t6_pc~0); 1552008#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1551564#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1551565#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1551617#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1551675#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1551676#L658 assume !(1 == ~t7_pc~0); 1551905#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1551906#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1552690#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1552146#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1551448#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1551449#L677 assume !(1 == ~t8_pc~0); 1551470#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1551246#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1551247#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1551520#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1551521#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1552355#L696 assume !(1 == ~t9_pc~0); 1551989#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1551990#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1551732#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1551733#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1552015#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1552283#L715 assume !(1 == ~t10_pc~0); 1552605#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1552124#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1551890#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1551891#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1551825#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1551240#L734 assume !(1 == ~t11_pc~0); 1551241#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1551752#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1551835#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1550980#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1550981#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1552086#L1213 assume !(1 == ~M_E~0); 1551822#L1213-2 assume !(1 == ~T1_E~0); 1551823#L1218-1 assume !(1 == ~T2_E~0); 1551015#L1223-1 assume !(1 == ~T3_E~0); 1551016#L1228-1 assume !(1 == ~T4_E~0); 1551798#L1233-1 assume !(1 == ~T5_E~0); 1552672#L1238-1 assume !(1 == ~T6_E~0); 1552225#L1243-1 assume !(1 == ~T7_E~0); 1552226#L1248-1 assume !(1 == ~T8_E~0); 1552290#L1253-1 assume !(1 == ~T9_E~0); 1552291#L1258-1 assume !(1 == ~T10_E~0); 1552258#L1263-1 assume !(1 == ~T11_E~0); 1552259#L1268-1 assume !(1 == ~E_1~0); 1552035#L1273-1 assume !(1 == ~E_2~0); 1552036#L1278-1 assume !(1 == ~E_3~0); 1551562#L1283-1 assume !(1 == ~E_4~0); 1551563#L1288-1 assume !(1 == ~E_5~0); 1552421#L1293-1 assume !(1 == ~E_6~0); 1552361#L1298-1 assume !(1 == ~E_7~0); 1552071#L1303-1 assume !(1 == ~E_8~0); 1551574#L1308-1 assume !(1 == ~E_9~0); 1551463#L1313-1 assume !(1 == ~E_10~0); 1551464#L1318-1 assume !(1 == ~E_11~0); 1551471#L1323-1 assume { :end_inline_reset_delta_events } true; 1551472#L1644-2 [2023-11-29 03:17:08,695 INFO L750 eck$LassoCheckResult]: Loop: 1551472#L1644-2 assume !false; 1582992#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1582987#L1065-1 assume !false; 1582985#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1582982#L829 assume !(0 == ~m_st~0); 1582983#L833 assume !(0 == ~t1_st~0); 1583812#L837 assume !(0 == ~t2_st~0); 1583809#L841 assume !(0 == ~t3_st~0); 1583807#L845 assume !(0 == ~t4_st~0); 1583805#L849 assume !(0 == ~t5_st~0); 1583803#L853 assume !(0 == ~t6_st~0); 1583801#L857 assume !(0 == ~t7_st~0); 1583800#L861 assume !(0 == ~t8_st~0); 1583796#L865 assume !(0 == ~t9_st~0); 1583794#L869 assume !(0 == ~t10_st~0); 1583791#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 1583788#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1583787#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1583785#L906 assume !(0 != eval_~tmp~0#1); 1583784#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1583783#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1583782#L1090-3 assume !(0 == ~M_E~0); 1583781#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1583780#L1095-3 assume !(0 == ~T2_E~0); 1583779#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1583777#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1583776#L1110-3 assume !(0 == ~T5_E~0); 1583775#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1583774#L1120-3 assume !(0 == ~T7_E~0); 1583772#L1125-3 assume !(0 == ~T8_E~0); 1583771#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1583770#L1135-3 assume !(0 == ~T10_E~0); 1583769#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1583768#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1583767#L1150-3 assume !(0 == ~E_2~0); 1583766#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1583765#L1160-3 assume !(0 == ~E_4~0); 1583764#L1165-3 assume !(0 == ~E_5~0); 1583763#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1583761#L1175-3 assume !(0 == ~E_7~0); 1583758#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1583756#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1583754#L1190-3 assume !(0 == ~E_10~0); 1583751#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1583749#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1583747#L525-36 assume 1 == ~m_pc~0; 1583745#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1583744#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1583742#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1583740#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1583739#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1583738#L544-36 assume !(1 == ~t1_pc~0); 1583734#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1583732#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1583730#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1583728#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1583723#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1583719#L563-36 assume !(1 == ~t2_pc~0); 1583717#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1583715#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1583713#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1583711#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1583709#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1583706#L582-36 assume !(1 == ~t3_pc~0); 1583704#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1583702#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1583700#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1583698#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1583696#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1583694#L601-36 assume !(1 == ~t4_pc~0); 1583691#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1583689#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1583687#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1583685#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1583683#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1583680#L620-36 assume !(1 == ~t5_pc~0); 1583678#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1583676#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1583674#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1583672#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1583670#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1583668#L639-36 assume 1 == ~t6_pc~0; 1583665#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1583663#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1583661#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1583659#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1583657#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1583655#L658-36 assume !(1 == ~t7_pc~0); 1583651#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1583649#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1583647#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1583645#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1583643#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1583640#L677-36 assume !(1 == ~t8_pc~0); 1583638#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1583636#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1583634#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1583632#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1583630#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1583625#L696-36 assume 1 == ~t9_pc~0; 1583626#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1583627#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1583773#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1583616#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1583612#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1583610#L715-36 assume !(1 == ~t10_pc~0); 1583608#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1583606#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1583603#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1583601#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1583599#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1583597#L734-36 assume !(1 == ~t11_pc~0); 1583594#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1583592#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1583590#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1583588#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1583586#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1583583#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1583581#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1583579#L1218-3 assume !(1 == ~T2_E~0); 1583577#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1583575#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1583574#L1233-3 assume !(1 == ~T5_E~0); 1583570#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1583568#L1243-3 assume !(1 == ~T7_E~0); 1583566#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1583563#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1583562#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1583560#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1583559#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1583558#L1273-3 assume !(1 == ~E_2~0); 1583554#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1583550#L1283-3 assume !(1 == ~E_4~0); 1583546#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1583542#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1583538#L1298-3 assume !(1 == ~E_7~0); 1583534#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1583530#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1583526#L1313-3 assume !(1 == ~E_10~0); 1583522#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1583518#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1583517#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1583516#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1583514#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1583012#L1663 assume !(0 == start_simulation_~tmp~3#1); 1583010#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1583007#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1583005#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1583003#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1583001#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1582999#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1582997#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1582995#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1551472#L1644-2 [2023-11-29 03:17:08,695 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:08,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 6 times [2023-11-29 03:17:08,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:08,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105150627] [2023-11-29 03:17:08,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:08,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:08,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:08,705 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:08,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:08,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:08,752 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:08,752 INFO L85 PathProgramCache]: Analyzing trace with hash 900696634, now seen corresponding path program 1 times [2023-11-29 03:17:08,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:08,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881637570] [2023-11-29 03:17:08,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:08,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:08,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:08,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:08,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:08,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881637570] [2023-11-29 03:17:08,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881637570] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:08,850 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:08,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:08,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203910846] [2023-11-29 03:17:08,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:08,851 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:08,851 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:08,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:08,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:08,852 INFO L87 Difference]: Start difference. First operand 98518 states and 133855 transitions. cyclomatic complexity: 35369 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:09,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:09,879 INFO L93 Difference]: Finished difference Result 183566 states and 247070 transitions. [2023-11-29 03:17:09,879 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 183566 states and 247070 transitions. [2023-11-29 03:17:10,476 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 182864 [2023-11-29 03:17:11,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 183566 states to 183566 states and 247070 transitions. [2023-11-29 03:17:11,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183566 [2023-11-29 03:17:11,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183566 [2023-11-29 03:17:11,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 183566 states and 247070 transitions. [2023-11-29 03:17:11,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:11,305 INFO L218 hiAutomatonCegarLoop]: Abstraction has 183566 states and 247070 transitions. [2023-11-29 03:17:11,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183566 states and 247070 transitions. [2023-11-29 03:17:12,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183566 to 99958. [2023-11-29 03:17:12,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99958 states, 99958 states have (on average 1.3491866583965266) internal successors, (134862), 99957 states have internal predecessors, (134862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:12,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99958 states to 99958 states and 134862 transitions. [2023-11-29 03:17:12,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99958 states and 134862 transitions. [2023-11-29 03:17:12,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:12,940 INFO L428 stractBuchiCegarLoop]: Abstraction has 99958 states and 134862 transitions. [2023-11-29 03:17:12,940 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2023-11-29 03:17:12,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99958 states and 134862 transitions. [2023-11-29 03:17:13,161 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99408 [2023-11-29 03:17:13,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:13,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:13,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:13,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:13,163 INFO L748 eck$LassoCheckResult]: Stem: 1833494#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1833495#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1834595#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1834596#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1833954#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1833955#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1833823#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1833713#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1833436#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1833088#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1833089#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1833133#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1833134#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1834101#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1834102#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1834152#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1833536#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1833537#L1090 assume !(0 == ~M_E~0); 1833580#L1090-2 assume !(0 == ~T1_E~0); 1833581#L1095-1 assume !(0 == ~T2_E~0); 1834320#L1100-1 assume !(0 == ~T3_E~0); 1834321#L1105-1 assume !(0 == ~T4_E~0); 1833355#L1110-1 assume !(0 == ~T5_E~0); 1833356#L1115-1 assume !(0 == ~T6_E~0); 1833751#L1120-1 assume !(0 == ~T7_E~0); 1834077#L1125-1 assume !(0 == ~T8_E~0); 1834724#L1130-1 assume !(0 == ~T9_E~0); 1834345#L1135-1 assume !(0 == ~T10_E~0); 1833542#L1140-1 assume !(0 == ~T11_E~0); 1833543#L1145-1 assume !(0 == ~E_1~0); 1834271#L1150-1 assume !(0 == ~E_2~0); 1833728#L1155-1 assume !(0 == ~E_3~0); 1833729#L1160-1 assume !(0 == ~E_4~0); 1833829#L1165-1 assume !(0 == ~E_5~0); 1833830#L1170-1 assume !(0 == ~E_6~0); 1834575#L1175-1 assume !(0 == ~E_7~0); 1833912#L1180-1 assume !(0 == ~E_8~0); 1833913#L1185-1 assume !(0 == ~E_9~0); 1833538#L1190-1 assume !(0 == ~E_10~0); 1833539#L1195-1 assume !(0 == ~E_11~0); 1833928#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1833744#L525 assume !(1 == ~m_pc~0); 1833177#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1833178#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1834532#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1834407#L1350 assume !(0 != activate_threads_~tmp~1#1); 1833528#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1833529#L544 assume !(1 == ~t1_pc~0); 1833749#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1833750#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1833151#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1833152#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1833379#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1834044#L563 assume !(1 == ~t2_pc~0); 1834256#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1833199#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1833200#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1833608#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1833609#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1834130#L582 assume !(1 == ~t3_pc~0); 1834270#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1834672#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1833080#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1833081#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1833262#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1833263#L601 assume !(1 == ~t4_pc~0); 1834285#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1833752#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1833272#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1833273#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1834280#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1834662#L620 assume !(1 == ~t5_pc~0); 1834091#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1834092#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1834149#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1834444#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1834684#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1834685#L639 assume !(1 == ~t6_pc~0); 1834076#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1833648#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1833649#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1833698#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1833757#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1833758#L658 assume !(1 == ~t7_pc~0); 1833980#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1833981#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1834696#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1834207#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1833531#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1833532#L677 assume !(1 == ~t8_pc~0); 1833553#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1833339#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1833340#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1833604#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1833605#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1834398#L696 assume !(1 == ~t9_pc~0); 1834057#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1834058#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1833813#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1833814#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1834082#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1834327#L715 assume !(1 == ~t10_pc~0); 1834617#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1834184#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1833968#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1833969#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1833905#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1833333#L734 assume !(1 == ~t11_pc~0); 1833334#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1833831#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1833915#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1833076#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1833077#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1834150#L1213 assume !(1 == ~M_E~0); 1833902#L1213-2 assume !(1 == ~T1_E~0); 1833903#L1218-1 assume !(1 == ~T2_E~0); 1833111#L1223-1 assume !(1 == ~T3_E~0); 1833112#L1228-1 assume !(1 == ~T4_E~0); 1833875#L1233-1 assume !(1 == ~T5_E~0); 1834686#L1238-1 assume !(1 == ~T6_E~0); 1834278#L1243-1 assume !(1 == ~T7_E~0); 1834279#L1248-1 assume !(1 == ~T8_E~0); 1834333#L1253-1 assume !(1 == ~T9_E~0); 1834334#L1258-1 assume !(1 == ~T10_E~0); 1834302#L1263-1 assume !(1 == ~T11_E~0); 1834303#L1268-1 assume !(1 == ~E_1~0); 1834098#L1273-1 assume !(1 == ~E_2~0); 1834099#L1278-1 assume !(1 == ~E_3~0); 1833646#L1283-1 assume !(1 == ~E_4~0); 1833647#L1288-1 assume !(1 == ~E_5~0); 1834450#L1293-1 assume !(1 == ~E_6~0); 1834403#L1298-1 assume !(1 == ~E_7~0); 1834134#L1303-1 assume !(1 == ~E_8~0); 1833656#L1308-1 assume !(1 == ~E_9~0); 1833546#L1313-1 assume !(1 == ~E_10~0); 1833547#L1318-1 assume !(1 == ~E_11~0); 1833554#L1323-1 assume { :end_inline_reset_delta_events } true; 1833555#L1644-2 [2023-11-29 03:17:13,163 INFO L750 eck$LassoCheckResult]: Loop: 1833555#L1644-2 assume !false; 1836267#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1836262#L1065-1 assume !false; 1836260#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1836257#L829 assume !(0 == ~m_st~0); 1836258#L833 assume !(0 == ~t1_st~0); 1837344#L837 assume !(0 == ~t2_st~0); 1837343#L841 assume !(0 == ~t3_st~0); 1837342#L845 assume !(0 == ~t4_st~0); 1837341#L849 assume !(0 == ~t5_st~0); 1837340#L853 assume !(0 == ~t6_st~0); 1837339#L857 assume !(0 == ~t7_st~0); 1837338#L861 assume !(0 == ~t8_st~0); 1837336#L865 assume !(0 == ~t9_st~0); 1837333#L869 assume !(0 == ~t10_st~0); 1837331#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 1837260#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1836908#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1836909#L906 assume !(0 != eval_~tmp~0#1); 1837256#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1837254#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1837250#L1090-3 assume !(0 == ~M_E~0); 1837248#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1837246#L1095-3 assume !(0 == ~T2_E~0); 1837244#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1837241#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1837239#L1110-3 assume !(0 == ~T5_E~0); 1837237#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1837235#L1120-3 assume !(0 == ~T7_E~0); 1837233#L1125-3 assume !(0 == ~T8_E~0); 1837231#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1837229#L1135-3 assume !(0 == ~T10_E~0); 1837227#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1837225#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1837222#L1150-3 assume !(0 == ~E_2~0); 1837220#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1837218#L1160-3 assume !(0 == ~E_4~0); 1837216#L1165-3 assume !(0 == ~E_5~0); 1837214#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1837015#L1175-3 assume !(0 == ~E_7~0); 1836990#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1836982#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1836969#L1190-3 assume !(0 == ~E_10~0); 1836957#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1836946#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1836936#L525-36 assume 1 == ~m_pc~0; 1836926#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1836917#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1836906#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1836904#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1836903#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1836902#L544-36 assume !(1 == ~t1_pc~0); 1836900#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1836897#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1836895#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1836892#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 1836887#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1836881#L563-36 assume !(1 == ~t2_pc~0); 1836875#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1836869#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1836865#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1836862#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1836858#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1836852#L582-36 assume !(1 == ~t3_pc~0); 1836847#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1836842#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1836836#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1836832#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1836829#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1836826#L601-36 assume !(1 == ~t4_pc~0); 1836822#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1836819#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1836816#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1836813#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1836809#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1836806#L620-36 assume !(1 == ~t5_pc~0); 1836803#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1836800#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1836797#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1836793#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 1836790#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1836787#L639-36 assume 1 == ~t6_pc~0; 1836783#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1836780#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1836777#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1836774#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1836770#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1836767#L658-36 assume !(1 == ~t7_pc~0); 1836763#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1836760#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1836757#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1836754#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1836750#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1836747#L677-36 assume !(1 == ~t8_pc~0); 1836744#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1836741#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1836738#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1836734#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1836731#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1836727#L696-36 assume !(1 == ~t9_pc~0); 1836724#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1836720#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1836716#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1836712#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1836707#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1836704#L715-36 assume !(1 == ~t10_pc~0); 1836701#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1836698#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1836695#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1836692#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1836688#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1836684#L734-36 assume 1 == ~t11_pc~0; 1836680#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1836675#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1836672#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1836669#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1836664#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1836661#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1836658#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1836655#L1218-3 assume !(1 == ~T2_E~0); 1836652#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1836650#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1836648#L1233-3 assume !(1 == ~T5_E~0); 1836646#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1836644#L1243-3 assume !(1 == ~T7_E~0); 1836642#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1836640#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1836638#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1836636#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1836633#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1836629#L1273-3 assume !(1 == ~E_2~0); 1836626#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1836621#L1283-3 assume !(1 == ~E_4~0); 1836617#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1836615#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1836613#L1298-3 assume !(1 == ~E_7~0); 1836604#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1836603#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1836601#L1313-3 assume !(1 == ~E_10~0); 1836600#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1836599#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1836594#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1836372#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1836361#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1836327#L1663 assume !(0 == start_simulation_~tmp~3#1); 1836325#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1836322#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1836319#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1836317#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1836305#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1836296#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1836288#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1836280#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1833555#L1644-2 [2023-11-29 03:17:13,164 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:13,164 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 7 times [2023-11-29 03:17:13,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:13,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848467285] [2023-11-29 03:17:13,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:13,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:13,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:13,179 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:13,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:13,211 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:13,212 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:13,212 INFO L85 PathProgramCache]: Analyzing trace with hash 771528758, now seen corresponding path program 1 times [2023-11-29 03:17:13,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:13,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629936340] [2023-11-29 03:17:13,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:13,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:13,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:13,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:13,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:13,288 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1629936340] [2023-11-29 03:17:13,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1629936340] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:13,288 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:13,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:13,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226856123] [2023-11-29 03:17:13,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:13,289 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:13,289 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:13,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:13,290 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:13,290 INFO L87 Difference]: Start difference. First operand 99958 states and 134862 transitions. cyclomatic complexity: 34936 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:13,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:13,765 INFO L93 Difference]: Finished difference Result 120998 states and 162389 transitions. [2023-11-29 03:17:13,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120998 states and 162389 transitions. [2023-11-29 03:17:14,187 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 120296 [2023-11-29 03:17:14,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120998 states to 120998 states and 162389 transitions. [2023-11-29 03:17:14,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120998 [2023-11-29 03:17:14,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120998 [2023-11-29 03:17:14,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120998 states and 162389 transitions. [2023-11-29 03:17:14,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:14,883 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120998 states and 162389 transitions. [2023-11-29 03:17:14,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120998 states and 162389 transitions. [2023-11-29 03:17:15,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120998 to 100102. [2023-11-29 03:17:15,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100102 states, 100102 states have (on average 1.3400431559808994) internal successors, (134141), 100101 states have internal predecessors, (134141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:16,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100102 states to 100102 states and 134141 transitions. [2023-11-29 03:17:16,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100102 states and 134141 transitions. [2023-11-29 03:17:16,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:16,094 INFO L428 stractBuchiCegarLoop]: Abstraction has 100102 states and 134141 transitions. [2023-11-29 03:17:16,095 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2023-11-29 03:17:16,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100102 states and 134141 transitions. [2023-11-29 03:17:16,276 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99552 [2023-11-29 03:17:16,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:16,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:16,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:16,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:16,278 INFO L748 eck$LassoCheckResult]: Stem: 2054469#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2054470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2055636#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2055637#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2054943#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2054944#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2054808#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2054695#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2054411#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2054056#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2054057#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2054101#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2054102#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2055101#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2055102#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2055156#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2054514#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2054515#L1090 assume !(0 == ~M_E~0); 2054560#L1090-2 assume !(0 == ~T1_E~0); 2054561#L1095-1 assume !(0 == ~T2_E~0); 2055334#L1100-1 assume !(0 == ~T3_E~0); 2055335#L1105-1 assume !(0 == ~T4_E~0); 2054327#L1110-1 assume !(0 == ~T5_E~0); 2054328#L1115-1 assume !(0 == ~T6_E~0); 2054731#L1120-1 assume !(0 == ~T7_E~0); 2055072#L1125-1 assume !(0 == ~T8_E~0); 2055790#L1130-1 assume !(0 == ~T9_E~0); 2055359#L1135-1 assume !(0 == ~T10_E~0); 2054520#L1140-1 assume !(0 == ~T11_E~0); 2054521#L1145-1 assume !(0 == ~E_1~0); 2055284#L1150-1 assume !(0 == ~E_2~0); 2054710#L1155-1 assume !(0 == ~E_3~0); 2054711#L1160-1 assume !(0 == ~E_4~0); 2054813#L1165-1 assume !(0 == ~E_5~0); 2054814#L1170-1 assume !(0 == ~E_6~0); 2055610#L1175-1 assume !(0 == ~E_7~0); 2054899#L1180-1 assume !(0 == ~E_8~0); 2054900#L1185-1 assume !(0 == ~E_9~0); 2054516#L1190-1 assume !(0 == ~E_10~0); 2054517#L1195-1 assume !(0 == ~E_11~0); 2054916#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2054724#L525 assume !(1 == ~m_pc~0); 2054145#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2054146#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2055558#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2055419#L1350 assume !(0 != activate_threads_~tmp~1#1); 2054506#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2054507#L544 assume !(1 == ~t1_pc~0); 2054729#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2054730#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2054119#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2054120#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2054354#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2055033#L563 assume !(1 == ~t2_pc~0); 2055268#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2054167#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2054168#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2054587#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2054588#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2055131#L582 assume !(1 == ~t3_pc~0); 2055283#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2055720#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2054048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2054049#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2054233#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2054234#L601 assume !(1 == ~t4_pc~0); 2055300#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2054732#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2054243#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2054244#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2055293#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2055709#L620 assume !(1 == ~t5_pc~0); 2055089#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2055090#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2055153#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2055463#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2055735#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2055736#L639 assume !(1 == ~t6_pc~0); 2055071#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2054627#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2054628#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2054681#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2054738#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2054739#L658 assume !(1 == ~t7_pc~0); 2054968#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2054969#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2055753#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2055216#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2054509#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2054510#L677 assume !(1 == ~t8_pc~0); 2054531#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2054311#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2054312#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2054583#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2054584#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2055408#L696 assume !(1 == ~t9_pc~0); 2055047#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2055048#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2054797#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2054798#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2055079#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2055341#L715 assume !(1 == ~t10_pc~0); 2055657#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2055193#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2054957#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2054958#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2054893#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2054305#L734 assume !(1 == ~t11_pc~0); 2054306#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2054815#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2054903#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2054044#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2054045#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2055154#L1213 assume !(1 == ~M_E~0); 2054890#L1213-2 assume !(1 == ~T1_E~0); 2054891#L1218-1 assume !(1 == ~T2_E~0); 2054079#L1223-1 assume !(1 == ~T3_E~0); 2054080#L1228-1 assume !(1 == ~T4_E~0); 2054862#L1233-1 assume !(1 == ~T5_E~0); 2055737#L1238-1 assume !(1 == ~T6_E~0); 2055291#L1243-1 assume !(1 == ~T7_E~0); 2055292#L1248-1 assume !(1 == ~T8_E~0); 2055345#L1253-1 assume !(1 == ~T9_E~0); 2055346#L1258-1 assume !(1 == ~T10_E~0); 2055318#L1263-1 assume !(1 == ~T11_E~0); 2055319#L1268-1 assume !(1 == ~E_1~0); 2055096#L1273-1 assume !(1 == ~E_2~0); 2055097#L1278-1 assume !(1 == ~E_3~0); 2054625#L1283-1 assume !(1 == ~E_4~0); 2054626#L1288-1 assume !(1 == ~E_5~0); 2055471#L1293-1 assume !(1 == ~E_6~0); 2055415#L1298-1 assume !(1 == ~E_7~0); 2055137#L1303-1 assume !(1 == ~E_8~0); 2054637#L1308-1 assume !(1 == ~E_9~0); 2054524#L1313-1 assume !(1 == ~E_10~0); 2054525#L1318-1 assume !(1 == ~E_11~0); 2054532#L1323-1 assume { :end_inline_reset_delta_events } true; 2054533#L1644-2 [2023-11-29 03:17:16,278 INFO L750 eck$LassoCheckResult]: Loop: 2054533#L1644-2 assume !false; 2115177#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2115170#L1065-1 assume !false; 2115168#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2115165#L829 assume !(0 == ~m_st~0); 2115166#L833 assume !(0 == ~t1_st~0); 2115563#L837 assume !(0 == ~t2_st~0); 2115561#L841 assume !(0 == ~t3_st~0); 2115557#L845 assume !(0 == ~t4_st~0); 2115555#L849 assume !(0 == ~t5_st~0); 2115553#L853 assume !(0 == ~t6_st~0); 2115551#L857 assume !(0 == ~t7_st~0); 2115548#L861 assume !(0 == ~t8_st~0); 2115546#L865 assume !(0 == ~t9_st~0); 2115544#L869 assume !(0 == ~t10_st~0); 2115541#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2115539#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2115537#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2115535#L906 assume !(0 != eval_~tmp~0#1); 2115533#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2115531#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2115528#L1090-3 assume !(0 == ~M_E~0); 2115526#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2115524#L1095-3 assume !(0 == ~T2_E~0); 2115522#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2115520#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2115516#L1110-3 assume !(0 == ~T5_E~0); 2115514#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2115512#L1120-3 assume !(0 == ~T7_E~0); 2115510#L1125-3 assume !(0 == ~T8_E~0); 2115509#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2115507#L1135-3 assume !(0 == ~T10_E~0); 2115504#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2115501#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2115497#L1150-3 assume !(0 == ~E_2~0); 2115493#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2115489#L1160-3 assume !(0 == ~E_4~0); 2115485#L1165-3 assume !(0 == ~E_5~0); 2115481#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2115479#L1175-3 assume !(0 == ~E_7~0); 2115477#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2115475#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2115473#L1190-3 assume !(0 == ~E_10~0); 2115471#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2115469#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2115467#L525-36 assume 1 == ~m_pc~0; 2115464#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2115461#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2115459#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2115456#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2115454#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2115452#L544-36 assume !(1 == ~t1_pc~0); 2115450#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2115448#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2115446#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2115444#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 2115442#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2115438#L563-36 assume !(1 == ~t2_pc~0); 2115435#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2115433#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2115431#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2115429#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 2115427#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2115425#L582-36 assume !(1 == ~t3_pc~0); 2115423#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2115421#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2115419#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2115417#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2115415#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2115413#L601-36 assume !(1 == ~t4_pc~0); 2115410#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2115407#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2115405#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2115403#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2115401#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2115399#L620-36 assume !(1 == ~t5_pc~0); 2115396#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2115394#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2115392#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2115390#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 2115388#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2115386#L639-36 assume 1 == ~t6_pc~0; 2115383#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2115381#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2115379#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2115377#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2115375#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2115373#L658-36 assume !(1 == ~t7_pc~0); 2115368#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2115366#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2115364#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2115362#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2115359#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2115357#L677-36 assume !(1 == ~t8_pc~0); 2115355#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2115353#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2115351#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2115349#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2115347#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2115340#L696-36 assume !(1 == ~t9_pc~0); 2115338#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2115336#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2115334#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2115332#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 2115330#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2115326#L715-36 assume !(1 == ~t10_pc~0); 2115324#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2115322#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2115319#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2115316#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2115314#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2115312#L734-36 assume !(1 == ~t11_pc~0); 2115309#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 2115307#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2115304#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2115302#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2115300#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2115298#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2115296#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2115294#L1218-3 assume !(1 == ~T2_E~0); 2115292#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2115290#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2115288#L1233-3 assume !(1 == ~T5_E~0); 2115286#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2115284#L1243-3 assume !(1 == ~T7_E~0); 2115282#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2115278#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2115276#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2115274#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2115272#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2115269#L1273-3 assume !(1 == ~E_2~0); 2115267#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2115265#L1283-3 assume !(1 == ~E_4~0); 2115263#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2115261#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2115259#L1298-3 assume !(1 == ~E_7~0); 2115257#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2115255#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2115253#L1313-3 assume !(1 == ~E_10~0); 2115250#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2115248#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2115245#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2115243#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2115241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2115193#L1663 assume !(0 == start_simulation_~tmp~3#1); 2115191#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2115189#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2115188#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2115187#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2115185#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2115183#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2115181#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2115178#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 2054533#L1644-2 [2023-11-29 03:17:16,279 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:16,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 8 times [2023-11-29 03:17:16,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:16,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165265543] [2023-11-29 03:17:16,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:16,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:16,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:16,291 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:16,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:16,329 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:16,329 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:16,329 INFO L85 PathProgramCache]: Analyzing trace with hash -1412485933, now seen corresponding path program 1 times [2023-11-29 03:17:16,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:16,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338910105] [2023-11-29 03:17:16,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:16,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:16,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:16,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:16,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:16,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338910105] [2023-11-29 03:17:16,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338910105] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:16,413 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:16,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:16,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480670] [2023-11-29 03:17:16,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:16,414 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:16,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:16,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:16,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:16,414 INFO L87 Difference]: Start difference. First operand 100102 states and 134141 transitions. cyclomatic complexity: 34071 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:17,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:17,023 INFO L93 Difference]: Finished difference Result 179510 states and 239160 transitions. [2023-11-29 03:17:17,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179510 states and 239160 transitions. [2023-11-29 03:17:17,973 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 178784 [2023-11-29 03:17:18,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179510 states to 179510 states and 239160 transitions. [2023-11-29 03:17:18,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179510 [2023-11-29 03:17:18,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179510 [2023-11-29 03:17:18,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179510 states and 239160 transitions. [2023-11-29 03:17:18,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:18,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179510 states and 239160 transitions. [2023-11-29 03:17:18,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179510 states and 239160 transitions. [2023-11-29 03:17:19,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179510 to 101542. [2023-11-29 03:17:19,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101542 states, 101542 states have (on average 1.3309566484804318) internal successors, (135148), 101541 states have internal predecessors, (135148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:19,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101542 states to 101542 states and 135148 transitions. [2023-11-29 03:17:19,873 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101542 states and 135148 transitions. [2023-11-29 03:17:19,873 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:19,874 INFO L428 stractBuchiCegarLoop]: Abstraction has 101542 states and 135148 transitions. [2023-11-29 03:17:19,874 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2023-11-29 03:17:19,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101542 states and 135148 transitions. [2023-11-29 03:17:20,123 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 100992 [2023-11-29 03:17:20,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:20,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:20,125 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:20,125 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:20,125 INFO L748 eck$LassoCheckResult]: Stem: 2334085#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2334086#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2335214#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2335215#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2334553#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2334554#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2334421#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2334311#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2334028#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2333680#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2333681#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2333725#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2333726#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2334710#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2334711#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2334758#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2334132#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2334133#L1090 assume !(0 == ~M_E~0); 2334178#L1090-2 assume !(0 == ~T1_E~0); 2334179#L1095-1 assume !(0 == ~T2_E~0); 2334922#L1100-1 assume !(0 == ~T3_E~0); 2334923#L1105-1 assume !(0 == ~T4_E~0); 2333945#L1110-1 assume !(0 == ~T5_E~0); 2333946#L1115-1 assume !(0 == ~T6_E~0); 2334347#L1120-1 assume !(0 == ~T7_E~0); 2334683#L1125-1 assume !(0 == ~T8_E~0); 2335341#L1130-1 assume !(0 == ~T9_E~0); 2334947#L1135-1 assume !(0 == ~T10_E~0); 2334138#L1140-1 assume !(0 == ~T11_E~0); 2334139#L1145-1 assume !(0 == ~E_1~0); 2334872#L1150-1 assume !(0 == ~E_2~0); 2334325#L1155-1 assume !(0 == ~E_3~0); 2334326#L1160-1 assume !(0 == ~E_4~0); 2334426#L1165-1 assume !(0 == ~E_5~0); 2334427#L1170-1 assume !(0 == ~E_6~0); 2335188#L1175-1 assume !(0 == ~E_7~0); 2334511#L1180-1 assume !(0 == ~E_8~0); 2334512#L1185-1 assume !(0 == ~E_9~0); 2334134#L1190-1 assume !(0 == ~E_10~0); 2334135#L1195-1 assume !(0 == ~E_11~0); 2334527#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2334340#L525 assume !(1 == ~m_pc~0); 2333769#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2333770#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2335146#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2335010#L1350 assume !(0 != activate_threads_~tmp~1#1); 2334123#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2334124#L544 assume !(1 == ~t1_pc~0); 2334345#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2334346#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2333744#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2333745#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2333970#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2334648#L563 assume !(1 == ~t2_pc~0); 2334857#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2333788#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2333789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2334206#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2334207#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2334738#L582 assume !(1 == ~t3_pc~0); 2334871#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2335293#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2333672#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2333673#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2333853#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2333854#L601 assume !(1 == ~t4_pc~0); 2334886#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2334348#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2333863#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2333864#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2334881#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2335283#L620 assume !(1 == ~t5_pc~0); 2334699#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2334700#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2334755#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2335048#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2335305#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2335306#L639 assume !(1 == ~t6_pc~0); 2334681#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2334245#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2334246#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2334295#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2334354#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2334355#L658 assume !(1 == ~t7_pc~0); 2334578#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2334579#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2335315#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2334813#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2334126#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2334127#L677 assume !(1 == ~t8_pc~0); 2334149#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2333928#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2333929#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2334202#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2334203#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2335000#L696 assume !(1 == ~t9_pc~0); 2334661#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2334662#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2334410#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2334411#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2334688#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2334927#L715 assume !(1 == ~t10_pc~0); 2335241#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2334791#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2334565#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2334566#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2334504#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2333922#L734 assume !(1 == ~t11_pc~0); 2333923#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2334428#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2334514#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2333668#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2333669#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2334756#L1213 assume !(1 == ~M_E~0); 2334501#L1213-2 assume !(1 == ~T1_E~0); 2334502#L1218-1 assume !(1 == ~T2_E~0); 2333703#L1223-1 assume !(1 == ~T3_E~0); 2333704#L1228-1 assume !(1 == ~T4_E~0); 2334475#L1233-1 assume !(1 == ~T5_E~0); 2335307#L1238-1 assume !(1 == ~T6_E~0); 2334879#L1243-1 assume !(1 == ~T7_E~0); 2334880#L1248-1 assume !(1 == ~T8_E~0); 2334934#L1253-1 assume !(1 == ~T9_E~0); 2334935#L1258-1 assume !(1 == ~T10_E~0); 2334906#L1263-1 assume !(1 == ~T11_E~0); 2334907#L1268-1 assume !(1 == ~E_1~0); 2334707#L1273-1 assume !(1 == ~E_2~0); 2334708#L1278-1 assume !(1 == ~E_3~0); 2334243#L1283-1 assume !(1 == ~E_4~0); 2334244#L1288-1 assume !(1 == ~E_5~0); 2335056#L1293-1 assume !(1 == ~E_6~0); 2335005#L1298-1 assume !(1 == ~E_7~0); 2334742#L1303-1 assume !(1 == ~E_8~0); 2334253#L1308-1 assume !(1 == ~E_9~0); 2334142#L1313-1 assume !(1 == ~E_10~0); 2334143#L1318-1 assume !(1 == ~E_11~0); 2334150#L1323-1 assume { :end_inline_reset_delta_events } true; 2334151#L1644-2 [2023-11-29 03:17:20,126 INFO L750 eck$LassoCheckResult]: Loop: 2334151#L1644-2 assume !false; 2349066#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2349061#L1065-1 assume !false; 2349059#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2349056#L829 assume !(0 == ~m_st~0); 2349057#L833 assume !(0 == ~t1_st~0); 2349529#L837 assume !(0 == ~t2_st~0); 2349526#L841 assume !(0 == ~t3_st~0); 2349524#L845 assume !(0 == ~t4_st~0); 2349522#L849 assume !(0 == ~t5_st~0); 2349520#L853 assume !(0 == ~t6_st~0); 2349518#L857 assume !(0 == ~t7_st~0); 2349516#L861 assume !(0 == ~t8_st~0); 2349514#L865 assume !(0 == ~t9_st~0); 2349512#L869 assume !(0 == ~t10_st~0); 2349509#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2349507#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2349505#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2349502#L906 assume !(0 != eval_~tmp~0#1); 2349499#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2349497#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2349495#L1090-3 assume !(0 == ~M_E~0); 2349493#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2349491#L1095-3 assume !(0 == ~T2_E~0); 2349489#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2349487#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2349485#L1110-3 assume !(0 == ~T5_E~0); 2349483#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2349481#L1120-3 assume !(0 == ~T7_E~0); 2349479#L1125-3 assume !(0 == ~T8_E~0); 2349477#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2349475#L1135-3 assume !(0 == ~T10_E~0); 2349472#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2349470#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2349468#L1150-3 assume !(0 == ~E_2~0); 2349466#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2349464#L1160-3 assume !(0 == ~E_4~0); 2349461#L1165-3 assume !(0 == ~E_5~0); 2349459#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2349457#L1175-3 assume !(0 == ~E_7~0); 2349455#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2349453#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2349451#L1190-3 assume !(0 == ~E_10~0); 2349449#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2349447#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2349445#L525-36 assume 1 == ~m_pc~0; 2349442#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2349440#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2349438#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2349436#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2349432#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2349430#L544-36 assume !(1 == ~t1_pc~0); 2349428#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2349426#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2349423#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2349421#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 2349419#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2349415#L563-36 assume !(1 == ~t2_pc~0); 2349413#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2349411#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2349409#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2349407#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 2349404#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2349402#L582-36 assume !(1 == ~t3_pc~0); 2349400#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2349398#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2349396#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2349394#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 2349392#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2349390#L601-36 assume !(1 == ~t4_pc~0); 2349387#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2349385#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2349383#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2349381#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2349379#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2349377#L620-36 assume !(1 == ~t5_pc~0); 2349375#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2349373#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2349371#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2349369#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 2349367#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2349365#L639-36 assume !(1 == ~t6_pc~0); 2349363#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2349360#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2349358#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2349356#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2349354#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2349352#L658-36 assume !(1 == ~t7_pc~0); 2349349#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2349347#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2349345#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2349343#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2349342#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2349341#L677-36 assume !(1 == ~t8_pc~0); 2349340#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2349339#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2349338#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2349337#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2349336#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2349335#L696-36 assume 1 == ~t9_pc~0; 2349334#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2349332#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2349330#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2349327#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2349326#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2349315#L715-36 assume !(1 == ~t10_pc~0); 2349313#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2349311#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2349308#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2349306#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2349304#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2349301#L734-36 assume 1 == ~t11_pc~0; 2349299#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2349296#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2349295#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2349294#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2349292#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2349291#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2349290#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2349289#L1218-3 assume !(1 == ~T2_E~0); 2349285#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2349283#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2349281#L1233-3 assume !(1 == ~T5_E~0); 2349279#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2349274#L1243-3 assume !(1 == ~T7_E~0); 2349272#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2349270#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2349268#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2349266#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2349264#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2349262#L1273-3 assume !(1 == ~E_2~0); 2349260#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2349257#L1283-3 assume !(1 == ~E_4~0); 2349255#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2349253#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2349251#L1298-3 assume !(1 == ~E_7~0); 2349249#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2349247#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2349245#L1313-3 assume !(1 == ~E_10~0); 2349243#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2349241#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2349238#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2349236#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2349234#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2349090#L1663 assume !(0 == start_simulation_~tmp~3#1); 2349087#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2349084#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2349082#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2349080#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2349078#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2349074#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2349072#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2349070#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 2334151#L1644-2 [2023-11-29 03:17:20,126 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:20,126 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 9 times [2023-11-29 03:17:20,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:20,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398184819] [2023-11-29 03:17:20,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:20,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:20,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:20,136 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:20,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:20,177 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:20,177 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:20,177 INFO L85 PathProgramCache]: Analyzing trace with hash -1322682828, now seen corresponding path program 1 times [2023-11-29 03:17:20,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:20,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568538532] [2023-11-29 03:17:20,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:20,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:20,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:20,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:20,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:20,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568538532] [2023-11-29 03:17:20,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568538532] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:20,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:20,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:20,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631670437] [2023-11-29 03:17:20,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:20,258 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:20,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:20,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:20,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:20,258 INFO L87 Difference]: Start difference. First operand 101542 states and 135148 transitions. cyclomatic complexity: 33638 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:20,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:20,699 INFO L93 Difference]: Finished difference Result 128150 states and 169063 transitions. [2023-11-29 03:17:20,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128150 states and 169063 transitions. [2023-11-29 03:17:21,500 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 127424 [2023-11-29 03:17:21,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128150 states to 128150 states and 169063 transitions. [2023-11-29 03:17:21,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128150 [2023-11-29 03:17:21,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128150 [2023-11-29 03:17:21,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128150 states and 169063 transitions. [2023-11-29 03:17:21,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:21,775 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128150 states and 169063 transitions. [2023-11-29 03:17:21,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128150 states and 169063 transitions. [2023-11-29 03:17:22,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128150 to 101686. [2023-11-29 03:17:22,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101686 states, 101686 states have (on average 1.3219813937021812) internal successors, (134427), 101685 states have internal predecessors, (134427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:22,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101686 states to 101686 states and 134427 transitions. [2023-11-29 03:17:22,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101686 states and 134427 transitions. [2023-11-29 03:17:22,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:22,932 INFO L428 stractBuchiCegarLoop]: Abstraction has 101686 states and 134427 transitions. [2023-11-29 03:17:22,932 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2023-11-29 03:17:22,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101686 states and 134427 transitions. [2023-11-29 03:17:23,177 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101136 [2023-11-29 03:17:23,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:23,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:23,178 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:23,178 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:23,179 INFO L748 eck$LassoCheckResult]: Stem: 2563791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2563792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2564964#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2564965#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2564270#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2564271#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2564136#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2564021#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2563734#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2563384#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2563385#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2563429#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2563430#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2564429#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2564430#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2564484#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2563839#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2563840#L1090 assume !(0 == ~M_E~0); 2563883#L1090-2 assume !(0 == ~T1_E~0); 2563884#L1095-1 assume !(0 == ~T2_E~0); 2564662#L1100-1 assume !(0 == ~T3_E~0); 2564663#L1105-1 assume !(0 == ~T4_E~0); 2563648#L1110-1 assume !(0 == ~T5_E~0); 2563649#L1115-1 assume !(0 == ~T6_E~0); 2564058#L1120-1 assume !(0 == ~T7_E~0); 2564401#L1125-1 assume !(0 == ~T8_E~0); 2565113#L1130-1 assume !(0 == ~T9_E~0); 2564685#L1135-1 assume !(0 == ~T10_E~0); 2563843#L1140-1 assume !(0 == ~T11_E~0); 2563844#L1145-1 assume !(0 == ~E_1~0); 2564608#L1150-1 assume !(0 == ~E_2~0); 2564036#L1155-1 assume !(0 == ~E_3~0); 2564037#L1160-1 assume !(0 == ~E_4~0); 2564141#L1165-1 assume !(0 == ~E_5~0); 2564142#L1170-1 assume !(0 == ~E_6~0); 2564934#L1175-1 assume !(0 == ~E_7~0); 2564228#L1180-1 assume !(0 == ~E_8~0); 2564229#L1185-1 assume !(0 == ~E_9~0); 2563837#L1190-1 assume !(0 == ~E_10~0); 2563838#L1195-1 assume !(0 == ~E_11~0); 2564244#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2564051#L525 assume !(1 == ~m_pc~0); 2563474#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2563475#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2564886#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2564750#L1350 assume !(0 != activate_threads_~tmp~1#1); 2563828#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2563829#L544 assume !(1 == ~t1_pc~0); 2564056#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2564057#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2563448#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2563449#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2563673#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2564366#L563 assume !(1 == ~t2_pc~0); 2564592#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2563493#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2563494#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2563912#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2563913#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2564459#L582 assume !(1 == ~t3_pc~0); 2564607#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2565048#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2563376#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2563377#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2563557#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2563558#L601 assume !(1 == ~t4_pc~0); 2564626#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2564059#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2563567#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2563568#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2564620#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2565034#L620 assume !(1 == ~t5_pc~0); 2564417#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2564418#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2564481#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2564787#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2565063#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2565064#L639 assume !(1 == ~t6_pc~0); 2564399#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2563951#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2563952#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2564005#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2564065#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2564066#L658 assume !(1 == ~t7_pc~0); 2564300#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2564301#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2565077#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2564539#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2563832#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2563833#L677 assume !(1 == ~t8_pc~0); 2563855#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2563632#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2563633#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2563907#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2563908#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2564743#L696 assume !(1 == ~t9_pc~0); 2564379#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2564380#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2564126#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2564127#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2564407#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2564667#L715 assume !(1 == ~t10_pc~0); 2564988#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2564516#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2564285#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2564286#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2564222#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2563626#L734 assume !(1 == ~t11_pc~0); 2563627#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2564143#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2564231#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2563372#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2563373#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2564482#L1213 assume !(1 == ~M_E~0); 2564219#L1213-2 assume !(1 == ~T1_E~0); 2564220#L1218-1 assume !(1 == ~T2_E~0); 2563407#L1223-1 assume !(1 == ~T3_E~0); 2563408#L1228-1 assume !(1 == ~T4_E~0); 2564189#L1233-1 assume !(1 == ~T5_E~0); 2565065#L1238-1 assume !(1 == ~T6_E~0); 2564618#L1243-1 assume !(1 == ~T7_E~0); 2564619#L1248-1 assume !(1 == ~T8_E~0); 2564672#L1253-1 assume !(1 == ~T9_E~0); 2564673#L1258-1 assume !(1 == ~T10_E~0); 2564645#L1263-1 assume !(1 == ~T11_E~0); 2564646#L1268-1 assume !(1 == ~E_1~0); 2564425#L1273-1 assume !(1 == ~E_2~0); 2564426#L1278-1 assume !(1 == ~E_3~0); 2563949#L1283-1 assume !(1 == ~E_4~0); 2563950#L1288-1 assume !(1 == ~E_5~0); 2564794#L1293-1 assume !(1 == ~E_6~0); 2564747#L1298-1 assume !(1 == ~E_7~0); 2564465#L1303-1 assume !(1 == ~E_8~0); 2563961#L1308-1 assume !(1 == ~E_9~0); 2563847#L1313-1 assume !(1 == ~E_10~0); 2563848#L1318-1 assume !(1 == ~E_11~0); 2563856#L1323-1 assume { :end_inline_reset_delta_events } true; 2563857#L1644-2 [2023-11-29 03:17:23,179 INFO L750 eck$LassoCheckResult]: Loop: 2563857#L1644-2 assume !false; 2580221#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2580217#L1065-1 assume !false; 2580215#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2580212#L829 assume !(0 == ~m_st~0); 2580213#L833 assume !(0 == ~t1_st~0); 2586286#L837 assume !(0 == ~t2_st~0); 2586284#L841 assume !(0 == ~t3_st~0); 2586282#L845 assume !(0 == ~t4_st~0); 2586280#L849 assume !(0 == ~t5_st~0); 2586278#L853 assume !(0 == ~t6_st~0); 2586275#L857 assume !(0 == ~t7_st~0); 2586273#L861 assume !(0 == ~t8_st~0); 2586271#L865 assume !(0 == ~t9_st~0); 2586269#L869 assume !(0 == ~t10_st~0); 2586266#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2586265#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2586261#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2586259#L906 assume !(0 != eval_~tmp~0#1); 2586257#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2586254#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2586253#L1090-3 assume !(0 == ~M_E~0); 2586252#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2586251#L1095-3 assume !(0 == ~T2_E~0); 2586250#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2586249#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2586248#L1110-3 assume !(0 == ~T5_E~0); 2586247#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2586245#L1120-3 assume !(0 == ~T7_E~0); 2586244#L1125-3 assume !(0 == ~T8_E~0); 2586243#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2586241#L1135-3 assume !(0 == ~T10_E~0); 2586240#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2586239#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2586238#L1150-3 assume !(0 == ~E_2~0); 2586237#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2586236#L1160-3 assume !(0 == ~E_4~0); 2586235#L1165-3 assume !(0 == ~E_5~0); 2586234#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2586233#L1175-3 assume !(0 == ~E_7~0); 2586231#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2586229#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2586227#L1190-3 assume !(0 == ~E_10~0); 2586226#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2586224#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2586222#L525-36 assume 1 == ~m_pc~0; 2586219#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2586217#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2586215#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2586212#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2586211#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2586208#L544-36 assume !(1 == ~t1_pc~0); 2586206#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2586204#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2586202#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2586200#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 2586198#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2586194#L563-36 assume !(1 == ~t2_pc~0); 2586192#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2586190#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2586188#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2586186#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 2586183#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2586181#L582-36 assume !(1 == ~t3_pc~0); 2586179#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2586177#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2586175#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2586173#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 2586171#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586169#L601-36 assume !(1 == ~t4_pc~0); 2586166#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2586164#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2586162#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2586160#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 2586158#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2586155#L620-36 assume !(1 == ~t5_pc~0); 2586153#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2586151#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2586149#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2586147#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 2586144#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2586142#L639-36 assume !(1 == ~t6_pc~0); 2586140#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2586137#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2586135#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2586133#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2586131#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2586129#L658-36 assume !(1 == ~t7_pc~0); 2586126#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2586124#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2586122#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2586120#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2586119#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2586115#L677-36 assume !(1 == ~t8_pc~0); 2586113#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2586111#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2586109#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2586106#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2586104#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2586099#L696-36 assume 1 == ~t9_pc~0; 2586100#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2586101#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2586246#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2586090#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2586088#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2586085#L715-36 assume !(1 == ~t10_pc~0); 2586083#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2586081#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2586079#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2586077#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2586075#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2586073#L734-36 assume 1 == ~t11_pc~0; 2586071#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2586068#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2586066#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2586064#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2586062#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2586060#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2586058#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2586056#L1218-3 assume !(1 == ~T2_E~0); 2586054#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2586052#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2586050#L1233-3 assume !(1 == ~T5_E~0); 2586048#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2586046#L1243-3 assume !(1 == ~T7_E~0); 2586044#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2586042#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2586040#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2586038#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2586036#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2586034#L1273-3 assume !(1 == ~E_2~0); 2586032#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2586030#L1283-3 assume !(1 == ~E_4~0); 2586028#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2586026#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2586025#L1298-3 assume !(1 == ~E_7~0); 2586024#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2586023#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2586022#L1313-3 assume !(1 == ~E_10~0); 2586021#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2586020#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2586019#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2586018#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2586017#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2585791#L1663 assume !(0 == start_simulation_~tmp~3#1); 2585789#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2585786#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2585784#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2585782#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2585780#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2585777#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2585775#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2585773#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 2563857#L1644-2 [2023-11-29 03:17:23,179 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:23,179 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 10 times [2023-11-29 03:17:23,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:23,180 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462045076] [2023-11-29 03:17:23,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:23,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:23,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:23,188 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:23,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:23,215 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:23,216 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:23,216 INFO L85 PathProgramCache]: Analyzing trace with hash 1829782002, now seen corresponding path program 1 times [2023-11-29 03:17:23,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:23,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824431896] [2023-11-29 03:17:23,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:23,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:23,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:23,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:23,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:23,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824431896] [2023-11-29 03:17:23,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824431896] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:23,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:23,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:23,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541810334] [2023-11-29 03:17:23,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:23,274 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:23,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:23,274 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:23,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:23,274 INFO L87 Difference]: Start difference. First operand 101686 states and 134427 transitions. cyclomatic complexity: 32773 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:24,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:24,363 INFO L93 Difference]: Finished difference Result 235771 states and 309717 transitions. [2023-11-29 03:17:24,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235771 states and 309717 transitions. [2023-11-29 03:17:25,255 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 234720 [2023-11-29 03:17:25,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235771 states to 235771 states and 309717 transitions. [2023-11-29 03:17:25,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 235771 [2023-11-29 03:17:25,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 235771 [2023-11-29 03:17:25,761 INFO L73 IsDeterministic]: Start isDeterministic. Operand 235771 states and 309717 transitions. [2023-11-29 03:17:25,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:25,826 INFO L218 hiAutomatonCegarLoop]: Abstraction has 235771 states and 309717 transitions. [2023-11-29 03:17:26,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235771 states and 309717 transitions. [2023-11-29 03:17:27,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235771 to 104425. [2023-11-29 03:17:27,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104425 states, 104425 states have (on average 1.313536030644003) internal successors, (137166), 104424 states have internal predecessors, (137166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:27,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104425 states to 104425 states and 137166 transitions. [2023-11-29 03:17:27,311 INFO L240 hiAutomatonCegarLoop]: Abstraction has 104425 states and 137166 transitions. [2023-11-29 03:17:27,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:27,312 INFO L428 stractBuchiCegarLoop]: Abstraction has 104425 states and 137166 transitions. [2023-11-29 03:17:27,312 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2023-11-29 03:17:27,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104425 states and 137166 transitions. [2023-11-29 03:17:27,879 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 103872 [2023-11-29 03:17:27,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:27,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:27,880 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:27,880 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:27,880 INFO L748 eck$LassoCheckResult]: Stem: 2901257#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2901258#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2902373#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2902374#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2901724#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2901725#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2901592#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2901483#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2901201#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2900853#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2900854#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2900898#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2900899#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2901871#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2901872#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2901922#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2901305#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2901306#L1090 assume !(0 == ~M_E~0); 2901350#L1090-2 assume !(0 == ~T1_E~0); 2901351#L1095-1 assume !(0 == ~T2_E~0); 2902094#L1100-1 assume !(0 == ~T3_E~0); 2902095#L1105-1 assume !(0 == ~T4_E~0); 2901120#L1110-1 assume !(0 == ~T5_E~0); 2901121#L1115-1 assume !(0 == ~T6_E~0); 2901520#L1120-1 assume !(0 == ~T7_E~0); 2901844#L1125-1 assume !(0 == ~T8_E~0); 2902512#L1130-1 assume !(0 == ~T9_E~0); 2902119#L1135-1 assume !(0 == ~T10_E~0); 2901311#L1140-1 assume !(0 == ~T11_E~0); 2901312#L1145-1 assume !(0 == ~E_1~0); 2902043#L1150-1 assume !(0 == ~E_2~0); 2901498#L1155-1 assume !(0 == ~E_3~0); 2901499#L1160-1 assume !(0 == ~E_4~0); 2901597#L1165-1 assume !(0 == ~E_5~0); 2901598#L1170-1 assume !(0 == ~E_6~0); 2902351#L1175-1 assume !(0 == ~E_7~0); 2901678#L1180-1 assume !(0 == ~E_8~0); 2901679#L1185-1 assume !(0 == ~E_9~0); 2901307#L1190-1 assume !(0 == ~E_10~0); 2901308#L1195-1 assume !(0 == ~E_11~0); 2901695#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2901513#L525 assume !(1 == ~m_pc~0); 2900943#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2900944#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2902215#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2902181#L1350 assume !(0 != activate_threads_~tmp~1#1); 2901297#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2901298#L544 assume !(1 == ~t1_pc~0); 2901518#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2901519#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2900917#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2900918#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2901144#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2901810#L563 assume !(1 == ~t2_pc~0); 2902024#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2900963#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2900964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2901376#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2901377#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2901898#L582 assume !(1 == ~t3_pc~0); 2902040#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2902447#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2900845#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2900846#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2901028#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2901029#L601 assume !(1 == ~t4_pc~0); 2902058#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2901521#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2901038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2901039#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2902053#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2902435#L620 assume !(1 == ~t5_pc~0); 2901860#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2901861#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2901918#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2902223#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2902466#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2902467#L639 assume !(1 == ~t6_pc~0); 2901842#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2901416#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2901417#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2902463#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2901526#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2901527#L658 assume !(1 == ~t7_pc~0); 2901749#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2901750#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2902477#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2901975#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2901300#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2901301#L677 assume !(1 == ~t8_pc~0); 2901322#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2901104#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2901105#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2901372#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2901373#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2902170#L696 assume !(1 == ~t9_pc~0); 2901823#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2901824#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2902568#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2901849#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2901850#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2902099#L715 assume !(1 == ~t10_pc~0); 2902394#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2901954#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2901736#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2901737#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2901672#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2901098#L734 assume !(1 == ~t11_pc~0); 2901099#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2901599#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2901682#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2900841#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2900842#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2901919#L1213 assume !(1 == ~M_E~0); 2901669#L1213-2 assume !(1 == ~T1_E~0); 2901670#L1218-1 assume !(1 == ~T2_E~0); 2900876#L1223-1 assume !(1 == ~T3_E~0); 2900877#L1228-1 assume !(1 == ~T4_E~0); 2901642#L1233-1 assume !(1 == ~T5_E~0); 2902468#L1238-1 assume !(1 == ~T6_E~0); 2902051#L1243-1 assume !(1 == ~T7_E~0); 2902052#L1248-1 assume !(1 == ~T8_E~0); 2902106#L1253-1 assume !(1 == ~T9_E~0); 2902107#L1258-1 assume !(1 == ~T10_E~0); 2902078#L1263-1 assume !(1 == ~T11_E~0); 2902079#L1268-1 assume !(1 == ~E_1~0); 2901868#L1273-1 assume !(1 == ~E_2~0); 2901869#L1278-1 assume !(1 == ~E_3~0); 2901414#L1283-1 assume !(1 == ~E_4~0); 2901415#L1288-1 assume !(1 == ~E_5~0); 2902230#L1293-1 assume !(1 == ~E_6~0); 2902176#L1298-1 assume !(1 == ~E_7~0); 2901902#L1303-1 assume !(1 == ~E_8~0); 2901424#L1308-1 assume !(1 == ~E_9~0); 2901315#L1313-1 assume !(1 == ~E_10~0); 2901316#L1318-1 assume !(1 == ~E_11~0); 2901323#L1323-1 assume { :end_inline_reset_delta_events } true; 2901324#L1644-2 [2023-11-29 03:17:27,880 INFO L750 eck$LassoCheckResult]: Loop: 2901324#L1644-2 assume !false; 2910936#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2910931#L1065-1 assume !false; 2910927#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2910923#L829 assume !(0 == ~m_st~0); 2910924#L833 assume !(0 == ~t1_st~0); 2912259#L837 assume !(0 == ~t2_st~0); 2912258#L841 assume !(0 == ~t3_st~0); 2912257#L845 assume !(0 == ~t4_st~0); 2912256#L849 assume !(0 == ~t5_st~0); 2912255#L853 assume !(0 == ~t6_st~0); 2912254#L857 assume !(0 == ~t7_st~0); 2912253#L861 assume !(0 == ~t8_st~0); 2912252#L865 assume !(0 == ~t9_st~0); 2912251#L869 assume !(0 == ~t10_st~0); 2912249#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2912248#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2912247#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2912246#L906 assume !(0 != eval_~tmp~0#1); 2912245#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2912244#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2912243#L1090-3 assume !(0 == ~M_E~0); 2912242#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2912241#L1095-3 assume !(0 == ~T2_E~0); 2912240#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2912239#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2912238#L1110-3 assume !(0 == ~T5_E~0); 2912237#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2912236#L1120-3 assume !(0 == ~T7_E~0); 2912235#L1125-3 assume !(0 == ~T8_E~0); 2912234#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2912233#L1135-3 assume !(0 == ~T10_E~0); 2912232#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2912231#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2912230#L1150-3 assume !(0 == ~E_2~0); 2912229#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2912228#L1160-3 assume !(0 == ~E_4~0); 2912227#L1165-3 assume !(0 == ~E_5~0); 2912226#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2912225#L1175-3 assume !(0 == ~E_7~0); 2912224#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2912223#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2912222#L1190-3 assume !(0 == ~E_10~0); 2912221#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2912220#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2912219#L525-36 assume 1 == ~m_pc~0; 2912217#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2912216#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2912215#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2912213#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2912212#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2912211#L544-36 assume !(1 == ~t1_pc~0); 2912210#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2912209#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2912208#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2912207#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 2912206#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2912204#L563-36 assume !(1 == ~t2_pc~0); 2912203#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2912202#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2912201#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2912200#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 2912199#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2912198#L582-36 assume !(1 == ~t3_pc~0); 2912197#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2912196#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2912195#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2912194#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 2912193#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2912192#L601-36 assume !(1 == ~t4_pc~0); 2912190#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2912189#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2912188#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2912187#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 2912186#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2912185#L620-36 assume !(1 == ~t5_pc~0); 2912184#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2912183#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2912182#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2912181#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 2912180#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2912179#L639-36 assume 1 == ~t6_pc~0; 2912177#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2912175#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2912173#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2912171#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2912169#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2911085#L658-36 assume !(1 == ~t7_pc~0); 2911082#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2911079#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2911077#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2911075#L1406-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2911073#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2911071#L677-36 assume !(1 == ~t8_pc~0); 2911069#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2911067#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2911065#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2911063#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2911061#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2911056#L696-36 assume !(1 == ~t9_pc~0); 2911052#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2911050#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2911048#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2911046#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 2911042#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2911040#L715-36 assume !(1 == ~t10_pc~0); 2911038#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2911036#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2911034#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2911032#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2911030#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2911028#L734-36 assume !(1 == ~t11_pc~0); 2911025#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 2911022#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2911020#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2911018#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2911016#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2911015#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2911014#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2911013#L1218-3 assume !(1 == ~T2_E~0); 2911011#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2911009#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2911007#L1233-3 assume !(1 == ~T5_E~0); 2911005#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2911003#L1243-3 assume !(1 == ~T7_E~0); 2911001#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2910999#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2910997#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2910995#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2910993#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2910991#L1273-3 assume !(1 == ~E_2~0); 2910989#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2910987#L1283-3 assume !(1 == ~E_4~0); 2910985#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2910983#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2910981#L1298-3 assume !(1 == ~E_7~0); 2910979#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2910977#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2910975#L1313-3 assume !(1 == ~E_10~0); 2910973#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2910971#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2910968#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2910966#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2910964#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2910961#L1663 assume !(0 == start_simulation_~tmp~3#1); 2910960#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2910958#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2910957#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2910955#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2910953#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2910951#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2910948#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2910944#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 2901324#L1644-2 [2023-11-29 03:17:27,881 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:27,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 11 times [2023-11-29 03:17:27,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:27,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49747666] [2023-11-29 03:17:27,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:27,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:27,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:27,890 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:27,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:27,918 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:27,918 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:27,918 INFO L85 PathProgramCache]: Analyzing trace with hash -218595889, now seen corresponding path program 1 times [2023-11-29 03:17:27,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:27,919 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317564979] [2023-11-29 03:17:27,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:27,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:27,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:27,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:27,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:27,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317564979] [2023-11-29 03:17:27,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317564979] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:27,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:27,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:27,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136793496] [2023-11-29 03:17:27,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:27,973 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:27,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:27,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:27,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:27,973 INFO L87 Difference]: Start difference. First operand 104425 states and 137166 transitions. cyclomatic complexity: 32773 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:28,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:28,499 INFO L93 Difference]: Finished difference Result 170281 states and 220733 transitions. [2023-11-29 03:17:28,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 170281 states and 220733 transitions. [2023-11-29 03:17:29,047 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 169328 [2023-11-29 03:17:29,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 170281 states to 170281 states and 220733 transitions. [2023-11-29 03:17:29,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 170281 [2023-11-29 03:17:29,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 170281 [2023-11-29 03:17:29,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 170281 states and 220733 transitions. [2023-11-29 03:17:29,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:29,835 INFO L218 hiAutomatonCegarLoop]: Abstraction has 170281 states and 220733 transitions. [2023-11-29 03:17:29,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170281 states and 220733 transitions. [2023-11-29 03:17:30,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170281 to 104713. [2023-11-29 03:17:30,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104713 states, 104713 states have (on average 1.3048714104265946) internal successors, (136637), 104712 states have internal predecessors, (136637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:31,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104713 states to 104713 states and 136637 transitions. [2023-11-29 03:17:31,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 104713 states and 136637 transitions. [2023-11-29 03:17:31,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:31,178 INFO L428 stractBuchiCegarLoop]: Abstraction has 104713 states and 136637 transitions. [2023-11-29 03:17:31,179 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2023-11-29 03:17:31,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104713 states and 136637 transitions. [2023-11-29 03:17:31,405 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 104160 [2023-11-29 03:17:31,405 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:31,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:31,407 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:31,407 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:31,408 INFO L748 eck$LassoCheckResult]: Stem: 3175987#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3175988#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 3177132#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3177133#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3176458#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 3176459#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3176324#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3176212#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3175928#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3175571#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3175572#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3175615#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3175616#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3176616#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3176617#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3176670#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3176038#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3176039#L1090 assume !(0 == ~M_E~0); 3176084#L1090-2 assume !(0 == ~T1_E~0); 3176085#L1095-1 assume !(0 == ~T2_E~0); 3176844#L1100-1 assume !(0 == ~T3_E~0); 3176845#L1105-1 assume !(0 == ~T4_E~0); 3175844#L1110-1 assume !(0 == ~T5_E~0); 3175845#L1115-1 assume !(0 == ~T6_E~0); 3176249#L1120-1 assume !(0 == ~T7_E~0); 3176585#L1125-1 assume !(0 == ~T8_E~0); 3177274#L1130-1 assume !(0 == ~T9_E~0); 3176874#L1135-1 assume !(0 == ~T10_E~0); 3176042#L1140-1 assume !(0 == ~T11_E~0); 3176043#L1145-1 assume !(0 == ~E_1~0); 3176791#L1150-1 assume !(0 == ~E_2~0); 3176226#L1155-1 assume !(0 == ~E_3~0); 3176227#L1160-1 assume !(0 == ~E_4~0); 3176329#L1165-1 assume !(0 == ~E_5~0); 3176330#L1170-1 assume !(0 == ~E_6~0); 3177108#L1175-1 assume !(0 == ~E_7~0); 3176413#L1180-1 assume !(0 == ~E_8~0); 3176414#L1185-1 assume !(0 == ~E_9~0); 3176036#L1190-1 assume !(0 == ~E_10~0); 3176037#L1195-1 assume !(0 == ~E_11~0); 3176429#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3176246#L525 assume !(1 == ~m_pc~0); 3175658#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3175659#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3177341#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3176940#L1350 assume !(0 != activate_threads_~tmp~1#1); 3176028#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3176029#L544 assume !(1 == ~t1_pc~0); 3176247#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3176248#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3175633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3175634#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3175868#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3176552#L563 assume !(1 == ~t2_pc~0); 3176775#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3175680#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3175681#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3176111#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3176112#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3176645#L582 assume !(1 == ~t3_pc~0); 3176790#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3177214#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3175563#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3175564#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3175749#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3175750#L601 assume !(1 == ~t4_pc~0); 3176806#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3176250#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3175761#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3175762#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 3176800#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3177204#L620 assume !(1 == ~t5_pc~0); 3176601#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3176602#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3176666#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3176979#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 3177232#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3177233#L639 assume !(1 == ~t6_pc~0); 3176583#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3176584#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3176198#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3176199#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3176255#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3176256#L658 assume !(1 == ~t7_pc~0); 3176486#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3176487#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3177245#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3176725#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3176031#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3176032#L677 assume !(1 == ~t8_pc~0); 3176053#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3175825#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3175826#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3176104#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3176105#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3176925#L696 assume !(1 == ~t9_pc~0); 3176566#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3176567#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3176683#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3176593#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 3176594#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3176850#L715 assume !(1 == ~t10_pc~0); 3177155#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3176704#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3176472#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3176473#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3176407#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3175819#L734 assume !(1 == ~t11_pc~0); 3175820#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3176331#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3176418#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3175559#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3175560#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3176667#L1213 assume !(1 == ~M_E~0); 3176403#L1213-2 assume !(1 == ~T1_E~0); 3176404#L1218-1 assume !(1 == ~T2_E~0); 3175594#L1223-1 assume !(1 == ~T3_E~0); 3175595#L1228-1 assume !(1 == ~T4_E~0); 3176378#L1233-1 assume !(1 == ~T5_E~0); 3177234#L1238-1 assume !(1 == ~T6_E~0); 3176798#L1243-1 assume !(1 == ~T7_E~0); 3176799#L1248-1 assume !(1 == ~T8_E~0); 3176857#L1253-1 assume !(1 == ~T9_E~0); 3176858#L1258-1 assume !(1 == ~T10_E~0); 3176826#L1263-1 assume !(1 == ~T11_E~0); 3176827#L1268-1 assume !(1 == ~E_1~0); 3176609#L1273-1 assume !(1 == ~E_2~0); 3176610#L1278-1 assume !(1 == ~E_3~0); 3176145#L1283-1 assume !(1 == ~E_4~0); 3176146#L1288-1 assume !(1 == ~E_5~0); 3176986#L1293-1 assume !(1 == ~E_6~0); 3176931#L1298-1 assume !(1 == ~E_7~0); 3176651#L1303-1 assume !(1 == ~E_8~0); 3176156#L1308-1 assume !(1 == ~E_9~0); 3176046#L1313-1 assume !(1 == ~E_10~0); 3176047#L1318-1 assume !(1 == ~E_11~0); 3176054#L1323-1 assume { :end_inline_reset_delta_events } true; 3176055#L1644-2 [2023-11-29 03:17:31,408 INFO L750 eck$LassoCheckResult]: Loop: 3176055#L1644-2 assume !false; 3195612#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3195607#L1065-1 assume !false; 3195605#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3195602#L829 assume !(0 == ~m_st~0); 3195603#L833 assume !(0 == ~t1_st~0); 3207200#L837 assume !(0 == ~t2_st~0); 3207194#L841 assume !(0 == ~t3_st~0); 3207188#L845 assume !(0 == ~t4_st~0); 3207182#L849 assume !(0 == ~t5_st~0); 3207175#L853 assume !(0 == ~t6_st~0); 3207170#L857 assume !(0 == ~t7_st~0); 3207165#L861 assume !(0 == ~t8_st~0); 3207159#L865 assume !(0 == ~t9_st~0); 3207153#L869 assume !(0 == ~t10_st~0); 3207147#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 3207141#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3207135#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3207127#L906 assume !(0 != eval_~tmp~0#1); 3207121#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3207114#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3207107#L1090-3 assume !(0 == ~M_E~0); 3207101#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3207093#L1095-3 assume !(0 == ~T2_E~0); 3207086#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3207080#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3207079#L1110-3 assume !(0 == ~T5_E~0); 3207078#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3207076#L1120-3 assume !(0 == ~T7_E~0); 3207075#L1125-3 assume !(0 == ~T8_E~0); 3207074#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3207073#L1135-3 assume !(0 == ~T10_E~0); 3207071#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3207070#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3207069#L1150-3 assume !(0 == ~E_2~0); 3207068#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3207067#L1160-3 assume !(0 == ~E_4~0); 3207065#L1165-3 assume !(0 == ~E_5~0); 3207063#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3207061#L1175-3 assume !(0 == ~E_7~0); 3207060#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3207058#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3207056#L1190-3 assume !(0 == ~E_10~0); 3207054#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3207052#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3207050#L525-36 assume 1 == ~m_pc~0; 3207047#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3207044#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3207042#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3207039#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3207037#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3207035#L544-36 assume !(1 == ~t1_pc~0); 3207033#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 3207029#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3207027#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3207025#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 3207023#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3207018#L563-36 assume !(1 == ~t2_pc~0); 3207014#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3207012#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3207010#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3207008#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 3207005#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3207003#L582-36 assume !(1 == ~t3_pc~0); 3207001#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3206999#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3206997#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3206996#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 3206995#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3206994#L601-36 assume !(1 == ~t4_pc~0); 3206992#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3206990#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3206988#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3206984#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 3206982#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3206980#L620-36 assume !(1 == ~t5_pc~0); 3206978#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3206974#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3206972#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3206970#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 3206968#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3206966#L639-36 assume 1 == ~t6_pc~0; 3206963#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3206961#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3206959#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3206948#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3195755#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3195752#L658-36 assume !(1 == ~t7_pc~0); 3195748#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3195745#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3195743#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3195740#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 3195738#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3195736#L677-36 assume !(1 == ~t8_pc~0); 3195734#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3195732#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3195730#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3195728#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3195726#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3195724#L696-36 assume 1 == ~t9_pc~0; 3195721#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3195718#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3195715#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3195712#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3195709#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3195706#L715-36 assume !(1 == ~t10_pc~0); 3195703#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3195700#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3195698#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3195696#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3195694#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3195692#L734-36 assume !(1 == ~t11_pc~0); 3195689#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 3195687#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3195685#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3195683#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3195680#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3195678#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3195676#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3195674#L1218-3 assume !(1 == ~T2_E~0); 3195672#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3195670#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3195668#L1233-3 assume !(1 == ~T5_E~0); 3195666#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3195664#L1243-3 assume !(1 == ~T7_E~0); 3195662#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3195660#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3195658#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3195656#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3195654#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3195652#L1273-3 assume !(1 == ~E_2~0); 3195650#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3195648#L1283-3 assume !(1 == ~E_4~0); 3195646#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3195644#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3195642#L1298-3 assume !(1 == ~E_7~0); 3195640#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3195638#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3195636#L1313-3 assume !(1 == ~E_10~0); 3195634#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3195632#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3195629#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3195627#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3195625#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3195622#L1663 assume !(0 == start_simulation_~tmp~3#1); 3195621#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3195619#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3195618#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3195617#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3195616#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3195615#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3195614#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3195613#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3176055#L1644-2 [2023-11-29 03:17:31,408 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:31,409 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 12 times [2023-11-29 03:17:31,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:31,409 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104005078] [2023-11-29 03:17:31,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:31,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:31,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:31,425 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:31,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:31,469 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:31,470 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:31,470 INFO L85 PathProgramCache]: Analyzing trace with hash 838955376, now seen corresponding path program 1 times [2023-11-29 03:17:31,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:31,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457654342] [2023-11-29 03:17:31,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:31,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:31,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:31,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:31,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:31,563 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457654342] [2023-11-29 03:17:31,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [457654342] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:31,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:31,563 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:31,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560598228] [2023-11-29 03:17:31,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:31,564 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:31,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:31,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:31,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:31,565 INFO L87 Difference]: Start difference. First operand 104713 states and 136637 transitions. cyclomatic complexity: 31956 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:32,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:32,227 INFO L93 Difference]: Finished difference Result 170165 states and 221112 transitions. [2023-11-29 03:17:32,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 170165 states and 221112 transitions. [2023-11-29 03:17:33,096 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 169460 [2023-11-29 03:17:33,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 170165 states to 170165 states and 221112 transitions. [2023-11-29 03:17:33,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 170165 [2023-11-29 03:17:33,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 170165 [2023-11-29 03:17:33,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 170165 states and 221112 transitions. [2023-11-29 03:17:33,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:33,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 170165 states and 221112 transitions. [2023-11-29 03:17:33,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170165 states and 221112 transitions. [2023-11-29 03:17:34,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170165 to 106153. [2023-11-29 03:17:34,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106153 states, 106153 states have (on average 1.2966567124810415) internal successors, (137644), 106152 states have internal predecessors, (137644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:34,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106153 states to 106153 states and 137644 transitions. [2023-11-29 03:17:34,993 INFO L240 hiAutomatonCegarLoop]: Abstraction has 106153 states and 137644 transitions. [2023-11-29 03:17:34,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:34,994 INFO L428 stractBuchiCegarLoop]: Abstraction has 106153 states and 137644 transitions. [2023-11-29 03:17:34,994 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2023-11-29 03:17:34,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 106153 states and 137644 transitions. [2023-11-29 03:17:35,230 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 105600 [2023-11-29 03:17:35,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:35,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:35,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:35,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:35,232 INFO L748 eck$LassoCheckResult]: Stem: 3450867#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3450868#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 3451998#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3451999#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3451343#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 3451344#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3451204#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3451097#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3450807#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3450461#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3450462#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3450505#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3450506#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3451492#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3451493#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3451543#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3450917#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3450918#L1090 assume !(0 == ~M_E~0); 3450962#L1090-2 assume !(0 == ~T1_E~0); 3450963#L1095-1 assume !(0 == ~T2_E~0); 3451709#L1100-1 assume !(0 == ~T3_E~0); 3451710#L1105-1 assume !(0 == ~T4_E~0); 3450726#L1110-1 assume !(0 == ~T5_E~0); 3450727#L1115-1 assume !(0 == ~T6_E~0); 3451132#L1120-1 assume !(0 == ~T7_E~0); 3451463#L1125-1 assume !(0 == ~T8_E~0); 3452115#L1130-1 assume !(0 == ~T9_E~0); 3451736#L1135-1 assume !(0 == ~T10_E~0); 3450921#L1140-1 assume !(0 == ~T11_E~0); 3450922#L1145-1 assume !(0 == ~E_1~0); 3451658#L1150-1 assume !(0 == ~E_2~0); 3451111#L1155-1 assume !(0 == ~E_3~0); 3451112#L1160-1 assume !(0 == ~E_4~0); 3451209#L1165-1 assume !(0 == ~E_5~0); 3451210#L1170-1 assume !(0 == ~E_6~0); 3451976#L1175-1 assume !(0 == ~E_7~0); 3451298#L1180-1 assume !(0 == ~E_8~0); 3451299#L1185-1 assume !(0 == ~E_9~0); 3450915#L1190-1 assume !(0 == ~E_10~0); 3450916#L1195-1 assume !(0 == ~E_11~0); 3451314#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3451129#L525 assume !(1 == ~m_pc~0); 3450549#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3450550#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3452173#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3451803#L1350 assume !(0 != activate_threads_~tmp~1#1); 3450907#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3450908#L544 assume !(1 == ~t1_pc~0); 3451130#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3451131#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3450524#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3450525#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3450749#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3451429#L563 assume !(1 == ~t2_pc~0); 3451645#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3450568#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3450569#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3450990#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3450991#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3451518#L582 assume !(1 == ~t3_pc~0); 3451657#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3452061#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3450453#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3450454#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3450632#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3450633#L601 assume !(1 == ~t4_pc~0); 3451673#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3451133#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3450644#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3450645#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 3451668#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3452051#L620 assume !(1 == ~t5_pc~0); 3451480#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3451481#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3451539#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3451841#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 3452078#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3452079#L639 assume !(1 == ~t6_pc~0); 3451461#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3451462#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3451081#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3451082#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3451138#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3451139#L658 assume !(1 == ~t7_pc~0); 3451368#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3451369#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3452087#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3451598#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3450910#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3450911#L677 assume !(1 == ~t8_pc~0); 3450932#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3450708#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3450709#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3450983#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3450984#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3451791#L696 assume !(1 == ~t9_pc~0); 3451443#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3451444#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3451556#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3451468#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 3451469#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3451716#L715 assume !(1 == ~t10_pc~0); 3452016#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3451575#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3451356#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3451357#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3451291#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3450702#L734 assume !(1 == ~t11_pc~0); 3450703#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3451211#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3451303#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3450449#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3450450#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3451540#L1213 assume !(1 == ~M_E~0); 3451288#L1213-2 assume !(1 == ~T1_E~0); 3451289#L1218-1 assume !(1 == ~T2_E~0); 3450484#L1223-1 assume !(1 == ~T3_E~0); 3450485#L1228-1 assume !(1 == ~T4_E~0); 3451259#L1233-1 assume !(1 == ~T5_E~0); 3452080#L1238-1 assume !(1 == ~T6_E~0); 3451666#L1243-1 assume !(1 == ~T7_E~0); 3451667#L1248-1 assume !(1 == ~T8_E~0); 3451724#L1253-1 assume !(1 == ~T9_E~0); 3451725#L1258-1 assume !(1 == ~T10_E~0); 3451692#L1263-1 assume !(1 == ~T11_E~0); 3451693#L1268-1 assume !(1 == ~E_1~0); 3451488#L1273-1 assume !(1 == ~E_2~0); 3451489#L1278-1 assume !(1 == ~E_3~0); 3451026#L1283-1 assume !(1 == ~E_4~0); 3451027#L1288-1 assume !(1 == ~E_5~0); 3451847#L1293-1 assume !(1 == ~E_6~0); 3451796#L1298-1 assume !(1 == ~E_7~0); 3451523#L1303-1 assume !(1 == ~E_8~0); 3451036#L1308-1 assume !(1 == ~E_9~0); 3450925#L1313-1 assume !(1 == ~E_10~0); 3450926#L1318-1 assume !(1 == ~E_11~0); 3450933#L1323-1 assume { :end_inline_reset_delta_events } true; 3450934#L1644-2 [2023-11-29 03:17:35,232 INFO L750 eck$LassoCheckResult]: Loop: 3450934#L1644-2 assume !false; 3467984#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3467980#L1065-1 assume !false; 3467978#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3467976#L829 assume !(0 == ~m_st~0); 3467977#L833 assume !(0 == ~t1_st~0); 3469417#L837 assume !(0 == ~t2_st~0); 3469415#L841 assume !(0 == ~t3_st~0); 3469413#L845 assume !(0 == ~t4_st~0); 3469411#L849 assume !(0 == ~t5_st~0); 3469409#L853 assume !(0 == ~t6_st~0); 3469407#L857 assume !(0 == ~t7_st~0); 3469405#L861 assume !(0 == ~t8_st~0); 3469403#L865 assume !(0 == ~t9_st~0); 3469400#L869 assume !(0 == ~t10_st~0); 3469397#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 3469395#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3469393#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3469385#L906 assume !(0 != eval_~tmp~0#1); 3469381#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3469377#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3469373#L1090-3 assume !(0 == ~M_E~0); 3469367#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3469361#L1095-3 assume !(0 == ~T2_E~0); 3469356#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3469351#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3469345#L1110-3 assume !(0 == ~T5_E~0); 3469338#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3469330#L1120-3 assume !(0 == ~T7_E~0); 3469323#L1125-3 assume !(0 == ~T8_E~0); 3469317#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3469311#L1135-3 assume !(0 == ~T10_E~0); 3469306#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3469299#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3469293#L1150-3 assume !(0 == ~E_2~0); 3469286#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3469150#L1160-3 assume !(0 == ~E_4~0); 3469147#L1165-3 assume !(0 == ~E_5~0); 3469145#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3469143#L1175-3 assume !(0 == ~E_7~0); 3469141#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3469139#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3469137#L1190-3 assume !(0 == ~E_10~0); 3469135#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3469133#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3469131#L525-36 assume 1 == ~m_pc~0; 3469128#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3469126#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3469124#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3469120#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3469118#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3469116#L544-36 assume !(1 == ~t1_pc~0); 3469114#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 3469112#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3469110#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3469108#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 3469106#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3469102#L563-36 assume !(1 == ~t2_pc~0); 3469100#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3469098#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3469094#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3469092#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 3469090#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3469088#L582-36 assume !(1 == ~t3_pc~0); 3469086#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3469084#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3469082#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3469079#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 3469077#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3469075#L601-36 assume !(1 == ~t4_pc~0); 3469072#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3469070#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3469068#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3469066#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 3469064#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3469062#L620-36 assume !(1 == ~t5_pc~0); 3469060#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3469058#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3469056#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3469054#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 3469052#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3469050#L639-36 assume 1 == ~t6_pc~0; 3469047#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3469045#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3469043#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3469034#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3469032#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3469030#L658-36 assume !(1 == ~t7_pc~0); 3469027#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3469024#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3469022#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3469020#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 3469018#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3469016#L677-36 assume !(1 == ~t8_pc~0); 3469014#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3469012#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3469010#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3469008#L1414-36 assume !(0 != activate_threads_~tmp___7~0#1); 3469006#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3468992#L696-36 assume 1 == ~t9_pc~0; 3468993#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3468994#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3469169#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3468982#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3468980#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3468978#L715-36 assume !(1 == ~t10_pc~0); 3468976#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3468974#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3468972#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3468970#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3468968#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3468966#L734-36 assume !(1 == ~t11_pc~0); 3468957#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 3468955#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3468952#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3468950#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3468947#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3468945#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3468943#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3468941#L1218-3 assume !(1 == ~T2_E~0); 3468939#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3468937#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3468935#L1233-3 assume !(1 == ~T5_E~0); 3468933#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3468931#L1243-3 assume !(1 == ~T7_E~0); 3468929#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3468927#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3468925#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3468921#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3468919#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3468917#L1273-3 assume !(1 == ~E_2~0); 3468915#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3468907#L1283-3 assume !(1 == ~E_4~0); 3468882#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3468838#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3468821#L1298-3 assume !(1 == ~E_7~0); 3468815#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3468808#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3468799#L1313-3 assume !(1 == ~E_10~0); 3468794#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3468789#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3468782#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3468776#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3468771#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3468005#L1663 assume !(0 == start_simulation_~tmp~3#1); 3468003#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3468000#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3467998#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3467996#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3467994#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3467992#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3467990#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3467987#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3450934#L1644-2 [2023-11-29 03:17:35,232 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:35,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 13 times [2023-11-29 03:17:35,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:35,232 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740211850] [2023-11-29 03:17:35,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:35,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:35,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:35,242 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:35,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:35,272 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:35,272 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:35,272 INFO L85 PathProgramCache]: Analyzing trace with hash 879630126, now seen corresponding path program 1 times [2023-11-29 03:17:35,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:35,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849082330] [2023-11-29 03:17:35,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:35,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:35,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:35,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:35,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:35,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849082330] [2023-11-29 03:17:35,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1849082330] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:35,353 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:35,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:35,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377267296] [2023-11-29 03:17:35,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:35,354 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:35,354 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:35,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:35,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:35,354 INFO L87 Difference]: Start difference. First operand 106153 states and 137644 transitions. cyclomatic complexity: 31523 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:35,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:35,959 INFO L93 Difference]: Finished difference Result 171721 states and 220683 transitions. [2023-11-29 03:17:35,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 171721 states and 220683 transitions. [2023-11-29 03:17:36,529 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 170944 [2023-11-29 03:17:37,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 171721 states to 171721 states and 220683 transitions. [2023-11-29 03:17:37,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171721 [2023-11-29 03:17:37,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171721 [2023-11-29 03:17:37,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171721 states and 220683 transitions. [2023-11-29 03:17:37,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:37,345 INFO L218 hiAutomatonCegarLoop]: Abstraction has 171721 states and 220683 transitions. [2023-11-29 03:17:37,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171721 states and 220683 transitions. [2023-11-29 03:17:38,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171721 to 107065. [2023-11-29 03:17:38,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 107065 states, 107065 states have (on average 1.2884416008966515) internal successors, (137947), 107064 states have internal predecessors, (137947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:38,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107065 states to 107065 states and 137947 transitions. [2023-11-29 03:17:38,762 INFO L240 hiAutomatonCegarLoop]: Abstraction has 107065 states and 137947 transitions. [2023-11-29 03:17:38,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:38,763 INFO L428 stractBuchiCegarLoop]: Abstraction has 107065 states and 137947 transitions. [2023-11-29 03:17:38,763 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2023-11-29 03:17:38,763 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107065 states and 137947 transitions. [2023-11-29 03:17:38,952 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 106512 [2023-11-29 03:17:38,952 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:38,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:38,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:38,954 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:38,954 INFO L748 eck$LassoCheckResult]: Stem: 3728752#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3728753#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 3729905#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3729906#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3729225#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 3729226#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3729093#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3728983#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3728694#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3728347#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3728348#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3728391#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3728392#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3729380#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3729381#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3729432#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3728798#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3728799#L1090 assume !(0 == ~M_E~0); 3728848#L1090-2 assume !(0 == ~T1_E~0); 3728849#L1095-1 assume !(0 == ~T2_E~0); 3729606#L1100-1 assume !(0 == ~T3_E~0); 3729607#L1105-1 assume !(0 == ~T4_E~0); 3728613#L1110-1 assume !(0 == ~T5_E~0); 3728614#L1115-1 assume !(0 == ~T6_E~0); 3729023#L1120-1 assume !(0 == ~T7_E~0); 3729347#L1125-1 assume !(0 == ~T8_E~0); 3730036#L1130-1 assume !(0 == ~T9_E~0); 3729633#L1135-1 assume !(0 == ~T10_E~0); 3728804#L1140-1 assume !(0 == ~T11_E~0); 3728805#L1145-1 assume !(0 == ~E_1~0); 3729551#L1150-1 assume !(0 == ~E_2~0); 3728998#L1155-1 assume !(0 == ~E_3~0); 3728999#L1160-1 assume !(0 == ~E_4~0); 3729098#L1165-1 assume !(0 == ~E_5~0); 3729099#L1170-1 assume !(0 == ~E_6~0); 3729882#L1175-1 assume !(0 == ~E_7~0); 3729183#L1180-1 assume !(0 == ~E_8~0); 3729184#L1185-1 assume !(0 == ~E_9~0); 3728800#L1190-1 assume !(0 == ~E_10~0); 3728801#L1195-1 assume !(0 == ~E_11~0); 3729199#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3729017#L525 assume !(1 == ~m_pc~0); 3728435#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3728436#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3730099#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3729702#L1350 assume !(0 != activate_threads_~tmp~1#1); 3728790#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3728791#L544 assume !(1 == ~t1_pc~0); 3729018#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3729019#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3728414#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3728415#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3728635#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3729313#L563 assume !(1 == ~t2_pc~0); 3729537#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3728457#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3728458#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3728873#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3728874#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3729404#L582 assume !(1 == ~t3_pc~0); 3729550#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3729973#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3728339#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3728340#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3728520#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3728521#L601 assume !(1 == ~t4_pc~0); 3729568#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3729022#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3728532#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3728533#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 3729561#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3729965#L620 assume !(1 == ~t5_pc~0); 3729368#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3729369#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3729423#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3729743#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 3729988#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3729989#L639 assume !(1 == ~t6_pc~0); 3729344#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3729345#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3728965#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3728966#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3729026#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3729027#L658 assume !(1 == ~t7_pc~0); 3729251#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3729252#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3730004#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3729485#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3728793#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3728794#L677 assume !(1 == ~t8_pc~0); 3728817#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3728600#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3728601#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3728866#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3728867#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3729688#L696 assume !(1 == ~t9_pc~0); 3729328#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3729329#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3729440#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3729357#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 3729358#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3729612#L715 assume !(1 == ~t10_pc~0); 3729927#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3729461#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3729237#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3729238#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3729176#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3728589#L734 assume !(1 == ~t11_pc~0); 3728590#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3729101#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3729188#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3728337#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3728338#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3729424#L1213 assume !(1 == ~M_E~0); 3729174#L1213-2 assume !(1 == ~T1_E~0); 3729175#L1218-1 assume !(1 == ~T2_E~0); 3728370#L1223-1 assume !(1 == ~T3_E~0); 3728371#L1228-1 assume !(1 == ~T4_E~0); 3729144#L1233-1 assume !(1 == ~T5_E~0); 3729990#L1238-1 assume !(1 == ~T6_E~0); 3729559#L1243-1 assume !(1 == ~T7_E~0); 3729560#L1248-1 assume !(1 == ~T8_E~0); 3729618#L1253-1 assume !(1 == ~T9_E~0); 3729619#L1258-1 assume !(1 == ~T10_E~0); 3729586#L1263-1 assume !(1 == ~T11_E~0); 3729587#L1268-1 assume !(1 == ~E_1~0); 3729373#L1273-1 assume !(1 == ~E_2~0); 3729374#L1278-1 assume !(1 == ~E_3~0); 3728910#L1283-1 assume !(1 == ~E_4~0); 3728911#L1288-1 assume !(1 == ~E_5~0); 3729750#L1293-1 assume !(1 == ~E_6~0); 3729697#L1298-1 assume !(1 == ~E_7~0); 3729408#L1303-1 assume !(1 == ~E_8~0); 3728922#L1308-1 assume !(1 == ~E_9~0); 3728808#L1313-1 assume !(1 == ~E_10~0); 3728809#L1318-1 assume !(1 == ~E_11~0); 3728818#L1323-1 assume { :end_inline_reset_delta_events } true; 3728819#L1644-2 [2023-11-29 03:17:38,954 INFO L750 eck$LassoCheckResult]: Loop: 3728819#L1644-2 assume !false; 3742161#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3742156#L1065-1 assume !false; 3742153#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3742150#L829 assume !(0 == ~m_st~0); 3742151#L833 assume !(0 == ~t1_st~0); 3744791#L837 assume !(0 == ~t2_st~0); 3744790#L841 assume !(0 == ~t3_st~0); 3744789#L845 assume !(0 == ~t4_st~0); 3744787#L849 assume !(0 == ~t5_st~0); 3744784#L853 assume !(0 == ~t6_st~0); 3744782#L857 assume !(0 == ~t7_st~0); 3744780#L861 assume !(0 == ~t8_st~0); 3744779#L865 assume !(0 == ~t9_st~0); 3744778#L869 assume !(0 == ~t10_st~0); 3744775#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 3744774#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3744773#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3744772#L906 assume !(0 != eval_~tmp~0#1); 3744768#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3744766#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3744764#L1090-3 assume !(0 == ~M_E~0); 3744762#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3744758#L1095-3 assume !(0 == ~T2_E~0); 3744756#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3744754#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3744752#L1110-3 assume !(0 == ~T5_E~0); 3744750#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3744748#L1120-3 assume !(0 == ~T7_E~0); 3744746#L1125-3 assume !(0 == ~T8_E~0); 3744744#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3744741#L1135-3 assume !(0 == ~T10_E~0); 3744739#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3744737#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3744735#L1150-3 assume !(0 == ~E_2~0); 3744733#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3744731#L1160-3 assume !(0 == ~E_4~0); 3744729#L1165-3 assume !(0 == ~E_5~0); 3744727#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3744725#L1175-3 assume !(0 == ~E_7~0); 3744723#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3744721#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3744719#L1190-3 assume !(0 == ~E_10~0); 3744716#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3744714#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3744712#L525-36 assume 1 == ~m_pc~0; 3744709#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3744707#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3744705#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3744702#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3744700#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3744698#L544-36 assume !(1 == ~t1_pc~0); 3744696#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 3744694#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3744692#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3744688#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 3744686#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3744682#L563-36 assume !(1 == ~t2_pc~0); 3744679#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3744677#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3744674#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3744672#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 3744670#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3744668#L582-36 assume !(1 == ~t3_pc~0); 3744666#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3744664#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3744662#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3744659#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 3744657#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3744655#L601-36 assume !(1 == ~t4_pc~0); 3744651#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3744649#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3744645#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3744643#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 3744641#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3744639#L620-36 assume !(1 == ~t5_pc~0); 3744636#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3744634#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3744632#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3744630#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 3744628#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3744626#L639-36 assume 1 == ~t6_pc~0; 3744623#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3744621#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3744608#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3744600#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3744594#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3744560#L658-36 assume !(1 == ~t7_pc~0); 3744557#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3744555#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3744552#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3744550#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 3744547#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3744545#L677-36 assume !(1 == ~t8_pc~0); 3744543#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3744541#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3744539#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3744537#L1414-36 assume !(0 != activate_threads_~tmp___7~0#1); 3744535#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3744504#L696-36 assume 1 == ~t9_pc~0; 3744505#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3744506#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3744565#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3744495#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3744493#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3744490#L715-36 assume !(1 == ~t10_pc~0); 3744488#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3744486#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3744484#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3744482#L1430-36 assume !(0 != activate_threads_~tmp___9~0#1); 3744480#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3744479#L734-36 assume !(1 == ~t11_pc~0); 3744475#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 3744473#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3744470#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3744468#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3744466#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3744464#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3744462#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3744460#L1218-3 assume !(1 == ~T2_E~0); 3744458#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3744456#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3744454#L1233-3 assume !(1 == ~T5_E~0); 3744452#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3744450#L1243-3 assume !(1 == ~T7_E~0); 3744448#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3744444#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3744442#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3744440#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3744438#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3744435#L1273-3 assume !(1 == ~E_2~0); 3744433#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3744430#L1283-3 assume !(1 == ~E_4~0); 3744428#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3744426#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3744424#L1298-3 assume !(1 == ~E_7~0); 3744422#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3744420#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3744418#L1313-3 assume !(1 == ~E_10~0); 3744416#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3744414#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3744411#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3744409#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3744407#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3744391#L1663 assume !(0 == start_simulation_~tmp~3#1); 3744389#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3744386#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3744384#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3744382#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3744380#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3744378#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3742168#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3742164#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3728819#L1644-2 [2023-11-29 03:17:38,955 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:38,955 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 14 times [2023-11-29 03:17:38,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:38,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363996974] [2023-11-29 03:17:38,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:38,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:38,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:38,968 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:38,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:38,995 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:38,995 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:38,995 INFO L85 PathProgramCache]: Analyzing trace with hash -1169757716, now seen corresponding path program 1 times [2023-11-29 03:17:38,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:38,996 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625432388] [2023-11-29 03:17:38,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:38,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:39,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:39,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:39,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:39,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625432388] [2023-11-29 03:17:39,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625432388] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:39,065 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:39,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:17:39,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [422900835] [2023-11-29 03:17:39,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:39,066 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:17:39,066 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:39,066 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:17:39,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:17:39,067 INFO L87 Difference]: Start difference. First operand 107065 states and 137947 transitions. cyclomatic complexity: 30914 Second operand has 5 states, 5 states have (on average 30.6) internal successors, (153), 5 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:39,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:39,786 INFO L93 Difference]: Finished difference Result 212118 states and 271017 transitions. [2023-11-29 03:17:39,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 212118 states and 271017 transitions. [2023-11-29 03:17:40,854 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 211136 [2023-11-29 03:17:41,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 212118 states to 212118 states and 271017 transitions. [2023-11-29 03:17:41,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212118 [2023-11-29 03:17:41,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212118 [2023-11-29 03:17:41,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212118 states and 271017 transitions. [2023-11-29 03:17:41,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:17:41,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 212118 states and 271017 transitions. [2023-11-29 03:17:41,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212118 states and 271017 transitions. [2023-11-29 03:17:42,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212118 to 109900. [2023-11-29 03:17:42,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109900 states, 109900 states have (on average 1.2810009099181074) internal successors, (140782), 109899 states have internal predecessors, (140782), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:42,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109900 states to 109900 states and 140782 transitions. [2023-11-29 03:17:42,827 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109900 states and 140782 transitions. [2023-11-29 03:17:42,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:17:42,828 INFO L428 stractBuchiCegarLoop]: Abstraction has 109900 states and 140782 transitions. [2023-11-29 03:17:42,828 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2023-11-29 03:17:42,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109900 states and 140782 transitions. [2023-11-29 03:17:43,093 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109344 [2023-11-29 03:17:43,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:17:43,093 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:17:43,095 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:43,095 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:17:43,095 INFO L748 eck$LassoCheckResult]: Stem: 4047954#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 4047955#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4049101#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4049102#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4048425#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 4048426#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4048287#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4048178#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4047895#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4047542#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4047543#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4047587#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4047588#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4048582#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4048583#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4048638#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4048002#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4048003#L1090 assume !(0 == ~M_E~0); 4048046#L1090-2 assume !(0 == ~T1_E~0); 4048047#L1095-1 assume !(0 == ~T2_E~0); 4048809#L1100-1 assume !(0 == ~T3_E~0); 4048810#L1105-1 assume !(0 == ~T4_E~0); 4047812#L1110-1 assume !(0 == ~T5_E~0); 4047813#L1115-1 assume !(0 == ~T6_E~0); 4048215#L1120-1 assume !(0 == ~T7_E~0); 4048556#L1125-1 assume !(0 == ~T8_E~0); 4049235#L1130-1 assume !(0 == ~T9_E~0); 4048838#L1135-1 assume !(0 == ~T10_E~0); 4048006#L1140-1 assume !(0 == ~T11_E~0); 4048007#L1145-1 assume !(0 == ~E_1~0); 4048759#L1150-1 assume !(0 == ~E_2~0); 4048193#L1155-1 assume !(0 == ~E_3~0); 4048194#L1160-1 assume !(0 == ~E_4~0); 4048294#L1165-1 assume !(0 == ~E_5~0); 4048295#L1170-1 assume !(0 == ~E_6~0); 4049078#L1175-1 assume !(0 == ~E_7~0); 4048380#L1180-1 assume !(0 == ~E_8~0); 4048381#L1185-1 assume !(0 == ~E_9~0); 4048000#L1190-1 assume !(0 == ~E_10~0); 4048001#L1195-1 assume !(0 == ~E_11~0); 4048396#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4048208#L525 assume !(1 == ~m_pc~0); 4047631#L525-2 is_master_triggered_~__retres1~0#1 := 0; 4047632#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4048933#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4048900#L1350 assume !(0 != activate_threads_~tmp~1#1); 4047991#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4047992#L544 assume !(1 == ~t1_pc~0); 4048213#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4048214#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4047605#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4047606#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 4047837#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4048523#L563 assume !(1 == ~t2_pc~0); 4048741#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4047653#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4047654#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4048072#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 4048073#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4048614#L582 assume !(1 == ~t3_pc~0); 4048758#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4049175#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4047534#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4047535#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 4047717#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4047718#L601 assume !(1 == ~t4_pc~0); 4048776#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4048216#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4047727#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4047728#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4048771#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4049164#L620 assume !(1 == ~t5_pc~0); 4048572#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4048573#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4048634#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4048940#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4049191#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4049192#L639 assume !(1 == ~t6_pc~0); 4048555#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4048113#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4048114#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4048164#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 4048221#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4048222#L658 assume !(1 == ~t7_pc~0); 4048454#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4048455#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4049206#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4048692#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 4047995#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4047996#L677 assume !(1 == ~t8_pc~0); 4048017#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4047796#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4047797#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4048068#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 4048069#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4048890#L696 assume !(1 == ~t9_pc~0); 4048535#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4048536#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4049292#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4048561#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 4048562#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4048815#L715 assume !(1 == ~t10_pc~0); 4049124#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4048671#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4048440#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4048441#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 4048373#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4047790#L734 assume !(1 == ~t11_pc~0); 4047791#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4048296#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4048383#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4047530#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 4047531#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4048635#L1213 assume !(1 == ~M_E~0); 4048369#L1213-2 assume !(1 == ~T1_E~0); 4048370#L1218-1 assume !(1 == ~T2_E~0); 4047565#L1223-1 assume !(1 == ~T3_E~0); 4047566#L1228-1 assume !(1 == ~T4_E~0); 4048342#L1233-1 assume !(1 == ~T5_E~0); 4049193#L1238-1 assume !(1 == ~T6_E~0); 4048769#L1243-1 assume !(1 == ~T7_E~0); 4048770#L1248-1 assume !(1 == ~T8_E~0); 4048822#L1253-1 assume !(1 == ~T9_E~0); 4048823#L1258-1 assume !(1 == ~T10_E~0); 4048792#L1263-1 assume !(1 == ~T11_E~0); 4048793#L1268-1 assume !(1 == ~E_1~0); 4048579#L1273-1 assume !(1 == ~E_2~0); 4048580#L1278-1 assume !(1 == ~E_3~0); 4048111#L1283-1 assume !(1 == ~E_4~0); 4048112#L1288-1 assume !(1 == ~E_5~0); 4048948#L1293-1 assume !(1 == ~E_6~0); 4048895#L1298-1 assume !(1 == ~E_7~0); 4048619#L1303-1 assume !(1 == ~E_8~0); 4048121#L1308-1 assume !(1 == ~E_9~0); 4048010#L1313-1 assume !(1 == ~E_10~0); 4048011#L1318-1 assume !(1 == ~E_11~0); 4048018#L1323-1 assume { :end_inline_reset_delta_events } true; 4048019#L1644-2 [2023-11-29 03:17:43,096 INFO L750 eck$LassoCheckResult]: Loop: 4048019#L1644-2 assume !false; 4062778#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4062772#L1065-1 assume !false; 4062768#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4062761#L829 assume !(0 == ~m_st~0); 4062762#L833 assume !(0 == ~t1_st~0); 4068709#L837 assume !(0 == ~t2_st~0); 4068708#L841 assume !(0 == ~t3_st~0); 4068707#L845 assume !(0 == ~t4_st~0); 4068706#L849 assume !(0 == ~t5_st~0); 4068705#L853 assume !(0 == ~t6_st~0); 4068704#L857 assume !(0 == ~t7_st~0); 4068703#L861 assume !(0 == ~t8_st~0); 4068702#L865 assume !(0 == ~t9_st~0); 4068701#L869 assume !(0 == ~t10_st~0); 4068699#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 4068698#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4068697#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4068696#L906 assume !(0 != eval_~tmp~0#1); 4068695#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4068694#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4068693#L1090-3 assume !(0 == ~M_E~0); 4068692#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4068691#L1095-3 assume !(0 == ~T2_E~0); 4068690#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4068689#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4068688#L1110-3 assume !(0 == ~T5_E~0); 4068687#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4068686#L1120-3 assume !(0 == ~T7_E~0); 4068685#L1125-3 assume !(0 == ~T8_E~0); 4068684#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4068683#L1135-3 assume !(0 == ~T10_E~0); 4068682#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4068681#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4068680#L1150-3 assume !(0 == ~E_2~0); 4068679#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4068678#L1160-3 assume !(0 == ~E_4~0); 4068677#L1165-3 assume !(0 == ~E_5~0); 4068676#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4068675#L1175-3 assume !(0 == ~E_7~0); 4068674#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4068673#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4068672#L1190-3 assume !(0 == ~E_10~0); 4068671#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4068670#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4068669#L525-36 assume 1 == ~m_pc~0; 4068667#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4068666#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4068665#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4068664#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4068663#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4068662#L544-36 assume !(1 == ~t1_pc~0); 4068661#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 4068660#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4068659#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4068658#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 4068657#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4068655#L563-36 assume !(1 == ~t2_pc~0); 4068654#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4068653#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4068652#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4068651#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 4068650#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4068649#L582-36 assume !(1 == ~t3_pc~0); 4068648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4068647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4068646#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4068645#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 4068644#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4068643#L601-36 assume !(1 == ~t4_pc~0); 4068641#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 4068640#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4068639#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4068638#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 4068637#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4068636#L620-36 assume !(1 == ~t5_pc~0); 4068635#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4068634#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4068633#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4068632#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 4068631#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4068630#L639-36 assume 1 == ~t6_pc~0; 4068628#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4068626#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4068624#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4068622#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4068621#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4068620#L658-36 assume !(1 == ~t7_pc~0); 4068618#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4068617#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4068616#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4068615#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 4068614#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4068613#L677-36 assume !(1 == ~t8_pc~0); 4068612#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4068611#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4068610#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4068609#L1414-36 assume !(0 != activate_threads_~tmp___7~0#1); 4068608#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4068607#L696-36 assume !(1 == ~t9_pc~0); 4068606#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4068604#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4068602#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4068600#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 4068598#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4068597#L715-36 assume !(1 == ~t10_pc~0); 4068596#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4068594#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4068591#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4068589#L1430-36 assume !(0 != activate_threads_~tmp___9~0#1); 4068587#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4068586#L734-36 assume 1 == ~t11_pc~0; 4068584#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4068582#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4068580#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4068578#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4062899#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4062898#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4062897#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4062896#L1218-3 assume !(1 == ~T2_E~0); 4062894#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4062892#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4062890#L1233-3 assume !(1 == ~T5_E~0); 4062888#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4062886#L1243-3 assume !(1 == ~T7_E~0); 4062884#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4062882#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4062880#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4062878#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4062876#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4062874#L1273-3 assume !(1 == ~E_2~0); 4062872#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4062870#L1283-3 assume !(1 == ~E_4~0); 4062867#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4062864#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4062861#L1298-3 assume !(1 == ~E_7~0); 4062858#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4062855#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4062852#L1313-3 assume !(1 == ~E_10~0); 4062849#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4062845#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4062840#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4062836#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4062832#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4062827#L1663 assume !(0 == start_simulation_~tmp~3#1); 4062824#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4062820#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4062817#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4062813#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 4062807#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4062803#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4062798#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4062792#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 4048019#L1644-2 [2023-11-29 03:17:43,096 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:43,096 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 15 times [2023-11-29 03:17:43,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:43,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554234362] [2023-11-29 03:17:43,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:43,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:43,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:43,107 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:43,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:43,134 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:43,135 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:43,135 INFO L85 PathProgramCache]: Analyzing trace with hash 607477674, now seen corresponding path program 1 times [2023-11-29 03:17:43,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:43,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325676361] [2023-11-29 03:17:43,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:43,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:43,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:43,144 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:17:43,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:17:43,166 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:17:43,167 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:43,167 INFO L85 PathProgramCache]: Analyzing trace with hash -570816975, now seen corresponding path program 1 times [2023-11-29 03:17:43,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:17:43,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800058149] [2023-11-29 03:17:43,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:17:43,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:17:43,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:43,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:43,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:17:43,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800058149] [2023-11-29 03:17:43,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800058149] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:17:43,221 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:17:43,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:17:43,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328138108] [2023-11-29 03:17:43,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:17:46,683 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 03:17:46,683 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 03:17:46,683 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 03:17:46,683 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 03:17:46,683 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-29 03:17:46,684 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:46,684 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 03:17:46,684 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 03:17:46,684 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.11.cil.c_Iteration43_Loop [2023-11-29 03:17:46,684 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 03:17:46,684 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 03:17:46,710 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,731 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,737 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,745 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,751 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,763 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,770 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,788 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,793 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,798 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,802 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,808 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,819 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,826 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,830 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,842 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,852 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,854 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,858 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,864 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,874 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,898 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,902 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,911 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,919 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,923 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,927 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,929 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,933 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,936 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,938 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,941 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,953 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,955 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,958 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,960 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,961 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,965 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,967 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,969 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,976 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,979 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,980 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,981 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,983 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,985 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,990 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:46,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,000 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,006 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,009 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,011 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,015 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,018 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:47,757 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 03:17:47,758 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-29 03:17:47,760 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,760 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,761 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,763 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-29 03:17:47,764 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,764 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,785 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,785 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,789 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:47,789 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,789 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,790 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,791 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-29 03:17:47,792 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,792 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,804 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,804 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,806 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2023-11-29 03:17:47,807 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,807 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,808 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,808 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-29 03:17:47,810 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,810 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,823 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,823 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,825 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2023-11-29 03:17:47,825 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,826 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,826 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-29 03:17:47,829 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,829 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,841 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,842 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___10~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___10~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,845 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2023-11-29 03:17:47,845 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,845 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,846 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,847 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-29 03:17:47,849 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,849 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,877 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,877 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit10_triggered_~__retres1~10#1=0} Honda state: {ULTIMATE.start_is_transmit10_triggered_~__retres1~10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,879 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2023-11-29 03:17:47,880 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,880 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,881 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-29 03:17:47,884 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,884 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,896 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,896 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,899 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2023-11-29 03:17:47,899 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,899 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,901 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,906 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-29 03:17:47,907 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,907 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,927 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,927 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret26#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret26#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,930 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2023-11-29 03:17:47,930 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,930 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,931 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-29 03:17:47,935 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,935 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,955 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,955 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_pc~0=4} Honda state: {~t4_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,957 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2023-11-29 03:17:47,958 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,958 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,958 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,959 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-29 03:17:47,961 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,961 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,972 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,972 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,974 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:47,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,976 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,977 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-29 03:17:47,978 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,978 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:47,990 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:47,990 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:47,992 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2023-11-29 03:17:47,993 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:47,993 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:47,993 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:47,994 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-29 03:17:47,996 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:47,996 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,007 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:48,008 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit7_triggered_~__retres1~7#1=0} Honda state: {ULTIMATE.start_is_transmit7_triggered_~__retres1~7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:48,010 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2023-11-29 03:17:48,010 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,010 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,011 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,011 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-29 03:17:48,013 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:48,013 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,025 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:48,025 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet16#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet16#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:48,027 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2023-11-29 03:17:48,027 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,028 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,028 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,030 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-29 03:17:48,031 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:48,031 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,042 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:48,042 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret31#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret31#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:48,045 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2023-11-29 03:17:48,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,046 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,047 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-29 03:17:48,048 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:48,048 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,060 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:48,060 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit6_triggered_#res#1=1} Honda state: {ULTIMATE.start_is_transmit6_triggered_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:48,062 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2023-11-29 03:17:48,063 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,063 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,064 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,064 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-29 03:17:48,066 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:48,066 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,077 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:48,077 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:48,080 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:48,080 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,080 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,081 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,081 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-29 03:17:48,083 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:48,083 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,100 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:48,100 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~T5_E~0=-1} Honda state: {~T5_E~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:48,103 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2023-11-29 03:17:48,103 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,103 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,104 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,105 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-29 03:17:48,107 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:48,107 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,118 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:48,118 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:48,121 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2023-11-29 03:17:48,121 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,121 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,122 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,122 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-29 03:17:48,124 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:48,124 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,141 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:17:48,141 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:17:48,144 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2023-11-29 03:17:48,144 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,144 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,145 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,146 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-29 03:17:48,147 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:17:48,147 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,161 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:48,161 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,161 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:48,162 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:48,163 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-29 03:17:48,164 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-29 03:17:48,164 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:17:48,178 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-29 03:17:48,181 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:48,181 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 03:17:48,181 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 03:17:48,181 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 03:17:48,181 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 03:17:48,181 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-29 03:17:48,181 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:48,181 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 03:17:48,181 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 03:17:48,181 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.11.cil.c_Iteration43_Loop [2023-11-29 03:17:48,181 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 03:17:48,181 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 03:17:48,187 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,192 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,197 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,199 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,200 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,202 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,206 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,208 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,210 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,212 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,218 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,220 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,224 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,226 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,227 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,231 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,235 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,240 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,242 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,246 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,247 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,249 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,252 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,256 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,263 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,265 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,271 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,273 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,275 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,278 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,281 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,289 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,291 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,294 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,297 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,298 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,300 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,307 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,309 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,323 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,327 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,329 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,331 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,336 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,338 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,340 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,341 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,345 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,350 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,359 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,361 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,363 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,366 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,370 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,377 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,382 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,384 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,394 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,403 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,405 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,412 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,414 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,418 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,427 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,429 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,435 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,437 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,447 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,451 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,462 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,464 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,470 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,471 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,473 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,475 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,478 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,480 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,482 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,487 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,491 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,494 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,497 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,502 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,507 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,509 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:48,510 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:17:49,179 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 03:17:49,182 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-29 03:17:49,183 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,183 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,184 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,186 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-29 03:17:49,187 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,197 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,197 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,197 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,197 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,197 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,199 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,199 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,200 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,203 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,203 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,203 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,204 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,204 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2023-11-29 03:17:49,206 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,215 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,216 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,216 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,216 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 03:17:49,216 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,217 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 03:17:49,217 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,219 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,222 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,222 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,222 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,223 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,224 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-29 03:17:49,225 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,235 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,235 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,235 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,235 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,235 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,236 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,236 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,238 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,240 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,241 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,241 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,241 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,242 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-29 03:17:49,244 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,253 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,254 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,254 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,254 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,254 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,254 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,254 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,256 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,258 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2023-11-29 03:17:49,258 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,258 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,259 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,260 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-29 03:17:49,261 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,271 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,271 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,271 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,271 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,271 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,272 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,272 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,273 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,275 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,276 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,276 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,277 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,277 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-29 03:17:49,279 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,288 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,288 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,289 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,289 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,289 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,289 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,289 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,291 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,294 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2023-11-29 03:17:49,294 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,294 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,295 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,295 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2023-11-29 03:17:49,297 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,307 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,307 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,307 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,307 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,307 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,308 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,308 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,309 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,311 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2023-11-29 03:17:49,311 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,312 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,312 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,313 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-29 03:17:49,315 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,324 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,324 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,325 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,325 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 03:17:49,325 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,325 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 03:17:49,325 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,327 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,329 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,329 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,330 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,330 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,331 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-29 03:17:49,332 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,342 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,342 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,342 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,342 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,342 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,343 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,343 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,344 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,346 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,346 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,347 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,347 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,348 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-29 03:17:49,349 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,359 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,359 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,359 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,359 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,360 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,360 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,360 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,361 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,363 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2023-11-29 03:17:49,364 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,364 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,364 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,365 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2023-11-29 03:17:49,366 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,376 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,376 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,376 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,376 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,376 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,377 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,377 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,378 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,380 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,380 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,381 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,382 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2023-11-29 03:17:49,383 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,393 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,393 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,393 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,393 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,393 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,394 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,394 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,395 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,397 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2023-11-29 03:17:49,397 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,397 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,398 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,399 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2023-11-29 03:17:49,400 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,410 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,410 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,410 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,410 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,410 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,410 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,410 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,412 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,414 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,414 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,415 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,415 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,416 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2023-11-29 03:17:49,417 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,427 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,427 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,427 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,427 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,427 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,428 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,428 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,429 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,431 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2023-11-29 03:17:49,431 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,431 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,432 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,433 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2023-11-29 03:17:49,434 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,444 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,444 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,444 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,444 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 03:17:49,444 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,445 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 03:17:49,445 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,447 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,449 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2023-11-29 03:17:49,449 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,449 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,450 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,451 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2023-11-29 03:17:49,452 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,462 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,462 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,462 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,462 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,462 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,462 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,463 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,464 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,466 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2023-11-29 03:17:49,466 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,466 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,467 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,468 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2023-11-29 03:17:49,469 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,479 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,479 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,479 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,479 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 03:17:49,479 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,480 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 03:17:49,480 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,481 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:17:49,484 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2023-11-29 03:17:49,484 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,484 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,485 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,485 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2023-11-29 03:17:49,487 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:17:49,497 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:17:49,497 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:17:49,497 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:17:49,497 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:17:49,497 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:17:49,498 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:17:49,498 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:17:49,500 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-29 03:17:49,503 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-29 03:17:49,503 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-29 03:17:49,504 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:17:49,504 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:17:49,539 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:17:49,540 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2023-11-29 03:17:49,541 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-29 03:17:49,541 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-29 03:17:49,541 INFO L513 LassoAnalysis]: Proved termination. [2023-11-29 03:17:49,541 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_9~0) = -1*~E_9~0 + 1 Supporting invariants [] [2023-11-29 03:17:49,544 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2023-11-29 03:17:49,546 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-29 03:17:49,688 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Ended with exit code 0 [2023-11-29 03:17:49,693 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:17:49,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:49,761 INFO L262 TraceCheckSpWp]: Trace formula consists of 383 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-29 03:17:49,765 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 03:17:50,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:17:50,007 INFO L262 TraceCheckSpWp]: Trace formula consists of 322 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-29 03:17:50,012 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 03:17:50,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:17:50,323 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-29 03:17:50,325 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 109900 states and 140782 transitions. cyclomatic complexity: 30914 Second operand has 5 states, 5 states have (on average 58.0) internal successors, (290), 5 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:51,440 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 109900 states and 140782 transitions. cyclomatic complexity: 30914. Second operand has 5 states, 5 states have (on average 58.0) internal successors, (290), 5 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 268538 states and 344973 transitions. Complement of second has 5 states. [2023-11-29 03:17:51,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-29 03:17:51,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 58.0) internal successors, (290), 5 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:51,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1952 transitions. [2023-11-29 03:17:51,446 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1952 transitions. Stem has 137 letters. Loop has 153 letters. [2023-11-29 03:17:51,451 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 03:17:51,451 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1952 transitions. Stem has 290 letters. Loop has 153 letters. [2023-11-29 03:17:51,452 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 03:17:51,452 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1952 transitions. Stem has 137 letters. Loop has 306 letters. [2023-11-29 03:17:51,456 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 03:17:51,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 268538 states and 344973 transitions. [2023-11-29 03:17:52,641 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 162524 [2023-11-29 03:17:53,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 268538 states to 268490 states and 344925 transitions. [2023-11-29 03:17:53,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 163281 [2023-11-29 03:17:53,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 163458 [2023-11-29 03:17:53,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 268490 states and 344925 transitions. [2023-11-29 03:17:53,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 03:17:53,250 INFO L218 hiAutomatonCegarLoop]: Abstraction has 268490 states and 344925 transitions. [2023-11-29 03:17:53,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268490 states and 344925 transitions. [2023-11-29 03:17:55,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268490 to 268169. [2023-11-29 03:17:55,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268169 states, 268169 states have (on average 1.284190193497384) internal successors, (344380), 268168 states have internal predecessors, (344380), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:56,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268169 states to 268169 states and 344380 transitions. [2023-11-29 03:17:56,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 268169 states and 344380 transitions. [2023-11-29 03:17:56,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:17:56,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:17:56,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:17:56,117 INFO L87 Difference]: Start difference. First operand 268169 states and 344380 transitions. Second operand has 3 states, 3 states have (on average 96.66666666666667) internal successors, (290), 3 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:17:57,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:17:57,435 INFO L93 Difference]: Finished difference Result 279397 states and 357624 transitions. [2023-11-29 03:17:57,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 279397 states and 357624 transitions. [2023-11-29 03:17:58,278 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 169280 [2023-11-29 03:17:58,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 279397 states to 279397 states and 357624 transitions. [2023-11-29 03:17:58,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 169989 [2023-11-29 03:17:58,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 169989 [2023-11-29 03:17:58,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 279397 states and 357624 transitions. [2023-11-29 03:17:58,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 03:17:58,815 INFO L218 hiAutomatonCegarLoop]: Abstraction has 279397 states and 357624 transitions. [2023-11-29 03:17:59,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279397 states and 357624 transitions. [2023-11-29 03:18:00,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279397 to 268169. [2023-11-29 03:18:01,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268169 states, 268169 states have (on average 1.2826985967803886) internal successors, (343980), 268168 states have internal predecessors, (343980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:18:01,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268169 states to 268169 states and 343980 transitions. [2023-11-29 03:18:01,502 INFO L240 hiAutomatonCegarLoop]: Abstraction has 268169 states and 343980 transitions. [2023-11-29 03:18:01,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:18:01,503 INFO L428 stractBuchiCegarLoop]: Abstraction has 268169 states and 343980 transitions. [2023-11-29 03:18:01,503 INFO L335 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2023-11-29 03:18:01,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 268169 states and 343980 transitions. [2023-11-29 03:18:02,452 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 162524 [2023-11-29 03:18:02,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:18:02,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:18:02,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:18:02,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:18:02,454 INFO L748 eck$LassoCheckResult]: Stem: 4975238#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 4975239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4977404#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4977405#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4976118#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 4976119#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4975862#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4975646#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4975127#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4974464#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4974465#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4974550#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4974551#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4976413#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4976414#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4976524#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4975319#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4975320#L1090 assume !(0 == ~M_E~0); 4975410#L1090-2 assume !(0 == ~T1_E~0); 4975411#L1095-1 assume !(0 == ~T2_E~0); 4976853#L1100-1 assume !(0 == ~T3_E~0); 4976854#L1105-1 assume !(0 == ~T4_E~0); 4974967#L1110-1 assume !(0 == ~T5_E~0); 4974968#L1115-1 assume !(0 == ~T6_E~0); 4975720#L1120-1 assume !(0 == ~T7_E~0); 4976357#L1125-1 assume !(0 == ~T8_E~0); 4977660#L1130-1 assume !(0 == ~T9_E~0); 4976895#L1135-1 assume !(0 == ~T10_E~0); 4975326#L1140-1 assume !(0 == ~T11_E~0); 4975327#L1145-1 assume !(0 == ~E_1~0); 4976759#L1150-1 assume !(0 == ~E_2~0); 4975675#L1155-1 assume !(0 == ~E_3~0); 4975676#L1160-1 assume !(0 == ~E_4~0); 4975871#L1165-1 assume !(0 == ~E_5~0); 4975872#L1170-1 assume !(0 == ~E_6~0); 4977356#L1175-1 assume !(0 == ~E_7~0); 4976035#L1180-1 assume !(0 == ~E_8~0); 4976036#L1185-1 assume !(0 == ~E_9~0); 4975321#L1190-1 assume !(0 == ~E_10~0); 4975322#L1195-1 assume !(0 == ~E_11~0); 4976065#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4975711#L525 assume !(1 == ~m_pc~0); 4974631#L525-2 is_master_triggered_~__retres1~0#1 := 0; 4974632#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4977081#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4977020#L1350 assume !(0 != activate_threads_~tmp~1#1); 4975308#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4975309#L544 assume !(1 == ~t1_pc~0); 4975712#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4975713#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4974593#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4974594#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 4975013#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4976295#L563 assume !(1 == ~t2_pc~0); 4976736#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4974668#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4974669#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4975454#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 4975455#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4976464#L582 assume !(1 == ~t3_pc~0); 4976758#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4977546#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4974454#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4974455#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 4974794#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4974795#L601 assume !(1 == ~t4_pc~0); 4976780#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4975721#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4974820#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4974821#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4976772#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4977520#L620 assume !(1 == ~t5_pc~0); 4976393#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4976394#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4976506#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4977098#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4977570#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4977571#L639 assume !(1 == ~t6_pc~0); 4976355#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4975520#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4975521#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4975616#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 4975728#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4975729#L658 assume !(1 == ~t7_pc~0); 4976171#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4976172#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4977600#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4976627#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 4975312#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4975313#L677 assume !(1 == ~t8_pc~0); 4975351#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4974945#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4974946#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4975442#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 4975443#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4977004#L696 assume !(1 == ~t9_pc~0); 4976326#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4976327#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4977798#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4976373#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 4976374#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4976862#L715 assume !(1 == ~t10_pc~0); 4977442#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4976586#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4976144#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4976145#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 4976023#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4974926#L734 assume !(1 == ~t11_pc~0); 4974927#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4975877#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4976648#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4974452#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 4974453#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4976507#L1213 assume !(1 == ~M_E~0); 4976021#L1213-2 assume !(1 == ~T1_E~0); 4976022#L1218-1 assume !(1 == ~T2_E~0); 4974508#L1223-1 assume !(1 == ~T3_E~0); 4974509#L1228-1 assume !(1 == ~T4_E~0); 4975964#L1233-1 assume !(1 == ~T5_E~0); 4977572#L1238-1 assume !(1 == ~T6_E~0); 4976770#L1243-1 assume !(1 == ~T7_E~0); 4976771#L1248-1 assume !(1 == ~T8_E~0); 4976868#L1253-1 assume !(1 == ~T9_E~0); 4976869#L1258-1 assume !(1 == ~T10_E~0); 4976816#L1263-1 assume !(1 == ~T11_E~0); 4976817#L1268-1 assume !(1 == ~E_1~0); 4976401#L1273-1 assume !(1 == ~E_2~0); 4976402#L1278-1 assume !(1 == ~E_3~0); 4975514#L1283-1 assume !(1 == ~E_4~0); 4975515#L1288-1 assume !(1 == ~E_5~0); 4977106#L1293-1 assume !(1 == ~E_6~0); 4977013#L1298-1 assume !(1 == ~E_7~0); 4976474#L1303-1 assume !(1 == ~E_8~0); 4975533#L1308-1 assume !(1 == ~E_9~0); 4975332#L1313-1 assume !(1 == ~E_10~0); 4975333#L1318-1 assume !(1 == ~E_11~0); 4975352#L1323-1 assume { :end_inline_reset_delta_events } true; 4975353#L1644-2 assume !false; 4983775#L1645 [2023-11-29 03:18:02,455 INFO L750 eck$LassoCheckResult]: Loop: 4983775#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5085410#L1065-1 assume !false; 5085407#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 5085404#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 5085401#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 5085397#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5085394#L906 assume 0 != eval_~tmp~0#1; 5085389#L906-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5085386#L914 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 5085310#L101 assume !(0 == ~m_pc~0); 5085312#L104 assume 1 == ~m_pc~0; 5101204#$Ultimate##421 assume !false; 5085287#L121 ~m_pc~0 := 1;~m_st~0 := 2; 5085285#master_returnLabel#1 assume { :end_inline_master } true; 5085282#L914-2 havoc eval_~tmp_ndt_1~0#1; 5085280#L911-1 assume !(0 == ~t1_st~0); 5085281#L925-1 assume !(0 == ~t2_st~0); 5095949#L939-1 assume !(0 == ~t3_st~0); 5095950#L953-1 assume !(0 == ~t4_st~0); 5104474#L967-1 assume !(0 == ~t5_st~0); 5104469#L981-1 assume !(0 == ~t6_st~0); 5104465#L995-1 assume !(0 == ~t7_st~0); 5104461#L1009-1 assume !(0 == ~t8_st~0); 5104457#L1023-1 assume !(0 == ~t9_st~0); 5104458#L1037-1 assume !(0 == ~t10_st~0); 5136543#L1051-1 assume !(0 == ~t11_st~0); 5234239#L1065-1 assume !false; 5234154#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 5234148#L829 assume !(0 == ~m_st~0); 5085301#L833 assume !(0 == ~t1_st~0); 5085291#L837 assume !(0 == ~t2_st~0); 5085292#L841 assume !(0 == ~t3_st~0); 5085297#L845 assume !(0 == ~t4_st~0); 5085300#L849 assume !(0 == ~t5_st~0); 5085295#L853 assume !(0 == ~t6_st~0); 5085296#L857 assume !(0 == ~t7_st~0); 5085299#L861 assume !(0 == ~t8_st~0); 5085293#L865 assume !(0 == ~t9_st~0); 5085294#L869 assume !(0 == ~t10_st~0); 5085298#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 5085302#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 5120324#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5120321#L906 assume !(0 != eval_~tmp~0#1); 5120316#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5120312#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5120310#L1090-3 assume !(0 == ~M_E~0); 5120308#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5120306#L1095-3 assume !(0 == ~T2_E~0); 5120305#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5120304#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5120303#L1110-3 assume !(0 == ~T5_E~0); 5120302#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5120301#L1120-3 assume !(0 == ~T7_E~0); 5120300#L1125-3 assume !(0 == ~T8_E~0); 5120299#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5120298#L1135-3 assume !(0 == ~T10_E~0); 5120109#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5120108#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5120106#L1150-3 assume !(0 == ~E_2~0); 5120103#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5120101#L1160-3 assume !(0 == ~E_4~0); 5120099#L1165-3 assume !(0 == ~E_5~0); 5120098#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5120097#L1175-3 assume !(0 == ~E_7~0); 5120096#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5120095#L1185-3 assume !(0 == ~E_9~0); 5120094#L1190-3 assume !(0 == ~E_10~0); 5120092#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5120091#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5120090#L525-36 assume 1 == ~m_pc~0; 5120087#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5120085#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5118253#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5118248#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5118242#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5118235#L544-36 assume !(1 == ~t1_pc~0); 5118229#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 5118222#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5118218#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5118214#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 5118210#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5118205#L563-36 assume !(1 == ~t2_pc~0); 5118201#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5118197#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5118155#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5118129#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 5118125#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5118120#L582-36 assume !(1 == ~t3_pc~0); 5118117#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5118114#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5118109#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5118105#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 5118101#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5118097#L601-36 assume !(1 == ~t4_pc~0); 5118092#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 5118087#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5118083#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5118079#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 5118067#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5118064#L620-36 assume !(1 == ~t5_pc~0); 5118062#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5118060#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5118058#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5118056#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 5118054#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5118052#L639-36 assume 1 == ~t6_pc~0; 5118050#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5118051#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5118039#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5118027#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5118022#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5118017#L658-36 assume !(1 == ~t7_pc~0); 5118012#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5118005#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5118000#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5117995#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 5117990#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5117985#L677-36 assume !(1 == ~t8_pc~0); 5117980#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 5117974#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5117967#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5117961#L1414-36 assume !(0 != activate_threads_~tmp___7~0#1); 5117954#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5117948#L696-36 assume 1 == ~t9_pc~0; 5117942#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5117936#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5117930#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5117924#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5117918#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5117913#L715-36 assume !(1 == ~t10_pc~0); 5117909#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5117901#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5117895#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5117890#L1430-36 assume !(0 != activate_threads_~tmp___9~0#1); 5117884#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5113867#L734-36 assume 1 == ~t11_pc~0; 5113865#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5113866#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5113883#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5113855#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5113853#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5113851#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5113849#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5113847#L1218-3 assume !(1 == ~T2_E~0); 5113845#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5113843#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5113840#L1233-3 assume !(1 == ~T5_E~0); 5113838#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5113836#L1243-3 assume !(1 == ~T7_E~0); 5113833#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5113831#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5113829#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5113827#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5113825#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5113823#L1273-3 assume !(1 == ~E_2~0); 5113821#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5113819#L1283-3 assume !(1 == ~E_4~0); 5113817#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5113815#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5113813#L1298-3 assume !(1 == ~E_7~0); 5113811#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5113809#L1308-3 assume !(1 == ~E_9~0); 5113805#L1313-3 assume !(1 == ~E_10~0); 5113803#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5113801#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 5113799#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 5113797#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 5113795#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5113783#L1663 assume !(0 == start_simulation_~tmp~3#1); 5113782#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 5113781#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 5113780#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 5110274#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5104262#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5104261#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5100581#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 5085425#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 5085421#L1644-2 assume !false; 4983775#L1645 [2023-11-29 03:18:02,455 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:18:02,455 INFO L85 PathProgramCache]: Analyzing trace with hash -1057194452, now seen corresponding path program 1 times [2023-11-29 03:18:02,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:18:02,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635070416] [2023-11-29 03:18:02,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:18:02,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:18:02,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:18:02,466 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:18:02,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:18:02,506 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:18:02,506 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:18:02,507 INFO L85 PathProgramCache]: Analyzing trace with hash -610514213, now seen corresponding path program 1 times [2023-11-29 03:18:02,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:18:02,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333246458] [2023-11-29 03:18:02,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:18:02,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:18:02,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:18:02,553 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2023-11-29 03:18:02,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:18:02,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1333246458] [2023-11-29 03:18:02,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1333246458] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:18:02,553 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:18:02,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:18:02,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181821330] [2023-11-29 03:18:02,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:18:02,554 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:18:02,554 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:18:02,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:18:02,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:18:02,555 INFO L87 Difference]: Start difference. First operand 268169 states and 343980 transitions. cyclomatic complexity: 75891 Second operand has 3 states, 3 states have (on average 58.0) internal successors, (174), 3 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:18:04,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:18:04,221 INFO L93 Difference]: Finished difference Result 506925 states and 646533 transitions. [2023-11-29 03:18:04,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 506925 states and 646533 transitions. [2023-11-29 03:18:06,048 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 289456 [2023-11-29 03:18:06,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 506925 states to 490797 states and 624581 transitions. [2023-11-29 03:18:06,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 290829 [2023-11-29 03:18:07,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 290829 [2023-11-29 03:18:07,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 490797 states and 624581 transitions. [2023-11-29 03:18:07,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 03:18:07,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 490797 states and 624581 transitions. [2023-11-29 03:18:07,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490797 states and 624581 transitions. [2023-11-29 03:18:10,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490797 to 490557. [2023-11-29 03:18:10,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 490557 states, 490557 states have (on average 1.272718562776599) internal successors, (624341), 490556 states have internal predecessors, (624341), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:18:12,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 490557 states to 490557 states and 624341 transitions. [2023-11-29 03:18:12,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 490557 states and 624341 transitions. [2023-11-29 03:18:12,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:18:12,329 INFO L428 stractBuchiCegarLoop]: Abstraction has 490557 states and 624341 transitions. [2023-11-29 03:18:12,329 INFO L335 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2023-11-29 03:18:12,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 490557 states and 624341 transitions. [2023-11-29 03:18:13,686 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 289264 [2023-11-29 03:18:13,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:18:13,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:18:13,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:18:13,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:18:13,688 INFO L748 eck$LassoCheckResult]: Stem: 5750330#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 5750331#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 5752484#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5752485#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5751199#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 5751200#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5750949#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5750732#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5750213#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5749564#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5749565#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5749650#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5749651#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5751490#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5751491#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5751601#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 5750413#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5750414#L1090 assume !(0 == ~M_E~0); 5750504#L1090-2 assume !(0 == ~T1_E~0); 5750505#L1095-1 assume !(0 == ~T2_E~0); 5751915#L1100-1 assume !(0 == ~T3_E~0); 5751916#L1105-1 assume !(0 == ~T4_E~0); 5750060#L1110-1 assume !(0 == ~T5_E~0); 5750061#L1115-1 assume !(0 == ~T6_E~0); 5750808#L1120-1 assume !(0 == ~T7_E~0); 5751434#L1125-1 assume !(0 == ~T8_E~0); 5752750#L1130-1 assume !(0 == ~T9_E~0); 5751961#L1135-1 assume !(0 == ~T10_E~0); 5750420#L1140-1 assume !(0 == ~T11_E~0); 5750421#L1145-1 assume !(0 == ~E_1~0); 5751821#L1150-1 assume !(0 == ~E_2~0); 5750764#L1155-1 assume !(0 == ~E_3~0); 5750765#L1160-1 assume !(0 == ~E_4~0); 5750958#L1165-1 assume !(0 == ~E_5~0); 5750959#L1170-1 assume !(0 == ~E_6~0); 5752434#L1175-1 assume !(0 == ~E_7~0); 5751117#L1180-1 assume !(0 == ~E_8~0); 5751118#L1185-1 assume 0 == ~E_9~0;~E_9~0 := 1; 5752124#L1190-1 assume !(0 == ~E_10~0); 5752936#L1195-1 assume !(0 == ~E_11~0); 5752935#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5750800#L525 assume !(1 == ~m_pc~0); 5749732#L525-2 is_master_triggered_~__retres1~0#1 := 0; 5749733#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5752149#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5752092#L1350 assume !(0 != activate_threads_~tmp~1#1); 5750401#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5750402#L544 assume !(1 == ~t1_pc~0); 5751253#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5751817#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5751818#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5750102#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 5750103#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5752924#L563 assume !(1 == ~t2_pc~0); 5751792#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5749768#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5749769#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5750549#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 5750550#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5751819#L582 assume !(1 == ~t3_pc~0); 5751820#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5752624#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5749554#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5749555#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 5752458#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5752791#L601 assume !(1 == ~t4_pc~0); 5751844#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5752000#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5752917#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5751835#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 5751836#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5752598#L620 assume !(1 == ~t5_pc~0); 5752599#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5751581#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5751582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5752165#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 5752655#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5752656#L639 assume !(1 == ~t6_pc~0); 5751432#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5750614#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5750615#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5750706#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 5752651#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5752906#L658 assume !(1 == ~t7_pc~0); 5752904#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5752682#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5752683#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5751700#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 5750406#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5750407#L677 assume !(1 == ~t8_pc~0); 5750443#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5750444#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5752896#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5750537#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 5750538#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5752071#L696 assume !(1 == ~t9_pc~0); 5751406#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5751407#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5752907#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5751450#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 5751451#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5751923#L715 assume !(1 == ~t10_pc~0); 5752720#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5752721#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5752897#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5752895#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 5752894#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5752892#L734 assume !(1 == ~t11_pc~0); 5752890#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 5752888#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5751716#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5749552#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 5749553#L1438-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5752593#L1213 assume !(1 == ~M_E~0); 5751103#L1213-2 assume !(1 == ~T1_E~0); 5751104#L1218-1 assume !(1 == ~T2_E~0); 5749608#L1223-1 assume !(1 == ~T3_E~0); 5749609#L1228-1 assume !(1 == ~T4_E~0); 5751051#L1233-1 assume !(1 == ~T5_E~0); 5752848#L1238-1 assume !(1 == ~T6_E~0); 5751833#L1243-1 assume !(1 == ~T7_E~0); 5751834#L1248-1 assume !(1 == ~T8_E~0); 5752875#L1253-1 assume !(1 == ~T9_E~0); 5752874#L1258-1 assume !(1 == ~T10_E~0); 5752873#L1263-1 assume !(1 == ~T11_E~0); 5752537#L1268-1 assume !(1 == ~E_1~0); 5751478#L1273-1 assume !(1 == ~E_2~0); 5751479#L1278-1 assume !(1 == ~E_3~0); 5750608#L1283-1 assume !(1 == ~E_4~0); 5750609#L1288-1 assume !(1 == ~E_5~0); 5752178#L1293-1 assume !(1 == ~E_6~0); 5752085#L1298-1 assume !(1 == ~E_7~0); 5751548#L1303-1 assume !(1 == ~E_8~0); 5750625#L1308-1 assume 1 == ~E_9~0;~E_9~0 := 2; 5750426#L1313-1 assume !(1 == ~E_10~0); 5750427#L1318-1 assume !(1 == ~E_11~0); 5750445#L1323-1 assume { :end_inline_reset_delta_events } true; 5750446#L1644-2 assume !false; 5764757#L1645 [2023-11-29 03:18:13,688 INFO L750 eck$LassoCheckResult]: Loop: 5764757#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5764744#L1065-1 assume !false; 5764735#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 5764724#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 5764714#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 5764704#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5764693#L906 assume 0 != eval_~tmp~0#1; 5764684#L906-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5764672#L914 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 5764664#L101 assume !(0 == ~m_pc~0); 5764655#L104 assume 1 == ~m_pc~0; 5764648#$Ultimate##421 assume !false; 5764641#L121 ~m_pc~0 := 1;~m_st~0 := 2; 5764631#master_returnLabel#1 assume { :end_inline_master } true; 5764621#L914-2 havoc eval_~tmp_ndt_1~0#1; 5764611#L911-1 assume !(0 == ~t1_st~0); 5764612#L925-1 assume !(0 == ~t2_st~0); 5765423#L939-1 assume !(0 == ~t3_st~0); 5765418#L953-1 assume !(0 == ~t4_st~0); 5765419#L967-1 assume !(0 == ~t5_st~0); 5765420#L981-1 assume !(0 == ~t6_st~0); 5765421#L995-1 assume !(0 == ~t7_st~0); 5765877#L1009-1 assume !(0 == ~t8_st~0); 5766600#L1023-1 assume !(0 == ~t9_st~0); 5766601#L1037-1 assume !(0 == ~t10_st~0); 5777455#L1051-1 assume !(0 == ~t11_st~0); 5779719#L1065-1 assume !false; 5779712#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 5779705#L829 assume !(0 == ~m_st~0); 5779696#L833 assume !(0 == ~t1_st~0); 5779689#L837 assume !(0 == ~t2_st~0); 5779679#L841 assume !(0 == ~t3_st~0); 5779673#L845 assume !(0 == ~t4_st~0); 5779668#L849 assume !(0 == ~t5_st~0); 5779662#L853 assume !(0 == ~t6_st~0); 5779657#L857 assume !(0 == ~t7_st~0); 5779652#L861 assume !(0 == ~t8_st~0); 5779647#L865 assume !(0 == ~t9_st~0); 5779643#L869 assume !(0 == ~t10_st~0); 5779638#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 5779633#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 5779626#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5779622#L906 assume !(0 != eval_~tmp~0#1); 5779618#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5779613#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5779608#L1090-3 assume !(0 == ~M_E~0); 5779603#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5779597#L1095-3 assume !(0 == ~T2_E~0); 5779592#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5779587#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5779581#L1110-3 assume !(0 == ~T5_E~0); 5779560#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5779557#L1120-3 assume !(0 == ~T7_E~0); 5779555#L1125-3 assume !(0 == ~T8_E~0); 5779553#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5779551#L1135-3 assume !(0 == ~T10_E~0); 5779549#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5779547#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5779545#L1150-3 assume !(0 == ~E_2~0); 5779543#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5779541#L1160-3 assume !(0 == ~E_4~0); 5779539#L1165-3 assume !(0 == ~E_5~0); 5779537#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5779535#L1175-3 assume !(0 == ~E_7~0); 5779531#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5779529#L1185-3 assume !(0 == ~E_9~0); 5779527#L1190-3 assume !(0 == ~E_10~0); 5779525#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5779523#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5779521#L525-36 assume 1 == ~m_pc~0; 5779517#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5779515#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5779514#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5779512#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5779507#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5779501#L544-36 assume !(1 == ~t1_pc~0); 5779496#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 5779491#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5778316#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5778313#L1358-36 assume !(0 != activate_threads_~tmp___0~0#1); 5778311#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5778305#L563-36 assume !(1 == ~t2_pc~0); 5778303#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5778301#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5778298#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5778296#L1366-36 assume !(0 != activate_threads_~tmp___1~0#1); 5778294#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5778293#L582-36 assume !(1 == ~t3_pc~0); 5778291#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5778289#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5778288#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5778285#L1374-36 assume !(0 != activate_threads_~tmp___2~0#1); 5778282#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5778279#L601-36 assume !(1 == ~t4_pc~0); 5778276#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 5778273#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5778271#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5778269#L1382-36 assume !(0 != activate_threads_~tmp___3~0#1); 5778266#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5778264#L620-36 assume !(1 == ~t5_pc~0); 5778262#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5778261#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5778260#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5778259#L1390-36 assume !(0 != activate_threads_~tmp___4~0#1); 5778258#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5778257#L639-36 assume !(1 == ~t6_pc~0); 5778253#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 5778252#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5778250#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5778248#L1398-36 assume !(0 != activate_threads_~tmp___5~0#1); 5778245#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5778243#L658-36 assume !(1 == ~t7_pc~0); 5778240#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5778238#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5778236#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5778234#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 5778231#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5778229#L677-36 assume !(1 == ~t8_pc~0); 5778227#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 5778225#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5778223#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5778221#L1414-36 assume !(0 != activate_threads_~tmp___7~0#1); 5778219#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5777816#L696-36 assume !(1 == ~t9_pc~0); 5777814#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5777812#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5777810#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5777808#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 5777806#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5777804#L715-36 assume !(1 == ~t10_pc~0); 5777802#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5777800#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5777798#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5777796#L1430-36 assume !(0 != activate_threads_~tmp___9~0#1); 5777794#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5777790#L734-36 assume 1 == ~t11_pc~0; 5777787#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5777785#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5777783#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5777776#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5777774#L1438-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5777772#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5777770#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5777768#L1218-3 assume !(1 == ~T2_E~0); 5777766#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5777764#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5777762#L1233-3 assume !(1 == ~T5_E~0); 5777760#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5777758#L1243-3 assume !(1 == ~T7_E~0); 5777756#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5777754#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5777751#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5777749#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5777747#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5777745#L1273-3 assume !(1 == ~E_2~0); 5777743#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5777741#L1283-3 assume !(1 == ~E_4~0); 5777739#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5777737#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5777735#L1298-3 assume !(1 == ~E_7~0); 5777733#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5777731#L1308-3 assume !(1 == ~E_9~0); 5777729#L1313-3 assume !(1 == ~E_10~0); 5777726#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5777723#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 5777721#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 5777719#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 5777716#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5777658#L1663 assume !(0 == start_simulation_~tmp~3#1); 5777656#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 5777654#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 5777652#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 5777650#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5777648#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5777646#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5777644#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 5777642#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 5764759#L1644-2 assume !false; 5764757#L1645 [2023-11-29 03:18:13,689 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:18:13,689 INFO L85 PathProgramCache]: Analyzing trace with hash 248100904, now seen corresponding path program 1 times [2023-11-29 03:18:13,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:18:13,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965350070] [2023-11-29 03:18:13,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:18:13,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:18:13,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:18:13,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:18:13,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:18:13,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965350070] [2023-11-29 03:18:13,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965350070] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:18:13,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:18:13,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:18:13,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475879473] [2023-11-29 03:18:13,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:18:13,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:18:13,748 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:18:13,748 INFO L85 PathProgramCache]: Analyzing trace with hash -2107867103, now seen corresponding path program 1 times [2023-11-29 03:18:13,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:18:13,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873251021] [2023-11-29 03:18:13,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:18:13,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:18:13,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:18:13,762 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:18:13,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:18:13,800 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:18:16,664 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 03:18:16,664 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 03:18:16,664 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 03:18:16,664 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 03:18:16,664 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-29 03:18:16,664 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:16,664 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 03:18:16,664 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 03:18:16,664 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.11.cil.c_Iteration45_Loop [2023-11-29 03:18:16,664 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 03:18:16,665 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 03:18:16,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,700 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,710 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,716 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,731 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,737 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,758 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,763 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,766 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,770 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,775 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,789 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,798 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,802 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,807 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,808 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,814 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,819 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,830 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,838 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,844 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,852 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,854 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,857 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,858 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,860 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,863 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,864 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,866 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,895 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,901 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,908 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,911 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,914 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,916 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,917 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:16,918 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,514 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 03:18:17,514 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-29 03:18:17,514 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:17,514 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:17,515 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:17,517 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2023-11-29 03:18:17,518 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:18:17,518 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:18:17,535 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:18:17,535 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:18:17,538 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Forceful destruction successful, exit code 0 [2023-11-29 03:18:17,538 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:17,539 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:17,539 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:17,540 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2023-11-29 03:18:17,541 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:18:17,541 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:18:17,553 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:18:17,553 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:18:17,555 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2023-11-29 03:18:17,555 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:17,555 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:17,556 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:17,557 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2023-11-29 03:18:17,559 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:18:17,559 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:18:17,570 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 03:18:17,570 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___9~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___9~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 03:18:17,573 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2023-11-29 03:18:17,573 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:17,573 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:17,574 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:17,574 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2023-11-29 03:18:17,576 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 03:18:17,576 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:18:17,589 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2023-11-29 03:18:17,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:17,590 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:17,591 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:17,591 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2023-11-29 03:18:17,593 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-29 03:18:17,593 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 03:18:17,608 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-29 03:18:17,614 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2023-11-29 03:18:17,614 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 03:18:17,614 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 03:18:17,614 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 03:18:17,614 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 03:18:17,614 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-29 03:18:17,615 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:17,615 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 03:18:17,615 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 03:18:17,615 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.11.cil.c_Iteration45_Loop [2023-11-29 03:18:17,615 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 03:18:17,615 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 03:18:17,617 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,619 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,623 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,627 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,629 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,631 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,632 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,633 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,642 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,658 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,660 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,664 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,666 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,682 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,700 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,702 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,716 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,734 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,759 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,767 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,769 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,770 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,775 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,781 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,788 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,791 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,793 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,814 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,816 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,819 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,826 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,829 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,842 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,844 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:17,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 03:18:18,482 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 03:18:18,482 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-29 03:18:18,482 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:18,482 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:18,483 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:18,483 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2023-11-29 03:18:18,485 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:18:18,494 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:18:18,494 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:18:18,495 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:18:18,495 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 03:18:18,495 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:18:18,495 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 03:18:18,496 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:18:18,497 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:18:18,499 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2023-11-29 03:18:18,500 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:18,500 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:18,500 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:18,501 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2023-11-29 03:18:18,503 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:18:18,512 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:18:18,512 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:18:18,513 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:18:18,513 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:18:18,513 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:18:18,513 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:18:18,513 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:18:18,514 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:18:18,516 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Forceful destruction successful, exit code 0 [2023-11-29 03:18:18,517 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:18,517 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:18,517 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:18,518 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2023-11-29 03:18:18,519 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:18:18,529 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:18:18,529 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:18:18,529 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:18:18,529 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:18:18,529 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:18:18,530 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:18:18,530 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:18:18,531 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:18:18,533 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Forceful destruction successful, exit code 0 [2023-11-29 03:18:18,533 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:18,534 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:18,534 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:18,535 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2023-11-29 03:18:18,536 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:18:18,546 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:18:18,546 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:18:18,546 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:18:18,546 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:18:18,546 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:18:18,547 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:18:18,547 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:18:18,548 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 03:18:18,551 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Forceful destruction successful, exit code 0 [2023-11-29 03:18:18,551 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:18,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:18,552 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:18,552 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2023-11-29 03:18:18,554 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 03:18:18,563 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 03:18:18,563 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 03:18:18,564 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 03:18:18,564 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 03:18:18,564 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 03:18:18,564 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 03:18:18,565 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 03:18:18,567 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-29 03:18:18,569 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-29 03:18:18,569 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-29 03:18:18,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:18:18,569 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:18:18,570 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:18:18,570 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2023-11-29 03:18:18,571 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-29 03:18:18,572 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-29 03:18:18,572 INFO L513 LassoAnalysis]: Proved termination. [2023-11-29 03:18:18,572 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T6_E~0) = -1*~T6_E~0 + 1 Supporting invariants [] [2023-11-29 03:18:18,574 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Ended with exit code 0 [2023-11-29 03:18:18,575 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-29 03:18:18,583 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:18:18,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:18:18,634 INFO L262 TraceCheckSpWp]: Trace formula consists of 390 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-29 03:18:18,636 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 03:18:18,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:18:18,812 INFO L262 TraceCheckSpWp]: Trace formula consists of 349 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-29 03:18:18,814 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 03:18:19,091 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2023-11-29 03:18:19,092 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-29 03:18:19,093 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 490557 states and 624341 transitions. cyclomatic complexity: 133896 Second operand has 5 states, 5 states have (on average 62.4) internal successors, (312), 5 states have internal predecessors, (312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:18:20,326 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7d799552-7b9c-48de-9910-3342ec4118f4/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Ended with exit code 0 [2023-11-29 03:18:22,505 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 490557 states and 624341 transitions. cyclomatic complexity: 133896. Second operand has 5 states, 5 states have (on average 62.4) internal successors, (312), 5 states have internal predecessors, (312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 982416 states and 1250514 transitions. Complement of second has 4 states. [2023-11-29 03:18:22,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-29 03:18:22,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 62.4) internal successors, (312), 5 states have internal predecessors, (312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:18:22,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 2066 transitions. [2023-11-29 03:18:22,508 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2066 transitions. Stem has 138 letters. Loop has 178 letters. [2023-11-29 03:18:22,510 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 03:18:22,511 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2066 transitions. Stem has 316 letters. Loop has 178 letters. [2023-11-29 03:18:22,512 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 03:18:22,512 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2066 transitions. Stem has 138 letters. Loop has 356 letters. [2023-11-29 03:18:22,515 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 03:18:22,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 982416 states and 1250514 transitions. [2023-11-29 03:18:25,992 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 289264 [2023-11-29 03:18:28,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 982416 states to 982416 states and 1250514 transitions. [2023-11-29 03:18:28,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 290766 [2023-11-29 03:18:28,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291247 [2023-11-29 03:18:28,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 982416 states and 1250514 transitions. [2023-11-29 03:18:28,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 03:18:28,385 INFO L218 hiAutomatonCegarLoop]: Abstraction has 982416 states and 1250514 transitions. [2023-11-29 03:18:29,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 982416 states and 1250514 transitions. [2023-11-29 03:18:35,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 982416 to 981935. [2023-11-29 03:18:36,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981935 states, 981935 states have (on average 1.2725414615020343) internal successors, (1249553), 981934 states have internal predecessors, (1249553), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:18:39,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981935 states to 981935 states and 1249553 transitions. [2023-11-29 03:18:39,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981935 states and 1249553 transitions. [2023-11-29 03:18:39,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:18:39,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:18:39,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:18:39,633 INFO L87 Difference]: Start difference. First operand 981935 states and 1249553 transitions. Second operand has 4 states, 4 states have (on average 34.5) internal successors, (138), 3 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:18:45,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:18:45,036 INFO L93 Difference]: Finished difference Result 1749435 states and 2223589 transitions. [2023-11-29 03:18:45,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1749435 states and 2223589 transitions. [2023-11-29 03:18:51,048 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 472112 [2023-11-29 03:18:55,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1749435 states to 1749435 states and 2223589 transitions. [2023-11-29 03:18:55,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 474393 [2023-11-29 03:18:55,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 474393 [2023-11-29 03:18:55,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1749435 states and 2223589 transitions. [2023-11-29 03:18:55,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 03:18:55,647 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1749435 states and 2223589 transitions. [2023-11-29 03:18:56,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1749435 states and 2223589 transitions. [2023-11-29 03:19:06,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1749435 to 981861. [2023-11-29 03:19:07,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981861 states, 981861 states have (on average 1.2724021017231564) internal successors, (1249322), 981860 states have internal predecessors, (1249322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:19:10,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981861 states to 981861 states and 1249322 transitions. [2023-11-29 03:19:10,470 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981861 states and 1249322 transitions. [2023-11-29 03:19:10,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:19:10,471 INFO L428 stractBuchiCegarLoop]: Abstraction has 981861 states and 1249322 transitions. [2023-11-29 03:19:10,471 INFO L335 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2023-11-29 03:19:10,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981861 states and 1249322 transitions.