./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 00:57:01,938 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 00:57:02,065 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/config/svcomp-Reach-32bit-Taipan_Default.epf [2023-11-12 00:57:02,072 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 00:57:02,073 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 00:57:02,128 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 00:57:02,129 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 00:57:02,130 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 00:57:02,131 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2023-11-12 00:57:02,136 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2023-11-12 00:57:02,136 INFO L153 SettingsManager]: * User list type=DISABLED [2023-11-12 00:57:02,138 INFO L151 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2023-11-12 00:57:02,138 INFO L153 SettingsManager]: * Explicit value domain=true [2023-11-12 00:57:02,140 INFO L153 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2023-11-12 00:57:02,141 INFO L153 SettingsManager]: * Octagon Domain=false [2023-11-12 00:57:02,141 INFO L153 SettingsManager]: * Abstract domain=CompoundDomain [2023-11-12 00:57:02,142 INFO L153 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2023-11-12 00:57:02,142 INFO L153 SettingsManager]: * Use the RCFG-of-the-future interface=true [2023-11-12 00:57:02,143 INFO L153 SettingsManager]: * Interval Domain=false [2023-11-12 00:57:02,144 INFO L151 SettingsManager]: Preferences of Sifa differ from their defaults: [2023-11-12 00:57:02,144 INFO L153 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2023-11-12 00:57:02,145 INFO L153 SettingsManager]: * Simplification Technique=POLY_PAC [2023-11-12 00:57:02,165 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 00:57:02,165 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2023-11-12 00:57:02,166 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 00:57:02,166 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 00:57:02,167 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 00:57:02,167 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 00:57:02,168 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2023-11-12 00:57:02,168 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2023-11-12 00:57:02,170 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2023-11-12 00:57:02,174 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 00:57:02,175 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 00:57:02,175 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 00:57:02,175 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 00:57:02,176 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2023-11-12 00:57:02,176 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2023-11-12 00:57:02,176 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 00:57:02,177 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2023-11-12 00:57:02,177 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2023-11-12 00:57:02,178 INFO L153 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2023-11-12 00:57:02,178 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2023-11-12 00:57:02,179 INFO L153 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2023-11-12 00:57:02,179 INFO L153 SettingsManager]: * Trace refinement exception blacklist=NONE [2023-11-12 00:57:02,180 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2023-11-12 00:57:02,180 INFO L153 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2023-11-12 00:57:02,473 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 00:57:02,496 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 00:57:02,499 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 00:57:02,501 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 00:57:02,501 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 00:57:02,503 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2023-11-12 00:57:05,703 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 00:57:05,960 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 00:57:05,961 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/sv-benchmarks/c/systemc/transmitter.15.cil.c [2023-11-12 00:57:05,978 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/data/581d2c522/1b95abc744ed4a7ba1ad5d958b095154/FLAG55c332605 [2023-11-12 00:57:05,992 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/data/581d2c522/1b95abc744ed4a7ba1ad5d958b095154 [2023-11-12 00:57:05,994 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 00:57:05,995 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 00:57:05,997 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 00:57:05,997 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 00:57:06,002 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 00:57:06,003 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 12:57:05" (1/1) ... [2023-11-12 00:57:06,004 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@da93208 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06, skipping insertion in model container [2023-11-12 00:57:06,004 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 12:57:05" (1/1) ... [2023-11-12 00:57:06,095 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 00:57:06,246 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2023-11-12 00:57:06,420 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 00:57:06,443 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 00:57:06,456 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2023-11-12 00:57:06,568 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 00:57:06,609 INFO L206 MainTranslator]: Completed translation [2023-11-12 00:57:06,609 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06 WrapperNode [2023-11-12 00:57:06,609 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 00:57:06,610 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 00:57:06,611 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 00:57:06,611 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 00:57:06,618 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,636 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,703 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 38, calls inlined = 38, statements flattened = 918 [2023-11-12 00:57:06,703 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 00:57:06,704 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 00:57:06,704 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 00:57:06,705 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 00:57:06,714 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,726 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,733 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,733 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,751 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,766 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,771 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,775 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,782 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 00:57:06,784 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 00:57:06,784 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 00:57:06,784 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 00:57:06,785 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (1/1) ... [2023-11-12 00:57:06,792 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2023-11-12 00:57:06,808 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/z3 [2023-11-12 00:57:06,824 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2023-11-12 00:57:06,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2023-11-12 00:57:06,859 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 00:57:06,859 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2023-11-12 00:57:06,859 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2023-11-12 00:57:06,859 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2023-11-12 00:57:06,859 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2023-11-12 00:57:06,860 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2023-11-12 00:57:06,860 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2023-11-12 00:57:06,860 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2023-11-12 00:57:06,860 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2023-11-12 00:57:06,861 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2023-11-12 00:57:06,861 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2023-11-12 00:57:06,861 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2023-11-12 00:57:06,861 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2023-11-12 00:57:06,861 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 00:57:06,861 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 00:57:06,861 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 00:57:07,059 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 00:57:07,062 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 00:57:08,133 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 00:57:08,933 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 00:57:08,933 INFO L302 CfgBuilder]: Removed 17 assume(true) statements. [2023-11-12 00:57:08,937 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 12:57:08 BoogieIcfgContainer [2023-11-12 00:57:08,937 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 00:57:08,940 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2023-11-12 00:57:08,940 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2023-11-12 00:57:08,943 INFO L274 PluginConnector]: TraceAbstraction initialized [2023-11-12 00:57:08,944 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 12.11 12:57:05" (1/3) ... [2023-11-12 00:57:08,944 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42a002e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.11 12:57:08, skipping insertion in model container [2023-11-12 00:57:08,945 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 12:57:06" (2/3) ... [2023-11-12 00:57:08,945 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42a002e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.11 12:57:08, skipping insertion in model container [2023-11-12 00:57:08,945 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 12:57:08" (3/3) ... [2023-11-12 00:57:08,947 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.15.cil.c [2023-11-12 00:57:08,968 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2023-11-12 00:57:08,968 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2023-11-12 00:57:09,025 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2023-11-12 00:57:09,033 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@163fcb74, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2023-11-12 00:57:09,033 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2023-11-12 00:57:09,039 INFO L276 IsEmpty]: Start isEmpty. Operand has 206 states, 172 states have (on average 1.5116279069767442) internal successors, (260), 174 states have internal predecessors, (260), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2023-11-12 00:57:09,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:09,052 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:09,052 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:09,053 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:09,058 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:09,059 INFO L85 PathProgramCache]: Analyzing trace with hash 536838258, now seen corresponding path program 1 times [2023-11-12 00:57:09,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:09,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944025288] [2023-11-12 00:57:09,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:09,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:09,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:09,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:09,663 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:09,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944025288] [2023-11-12 00:57:09,664 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944025288] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:09,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:09,664 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 00:57:09,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312441921] [2023-11-12 00:57:09,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:09,672 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2023-11-12 00:57:09,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:09,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 00:57:09,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 00:57:09,724 INFO L87 Difference]: Start difference. First operand has 206 states, 172 states have (on average 1.5116279069767442) internal successors, (260), 174 states have internal predecessors, (260), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:10,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:10,406 INFO L93 Difference]: Finished difference Result 601 states and 940 transitions. [2023-11-12 00:57:10,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 00:57:10,409 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:10,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:10,423 INFO L225 Difference]: With dead ends: 601 [2023-11-12 00:57:10,423 INFO L226 Difference]: Without dead ends: 396 [2023-11-12 00:57:10,430 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 00:57:10,434 INFO L413 NwaCegarLoop]: 486 mSDtfsCounter, 542 mSDsluCounter, 392 mSDsCounter, 0 mSdLazyCounter, 302 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 542 SdHoareTripleChecker+Valid, 878 SdHoareTripleChecker+Invalid, 316 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 302 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:10,435 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [542 Valid, 878 Invalid, 316 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 302 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2023-11-12 00:57:10,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states. [2023-11-12 00:57:10,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 393. [2023-11-12 00:57:10,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 333 states have (on average 1.4714714714714714) internal successors, (490), 334 states have internal predecessors, (490), 47 states have call successors, (47), 12 states have call predecessors, (47), 12 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2023-11-12 00:57:10,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 584 transitions. [2023-11-12 00:57:10,529 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 584 transitions. Word has length 67 [2023-11-12 00:57:10,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:10,530 INFO L495 AbstractCegarLoop]: Abstraction has 393 states and 584 transitions. [2023-11-12 00:57:10,530 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:10,530 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 584 transitions. [2023-11-12 00:57:10,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:10,534 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:10,534 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:10,534 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2023-11-12 00:57:10,535 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:10,535 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:10,535 INFO L85 PathProgramCache]: Analyzing trace with hash 777105587, now seen corresponding path program 1 times [2023-11-12 00:57:10,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:10,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481017491] [2023-11-12 00:57:10,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:10,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:10,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:10,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:10,772 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:10,773 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481017491] [2023-11-12 00:57:10,773 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481017491] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:10,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:10,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 00:57:10,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454784734] [2023-11-12 00:57:10,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:10,777 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2023-11-12 00:57:10,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:10,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 00:57:10,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 00:57:10,779 INFO L87 Difference]: Start difference. First operand 393 states and 584 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:11,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:11,777 INFO L93 Difference]: Finished difference Result 1350 states and 2030 transitions. [2023-11-12 00:57:11,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-12 00:57:11,778 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:11,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:11,785 INFO L225 Difference]: With dead ends: 1350 [2023-11-12 00:57:11,785 INFO L226 Difference]: Without dead ends: 935 [2023-11-12 00:57:11,788 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2023-11-12 00:57:11,790 INFO L413 NwaCegarLoop]: 478 mSDtfsCounter, 1161 mSDsluCounter, 857 mSDsCounter, 0 mSdLazyCounter, 479 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1335 SdHoareTripleChecker+Invalid, 689 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 479 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:11,790 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1335 Invalid, 689 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 479 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2023-11-12 00:57:11,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 935 states. [2023-11-12 00:57:11,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 935 to 923. [2023-11-12 00:57:11,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 923 states, 802 states have (on average 1.4600997506234414) internal successors, (1171), 791 states have internal predecessors, (1171), 92 states have call successors, (92), 26 states have call predecessors, (92), 28 states have return successors, (106), 106 states have call predecessors, (106), 92 states have call successors, (106) [2023-11-12 00:57:11,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 923 states to 923 states and 1369 transitions. [2023-11-12 00:57:11,874 INFO L78 Accepts]: Start accepts. Automaton has 923 states and 1369 transitions. Word has length 67 [2023-11-12 00:57:11,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:11,875 INFO L495 AbstractCegarLoop]: Abstraction has 923 states and 1369 transitions. [2023-11-12 00:57:11,875 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:11,875 INFO L276 IsEmpty]: Start isEmpty. Operand 923 states and 1369 transitions. [2023-11-12 00:57:11,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:11,885 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:11,885 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:11,885 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2023-11-12 00:57:11,886 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:11,891 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:11,896 INFO L85 PathProgramCache]: Analyzing trace with hash -1323735628, now seen corresponding path program 1 times [2023-11-12 00:57:11,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:11,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105400218] [2023-11-12 00:57:11,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:11,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:11,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:12,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:12,080 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:12,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105400218] [2023-11-12 00:57:12,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1105400218] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:12,081 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:12,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 00:57:12,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498780372] [2023-11-12 00:57:12,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:12,082 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2023-11-12 00:57:12,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:12,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 00:57:12,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 00:57:12,084 INFO L87 Difference]: Start difference. First operand 923 states and 1369 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:13,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:13,003 INFO L93 Difference]: Finished difference Result 3251 states and 4886 transitions. [2023-11-12 00:57:13,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-12 00:57:13,004 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:13,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:13,020 INFO L225 Difference]: With dead ends: 3251 [2023-11-12 00:57:13,021 INFO L226 Difference]: Without dead ends: 2282 [2023-11-12 00:57:13,025 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2023-11-12 00:57:13,027 INFO L413 NwaCegarLoop]: 478 mSDtfsCounter, 1161 mSDsluCounter, 812 mSDsCounter, 0 mSdLazyCounter, 475 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1290 SdHoareTripleChecker+Invalid, 685 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 475 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:13,028 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1290 Invalid, 685 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 475 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2023-11-12 00:57:13,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2282 states. [2023-11-12 00:57:13,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2282 to 1762. [2023-11-12 00:57:13,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1762 states, 1533 states have (on average 1.4644487932159165) internal successors, (2245), 1523 states have internal predecessors, (2245), 172 states have call successors, (172), 50 states have call predecessors, (172), 56 states have return successors, (213), 189 states have call predecessors, (213), 172 states have call successors, (213) [2023-11-12 00:57:13,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1762 states to 1762 states and 2630 transitions. [2023-11-12 00:57:13,160 INFO L78 Accepts]: Start accepts. Automaton has 1762 states and 2630 transitions. Word has length 67 [2023-11-12 00:57:13,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:13,161 INFO L495 AbstractCegarLoop]: Abstraction has 1762 states and 2630 transitions. [2023-11-12 00:57:13,161 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:13,161 INFO L276 IsEmpty]: Start isEmpty. Operand 1762 states and 2630 transitions. [2023-11-12 00:57:13,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:13,163 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:13,163 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:13,163 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2023-11-12 00:57:13,163 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:13,164 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:13,164 INFO L85 PathProgramCache]: Analyzing trace with hash 109099091, now seen corresponding path program 1 times [2023-11-12 00:57:13,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:13,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514892407] [2023-11-12 00:57:13,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:13,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:13,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:13,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:13,381 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:13,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514892407] [2023-11-12 00:57:13,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514892407] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:13,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:13,383 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 00:57:13,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128494043] [2023-11-12 00:57:13,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:13,384 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2023-11-12 00:57:13,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:13,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 00:57:13,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 00:57:13,387 INFO L87 Difference]: Start difference. First operand 1762 states and 2630 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:14,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:14,231 INFO L93 Difference]: Finished difference Result 6134 states and 9307 transitions. [2023-11-12 00:57:14,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-12 00:57:14,232 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:14,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:14,303 INFO L225 Difference]: With dead ends: 6134 [2023-11-12 00:57:14,303 INFO L226 Difference]: Without dead ends: 4279 [2023-11-12 00:57:14,312 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2023-11-12 00:57:14,313 INFO L413 NwaCegarLoop]: 472 mSDtfsCounter, 1161 mSDsluCounter, 580 mSDsCounter, 0 mSdLazyCounter, 424 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1052 SdHoareTripleChecker+Invalid, 634 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 424 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:14,313 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1052 Invalid, 634 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 424 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2023-11-12 00:57:14,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4279 states. [2023-11-12 00:57:14,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4279 to 3414. [2023-11-12 00:57:14,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3414 states, 2973 states have (on average 1.46552304069963) internal successors, (4357), 2967 states have internal predecessors, (4357), 328 states have call successors, (328), 98 states have call predecessors, (328), 112 states have return successors, (421), 349 states have call predecessors, (421), 328 states have call successors, (421) [2023-11-12 00:57:14,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3414 states to 3414 states and 5106 transitions. [2023-11-12 00:57:14,536 INFO L78 Accepts]: Start accepts. Automaton has 3414 states and 5106 transitions. Word has length 67 [2023-11-12 00:57:14,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:14,537 INFO L495 AbstractCegarLoop]: Abstraction has 3414 states and 5106 transitions. [2023-11-12 00:57:14,537 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:14,537 INFO L276 IsEmpty]: Start isEmpty. Operand 3414 states and 5106 transitions. [2023-11-12 00:57:14,538 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:14,538 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:14,538 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:14,539 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2023-11-12 00:57:14,539 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:14,539 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:14,540 INFO L85 PathProgramCache]: Analyzing trace with hash -2046415310, now seen corresponding path program 1 times [2023-11-12 00:57:14,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:14,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101161901] [2023-11-12 00:57:14,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:14,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:14,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:14,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:14,650 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:14,650 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101161901] [2023-11-12 00:57:14,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101161901] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:14,650 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:14,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 00:57:14,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40764350] [2023-11-12 00:57:14,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:14,652 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2023-11-12 00:57:14,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:14,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 00:57:14,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 00:57:14,653 INFO L87 Difference]: Start difference. First operand 3414 states and 5106 transitions. Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:15,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:15,415 INFO L93 Difference]: Finished difference Result 10175 states and 15493 transitions. [2023-11-12 00:57:15,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 00:57:15,416 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:15,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:15,465 INFO L225 Difference]: With dead ends: 10175 [2023-11-12 00:57:15,466 INFO L226 Difference]: Without dead ends: 6766 [2023-11-12 00:57:15,483 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 00:57:15,484 INFO L413 NwaCegarLoop]: 485 mSDtfsCounter, 563 mSDsluCounter, 391 mSDsCounter, 0 mSdLazyCounter, 304 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 563 SdHoareTripleChecker+Valid, 876 SdHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 304 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:15,484 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [563 Valid, 876 Invalid, 309 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 304 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2023-11-12 00:57:15,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6766 states. [2023-11-12 00:57:15,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6766 to 6746. [2023-11-12 00:57:15,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6746 states, 5885 states have (on average 1.4569243840271877) internal successors, (8574), 5873 states have internal predecessors, (8574), 636 states have call successors, (636), 196 states have call predecessors, (636), 224 states have return successors, (815), 677 states have call predecessors, (815), 636 states have call successors, (815) [2023-11-12 00:57:15,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6746 states to 6746 states and 10025 transitions. [2023-11-12 00:57:15,967 INFO L78 Accepts]: Start accepts. Automaton has 6746 states and 10025 transitions. Word has length 67 [2023-11-12 00:57:15,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:15,969 INFO L495 AbstractCegarLoop]: Abstraction has 6746 states and 10025 transitions. [2023-11-12 00:57:15,969 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:15,969 INFO L276 IsEmpty]: Start isEmpty. Operand 6746 states and 10025 transitions. [2023-11-12 00:57:15,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:15,971 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:15,972 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:15,972 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2023-11-12 00:57:15,972 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:15,973 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:15,973 INFO L85 PathProgramCache]: Analyzing trace with hash 483735377, now seen corresponding path program 1 times [2023-11-12 00:57:15,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:15,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571988969] [2023-11-12 00:57:15,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:15,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:16,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:16,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:16,217 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:16,217 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571988969] [2023-11-12 00:57:16,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571988969] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:16,218 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:16,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 00:57:16,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747015971] [2023-11-12 00:57:16,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:16,219 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2023-11-12 00:57:16,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:16,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 00:57:16,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 00:57:16,220 INFO L87 Difference]: Start difference. First operand 6746 states and 10025 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:17,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:17,605 INFO L93 Difference]: Finished difference Result 22978 states and 34778 transitions. [2023-11-12 00:57:17,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-12 00:57:17,615 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:17,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:17,752 INFO L225 Difference]: With dead ends: 22978 [2023-11-12 00:57:17,752 INFO L226 Difference]: Without dead ends: 15865 [2023-11-12 00:57:17,790 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2023-11-12 00:57:17,795 INFO L413 NwaCegarLoop]: 472 mSDtfsCounter, 1161 mSDsluCounter, 580 mSDsCounter, 0 mSdLazyCounter, 424 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1052 SdHoareTripleChecker+Invalid, 634 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 424 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:17,796 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1052 Invalid, 634 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 424 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2023-11-12 00:57:17,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15865 states. [2023-11-12 00:57:18,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15865 to 13187. [2023-11-12 00:57:18,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13187 states, 11510 states have (on average 1.455516941789748) internal successors, (16753), 11514 states have internal predecessors, (16753), 1228 states have call successors, (1228), 388 states have call predecessors, (1228), 448 states have return successors, (1599), 1285 states have call predecessors, (1599), 1228 states have call successors, (1599) [2023-11-12 00:57:18,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13187 states to 13187 states and 19580 transitions. [2023-11-12 00:57:18,823 INFO L78 Accepts]: Start accepts. Automaton has 13187 states and 19580 transitions. Word has length 67 [2023-11-12 00:57:18,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:18,824 INFO L495 AbstractCegarLoop]: Abstraction has 13187 states and 19580 transitions. [2023-11-12 00:57:18,825 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:18,825 INFO L276 IsEmpty]: Start isEmpty. Operand 13187 states and 19580 transitions. [2023-11-12 00:57:18,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:18,826 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:18,826 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:18,827 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2023-11-12 00:57:18,827 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:18,829 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:18,829 INFO L85 PathProgramCache]: Analyzing trace with hash 426591152, now seen corresponding path program 1 times [2023-11-12 00:57:18,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:18,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948286210] [2023-11-12 00:57:18,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:18,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:18,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:18,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:18,974 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:18,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948286210] [2023-11-12 00:57:18,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948286210] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:18,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:18,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 00:57:18,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492543116] [2023-11-12 00:57:18,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:18,976 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2023-11-12 00:57:18,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:18,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 00:57:18,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 00:57:18,977 INFO L87 Difference]: Start difference. First operand 13187 states and 19580 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:21,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:21,220 INFO L93 Difference]: Finished difference Result 44333 states and 67091 transitions. [2023-11-12 00:57:21,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-12 00:57:21,221 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:21,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:21,352 INFO L225 Difference]: With dead ends: 44333 [2023-11-12 00:57:21,352 INFO L226 Difference]: Without dead ends: 30427 [2023-11-12 00:57:21,406 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2023-11-12 00:57:21,407 INFO L413 NwaCegarLoop]: 472 mSDtfsCounter, 1161 mSDsluCounter, 580 mSDsCounter, 0 mSdLazyCounter, 424 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1052 SdHoareTripleChecker+Invalid, 634 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 424 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:21,407 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1052 Invalid, 634 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 424 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2023-11-12 00:57:21,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30427 states. [2023-11-12 00:57:22,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30427 to 25925. [2023-11-12 00:57:22,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25925 states, 22648 states have (on average 1.4531525962557401) internal successors, (32911), 22684 states have internal predecessors, (32911), 2380 states have call successors, (2380), 772 states have call predecessors, (2380), 896 states have return successors, (3119), 2469 states have call predecessors, (3119), 2380 states have call successors, (3119) [2023-11-12 00:57:23,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25925 states to 25925 states and 38410 transitions. [2023-11-12 00:57:23,120 INFO L78 Accepts]: Start accepts. Automaton has 25925 states and 38410 transitions. Word has length 67 [2023-11-12 00:57:23,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:23,121 INFO L495 AbstractCegarLoop]: Abstraction has 25925 states and 38410 transitions. [2023-11-12 00:57:23,121 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:23,121 INFO L276 IsEmpty]: Start isEmpty. Operand 25925 states and 38410 transitions. [2023-11-12 00:57:23,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:23,127 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:23,127 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:23,127 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2023-11-12 00:57:23,128 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:23,128 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:23,128 INFO L85 PathProgramCache]: Analyzing trace with hash -1163803825, now seen corresponding path program 1 times [2023-11-12 00:57:23,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:23,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134209763] [2023-11-12 00:57:23,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:23,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:23,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:23,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:23,254 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:23,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134209763] [2023-11-12 00:57:23,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134209763] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:23,255 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:23,255 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 00:57:23,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087501277] [2023-11-12 00:57:23,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:23,256 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2023-11-12 00:57:23,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:23,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 00:57:23,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 00:57:23,257 INFO L87 Difference]: Start difference. First operand 25925 states and 38410 transitions. Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:26,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:26,074 INFO L93 Difference]: Finished difference Result 77316 states and 116534 transitions. [2023-11-12 00:57:26,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 00:57:26,075 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:26,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:26,303 INFO L225 Difference]: With dead ends: 77316 [2023-11-12 00:57:26,304 INFO L226 Difference]: Without dead ends: 51396 [2023-11-12 00:57:26,512 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 00:57:26,527 INFO L413 NwaCegarLoop]: 485 mSDtfsCounter, 578 mSDsluCounter, 391 mSDsCounter, 0 mSdLazyCounter, 304 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 578 SdHoareTripleChecker+Valid, 876 SdHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 304 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:26,527 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [578 Valid, 876 Invalid, 309 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 304 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2023-11-12 00:57:26,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51396 states. [2023-11-12 00:57:29,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51396 to 51262. [2023-11-12 00:57:29,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51262 states, 44841 states have (on average 1.4435226689859726) internal successors, (64729), 44914 states have internal predecessors, (64729), 4628 states have call successors, (4628), 1544 states have call predecessors, (4628), 1792 states have return successors, (6044), 4804 states have call predecessors, (6044), 4628 states have call successors, (6044) [2023-11-12 00:57:30,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51262 states to 51262 states and 75401 transitions. [2023-11-12 00:57:30,343 INFO L78 Accepts]: Start accepts. Automaton has 51262 states and 75401 transitions. Word has length 67 [2023-11-12 00:57:30,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:30,344 INFO L495 AbstractCegarLoop]: Abstraction has 51262 states and 75401 transitions. [2023-11-12 00:57:30,344 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:30,344 INFO L276 IsEmpty]: Start isEmpty. Operand 51262 states and 75401 transitions. [2023-11-12 00:57:30,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2023-11-12 00:57:30,345 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:30,345 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:30,346 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2023-11-12 00:57:30,346 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:30,346 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:30,347 INFO L85 PathProgramCache]: Analyzing trace with hash -2137292784, now seen corresponding path program 1 times [2023-11-12 00:57:30,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:30,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119254493] [2023-11-12 00:57:30,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:30,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:30,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 00:57:30,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 00:57:30,680 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2023-11-12 00:57:30,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119254493] [2023-11-12 00:57:30,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119254493] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 00:57:30,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 00:57:30,680 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2023-11-12 00:57:30,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232915938] [2023-11-12 00:57:30,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 00:57:30,681 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2023-11-12 00:57:30,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2023-11-12 00:57:30,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2023-11-12 00:57:30,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2023-11-12 00:57:30,683 INFO L87 Difference]: Start difference. First operand 51262 states and 75401 transitions. Second operand has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:34,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 00:57:34,793 INFO L93 Difference]: Finished difference Result 150064 states and 221945 transitions. [2023-11-12 00:57:34,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2023-11-12 00:57:34,794 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2023-11-12 00:57:34,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2023-11-12 00:57:35,214 INFO L225 Difference]: With dead ends: 150064 [2023-11-12 00:57:35,214 INFO L226 Difference]: Without dead ends: 98808 [2023-11-12 00:57:35,323 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2023-11-12 00:57:35,326 INFO L413 NwaCegarLoop]: 238 mSDtfsCounter, 917 mSDsluCounter, 502 mSDsCounter, 0 mSdLazyCounter, 278 mSolverCounterSat, 146 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 924 SdHoareTripleChecker+Valid, 740 SdHoareTripleChecker+Invalid, 424 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 146 IncrementalHoareTripleChecker+Valid, 278 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2023-11-12 00:57:35,326 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [924 Valid, 740 Invalid, 424 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [146 Valid, 278 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2023-11-12 00:57:35,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98808 states. [2023-11-12 00:57:40,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98808 to 86564. [2023-11-12 00:57:40,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86564 states, 76479 states have (on average 1.4355182468390015) internal successors, (109787), 76624 states have internal predecessors, (109787), 7012 states have call successors, (7012), 2576 states have call predecessors, (7012), 3072 states have return successors, (9844), 7364 states have call predecessors, (9844), 7012 states have call successors, (9844) [2023-11-12 00:57:41,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86564 states to 86564 states and 126643 transitions. [2023-11-12 00:57:41,163 INFO L78 Accepts]: Start accepts. Automaton has 86564 states and 126643 transitions. Word has length 67 [2023-11-12 00:57:41,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2023-11-12 00:57:41,164 INFO L495 AbstractCegarLoop]: Abstraction has 86564 states and 126643 transitions. [2023-11-12 00:57:41,164 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2023-11-12 00:57:41,164 INFO L276 IsEmpty]: Start isEmpty. Operand 86564 states and 126643 transitions. [2023-11-12 00:57:41,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2023-11-12 00:57:41,165 INFO L187 NwaCegarLoop]: Found error trace [2023-11-12 00:57:41,166 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:41,166 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2023-11-12 00:57:41,166 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2023-11-12 00:57:41,166 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 00:57:41,167 INFO L85 PathProgramCache]: Analyzing trace with hash 1853638562, now seen corresponding path program 1 times [2023-11-12 00:57:41,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2023-11-12 00:57:41,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543087501] [2023-11-12 00:57:41,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 00:57:41,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 00:57:41,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 00:57:41,213 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 00:57:41,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 00:57:41,387 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2023-11-12 00:57:41,387 INFO L360 BasicCegarLoop]: Counterexample is feasible [2023-11-12 00:57:41,388 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2023-11-12 00:57:41,391 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2023-11-12 00:57:41,396 INFO L445 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 00:57:41,402 INFO L179 ceAbstractionStarter]: Computing trace abstraction results [2023-11-12 00:57:41,563 WARN L1567 BoogieBacktranslator]: Unfinished Backtranslation: IdentifierExpression #t~ret4 could not be translated [2023-11-12 00:57:41,614 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.11 12:57:41 BoogieIcfgContainer [2023-11-12 00:57:41,615 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2023-11-12 00:57:41,615 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-12 00:57:41,615 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-12 00:57:41,616 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-12 00:57:41,616 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 12:57:08" (3/4) ... [2023-11-12 00:57:41,617 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2023-11-12 00:57:41,682 WARN L1567 BoogieBacktranslator]: Unfinished Backtranslation: IdentifierExpression #t~ret4 could not be translated [2023-11-12 00:57:41,817 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/witness.graphml [2023-11-12 00:57:41,817 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-12 00:57:41,818 INFO L158 Benchmark]: Toolchain (without parser) took 35822.63ms. Allocated memory was 132.1MB in the beginning and 10.9GB in the end (delta: 10.7GB). Free memory was 87.3MB in the beginning and 10.0GB in the end (delta: -9.9GB). Peak memory consumption was 822.8MB. Max. memory is 16.1GB. [2023-11-12 00:57:41,818 INFO L158 Benchmark]: CDTParser took 0.36ms. Allocated memory is still 132.1MB. Free memory is still 99.6MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-12 00:57:41,819 INFO L158 Benchmark]: CACSL2BoogieTranslator took 612.97ms. Allocated memory is still 132.1MB. Free memory was 86.8MB in the beginning and 62.9MB in the end (delta: 23.9MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. [2023-11-12 00:57:41,819 INFO L158 Benchmark]: Boogie Procedure Inliner took 93.23ms. Allocated memory is still 132.1MB. Free memory was 62.9MB in the beginning and 58.7MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-12 00:57:41,820 INFO L158 Benchmark]: Boogie Preprocessor took 78.57ms. Allocated memory is still 132.1MB. Free memory was 58.7MB in the beginning and 55.0MB in the end (delta: 3.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-12 00:57:41,820 INFO L158 Benchmark]: RCFGBuilder took 2153.84ms. Allocated memory was 132.1MB in the beginning and 190.8MB in the end (delta: 58.7MB). Free memory was 55.0MB in the beginning and 124.9MB in the end (delta: -69.9MB). Peak memory consumption was 53.4MB. Max. memory is 16.1GB. [2023-11-12 00:57:41,821 INFO L158 Benchmark]: TraceAbstraction took 32675.23ms. Allocated memory was 190.8MB in the beginning and 10.9GB in the end (delta: 10.7GB). Free memory was 124.9MB in the beginning and 10.0GB in the end (delta: -9.9GB). Peak memory consumption was 779.9MB. Max. memory is 16.1GB. [2023-11-12 00:57:41,825 INFO L158 Benchmark]: Witness Printer took 202.18ms. Allocated memory is still 10.9GB. Free memory was 10.0GB in the beginning and 10.0GB in the end (delta: 19.9MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2023-11-12 00:57:41,828 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.36ms. Allocated memory is still 132.1MB. Free memory is still 99.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 612.97ms. Allocated memory is still 132.1MB. Free memory was 86.8MB in the beginning and 62.9MB in the end (delta: 23.9MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 93.23ms. Allocated memory is still 132.1MB. Free memory was 62.9MB in the beginning and 58.7MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 78.57ms. Allocated memory is still 132.1MB. Free memory was 58.7MB in the beginning and 55.0MB in the end (delta: 3.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 2153.84ms. Allocated memory was 132.1MB in the beginning and 190.8MB in the end (delta: 58.7MB). Free memory was 55.0MB in the beginning and 124.9MB in the end (delta: -69.9MB). Peak memory consumption was 53.4MB. Max. memory is 16.1GB. * TraceAbstraction took 32675.23ms. Allocated memory was 190.8MB in the beginning and 10.9GB in the end (delta: 10.7GB). Free memory was 124.9MB in the beginning and 10.0GB in the end (delta: -9.9GB). Peak memory consumption was 779.9MB. Max. memory is 16.1GB. * Witness Printer took 202.18ms. Allocated memory is still 10.9GB. Free memory was 10.0GB in the beginning and 10.0GB in the end (delta: 19.9MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IdentifierExpression #t~ret4 could not be translated - GenericResult: Unfinished Backtranslation The program execution was not completely translated back. - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IdentifierExpression #t~ret4 could not be translated - GenericResult: Unfinished Backtranslation The program execution was not completely translated back. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int m_st ; [L40] int t1_st ; [L41] int t2_st ; [L42] int t3_st ; [L43] int t4_st ; [L44] int t5_st ; [L45] int t6_st ; [L46] int t7_st ; [L47] int t8_st ; [L48] int t9_st ; [L49] int t10_st ; [L50] int t11_st ; [L51] int t12_st ; [L52] int t13_st ; [L53] int m_i ; [L54] int t1_i ; [L55] int t2_i ; [L56] int t3_i ; [L57] int t4_i ; [L58] int t5_i ; [L59] int t6_i ; [L60] int t7_i ; [L61] int t8_i ; [L62] int t9_i ; [L63] int t10_i ; [L64] int t11_i ; [L65] int t12_i ; [L66] int t13_i ; [L67] int M_E = 2; [L68] int T1_E = 2; [L69] int T2_E = 2; [L70] int T3_E = 2; [L71] int T4_E = 2; [L72] int T5_E = 2; [L73] int T6_E = 2; [L74] int T7_E = 2; [L75] int T8_E = 2; [L76] int T9_E = 2; [L77] int T10_E = 2; [L78] int T11_E = 2; [L79] int T12_E = 2; [L80] int T13_E = 2; [L81] int E_1 = 2; [L82] int E_2 = 2; [L83] int E_3 = 2; [L84] int E_4 = 2; [L85] int E_5 = 2; [L86] int E_6 = 2; [L87] int E_7 = 2; [L88] int E_8 = 2; [L89] int E_9 = 2; [L90] int E_10 = 2; [L91] int E_11 = 2; [L92] int E_12 = 2; [L93] int E_13 = 2; [L1937] int __retres1 ; [L1941] CALL init_model() [L1840] m_i = 1 [L1841] t1_i = 1 [L1842] t2_i = 1 [L1843] t3_i = 1 [L1844] t4_i = 1 [L1845] t5_i = 1 [L1846] t6_i = 1 [L1847] t7_i = 1 [L1848] t8_i = 1 [L1849] t9_i = 1 [L1850] t10_i = 1 [L1851] t11_i = 1 [L1852] t12_i = 1 [L1853] t13_i = 1 [L1941] RET init_model() [L1942] CALL start_simulation() [L1878] int kernel_st ; [L1879] int tmp ; [L1880] int tmp___0 ; [L1884] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1885] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1886] CALL init_threads() [L881] COND TRUE m_i == 1 [L882] m_st = 0 [L886] COND TRUE t1_i == 1 [L887] t1_st = 0 [L891] COND TRUE t2_i == 1 [L892] t2_st = 0 [L896] COND TRUE t3_i == 1 [L897] t3_st = 0 [L901] COND TRUE t4_i == 1 [L902] t4_st = 0 [L906] COND TRUE t5_i == 1 [L907] t5_st = 0 [L911] COND TRUE t6_i == 1 [L912] t6_st = 0 [L916] COND TRUE t7_i == 1 [L917] t7_st = 0 [L921] COND TRUE t8_i == 1 [L922] t8_st = 0 [L926] COND TRUE t9_i == 1 [L927] t9_st = 0 [L931] COND TRUE t10_i == 1 [L932] t10_st = 0 [L936] COND TRUE t11_i == 1 [L937] t11_st = 0 [L941] COND TRUE t12_i == 1 [L942] t12_st = 0 [L946] COND TRUE t13_i == 1 [L947] t13_st = 0 [L1886] RET init_threads() [L1887] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(M_E == 0) [L1263] COND FALSE !(T1_E == 0) [L1268] COND FALSE !(T2_E == 0) [L1273] COND FALSE !(T3_E == 0) [L1278] COND FALSE !(T4_E == 0) [L1283] COND FALSE !(T5_E == 0) [L1288] COND FALSE !(T6_E == 0) [L1293] COND FALSE !(T7_E == 0) [L1298] COND FALSE !(T8_E == 0) [L1303] COND FALSE !(T9_E == 0) [L1308] COND FALSE !(T10_E == 0) [L1313] COND FALSE !(T11_E == 0) [L1318] COND FALSE !(T12_E == 0) [L1323] COND FALSE !(T13_E == 0) [L1328] COND FALSE !(E_1 == 0) [L1333] COND FALSE !(E_2 == 0) [L1338] COND FALSE !(E_3 == 0) [L1343] COND FALSE !(E_4 == 0) [L1348] COND FALSE !(E_5 == 0) [L1353] COND FALSE !(E_6 == 0) [L1358] COND FALSE !(E_7 == 0) [L1363] COND FALSE !(E_8 == 0) [L1368] COND FALSE !(E_9 == 0) [L1373] COND FALSE !(E_10 == 0) [L1378] COND FALSE !(E_11 == 0) [L1383] COND FALSE !(E_12 == 0) [L1388] COND FALSE !(E_13 == 0) [L1887] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1888] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1541] int tmp ; [L1542] int tmp___0 ; [L1543] int tmp___1 ; [L1544] int tmp___2 ; [L1545] int tmp___3 ; [L1546] int tmp___4 ; [L1547] int tmp___5 ; [L1548] int tmp___6 ; [L1549] int tmp___7 ; [L1550] int tmp___8 ; [L1551] int tmp___9 ; [L1552] int tmp___10 ; [L1553] int tmp___11 ; [L1554] int tmp___12 ; [L1558] CALL, EXPR is_master_triggered() [L604] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L607] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L617] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L619] return (__retres1); [L1558] RET, EXPR is_master_triggered() [L1558] tmp = is_master_triggered() [L1560] COND FALSE !(\read(tmp)) [L1566] CALL, EXPR is_transmit1_triggered() [L623] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L626] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L636] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L638] return (__retres1); [L1566] RET, EXPR is_transmit1_triggered() [L1566] tmp___0 = is_transmit1_triggered() [L1568] COND FALSE !(\read(tmp___0)) [L1574] CALL, EXPR is_transmit2_triggered() [L642] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L645] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L655] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L657] return (__retres1); [L1574] RET, EXPR is_transmit2_triggered() [L1574] tmp___1 = is_transmit2_triggered() [L1576] COND FALSE !(\read(tmp___1)) [L1582] CALL, EXPR is_transmit3_triggered() [L661] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L664] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L674] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L676] return (__retres1); [L1582] RET, EXPR is_transmit3_triggered() [L1582] tmp___2 = is_transmit3_triggered() [L1584] COND FALSE !(\read(tmp___2)) [L1590] CALL, EXPR is_transmit4_triggered() [L680] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L683] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L693] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L695] return (__retres1); [L1590] RET, EXPR is_transmit4_triggered() [L1590] tmp___3 = is_transmit4_triggered() [L1592] COND FALSE !(\read(tmp___3)) [L1598] CALL, EXPR is_transmit5_triggered() [L699] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L702] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L712] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L714] return (__retres1); [L1598] RET, EXPR is_transmit5_triggered() [L1598] tmp___4 = is_transmit5_triggered() [L1600] COND FALSE !(\read(tmp___4)) [L1606] CALL, EXPR is_transmit6_triggered() [L718] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L721] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L731] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L733] return (__retres1); [L1606] RET, EXPR is_transmit6_triggered() [L1606] tmp___5 = is_transmit6_triggered() [L1608] COND FALSE !(\read(tmp___5)) [L1614] CALL, EXPR is_transmit7_triggered() [L737] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L740] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L750] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L752] return (__retres1); [L1614] RET, EXPR is_transmit7_triggered() [L1614] tmp___6 = is_transmit7_triggered() [L1616] COND FALSE !(\read(tmp___6)) [L1622] CALL, EXPR is_transmit8_triggered() [L756] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L759] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L769] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L771] return (__retres1); [L1622] RET, EXPR is_transmit8_triggered() [L1622] tmp___7 = is_transmit8_triggered() [L1624] COND FALSE !(\read(tmp___7)) [L1630] CALL, EXPR is_transmit9_triggered() [L775] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L778] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L788] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L790] return (__retres1); [L1630] RET, EXPR is_transmit9_triggered() [L1630] tmp___8 = is_transmit9_triggered() [L1632] COND FALSE !(\read(tmp___8)) [L1638] CALL, EXPR is_transmit10_triggered() [L794] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L797] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L807] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L809] return (__retres1); [L1638] RET, EXPR is_transmit10_triggered() [L1638] tmp___9 = is_transmit10_triggered() [L1640] COND FALSE !(\read(tmp___9)) [L1646] CALL, EXPR is_transmit11_triggered() [L813] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L816] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L826] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L828] return (__retres1); [L1646] RET, EXPR is_transmit11_triggered() [L1646] tmp___10 = is_transmit11_triggered() [L1648] COND FALSE !(\read(tmp___10)) [L1654] CALL, EXPR is_transmit12_triggered() [L832] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L835] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L845] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L847] return (__retres1); [L1654] RET, EXPR is_transmit12_triggered() [L1654] tmp___11 = is_transmit12_triggered() [L1656] COND FALSE !(\read(tmp___11)) [L1662] CALL, EXPR is_transmit13_triggered() [L851] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L854] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L864] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L866] return (__retres1); [L1662] RET, EXPR is_transmit13_triggered() [L1662] tmp___12 = is_transmit13_triggered() [L1664] COND FALSE !(\read(tmp___12)) [L1888] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1889] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(M_E == 1) [L1406] COND FALSE !(T1_E == 1) [L1411] COND FALSE !(T2_E == 1) [L1416] COND FALSE !(T3_E == 1) [L1421] COND FALSE !(T4_E == 1) [L1426] COND FALSE !(T5_E == 1) [L1431] COND FALSE !(T6_E == 1) [L1436] COND FALSE !(T7_E == 1) [L1441] COND FALSE !(T8_E == 1) [L1446] COND FALSE !(T9_E == 1) [L1451] COND FALSE !(T10_E == 1) [L1456] COND FALSE !(T11_E == 1) [L1461] COND FALSE !(T12_E == 1) [L1466] COND FALSE !(T13_E == 1) [L1471] COND FALSE !(E_1 == 1) [L1476] COND FALSE !(E_2 == 1) [L1481] COND FALSE !(E_3 == 1) [L1486] COND FALSE !(E_4 == 1) [L1491] COND FALSE !(E_5 == 1) [L1496] COND FALSE !(E_6 == 1) [L1501] COND FALSE !(E_7 == 1) [L1506] COND FALSE !(E_8 == 1) [L1511] COND FALSE !(E_9 == 1) [L1516] COND FALSE !(E_10 == 1) [L1521] COND FALSE !(E_11 == 1) [L1526] COND FALSE !(E_12 == 1) [L1531] COND FALSE !(E_13 == 1) [L1889] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1892] COND TRUE 1 [L1895] kernel_st = 1 [L1896] CALL eval() [L1037] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE 1 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L956] int __retres1 ; [L959] COND TRUE m_st == 0 [L960] __retres1 = 1 [L1032] return (__retres1); [L1044] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] tmp = exists_runnable_thread() [L1046] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0, tmp=1] [L1051] COND TRUE m_st == 0 [L1052] int tmp_ndt_1; [L1053] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L1054] COND FALSE, EXPR !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0, tmp=1, tmp_ndt_1=0] [L1051-L1062] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0, tmp=1] [L1065] COND TRUE t1_st == 0 [L1066] int tmp_ndt_2; [L1067] tmp_ndt_2 = __VERIFIER_nondet_int() [L1068] COND FALSE !(\read(tmp_ndt_2)) [L1074] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 206 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 32.4s, OverallIterations: 10, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 16.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 8482 SdHoareTripleChecker+Valid, 5.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 8405 mSDsluCounter, 9151 SdHoareTripleChecker+Invalid, 4.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5085 mSDsCounter, 1220 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 3414 IncrementalHoareTripleChecker+Invalid, 4634 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1220 mSolverCounterUnsat, 4066 mSDtfsCounter, 3414 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 72 GetRequests, 32 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=86564occurred in iteration=9, InterpolantAutomatonStates: 45, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 13.4s AutomataMinimizationTime, 9 MinimizatonAttempts, 20978 StatesRemovedByMinimization, 9 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 672 NumberOfCodeBlocks, 672 NumberOfCodeBlocksAsserted, 10 NumberOfCheckSat, 594 ConstructedInterpolants, 0 QuantifiedInterpolants, 1540 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 9 InterpolantComputations, 9 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2023-11-12 00:57:41,873 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b663a3db-b68c-4e2b-9ee2-83be20f112ec/bin/utaipan-verify-NcY6lQBIFX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE