./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 84cfde4a Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-84cfde4 [2024-10-12 01:02:02,721 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-12 01:02:02,765 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-12 01:02:02,768 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-12 01:02:02,769 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-12 01:02:02,797 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-12 01:02:02,798 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-12 01:02:02,798 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-12 01:02:02,799 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-12 01:02:02,800 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-12 01:02:02,800 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-12 01:02:02,800 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-12 01:02:02,801 INFO L153 SettingsManager]: * Use SBE=true [2024-10-12 01:02:02,801 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-12 01:02:02,801 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-12 01:02:02,801 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-12 01:02:02,802 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-12 01:02:02,802 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-12 01:02:02,802 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-12 01:02:02,804 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-12 01:02:02,805 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-12 01:02:02,807 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-12 01:02:02,807 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-12 01:02:02,807 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-12 01:02:02,807 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-12 01:02:02,807 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-12 01:02:02,808 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-12 01:02:02,808 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-12 01:02:02,808 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-12 01:02:02,808 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-12 01:02:02,808 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-12 01:02:02,808 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-12 01:02:02,809 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-12 01:02:02,809 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-12 01:02:02,809 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-12 01:02:02,809 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-12 01:02:02,809 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-12 01:02:02,809 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-12 01:02:02,810 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-12 01:02:02,810 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2024-10-12 01:02:03,044 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-12 01:02:03,076 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-12 01:02:03,082 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-12 01:02:03,083 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-12 01:02:03,084 INFO L274 PluginConnector]: CDTParser initialized [2024-10-12 01:02:03,084 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2024-10-12 01:02:04,428 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-12 01:02:04,612 INFO L384 CDTParser]: Found 1 translation units. [2024-10-12 01:02:04,613 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2024-10-12 01:02:04,627 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/data/2fdfce6c0/4bce95bea10847908c0ea85dcf53f001/FLAG586100941 [2024-10-12 01:02:05,004 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/data/2fdfce6c0/4bce95bea10847908c0ea85dcf53f001 [2024-10-12 01:02:05,007 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-12 01:02:05,009 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-12 01:02:05,011 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-12 01:02:05,011 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-12 01:02:05,016 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-12 01:02:05,017 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,017 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7f4ba0cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05, skipping insertion in model container [2024-10-12 01:02:05,017 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,056 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-12 01:02:05,253 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-12 01:02:05,264 INFO L200 MainTranslator]: Completed pre-run [2024-10-12 01:02:05,289 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-12 01:02:05,303 INFO L204 MainTranslator]: Completed translation [2024-10-12 01:02:05,304 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05 WrapperNode [2024-10-12 01:02:05,304 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-12 01:02:05,305 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-12 01:02:05,305 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-12 01:02:05,305 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-12 01:02:05,310 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,319 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,345 INFO L138 Inliner]: procedures = 31, calls = 36, calls flagged for inlining = 31, calls inlined = 35, statements flattened = 410 [2024-10-12 01:02:05,346 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-12 01:02:05,346 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-12 01:02:05,347 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-12 01:02:05,347 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-12 01:02:05,372 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,373 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,377 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,405 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-12 01:02:05,405 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,405 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,410 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,418 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,419 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,420 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,425 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-12 01:02:05,426 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-12 01:02:05,426 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-12 01:02:05,426 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-12 01:02:05,431 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (1/1) ... [2024-10-12 01:02:05,438 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-12 01:02:05,453 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/z3 [2024-10-12 01:02:05,468 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-12 01:02:05,474 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-12 01:02:05,525 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-12 01:02:05,525 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-12 01:02:05,525 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-12 01:02:05,526 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-12 01:02:05,600 INFO L238 CfgBuilder]: Building ICFG [2024-10-12 01:02:05,602 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-12 01:02:05,984 INFO L733 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2024-10-12 01:02:05,984 INFO L733 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2024-10-12 01:02:06,027 INFO L? ?]: Removed 54 outVars from TransFormulas that were not future-live. [2024-10-12 01:02:06,027 INFO L287 CfgBuilder]: Performing block encoding [2024-10-12 01:02:06,041 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-12 01:02:06,045 INFO L314 CfgBuilder]: Removed 4 assume(true) statements. [2024-10-12 01:02:06,045 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.10 01:02:06 BoogieIcfgContainer [2024-10-12 01:02:06,046 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-12 01:02:06,049 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-12 01:02:06,049 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-12 01:02:06,055 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-12 01:02:06,055 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-12 01:02:06,056 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.10 01:02:05" (1/3) ... [2024-10-12 01:02:06,056 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@18f8fc4c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.10 01:02:06, skipping insertion in model container [2024-10-12 01:02:06,056 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-12 01:02:06,057 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.10 01:02:05" (2/3) ... [2024-10-12 01:02:06,057 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@18f8fc4c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.10 01:02:06, skipping insertion in model container [2024-10-12 01:02:06,057 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-12 01:02:06,057 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.10 01:02:06" (3/3) ... [2024-10-12 01:02:06,058 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2024-10-12 01:02:06,141 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-12 01:02:06,145 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-12 01:02:06,145 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-12 01:02:06,145 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-12 01:02:06,146 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-12 01:02:06,146 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-12 01:02:06,146 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-12 01:02:06,147 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-12 01:02:06,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:06,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 [2024-10-12 01:02:06,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:06,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:06,212 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:06,212 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:06,213 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-12 01:02:06,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:06,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 [2024-10-12 01:02:06,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:06,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:06,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:06,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:06,241 INFO L745 eck$LassoCheckResult]: Stem: 22#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 36#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 140#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25#L258true assume !(1 == ~q_req_up~0); 69#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 114#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 101#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47#L311true assume !(0 == ~q_read_ev~0); 102#L311-2true assume !(0 == ~q_write_ev~0); 78#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 31#L66true assume 1 == ~p_dw_pc~0; 131#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 55#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 98#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 53#L387true assume !(0 != activate_threads_~tmp~1#1); 106#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 86#L95true assume 1 == ~c_dr_pc~0; 120#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 21#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 27#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 79#L395true assume !(0 != activate_threads_~tmp___0~1#1); 11#L395-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 56#L329-2true assume !(1 == ~q_write_ev~0); 33#L334-1true assume { :end_inline_reset_delta_events } true; 128#L491-2true [2024-10-12 01:02:06,243 INFO L747 eck$LassoCheckResult]: Loop: 128#L491-2true assume !false; 129#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 97#L435true assume !true; 82#eval_returnLabel#1true havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59#L258-3true assume !(1 == ~q_req_up~0); 109#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 115#L311-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 70#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 113#L66-3true assume 1 == ~p_dw_pc~0; 94#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 8#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 63#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 124#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 32#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 126#L95-3true assume 1 == ~c_dr_pc~0; 65#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 104#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 35#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 133#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 16#L395-5true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 90#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 142#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 51#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 105#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 100#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 80#L510true assume !(0 == start_simulation_~tmp~4#1); 6#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 75#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 93#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 143#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 29#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 77#L523true assume !(0 != start_simulation_~tmp___0~3#1); 128#L491-2true [2024-10-12 01:02:06,255 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:06,257 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2024-10-12 01:02:06,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:06,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014981322] [2024-10-12 01:02:06,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:06,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:06,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:06,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:06,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:06,533 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014981322] [2024-10-12 01:02:06,533 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014981322] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:06,533 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:06,533 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-12 01:02:06,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755128224] [2024-10-12 01:02:06,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:06,538 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-12 01:02:06,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:06,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1919014688, now seen corresponding path program 1 times [2024-10-12 01:02:06,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:06,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583921521] [2024-10-12 01:02:06,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:06,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:06,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:06,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:06,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:06,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583921521] [2024-10-12 01:02:06,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1583921521] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:06,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:06,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-12 01:02:06,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [465298739] [2024-10-12 01:02:06,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:06,561 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-12 01:02:06,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:06,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-12 01:02:06,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-12 01:02:06,588 INFO L87 Difference]: Start difference. First operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:06,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:06,627 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2024-10-12 01:02:06,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2024-10-12 01:02:06,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2024-10-12 01:02:06,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2024-10-12 01:02:06,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2024-10-12 01:02:06,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2024-10-12 01:02:06,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2024-10-12 01:02:06,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:06,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2024-10-12 01:02:06,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2024-10-12 01:02:06,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2024-10-12 01:02:06,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:06,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2024-10-12 01:02:06,702 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2024-10-12 01:02:06,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-12 01:02:06,706 INFO L425 stractBuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2024-10-12 01:02:06,709 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-12 01:02:06,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2024-10-12 01:02:06,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2024-10-12 01:02:06,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:06,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:06,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:06,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:06,718 INFO L745 eck$LassoCheckResult]: Stem: 334#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 335#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 359#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 339#L258 assume !(1 == ~q_req_up~0); 341#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 393#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 394#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 418#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 372#L311 assume !(0 == ~q_read_ev~0); 373#L311-2 assume !(0 == ~q_write_ev~0); 405#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 348#L66 assume 1 == ~p_dw_pc~0; 350#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 386#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 387#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 382#L387 assume !(0 != activate_threads_~tmp~1#1); 383#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 411#L95 assume 1 == ~c_dr_pc~0; 413#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 330#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 331#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 342#L395 assume !(0 != activate_threads_~tmp___0~1#1); 308#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 345#L329-2 assume !(1 == ~q_write_ev~0); 353#L334-1 assume { :end_inline_reset_delta_events } true; 354#L491-2 [2024-10-12 01:02:06,719 INFO L747 eck$LassoCheckResult]: Loop: 354#L491-2 assume !false; 426#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 356#L435 assume !false; 388#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 389#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 299#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 312#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 313#L415 assume !(0 != eval_~tmp___1~0#1); 409#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 390#L258-3 assume !(1 == ~q_req_up~0); 392#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 420#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 424#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 402#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 403#L66-3 assume 1 == ~p_dw_pc~0; 416#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 303#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 305#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 396#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 351#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 352#L95-3 assume 1 == ~c_dr_pc~0; 397#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 398#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 357#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 358#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 318#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 366#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 414#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 379#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 381#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 406#L510 assume !(0 == start_simulation_~tmp~4#1); 300#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 333#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 346#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 347#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 343#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 344#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 404#L523 assume !(0 != start_simulation_~tmp___0~3#1); 354#L491-2 [2024-10-12 01:02:06,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:06,719 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2024-10-12 01:02:06,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:06,722 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39198379] [2024-10-12 01:02:06,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:06,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:06,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:06,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:06,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:06,927 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39198379] [2024-10-12 01:02:06,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39198379] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:06,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:06,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-12 01:02:06,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663942940] [2024-10-12 01:02:06,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:06,928 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-12 01:02:06,929 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:06,929 INFO L85 PathProgramCache]: Analyzing trace with hash -848315206, now seen corresponding path program 1 times [2024-10-12 01:02:06,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:06,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688443340] [2024-10-12 01:02:06,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:06,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:06,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:06,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:06,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:06,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688443340] [2024-10-12 01:02:06,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688443340] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:06,996 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:06,996 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-12 01:02:06,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340589811] [2024-10-12 01:02:06,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:06,996 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-12 01:02:06,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:06,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-12 01:02:06,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-12 01:02:06,998 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:07,046 INFO L93 Difference]: Finished difference Result 221 states and 321 transitions. [2024-10-12 01:02:07,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 221 states and 321 transitions. [2024-10-12 01:02:07,048 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 186 [2024-10-12 01:02:07,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 221 states to 221 states and 321 transitions. [2024-10-12 01:02:07,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2024-10-12 01:02:07,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2024-10-12 01:02:07,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221 states and 321 transitions. [2024-10-12 01:02:07,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:07,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 221 states and 321 transitions. [2024-10-12 01:02:07,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states and 321 transitions. [2024-10-12 01:02:07,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 219. [2024-10-12 01:02:07,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 219 states have (on average 1.45662100456621) internal successors, (319), 218 states have internal predecessors, (319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 319 transitions. [2024-10-12 01:02:07,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 219 states and 319 transitions. [2024-10-12 01:02:07,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-12 01:02:07,060 INFO L425 stractBuchiCegarLoop]: Abstraction has 219 states and 319 transitions. [2024-10-12 01:02:07,060 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-12 01:02:07,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 219 states and 319 transitions. [2024-10-12 01:02:07,061 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 184 [2024-10-12 01:02:07,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:07,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:07,062 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,062 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,063 INFO L745 eck$LassoCheckResult]: Stem: 699#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 700#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 704#L258 assume !(1 == ~q_req_up~0); 706#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 757#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 758#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 787#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 737#L311 assume !(0 == ~q_read_ev~0); 738#L311-2 assume !(0 == ~q_write_ev~0); 770#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 715#L66 assume !(1 == ~p_dw_pc~0); 716#L66-2 assume !(2 == ~p_dw_pc~0); 729#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 750#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 751#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 746#L387 assume !(0 != activate_threads_~tmp~1#1); 747#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 779#L95 assume 1 == ~c_dr_pc~0; 781#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 695#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 696#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 707#L395 assume !(0 != activate_threads_~tmp___0~1#1); 674#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 675#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 710#L329-2 assume !(1 == ~q_write_ev~0); 717#L334-1 assume { :end_inline_reset_delta_events } true; 718#L491-2 [2024-10-12 01:02:07,063 INFO L747 eck$LassoCheckResult]: Loop: 718#L491-2 assume !false; 817#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 815#L435 assume !false; 812#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 809#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 807#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 806#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 804#L415 assume !(0 != eval_~tmp___1~0#1); 805#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 872#L258-3 assume !(1 == ~q_req_up~0); 870#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 869#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 868#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 766#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 767#L66-3 assume !(1 == ~p_dw_pc~0); 739#L66-5 assume !(2 == ~p_dw_pc~0); 666#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 667#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 668#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 760#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 713#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 714#L95-3 assume 1 == ~c_dr_pc~0; 761#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 762#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 721#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 722#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 683#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 728#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 782#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 743#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 745#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 786#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 771#L510 assume !(0 == start_simulation_~tmp~4#1); 664#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 665#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 698#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 712#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 799#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 828#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 825#L523 assume !(0 != start_simulation_~tmp___0~3#1); 718#L491-2 [2024-10-12 01:02:07,063 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,064 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2024-10-12 01:02:07,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139045456] [2024-10-12 01:02:07,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:07,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:07,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:07,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139045456] [2024-10-12 01:02:07,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139045456] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:07,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:07,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-12 01:02:07,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151672083] [2024-10-12 01:02:07,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:07,107 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-12 01:02:07,108 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,108 INFO L85 PathProgramCache]: Analyzing trace with hash 54589687, now seen corresponding path program 1 times [2024-10-12 01:02:07,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681716476] [2024-10-12 01:02:07,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:07,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:07,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:07,151 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681716476] [2024-10-12 01:02:07,151 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1681716476] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:07,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:07,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-12 01:02:07,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1935838743] [2024-10-12 01:02:07,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:07,152 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-12 01:02:07,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:07,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-12 01:02:07,153 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-12 01:02:07,153 INFO L87 Difference]: Start difference. First operand 219 states and 319 transitions. cyclomatic complexity: 102 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:07,244 INFO L93 Difference]: Finished difference Result 471 states and 676 transitions. [2024-10-12 01:02:07,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 676 transitions. [2024-10-12 01:02:07,247 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 425 [2024-10-12 01:02:07,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 676 transitions. [2024-10-12 01:02:07,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2024-10-12 01:02:07,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2024-10-12 01:02:07,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 676 transitions. [2024-10-12 01:02:07,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:07,252 INFO L218 hiAutomatonCegarLoop]: Abstraction has 471 states and 676 transitions. [2024-10-12 01:02:07,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 676 transitions. [2024-10-12 01:02:07,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 377. [2024-10-12 01:02:07,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 377 states, 377 states have (on average 1.4456233421750664) internal successors, (545), 376 states have internal predecessors, (545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 545 transitions. [2024-10-12 01:02:07,272 INFO L240 hiAutomatonCegarLoop]: Abstraction has 377 states and 545 transitions. [2024-10-12 01:02:07,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-12 01:02:07,273 INFO L425 stractBuchiCegarLoop]: Abstraction has 377 states and 545 transitions. [2024-10-12 01:02:07,273 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-12 01:02:07,273 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 377 states and 545 transitions. [2024-10-12 01:02:07,274 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 342 [2024-10-12 01:02:07,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:07,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:07,275 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,275 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,276 INFO L745 eck$LassoCheckResult]: Stem: 1402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 1403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1426#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1407#L258 assume !(1 == ~q_req_up~0); 1409#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1461#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1462#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1498#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1440#L311 assume !(0 == ~q_read_ev~0); 1441#L311-2 assume !(0 == ~q_write_ev~0); 1479#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1418#L66 assume !(1 == ~p_dw_pc~0); 1419#L66-2 assume !(2 == ~p_dw_pc~0); 1432#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1456#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1457#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1450#L387 assume !(0 != activate_threads_~tmp~1#1); 1451#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1489#L95 assume !(1 == ~c_dr_pc~0); 1490#L95-2 assume 2 == ~c_dr_pc~0; 1502#L106 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1398#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1399#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1410#L395 assume !(0 != activate_threads_~tmp___0~1#1); 1377#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1378#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1413#L329-2 assume !(1 == ~q_write_ev~0); 1422#L334-1 assume { :end_inline_reset_delta_events } true; 1423#L491-2 [2024-10-12 01:02:07,276 INFO L747 eck$LassoCheckResult]: Loop: 1423#L491-2 assume !false; 1510#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1421#L435 assume !false; 1454#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1455#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1366#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1379#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1380#L415 assume !(0 != eval_~tmp___1~0#1); 1483#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1458#L258-3 assume !(1 == ~q_req_up~0); 1460#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1505#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1508#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1472#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1473#L66-3 assume !(1 == ~p_dw_pc~0); 1442#L66-5 assume !(2 == ~p_dw_pc~0); 1369#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 1370#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1371#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1464#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1416#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1417#L95-3 assume !(1 == ~c_dr_pc~0); 1360#L95-5 assume 2 == ~c_dr_pc~0; 1361#L106-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1499#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1424#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1425#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1385#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1386#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1431#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1491#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1446#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1448#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1480#L510 assume !(0 == start_simulation_~tmp~4#1); 1367#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1368#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1401#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1415#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1411#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1412#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1478#L523 assume !(0 != start_simulation_~tmp___0~3#1); 1423#L491-2 [2024-10-12 01:02:07,276 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,276 INFO L85 PathProgramCache]: Analyzing trace with hash -1943531092, now seen corresponding path program 1 times [2024-10-12 01:02:07,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552783968] [2024-10-12 01:02:07,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:07,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:07,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:07,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552783968] [2024-10-12 01:02:07,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552783968] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:07,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:07,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-12 01:02:07,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867143482] [2024-10-12 01:02:07,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:07,318 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-12 01:02:07,319 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,319 INFO L85 PathProgramCache]: Analyzing trace with hash 2126410793, now seen corresponding path program 1 times [2024-10-12 01:02:07,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,319 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769719249] [2024-10-12 01:02:07,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:07,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:07,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:07,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769719249] [2024-10-12 01:02:07,360 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769719249] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:07,360 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:07,360 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-12 01:02:07,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109406489] [2024-10-12 01:02:07,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:07,361 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-12 01:02:07,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:07,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-12 01:02:07,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-10-12 01:02:07,362 INFO L87 Difference]: Start difference. First operand 377 states and 545 transitions. cyclomatic complexity: 170 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:07,426 INFO L93 Difference]: Finished difference Result 555 states and 772 transitions. [2024-10-12 01:02:07,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 555 states and 772 transitions. [2024-10-12 01:02:07,430 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2024-10-12 01:02:07,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 555 states to 555 states and 772 transitions. [2024-10-12 01:02:07,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 555 [2024-10-12 01:02:07,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 555 [2024-10-12 01:02:07,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 555 states and 772 transitions. [2024-10-12 01:02:07,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:07,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 555 states and 772 transitions. [2024-10-12 01:02:07,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states and 772 transitions. [2024-10-12 01:02:07,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 551. [2024-10-12 01:02:07,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.3938294010889292) internal successors, (768), 550 states have internal predecessors, (768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 768 transitions. [2024-10-12 01:02:07,465 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 768 transitions. [2024-10-12 01:02:07,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-12 01:02:07,466 INFO L425 stractBuchiCegarLoop]: Abstraction has 551 states and 768 transitions. [2024-10-12 01:02:07,467 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-12 01:02:07,467 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 768 transitions. [2024-10-12 01:02:07,469 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2024-10-12 01:02:07,470 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:07,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:07,471 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,471 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,472 INFO L745 eck$LassoCheckResult]: Stem: 2341#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2367#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2346#L258 assume !(1 == ~q_req_up~0); 2348#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2404#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2405#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2458#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2382#L311 assume !(0 == ~q_read_ev~0); 2383#L311-2 assume !(0 == ~q_write_ev~0); 2449#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2484#L66 assume !(1 == ~p_dw_pc~0); 2372#L66-2 assume !(2 == ~p_dw_pc~0); 2373#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 2395#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2396#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2391#L387 assume !(0 != activate_threads_~tmp~1#1); 2392#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2433#L95 assume !(1 == ~c_dr_pc~0); 2434#L95-2 assume !(2 == ~c_dr_pc~0); 2481#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 2337#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2338#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2423#L395 assume !(0 != activate_threads_~tmp___0~1#1); 2424#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2353#L329 assume !(1 == ~q_read_ev~0); 2354#L329-2 assume !(1 == ~q_write_ev~0); 2822#L334-1 assume { :end_inline_reset_delta_events } true; 2820#L491-2 [2024-10-12 01:02:07,472 INFO L747 eck$LassoCheckResult]: Loop: 2820#L491-2 assume !false; 2819#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2637#L435 assume !false; 2674#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2669#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2667#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2666#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2662#L415 assume !(0 != eval_~tmp___1~0#1); 2663#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2813#L258-3 assume !(1 == ~q_req_up~0); 2808#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2806#L311-3 assume !(0 == ~q_read_ev~0); 2804#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2802#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2800#L66-3 assume !(1 == ~p_dw_pc~0); 2798#L66-5 assume !(2 == ~p_dw_pc~0); 2796#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 2794#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2792#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2790#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2788#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2786#L95-3 assume !(1 == ~c_dr_pc~0); 2302#L95-5 assume !(2 == ~c_dr_pc~0); 2303#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 2448#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2365#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2366#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2325#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2326#L329-3 assume !(1 == ~q_read_ev~0); 2371#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2838#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2837#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2834#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2833#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2832#L510 assume !(0 == start_simulation_~tmp~4#1); 2830#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2829#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2827#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2826#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2825#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2824#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2823#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2821#L523 assume !(0 != start_simulation_~tmp___0~3#1); 2820#L491-2 [2024-10-12 01:02:07,473 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,473 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2024-10-12 01:02:07,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028479911] [2024-10-12 01:02:07,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:07,489 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:07,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:07,528 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-12 01:02:07,529 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,529 INFO L85 PathProgramCache]: Analyzing trace with hash 147817770, now seen corresponding path program 1 times [2024-10-12 01:02:07,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069213631] [2024-10-12 01:02:07,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:07,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:07,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:07,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069213631] [2024-10-12 01:02:07,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2069213631] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:07,587 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:07,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-12 01:02:07,587 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207448201] [2024-10-12 01:02:07,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:07,588 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-12 01:02:07,588 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:07,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-12 01:02:07,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-12 01:02:07,588 INFO L87 Difference]: Start difference. First operand 551 states and 768 transitions. cyclomatic complexity: 221 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:07,627 INFO L93 Difference]: Finished difference Result 593 states and 810 transitions. [2024-10-12 01:02:07,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 593 states and 810 transitions. [2024-10-12 01:02:07,631 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 530 [2024-10-12 01:02:07,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 593 states to 593 states and 810 transitions. [2024-10-12 01:02:07,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 593 [2024-10-12 01:02:07,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 593 [2024-10-12 01:02:07,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 593 states and 810 transitions. [2024-10-12 01:02:07,635 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:07,635 INFO L218 hiAutomatonCegarLoop]: Abstraction has 593 states and 810 transitions. [2024-10-12 01:02:07,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 593 states and 810 transitions. [2024-10-12 01:02:07,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 593 to 569. [2024-10-12 01:02:07,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 569 states, 569 states have (on average 1.3813708260105448) internal successors, (786), 568 states have internal predecessors, (786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 786 transitions. [2024-10-12 01:02:07,642 INFO L240 hiAutomatonCegarLoop]: Abstraction has 569 states and 786 transitions. [2024-10-12 01:02:07,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-12 01:02:07,643 INFO L425 stractBuchiCegarLoop]: Abstraction has 569 states and 786 transitions. [2024-10-12 01:02:07,643 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-12 01:02:07,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 786 transitions. [2024-10-12 01:02:07,660 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 506 [2024-10-12 01:02:07,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:07,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:07,661 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,662 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,663 INFO L745 eck$LassoCheckResult]: Stem: 3494#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 3495#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3520#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3499#L258 assume !(1 == ~q_req_up~0); 3501#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3559#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3560#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3630#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3537#L311 assume !(0 == ~q_read_ev~0); 3538#L311-2 assume !(0 == ~q_write_ev~0); 3616#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3658#L66 assume !(1 == ~p_dw_pc~0); 3526#L66-2 assume !(2 == ~p_dw_pc~0); 3527#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 3549#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3550#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3545#L387 assume !(0 != activate_threads_~tmp~1#1); 3546#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3596#L95 assume !(1 == ~c_dr_pc~0); 3597#L95-2 assume !(2 == ~c_dr_pc~0); 3655#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 3490#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3491#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3580#L395 assume !(0 != activate_threads_~tmp___0~1#1); 3581#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3506#L329 assume !(1 == ~q_read_ev~0); 3507#L329-2 assume !(1 == ~q_write_ev~0); 3516#L334-1 assume { :end_inline_reset_delta_events } true; 3517#L491-2 [2024-10-12 01:02:07,663 INFO L747 eck$LassoCheckResult]: Loop: 3517#L491-2 assume !false; 3638#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3606#L435 assume !false; 3553#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3554#L291 assume !(0 == ~p_dw_st~0); 3578#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 3949#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3944#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3945#L415 assume !(0 != eval_~tmp___1~0#1); 3946#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3556#L258-3 assume !(1 == ~q_req_up~0); 3558#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3639#L311-3 assume !(0 == ~q_read_ev~0); 3640#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3569#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3570#L66-3 assume !(1 == ~p_dw_pc~0); 3539#L66-5 assume !(2 == ~p_dw_pc~0); 3463#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 3464#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3465#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3563#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3510#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3511#L95-3 assume !(1 == ~c_dr_pc~0); 3634#L95-5 assume !(2 == ~c_dr_pc~0); 3981#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 3980#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3518#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3519#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3478#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3479#L329-3 assume !(1 == ~q_read_ev~0); 3525#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 4022#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4021#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4019#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3994#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3582#L510 assume !(0 == start_simulation_~tmp~4#1); 3461#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3462#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3493#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3961#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3959#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3504#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3505#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3576#L523 assume !(0 != start_simulation_~tmp___0~3#1); 3517#L491-2 [2024-10-12 01:02:07,663 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,663 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2024-10-12 01:02:07,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451958477] [2024-10-12 01:02:07,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:07,675 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:07,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:07,688 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-12 01:02:07,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,689 INFO L85 PathProgramCache]: Analyzing trace with hash 657647766, now seen corresponding path program 1 times [2024-10-12 01:02:07,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588072468] [2024-10-12 01:02:07,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:07,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:07,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:07,762 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588072468] [2024-10-12 01:02:07,762 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588072468] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:07,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:07,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-12 01:02:07,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255024475] [2024-10-12 01:02:07,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:07,765 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-12 01:02:07,766 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:07,766 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-12 01:02:07,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-12 01:02:07,771 INFO L87 Difference]: Start difference. First operand 569 states and 786 transitions. cyclomatic complexity: 221 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:07,815 INFO L93 Difference]: Finished difference Result 587 states and 796 transitions. [2024-10-12 01:02:07,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 587 states and 796 transitions. [2024-10-12 01:02:07,818 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 524 [2024-10-12 01:02:07,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 587 states to 587 states and 796 transitions. [2024-10-12 01:02:07,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 587 [2024-10-12 01:02:07,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 587 [2024-10-12 01:02:07,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 587 states and 796 transitions. [2024-10-12 01:02:07,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:07,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 587 states and 796 transitions. [2024-10-12 01:02:07,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 587 states and 796 transitions. [2024-10-12 01:02:07,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 587 to 587. [2024-10-12 01:02:07,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 587 states, 587 states have (on average 1.3560477001703577) internal successors, (796), 586 states have internal predecessors, (796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 796 transitions. [2024-10-12 01:02:07,830 INFO L240 hiAutomatonCegarLoop]: Abstraction has 587 states and 796 transitions. [2024-10-12 01:02:07,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-12 01:02:07,833 INFO L425 stractBuchiCegarLoop]: Abstraction has 587 states and 796 transitions. [2024-10-12 01:02:07,833 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-12 01:02:07,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 587 states and 796 transitions. [2024-10-12 01:02:07,835 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 524 [2024-10-12 01:02:07,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:07,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:07,838 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,838 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,839 INFO L745 eck$LassoCheckResult]: Stem: 4658#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 4659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4683#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4663#L258 assume !(1 == ~q_req_up~0); 4665#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4718#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4719#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4768#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4697#L311 assume !(0 == ~q_read_ev~0); 4698#L311-2 assume !(0 == ~q_write_ev~0); 4760#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4814#L66 assume !(1 == ~p_dw_pc~0); 4688#L66-2 assume !(2 == ~p_dw_pc~0); 4689#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 4812#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4811#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4810#L387 assume !(0 != activate_threads_~tmp~1#1); 4809#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4746#L95 assume !(1 == ~c_dr_pc~0); 4747#L95-2 assume !(2 == ~c_dr_pc~0); 4720#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 4654#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4655#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4666#L395 assume !(0 != activate_threads_~tmp___0~1#1); 4735#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4669#L329 assume !(1 == ~q_read_ev~0); 4670#L329-2 assume !(1 == ~q_write_ev~0); 5167#L334-1 assume { :end_inline_reset_delta_events } true; 5164#L491-2 [2024-10-12 01:02:07,839 INFO L747 eck$LassoCheckResult]: Loop: 5164#L491-2 assume !false; 5162#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4782#L435 assume !false; 5159#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4732#L291 assume !(0 == ~p_dw_st~0); 4622#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 4624#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5158#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5155#L415 assume !(0 != eval_~tmp___1~0#1); 4739#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4715#L258-3 assume !(1 == ~q_req_up~0); 4717#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4762#L311-3 assume !(0 == ~q_read_ev~0); 4767#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 4727#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4728#L66-3 assume !(1 == ~p_dw_pc~0); 4701#L66-5 assume !(2 == ~p_dw_pc~0); 4627#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 4628#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4629#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4721#L387-3 assume !(0 != activate_threads_~tmp~1#1); 4673#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4674#L95-3 assume !(1 == ~c_dr_pc~0); 4776#L95-5 assume !(2 == ~c_dr_pc~0); 5115#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 5111#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5109#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4779#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4642#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4643#L329-3 assume !(1 == ~q_read_ev~0); 4687#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5188#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5186#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5183#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5182#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5180#L510 assume !(0 == start_simulation_~tmp~4#1); 5178#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5177#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5175#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5174#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5173#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5172#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5171#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5166#L523 assume !(0 != start_simulation_~tmp___0~3#1); 5164#L491-2 [2024-10-12 01:02:07,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,841 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2024-10-12 01:02:07,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658558925] [2024-10-12 01:02:07,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:07,851 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:07,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:07,859 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-12 01:02:07,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,859 INFO L85 PathProgramCache]: Analyzing trace with hash 523634260, now seen corresponding path program 1 times [2024-10-12 01:02:07,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722883866] [2024-10-12 01:02:07,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:07,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:07,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:07,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722883866] [2024-10-12 01:02:07,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722883866] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:07,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:07,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-12 01:02:07,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652595238] [2024-10-12 01:02:07,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:07,886 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-12 01:02:07,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:07,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-12 01:02:07,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-12 01:02:07,886 INFO L87 Difference]: Start difference. First operand 587 states and 796 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:07,926 INFO L93 Difference]: Finished difference Result 850 states and 1119 transitions. [2024-10-12 01:02:07,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 850 states and 1119 transitions. [2024-10-12 01:02:07,930 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2024-10-12 01:02:07,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 850 states to 850 states and 1119 transitions. [2024-10-12 01:02:07,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 850 [2024-10-12 01:02:07,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 850 [2024-10-12 01:02:07,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 850 states and 1119 transitions. [2024-10-12 01:02:07,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:07,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 850 states and 1119 transitions. [2024-10-12 01:02:07,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states and 1119 transitions. [2024-10-12 01:02:07,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 850. [2024-10-12 01:02:07,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 850 states, 850 states have (on average 1.316470588235294) internal successors, (1119), 849 states have internal predecessors, (1119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:07,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 850 states to 850 states and 1119 transitions. [2024-10-12 01:02:07,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 850 states and 1119 transitions. [2024-10-12 01:02:07,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-12 01:02:07,945 INFO L425 stractBuchiCegarLoop]: Abstraction has 850 states and 1119 transitions. [2024-10-12 01:02:07,946 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-12 01:02:07,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 850 states and 1119 transitions. [2024-10-12 01:02:07,948 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2024-10-12 01:02:07,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:07,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:07,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:07,950 INFO L745 eck$LassoCheckResult]: Stem: 6099#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 6100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6125#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6106#L258 assume !(1 == ~q_req_up~0); 6108#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6166#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 6760#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6891#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6890#L311 assume !(0 == ~q_read_ev~0); 6889#L311-2 assume !(0 == ~q_write_ev~0); 6888#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6887#L66 assume !(1 == ~p_dw_pc~0); 6886#L66-2 assume !(2 == ~p_dw_pc~0); 6885#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 6883#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6881#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6879#L387 assume !(0 != activate_threads_~tmp~1#1); 6877#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6873#L95 assume !(1 == ~c_dr_pc~0); 6871#L95-2 assume !(2 == ~c_dr_pc~0); 6869#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 6867#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6865#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6863#L395 assume !(0 != activate_threads_~tmp___0~1#1); 6861#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6859#L329 assume !(1 == ~q_read_ev~0); 6857#L329-2 assume !(1 == ~q_write_ev~0); 6856#L334-1 assume { :end_inline_reset_delta_events } true; 6854#L491-2 [2024-10-12 01:02:07,950 INFO L747 eck$LassoCheckResult]: Loop: 6854#L491-2 assume !false; 6206#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6122#L435 assume !false; 6188#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6849#L291 assume !(0 == ~p_dw_st~0); 6426#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6847#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6846#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6844#L415 assume !(0 != eval_~tmp___1~0#1); 6842#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6840#L258-3 assume !(1 == ~q_req_up~0); 6838#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6837#L311-3 assume !(0 == ~q_read_ev~0); 6836#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 6835#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6834#L66-3 assume !(1 == ~p_dw_pc~0); 6142#L66-5 assume !(2 == ~p_dw_pc~0); 6070#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 6071#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6832#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6831#L387-3 assume !(0 != activate_threads_~tmp~1#1); 6830#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6829#L95-3 assume !(1 == ~c_dr_pc~0); 6828#L95-5 assume !(2 == ~c_dr_pc~0); 6827#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 6192#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6123#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6124#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6086#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6087#L329-3 assume !(1 == ~q_read_ev~0); 6130#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 6182#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6884#L291-1 assume !(0 == ~p_dw_st~0); 6882#L295-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6880#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6878#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6875#L510 assume !(0 == start_simulation_~tmp~4#1); 6872#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6870#L291-2 assume !(0 == ~p_dw_st~0); 6868#L295-2 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6866#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6864#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6862#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6860#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6858#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6855#L523 assume !(0 != start_simulation_~tmp___0~3#1); 6854#L491-2 [2024-10-12 01:02:07,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,951 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2024-10-12 01:02:07,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226673287] [2024-10-12 01:02:07,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:07,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:07,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:07,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226673287] [2024-10-12 01:02:07,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226673287] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:07,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:07,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-12 01:02:07,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750274193] [2024-10-12 01:02:07,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:07,975 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-12 01:02:07,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:07,975 INFO L85 PathProgramCache]: Analyzing trace with hash -1954829134, now seen corresponding path program 1 times [2024-10-12 01:02:07,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:07,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359328993] [2024-10-12 01:02:07,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:07,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:07,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:08,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:08,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:08,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359328993] [2024-10-12 01:02:08,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359328993] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:08,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:08,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-12 01:02:08,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235116980] [2024-10-12 01:02:08,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:08,033 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-12 01:02:08,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:08,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-12 01:02:08,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-12 01:02:08,033 INFO L87 Difference]: Start difference. First operand 850 states and 1119 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:08,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:08,039 INFO L93 Difference]: Finished difference Result 806 states and 1065 transitions. [2024-10-12 01:02:08,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 806 states and 1065 transitions. [2024-10-12 01:02:08,041 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2024-10-12 01:02:08,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 806 states to 806 states and 1065 transitions. [2024-10-12 01:02:08,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 806 [2024-10-12 01:02:08,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 806 [2024-10-12 01:02:08,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 806 states and 1065 transitions. [2024-10-12 01:02:08,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:08,045 INFO L218 hiAutomatonCegarLoop]: Abstraction has 806 states and 1065 transitions. [2024-10-12 01:02:08,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 806 states and 1065 transitions. [2024-10-12 01:02:08,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 806 to 806. [2024-10-12 01:02:08,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 806 states, 806 states have (on average 1.3213399503722085) internal successors, (1065), 805 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:08,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 806 states to 806 states and 1065 transitions. [2024-10-12 01:02:08,053 INFO L240 hiAutomatonCegarLoop]: Abstraction has 806 states and 1065 transitions. [2024-10-12 01:02:08,053 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-12 01:02:08,054 INFO L425 stractBuchiCegarLoop]: Abstraction has 806 states and 1065 transitions. [2024-10-12 01:02:08,054 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-12 01:02:08,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 806 states and 1065 transitions. [2024-10-12 01:02:08,056 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2024-10-12 01:02:08,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:08,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:08,056 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:08,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:08,057 INFO L745 eck$LassoCheckResult]: Stem: 7763#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 7764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 7790#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7770#L258 assume !(1 == ~q_req_up~0); 7772#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7836#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 7888#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 7889#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7806#L311 assume !(0 == ~q_read_ev~0); 7807#L311-2 assume !(0 == ~q_write_ev~0); 7845#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 7846#L66 assume !(1 == ~p_dw_pc~0); 7794#L66-2 assume !(2 == ~p_dw_pc~0); 7795#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 7817#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 7818#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7813#L387 assume !(0 != activate_threads_~tmp~1#1); 7814#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7856#L95 assume !(1 == ~c_dr_pc~0); 7857#L95-2 assume !(2 == ~c_dr_pc~0); 7827#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 7828#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7773#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7774#L395 assume !(0 != activate_threads_~tmp___0~1#1); 7741#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7742#L329 assume !(1 == ~q_read_ev~0); 7775#L329-2 assume !(1 == ~q_write_ev~0); 7784#L334-1 assume { :end_inline_reset_delta_events } true; 7785#L491-2 assume !false; 8398#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8396#L435 [2024-10-12 01:02:08,057 INFO L747 eck$LassoCheckResult]: Loop: 8396#L435 assume !false; 8394#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8391#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8390#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8388#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8386#L415 assume 0 != eval_~tmp___1~0#1; 8382#L415-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 8379#L424 assume !(0 != eval_~tmp~2#1); 8380#L420 assume !(0 == ~c_dr_st~0); 8396#L435 [2024-10-12 01:02:08,057 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:08,057 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2024-10-12 01:02:08,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:08,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615957786] [2024-10-12 01:02:08,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:08,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:08,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,064 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:08,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,069 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-12 01:02:08,069 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:08,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877041, now seen corresponding path program 1 times [2024-10-12 01:02:08,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:08,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831316698] [2024-10-12 01:02:08,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:08,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:08,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,071 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:08,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,073 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-12 01:02:08,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:08,074 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124191, now seen corresponding path program 1 times [2024-10-12 01:02:08,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:08,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006273414] [2024-10-12 01:02:08,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:08,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:08,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-12 01:02:08,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-12 01:02:08,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-12 01:02:08,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006273414] [2024-10-12 01:02:08,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006273414] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-12 01:02:08,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-12 01:02:08,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-12 01:02:08,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850797086] [2024-10-12 01:02:08,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-12 01:02:08,157 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-12 01:02:08,157 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-12 01:02:08,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-12 01:02:08,158 INFO L87 Difference]: Start difference. First operand 806 states and 1065 transitions. cyclomatic complexity: 266 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:08,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-12 01:02:08,181 INFO L93 Difference]: Finished difference Result 922 states and 1209 transitions. [2024-10-12 01:02:08,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 922 states and 1209 transitions. [2024-10-12 01:02:08,185 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 850 [2024-10-12 01:02:08,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 922 states to 922 states and 1209 transitions. [2024-10-12 01:02:08,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 922 [2024-10-12 01:02:08,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 922 [2024-10-12 01:02:08,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 922 states and 1209 transitions. [2024-10-12 01:02:08,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-12 01:02:08,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 922 states and 1209 transitions. [2024-10-12 01:02:08,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 922 states and 1209 transitions. [2024-10-12 01:02:08,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 922 to 814. [2024-10-12 01:02:08,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 814 states, 814 states have (on average 1.3194103194103195) internal successors, (1074), 813 states have internal predecessors, (1074), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-12 01:02:08,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 814 states to 814 states and 1074 transitions. [2024-10-12 01:02:08,197 INFO L240 hiAutomatonCegarLoop]: Abstraction has 814 states and 1074 transitions. [2024-10-12 01:02:08,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-12 01:02:08,198 INFO L425 stractBuchiCegarLoop]: Abstraction has 814 states and 1074 transitions. [2024-10-12 01:02:08,198 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-12 01:02:08,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 814 states and 1074 transitions. [2024-10-12 01:02:08,200 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 743 [2024-10-12 01:02:08,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-12 01:02:08,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-12 01:02:08,200 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:08,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-12 01:02:08,201 INFO L745 eck$LassoCheckResult]: Stem: 9498#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 9499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 9524#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9505#L258 assume !(1 == ~q_req_up~0); 9507#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9562#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 9563#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 9630#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9539#L311 assume !(0 == ~q_read_ev~0); 9540#L311-2 assume !(0 == ~q_write_ev~0); 9612#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9515#L66 assume !(1 == ~p_dw_pc~0); 9516#L66-2 assume !(2 == ~p_dw_pc~0); 9660#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 9552#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9553#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9548#L387 assume !(0 != activate_threads_~tmp~1#1); 9549#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9597#L95 assume !(1 == ~c_dr_pc~0); 9598#L95-2 assume !(2 == ~c_dr_pc~0); 9564#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 9565#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9508#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9509#L395 assume !(0 != activate_threads_~tmp___0~1#1); 9476#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9477#L329 assume !(1 == ~q_read_ev~0); 9510#L329-2 assume !(1 == ~q_write_ev~0); 9822#L334-1 assume { :end_inline_reset_delta_events } true; 9821#L491-2 assume !false; 9819#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 9799#L435 [2024-10-12 01:02:08,201 INFO L747 eck$LassoCheckResult]: Loop: 9799#L435 assume !false; 9817#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9815#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9813#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9811#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9809#L415 assume 0 != eval_~tmp___1~0#1; 9807#L415-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 9804#L424 assume !(0 != eval_~tmp~2#1); 9802#L420 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 9798#L439 assume !(0 != eval_~tmp___0~2#1); 9799#L435 [2024-10-12 01:02:08,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:08,201 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 2 times [2024-10-12 01:02:08,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:08,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478126105] [2024-10-12 01:02:08,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:08,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:08,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,206 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:08,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,212 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-12 01:02:08,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:08,212 INFO L85 PathProgramCache]: Analyzing trace with hash -418551845, now seen corresponding path program 1 times [2024-10-12 01:02:08,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:08,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429783405] [2024-10-12 01:02:08,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:08,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:08,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,214 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:08,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,216 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-12 01:02:08,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-12 01:02:08,217 INFO L85 PathProgramCache]: Analyzing trace with hash 1670788587, now seen corresponding path program 1 times [2024-10-12 01:02:08,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-12 01:02:08,217 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618289852] [2024-10-12 01:02:08,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-12 01:02:08,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-12 01:02:08,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,221 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:08,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,250 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-12 01:02:08,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,832 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-12 01:02:08,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-12 01:02:08,920 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 12.10 01:02:08 BoogieIcfgContainer [2024-10-12 01:02:08,920 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-10-12 01:02:08,921 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-10-12 01:02:08,921 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-10-12 01:02:08,921 INFO L274 PluginConnector]: Witness Printer initialized [2024-10-12 01:02:08,922 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.10 01:02:06" (3/4) ... [2024-10-12 01:02:08,926 INFO L136 WitnessPrinter]: Generating witness for non-termination counterexample [2024-10-12 01:02:08,989 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-10-12 01:02:08,989 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-10-12 01:02:08,990 INFO L158 Benchmark]: Toolchain (without parser) took 3980.80ms. Allocated memory was 142.6MB in the beginning and 274.7MB in the end (delta: 132.1MB). Free memory was 71.4MB in the beginning and 115.6MB in the end (delta: -44.3MB). Peak memory consumption was 89.6MB. Max. memory is 16.1GB. [2024-10-12 01:02:08,990 INFO L158 Benchmark]: CDTParser took 0.08ms. Allocated memory is still 142.6MB. Free memory is still 112.1MB. There was no memory consumed. Max. memory is 16.1GB. [2024-10-12 01:02:08,990 INFO L158 Benchmark]: CACSL2BoogieTranslator took 293.55ms. Allocated memory is still 142.6MB. Free memory was 71.1MB in the beginning and 56.0MB in the end (delta: 15.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-10-12 01:02:08,990 INFO L158 Benchmark]: Boogie Procedure Inliner took 41.09ms. Allocated memory is still 142.6MB. Free memory was 55.8MB in the beginning and 53.3MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-10-12 01:02:08,991 INFO L158 Benchmark]: Boogie Preprocessor took 78.74ms. Allocated memory was 142.6MB in the beginning and 228.6MB in the end (delta: 86.0MB). Free memory was 53.3MB in the beginning and 195.0MB in the end (delta: -141.7MB). Peak memory consumption was 8.5MB. Max. memory is 16.1GB. [2024-10-12 01:02:08,991 INFO L158 Benchmark]: RCFGBuilder took 619.81ms. Allocated memory is still 228.6MB. Free memory was 195.0MB in the beginning and 173.0MB in the end (delta: 22.0MB). Peak memory consumption was 25.8MB. Max. memory is 16.1GB. [2024-10-12 01:02:08,991 INFO L158 Benchmark]: BuchiAutomizer took 2871.56ms. Allocated memory was 228.6MB in the beginning and 274.7MB in the end (delta: 46.1MB). Free memory was 173.0MB in the beginning and 120.9MB in the end (delta: 52.1MB). Peak memory consumption was 97.2MB. Max. memory is 16.1GB. [2024-10-12 01:02:08,991 INFO L158 Benchmark]: Witness Printer took 68.44ms. Allocated memory is still 274.7MB. Free memory was 120.9MB in the beginning and 115.6MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-10-12 01:02:08,992 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.08ms. Allocated memory is still 142.6MB. Free memory is still 112.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 293.55ms. Allocated memory is still 142.6MB. Free memory was 71.1MB in the beginning and 56.0MB in the end (delta: 15.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 41.09ms. Allocated memory is still 142.6MB. Free memory was 55.8MB in the beginning and 53.3MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 78.74ms. Allocated memory was 142.6MB in the beginning and 228.6MB in the end (delta: 86.0MB). Free memory was 53.3MB in the beginning and 195.0MB in the end (delta: -141.7MB). Peak memory consumption was 8.5MB. Max. memory is 16.1GB. * RCFGBuilder took 619.81ms. Allocated memory is still 228.6MB. Free memory was 195.0MB in the beginning and 173.0MB in the end (delta: 22.0MB). Peak memory consumption was 25.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 2871.56ms. Allocated memory was 228.6MB in the beginning and 274.7MB in the end (delta: 46.1MB). Free memory was 173.0MB in the beginning and 120.9MB in the end (delta: 52.1MB). Peak memory consumption was 97.2MB. Max. memory is 16.1GB. * Witness Printer took 68.44ms. Allocated memory is still 274.7MB. Free memory was 120.9MB in the beginning and 115.6MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 814 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.7s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 1.8s. Construction of modules took 0.2s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 9 MinimizatonAttempts, 232 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1649 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1649 mSDsluCounter, 3336 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1737 mSDsCounter, 74 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 241 IncrementalHoareTripleChecker+Invalid, 315 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 74 mSolverCounterUnsat, 1599 mSDtfsCounter, 241 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-10-12 01:02:09,036 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-clean/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)