./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a046e57d Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-mul-div-a046e57-m [2024-10-13 17:43:43,309 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-13 17:43:43,350 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-13 17:43:43,353 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-13 17:43:43,354 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-13 17:43:43,377 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-13 17:43:43,378 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-13 17:43:43,378 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-13 17:43:43,379 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-13 17:43:43,380 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-13 17:43:43,380 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-13 17:43:43,381 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-13 17:43:43,381 INFO L153 SettingsManager]: * Use SBE=true [2024-10-13 17:43:43,381 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-13 17:43:43,383 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-13 17:43:43,383 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-13 17:43:43,383 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-13 17:43:43,383 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-13 17:43:43,384 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-13 17:43:43,384 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-13 17:43:43,384 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-13 17:43:43,387 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-13 17:43:43,388 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-13 17:43:43,388 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-13 17:43:43,388 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-13 17:43:43,388 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-13 17:43:43,388 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-13 17:43:43,389 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-13 17:43:43,389 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-13 17:43:43,389 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-13 17:43:43,390 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-13 17:43:43,390 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-13 17:43:43,390 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-13 17:43:43,390 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-13 17:43:43,391 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-13 17:43:43,391 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-13 17:43:43,391 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-13 17:43:43,391 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-13 17:43:43,392 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-13 17:43:43,392 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2024-10-13 17:43:43,559 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-13 17:43:43,578 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-13 17:43:43,580 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-13 17:43:43,581 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-13 17:43:43,581 INFO L274 PluginConnector]: CDTParser initialized [2024-10-13 17:43:43,582 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2024-10-13 17:43:44,847 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-13 17:43:45,086 INFO L384 CDTParser]: Found 1 translation units. [2024-10-13 17:43:45,086 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2024-10-13 17:43:45,095 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/002e16aeb/60ee2034a86343a2aeefc42648b19258/FLAGc3b94b11b [2024-10-13 17:43:45,109 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/002e16aeb/60ee2034a86343a2aeefc42648b19258 [2024-10-13 17:43:45,111 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-13 17:43:45,112 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-13 17:43:45,113 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-13 17:43:45,114 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-13 17:43:45,120 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-13 17:43:45,120 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,121 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44ca646 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45, skipping insertion in model container [2024-10-13 17:43:45,121 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,146 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-13 17:43:45,309 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:43:45,321 INFO L200 MainTranslator]: Completed pre-run [2024-10-13 17:43:45,345 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:43:45,363 INFO L204 MainTranslator]: Completed translation [2024-10-13 17:43:45,363 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45 WrapperNode [2024-10-13 17:43:45,363 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-13 17:43:45,364 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-13 17:43:45,364 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-13 17:43:45,364 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-13 17:43:45,369 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,376 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,396 INFO L138 Inliner]: procedures = 30, calls = 31, calls flagged for inlining = 26, calls inlined = 32, statements flattened = 345 [2024-10-13 17:43:45,396 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-13 17:43:45,396 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-13 17:43:45,397 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-13 17:43:45,397 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-13 17:43:45,407 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,407 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,409 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,418 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-13 17:43:45,418 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,418 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,422 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,429 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,430 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,431 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,433 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-13 17:43:45,434 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-13 17:43:45,434 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-13 17:43:45,434 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-13 17:43:45,436 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (1/1) ... [2024-10-13 17:43:45,440 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:45,449 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:45,465 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:45,467 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-13 17:43:45,505 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-13 17:43:45,505 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-13 17:43:45,505 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-13 17:43:45,506 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-13 17:43:45,572 INFO L238 CfgBuilder]: Building ICFG [2024-10-13 17:43:45,574 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-13 17:43:45,879 INFO L? ?]: Removed 36 outVars from TransFormulas that were not future-live. [2024-10-13 17:43:45,879 INFO L287 CfgBuilder]: Performing block encoding [2024-10-13 17:43:45,891 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-13 17:43:45,894 INFO L314 CfgBuilder]: Removed 2 assume(true) statements. [2024-10-13 17:43:45,894 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:43:45 BoogieIcfgContainer [2024-10-13 17:43:45,894 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-13 17:43:45,895 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-13 17:43:45,895 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-13 17:43:45,898 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-13 17:43:45,900 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:43:45,900 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 05:43:45" (1/3) ... [2024-10-13 17:43:45,901 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@440a2f9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:43:45, skipping insertion in model container [2024-10-13 17:43:45,902 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:43:45,902 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:43:45" (2/3) ... [2024-10-13 17:43:45,903 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@440a2f9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:43:45, skipping insertion in model container [2024-10-13 17:43:45,903 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:43:45,903 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:43:45" (3/3) ... [2024-10-13 17:43:45,904 INFO L332 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2024-10-13 17:43:45,942 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-13 17:43:45,942 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-13 17:43:45,942 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-13 17:43:45,942 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-13 17:43:45,942 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-13 17:43:45,943 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-13 17:43:45,943 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-13 17:43:45,943 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-13 17:43:45,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:45,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:45,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:45,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:45,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:45,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:45,969 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-13 17:43:45,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:45,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:45,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:45,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:45,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:45,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:45,982 INFO L745 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 41#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 118#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70#L212true assume !(1 == ~b0_req_up~0); 122#L212-2true assume !(1 == ~b1_req_up~0); 78#L219-1true assume !(1 == ~d0_req_up~0); 42#L226-1true assume !(1 == ~d1_req_up~0); 61#L233-1true assume !(1 == ~z_req_up~0); 105#L240-1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13#L255true assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 115#L255-2true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62#L321true assume !(0 == ~b0_ev~0); 77#L321-2true assume !(0 == ~b1_ev~0); 22#L326-1true assume !(0 == ~d0_ev~0); 25#L331-1true assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 5#L336-1true assume !(0 == ~z_ev~0); 120#L341-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 116#L107true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 104#L129true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 75#is_method1_triggered_returnLabel#1true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 87#L390true assume !(0 != activate_threads_~tmp~1#1); 110#L390-2true havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53#L354true assume !(1 == ~b0_ev~0); 38#L354-2true assume !(1 == ~b1_ev~0); 85#L359-1true assume !(1 == ~d0_ev~0); 40#L364-1true assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 45#L369-1true assume !(1 == ~z_ev~0); 92#L374-1true assume { :end_inline_reset_delta_events } true; 33#L432-2true [2024-10-13 17:43:45,982 INFO L747 eck$LassoCheckResult]: Loop: 33#L432-2true assume !false; 64#L433true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 4#L295true assume !true; 84#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79#L212-3true assume !(1 == ~b0_req_up~0); 107#L212-5true assume !(1 == ~b1_req_up~0); 83#L219-3true assume !(1 == ~d0_req_up~0); 3#L226-3true assume !(1 == ~d1_req_up~0); 36#L233-3true assume !(1 == ~z_req_up~0); 14#L240-3true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74#L321-3true assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 60#L321-5true assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 89#L326-3true assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 48#L331-3true assume !(0 == ~d1_ev~0); 9#L336-3true assume 0 == ~z_ev~0;~z_ev~0 := 1; 15#L341-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 112#L107-1true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 43#L129-1true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 113#is_method1_triggered_returnLabel#2true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 6#L390-3true assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 21#L390-5true havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31#L354-3true assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 97#L354-5true assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 95#L359-3true assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 76#L364-3true assume !(1 == ~d1_ev~0); 73#L369-3true assume 1 == ~z_ev~0;~z_ev~0 := 2; 47#L374-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 66#L268-1true assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 117#L275-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 90#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 11#L407true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114#L414true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123#stop_simulation_returnLabel#1true start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 67#L449true assume !(0 != start_simulation_~tmp~3#1); 33#L432-2true [2024-10-13 17:43:45,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:45,986 INFO L85 PathProgramCache]: Analyzing trace with hash -1345002148, now seen corresponding path program 1 times [2024-10-13 17:43:45,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:45,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91884887] [2024-10-13 17:43:45,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:45,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,164 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91884887] [2024-10-13 17:43:46,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91884887] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,166 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:46,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407366540] [2024-10-13 17:43:46,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,179 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:46,180 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,180 INFO L85 PathProgramCache]: Analyzing trace with hash 972845291, now seen corresponding path program 1 times [2024-10-13 17:43:46,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,180 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365963286] [2024-10-13 17:43:46,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365963286] [2024-10-13 17:43:46,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365963286] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:43:46,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554985048] [2024-10-13 17:43:46,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,220 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:46,222 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:46,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:46,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:46,255 INFO L87 Difference]: Start difference. First operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:46,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:46,290 INFO L93 Difference]: Finished difference Result 124 states and 190 transitions. [2024-10-13 17:43:46,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 190 transitions. [2024-10-13 17:43:46,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:46,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 117 states and 183 transitions. [2024-10-13 17:43:46,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-10-13 17:43:46,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-10-13 17:43:46,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 183 transitions. [2024-10-13 17:43:46,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:43:46,332 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2024-10-13 17:43:46,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 183 transitions. [2024-10-13 17:43:46,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-10-13 17:43:46,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.564102564102564) internal successors, (183), 116 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:46,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 183 transitions. [2024-10-13 17:43:46,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2024-10-13 17:43:46,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:46,389 INFO L425 stractBuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2024-10-13 17:43:46,389 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-13 17:43:46,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 183 transitions. [2024-10-13 17:43:46,391 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:46,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:46,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:46,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:46,394 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:46,396 INFO L745 eck$LassoCheckResult]: Stem: 302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 355#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 343#L137 assume !(~b0_val~0 != ~b0_val_t~0); 344#L137-2 ~b0_req_up~0 := 0; 371#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 375#L212-2 assume !(1 == ~b1_req_up~0); 278#L219-1 assume !(1 == ~d0_req_up~0); 325#L226-1 assume !(1 == ~d1_req_up~0); 327#L233-1 assume !(1 == ~z_req_up~0); 348#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 279#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 280#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 349#L321 assume !(0 == ~b0_ev~0); 350#L321-2 assume !(0 == ~b1_ev~0); 295#L326-1 assume !(0 == ~d0_ev~0); 296#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 264#L336-1 assume !(0 == ~z_ev~0); 265#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 374#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 288#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 358#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 359#L390 assume !(0 != activate_threads_~tmp~1#1); 364#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336#L354 assume !(1 == ~b0_ev~0); 318#L354-2 assume !(1 == ~b1_ev~0); 319#L359-1 assume !(1 == ~d0_ev~0); 322#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 323#L369-1 assume !(1 == ~z_ev~0); 329#L374-1 assume { :end_inline_reset_delta_events } true; 310#L432-2 [2024-10-13 17:43:46,396 INFO L747 eck$LassoCheckResult]: Loop: 310#L432-2 assume !false; 311#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 262#L295 assume !false; 263#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 292#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 293#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 273#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 274#L290 assume !(0 != eval_~tmp___0~0#1); 363#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 361#L212-3 assume !(1 == ~b0_req_up~0); 314#L212-5 assume !(1 == ~b1_req_up~0); 321#L219-3 assume !(1 == ~d0_req_up~0); 259#L226-3 assume !(1 == ~d1_req_up~0); 260#L233-3 assume !(1 == ~z_req_up~0); 281#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 345#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 346#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 332#L331-3 assume !(0 == ~d1_ev~0); 271#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 272#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 283#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 301#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 328#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 266#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 267#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 307#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 368#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 360#L364-3 assume !(1 == ~d1_ev~0); 357#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 330#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 331#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 351#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 365#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 275#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 276#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 373#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 352#L449 assume !(0 != start_simulation_~tmp~3#1); 310#L432-2 [2024-10-13 17:43:46,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1840469421, now seen corresponding path program 1 times [2024-10-13 17:43:46,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607070487] [2024-10-13 17:43:46,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607070487] [2024-10-13 17:43:46,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607070487] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,518 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,518 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:46,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572603578] [2024-10-13 17:43:46,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,519 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:46,519 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,519 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 1 times [2024-10-13 17:43:46,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970484548] [2024-10-13 17:43:46,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,607 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970484548] [2024-10-13 17:43:46,608 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970484548] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,608 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,608 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:43:46,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365006440] [2024-10-13 17:43:46,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,608 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:46,609 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:46,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:46,610 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:46,610 INFO L87 Difference]: Start difference. First operand 117 states and 183 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:46,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:46,630 INFO L93 Difference]: Finished difference Result 117 states and 182 transitions. [2024-10-13 17:43:46,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 182 transitions. [2024-10-13 17:43:46,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:46,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 182 transitions. [2024-10-13 17:43:46,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-10-13 17:43:46,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-10-13 17:43:46,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 182 transitions. [2024-10-13 17:43:46,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:43:46,634 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2024-10-13 17:43:46,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 182 transitions. [2024-10-13 17:43:46,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-10-13 17:43:46,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5555555555555556) internal successors, (182), 116 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:46,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 182 transitions. [2024-10-13 17:43:46,643 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2024-10-13 17:43:46,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:46,644 INFO L425 stractBuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2024-10-13 17:43:46,646 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-13 17:43:46,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 182 transitions. [2024-10-13 17:43:46,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:46,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:46,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:46,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:46,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:46,649 INFO L745 eck$LassoCheckResult]: Stem: 545#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 567#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 598#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 586#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 587#L137-2 ~b0_req_up~0 := 0; 614#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 618#L212-2 assume !(1 == ~b1_req_up~0); 521#L219-1 assume !(1 == ~d0_req_up~0); 568#L226-1 assume !(1 == ~d1_req_up~0); 570#L233-1 assume !(1 == ~z_req_up~0); 591#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 522#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 523#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 592#L321 assume !(0 == ~b0_ev~0); 593#L321-2 assume !(0 == ~b1_ev~0); 538#L326-1 assume !(0 == ~d0_ev~0); 539#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 507#L336-1 assume !(0 == ~z_ev~0); 508#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 617#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 531#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 601#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 602#L390 assume !(0 != activate_threads_~tmp~1#1); 607#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 579#L354 assume !(1 == ~b0_ev~0); 561#L354-2 assume !(1 == ~b1_ev~0); 562#L359-1 assume !(1 == ~d0_ev~0); 565#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 566#L369-1 assume !(1 == ~z_ev~0); 572#L374-1 assume { :end_inline_reset_delta_events } true; 553#L432-2 [2024-10-13 17:43:46,649 INFO L747 eck$LassoCheckResult]: Loop: 553#L432-2 assume !false; 554#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 505#L295 assume !false; 506#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 535#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 536#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 516#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 517#L290 assume !(0 != eval_~tmp___0~0#1); 606#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 604#L212-3 assume !(1 == ~b0_req_up~0); 557#L212-5 assume !(1 == ~b1_req_up~0); 564#L219-3 assume !(1 == ~d0_req_up~0); 502#L226-3 assume !(1 == ~d1_req_up~0); 503#L233-3 assume !(1 == ~z_req_up~0); 524#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 525#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 588#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 589#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 575#L331-3 assume !(0 == ~d1_ev~0); 514#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 515#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 526#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 544#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 571#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 509#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 510#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 537#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 550#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 611#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 603#L364-3 assume !(1 == ~d1_ev~0); 600#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 573#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 574#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 594#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 608#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 518#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 519#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 616#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 595#L449 assume !(0 != start_simulation_~tmp~3#1); 553#L432-2 [2024-10-13 17:43:46,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,650 INFO L85 PathProgramCache]: Analyzing trace with hash 531269841, now seen corresponding path program 1 times [2024-10-13 17:43:46,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339179516] [2024-10-13 17:43:46,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339179516] [2024-10-13 17:43:46,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339179516] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,677 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:46,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685999698] [2024-10-13 17:43:46,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,678 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:46,678 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,678 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 2 times [2024-10-13 17:43:46,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64954538] [2024-10-13 17:43:46,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,729 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64954538] [2024-10-13 17:43:46,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64954538] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:43:46,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852086502] [2024-10-13 17:43:46,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,730 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:46,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:46,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:46,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:46,731 INFO L87 Difference]: Start difference. First operand 117 states and 182 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:46,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:46,746 INFO L93 Difference]: Finished difference Result 117 states and 181 transitions. [2024-10-13 17:43:46,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 181 transitions. [2024-10-13 17:43:46,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:46,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 181 transitions. [2024-10-13 17:43:46,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-10-13 17:43:46,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-10-13 17:43:46,751 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 181 transitions. [2024-10-13 17:43:46,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:43:46,752 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2024-10-13 17:43:46,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 181 transitions. [2024-10-13 17:43:46,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-10-13 17:43:46,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.547008547008547) internal successors, (181), 116 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:46,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 181 transitions. [2024-10-13 17:43:46,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2024-10-13 17:43:46,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:46,757 INFO L425 stractBuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2024-10-13 17:43:46,758 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-13 17:43:46,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 181 transitions. [2024-10-13 17:43:46,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:46,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:46,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:46,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:46,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:46,762 INFO L745 eck$LassoCheckResult]: Stem: 788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 810#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 841#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 829#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 830#L137-2 ~b0_req_up~0 := 0; 857#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 861#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 790#L152 assume !(~b1_val~0 != ~b1_val_t~0); 791#L152-2 ~b1_req_up~0 := 0; 763#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 764#L219-1 assume !(1 == ~d0_req_up~0); 811#L226-1 assume !(1 == ~d1_req_up~0); 813#L233-1 assume !(1 == ~z_req_up~0); 834#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 765#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 766#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 835#L321 assume !(0 == ~b0_ev~0); 836#L321-2 assume !(0 == ~b1_ev~0); 781#L326-1 assume !(0 == ~d0_ev~0); 782#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 750#L336-1 assume !(0 == ~z_ev~0); 751#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 860#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 774#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 844#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 845#L390 assume !(0 != activate_threads_~tmp~1#1); 850#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 822#L354 assume !(1 == ~b0_ev~0); 804#L354-2 assume !(1 == ~b1_ev~0); 805#L359-1 assume !(1 == ~d0_ev~0); 808#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 809#L369-1 assume !(1 == ~z_ev~0); 815#L374-1 assume { :end_inline_reset_delta_events } true; 796#L432-2 [2024-10-13 17:43:46,763 INFO L747 eck$LassoCheckResult]: Loop: 796#L432-2 assume !false; 797#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 748#L295 assume !false; 749#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 778#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 779#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 759#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 760#L290 assume !(0 != eval_~tmp___0~0#1); 849#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 847#L212-3 assume !(1 == ~b0_req_up~0); 800#L212-5 assume !(1 == ~b1_req_up~0); 807#L219-3 assume !(1 == ~d0_req_up~0); 745#L226-3 assume !(1 == ~d1_req_up~0); 746#L233-3 assume !(1 == ~z_req_up~0); 767#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 768#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 831#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 832#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 818#L331-3 assume !(0 == ~d1_ev~0); 757#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 758#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 769#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 787#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 814#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 752#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 753#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 780#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 793#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 854#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 846#L364-3 assume !(1 == ~d1_ev~0); 843#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 816#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 817#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 837#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 851#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 761#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 762#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 859#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 838#L449 assume !(0 != start_simulation_~tmp~3#1); 796#L432-2 [2024-10-13 17:43:46,763 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,763 INFO L85 PathProgramCache]: Analyzing trace with hash 1296388927, now seen corresponding path program 1 times [2024-10-13 17:43:46,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326613190] [2024-10-13 17:43:46,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,820 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,820 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326613190] [2024-10-13 17:43:46,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1326613190] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-13 17:43:46,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388594297] [2024-10-13 17:43:46,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,823 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:46,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 3 times [2024-10-13 17:43:46,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965617977] [2024-10-13 17:43:46,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965617977] [2024-10-13 17:43:46,877 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965617977] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,877 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,877 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:43:46,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1875685728] [2024-10-13 17:43:46,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,878 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:46,878 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:46,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:43:46,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:43:46,879 INFO L87 Difference]: Start difference. First operand 117 states and 181 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:46,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:46,933 INFO L93 Difference]: Finished difference Result 117 states and 180 transitions. [2024-10-13 17:43:46,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 180 transitions. [2024-10-13 17:43:46,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:46,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 180 transitions. [2024-10-13 17:43:46,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-10-13 17:43:46,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-10-13 17:43:46,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 180 transitions. [2024-10-13 17:43:46,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:43:46,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2024-10-13 17:43:46,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 180 transitions. [2024-10-13 17:43:46,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-10-13 17:43:46,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5384615384615385) internal successors, (180), 116 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:46,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 180 transitions. [2024-10-13 17:43:46,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2024-10-13 17:43:46,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:43:46,945 INFO L425 stractBuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2024-10-13 17:43:46,945 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-13 17:43:46,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 180 transitions. [2024-10-13 17:43:46,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:46,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:46,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:46,947 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:46,947 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:46,947 INFO L745 eck$LassoCheckResult]: Stem: 1034#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1056#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1087#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1075#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1076#L137-2 ~b0_req_up~0 := 0; 1103#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1107#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1036#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1037#L152-2 ~b1_req_up~0 := 0; 1009#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1010#L219-1 assume !(1 == ~d0_req_up~0); 1057#L226-1 assume !(1 == ~d1_req_up~0); 1059#L233-1 assume !(1 == ~z_req_up~0); 1080#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1011#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1012#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1081#L321 assume !(0 == ~b0_ev~0); 1082#L321-2 assume !(0 == ~b1_ev~0); 1027#L326-1 assume !(0 == ~d0_ev~0); 1028#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 996#L336-1 assume !(0 == ~z_ev~0); 997#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1106#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1020#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1090#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1091#L390 assume !(0 != activate_threads_~tmp~1#1); 1096#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1068#L354 assume !(1 == ~b0_ev~0); 1050#L354-2 assume !(1 == ~b1_ev~0); 1051#L359-1 assume !(1 == ~d0_ev~0); 1054#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1055#L369-1 assume !(1 == ~z_ev~0); 1061#L374-1 assume { :end_inline_reset_delta_events } true; 1042#L432-2 [2024-10-13 17:43:46,947 INFO L747 eck$LassoCheckResult]: Loop: 1042#L432-2 assume !false; 1043#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 994#L295 assume !false; 995#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1024#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1025#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1005#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1006#L290 assume !(0 != eval_~tmp___0~0#1); 1095#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1093#L212-3 assume !(1 == ~b0_req_up~0); 1046#L212-5 assume !(1 == ~b1_req_up~0); 1053#L219-3 assume !(1 == ~d0_req_up~0); 991#L226-3 assume !(1 == ~d1_req_up~0); 992#L233-3 assume !(1 == ~z_req_up~0); 1013#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1014#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1077#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1078#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1064#L331-3 assume !(0 == ~d1_ev~0); 1003#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1004#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1015#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1033#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1060#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 998#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 999#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1026#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1039#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1100#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1092#L364-3 assume !(1 == ~d1_ev~0); 1089#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1062#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1063#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1083#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1097#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1007#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1008#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1105#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1084#L449 assume !(0 != start_simulation_~tmp~3#1); 1042#L432-2 [2024-10-13 17:43:46,948 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,948 INFO L85 PathProgramCache]: Analyzing trace with hash 1234349313, now seen corresponding path program 1 times [2024-10-13 17:43:46,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854597218] [2024-10-13 17:43:46,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:46,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:46,982 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:46,982 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854597218] [2024-10-13 17:43:46,983 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854597218] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:46,983 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:46,983 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:46,983 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559087302] [2024-10-13 17:43:46,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:46,983 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:46,984 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:46,984 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 4 times [2024-10-13 17:43:46,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:46,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541332681] [2024-10-13 17:43:46,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:46,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:46,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:47,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:47,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:47,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541332681] [2024-10-13 17:43:47,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541332681] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:47,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:47,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:43:47,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884360142] [2024-10-13 17:43:47,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:47,025 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:47,025 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:47,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:47,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:47,026 INFO L87 Difference]: Start difference. First operand 117 states and 180 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:47,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:47,038 INFO L93 Difference]: Finished difference Result 117 states and 179 transitions. [2024-10-13 17:43:47,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 179 transitions. [2024-10-13 17:43:47,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:47,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 179 transitions. [2024-10-13 17:43:47,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-10-13 17:43:47,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-10-13 17:43:47,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 179 transitions. [2024-10-13 17:43:47,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:43:47,041 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2024-10-13 17:43:47,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 179 transitions. [2024-10-13 17:43:47,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-10-13 17:43:47,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5299145299145298) internal successors, (179), 116 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:47,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 179 transitions. [2024-10-13 17:43:47,049 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2024-10-13 17:43:47,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:47,050 INFO L425 stractBuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2024-10-13 17:43:47,050 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-13 17:43:47,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 179 transitions. [2024-10-13 17:43:47,051 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:47,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:47,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:47,053 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:47,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:47,054 INFO L745 eck$LassoCheckResult]: Stem: 1277#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1299#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1330#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1318#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1319#L137-2 ~b0_req_up~0 := 0; 1346#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1350#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1279#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1280#L152-2 ~b1_req_up~0 := 0; 1252#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1253#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1259#L167 assume !(~d0_val~0 != ~d0_val_t~0); 1260#L167-2 ~d0_req_up~0 := 0; 1274#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1300#L226-1 assume !(1 == ~d1_req_up~0); 1302#L233-1 assume !(1 == ~z_req_up~0); 1323#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1254#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1255#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1324#L321 assume !(0 == ~b0_ev~0); 1325#L321-2 assume !(0 == ~b1_ev~0); 1270#L326-1 assume !(0 == ~d0_ev~0); 1271#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1239#L336-1 assume !(0 == ~z_ev~0); 1240#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1349#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1263#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1333#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1334#L390 assume !(0 != activate_threads_~tmp~1#1); 1339#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1311#L354 assume !(1 == ~b0_ev~0); 1293#L354-2 assume !(1 == ~b1_ev~0); 1294#L359-1 assume !(1 == ~d0_ev~0); 1297#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1298#L369-1 assume !(1 == ~z_ev~0); 1304#L374-1 assume { :end_inline_reset_delta_events } true; 1285#L432-2 [2024-10-13 17:43:47,054 INFO L747 eck$LassoCheckResult]: Loop: 1285#L432-2 assume !false; 1286#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1237#L295 assume !false; 1238#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1267#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1268#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1248#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1249#L290 assume !(0 != eval_~tmp___0~0#1); 1338#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1336#L212-3 assume !(1 == ~b0_req_up~0); 1289#L212-5 assume !(1 == ~b1_req_up~0); 1296#L219-3 assume !(1 == ~d0_req_up~0); 1234#L226-3 assume !(1 == ~d1_req_up~0); 1235#L233-3 assume !(1 == ~z_req_up~0); 1256#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1257#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1320#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1321#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1307#L331-3 assume !(0 == ~d1_ev~0); 1246#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1247#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1258#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1276#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1303#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1241#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1242#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1269#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1282#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1343#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1335#L364-3 assume !(1 == ~d1_ev~0); 1332#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1305#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1306#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1326#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1340#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1250#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1251#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1348#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1327#L449 assume !(0 != start_simulation_~tmp~3#1); 1285#L432-2 [2024-10-13 17:43:47,055 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:47,055 INFO L85 PathProgramCache]: Analyzing trace with hash -2115080082, now seen corresponding path program 1 times [2024-10-13 17:43:47,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:47,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224039677] [2024-10-13 17:43:47,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:47,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:47,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:47,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:47,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:47,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [224039677] [2024-10-13 17:43:47,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [224039677] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:47,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:47,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-13 17:43:47,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984637865] [2024-10-13 17:43:47,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:47,125 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:47,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:47,126 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 5 times [2024-10-13 17:43:47,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:47,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280490621] [2024-10-13 17:43:47,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:47,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:47,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:47,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:47,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:47,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280490621] [2024-10-13 17:43:47,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280490621] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:47,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:47,170 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:43:47,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605512921] [2024-10-13 17:43:47,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:47,170 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:47,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:47,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:43:47,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:43:47,171 INFO L87 Difference]: Start difference. First operand 117 states and 179 transitions. cyclomatic complexity: 63 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:47,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:47,205 INFO L93 Difference]: Finished difference Result 117 states and 178 transitions. [2024-10-13 17:43:47,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 178 transitions. [2024-10-13 17:43:47,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:47,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 178 transitions. [2024-10-13 17:43:47,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-10-13 17:43:47,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-10-13 17:43:47,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 178 transitions. [2024-10-13 17:43:47,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:43:47,209 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2024-10-13 17:43:47,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 178 transitions. [2024-10-13 17:43:47,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-10-13 17:43:47,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5213675213675213) internal successors, (178), 116 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:47,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 178 transitions. [2024-10-13 17:43:47,214 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2024-10-13 17:43:47,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:43:47,215 INFO L425 stractBuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2024-10-13 17:43:47,215 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-13 17:43:47,215 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 178 transitions. [2024-10-13 17:43:47,215 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:47,215 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:47,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:47,216 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:47,216 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:47,216 INFO L745 eck$LassoCheckResult]: Stem: 1523#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1576#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1564#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1565#L137-2 ~b0_req_up~0 := 0; 1592#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1596#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1525#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1526#L152-2 ~b1_req_up~0 := 0; 1498#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1499#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1505#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1506#L167-2 ~d0_req_up~0 := 0; 1520#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1546#L226-1 assume !(1 == ~d1_req_up~0); 1548#L233-1 assume !(1 == ~z_req_up~0); 1569#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1500#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1501#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1570#L321 assume !(0 == ~b0_ev~0); 1571#L321-2 assume !(0 == ~b1_ev~0); 1516#L326-1 assume !(0 == ~d0_ev~0); 1517#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1485#L336-1 assume !(0 == ~z_ev~0); 1486#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1595#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1509#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1579#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1580#L390 assume !(0 != activate_threads_~tmp~1#1); 1585#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1557#L354 assume !(1 == ~b0_ev~0); 1539#L354-2 assume !(1 == ~b1_ev~0); 1540#L359-1 assume !(1 == ~d0_ev~0); 1543#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1544#L369-1 assume !(1 == ~z_ev~0); 1550#L374-1 assume { :end_inline_reset_delta_events } true; 1531#L432-2 [2024-10-13 17:43:47,216 INFO L747 eck$LassoCheckResult]: Loop: 1531#L432-2 assume !false; 1532#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1483#L295 assume !false; 1484#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1513#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1514#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1494#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1495#L290 assume !(0 != eval_~tmp___0~0#1); 1584#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1582#L212-3 assume !(1 == ~b0_req_up~0); 1535#L212-5 assume !(1 == ~b1_req_up~0); 1542#L219-3 assume !(1 == ~d0_req_up~0); 1480#L226-3 assume !(1 == ~d1_req_up~0); 1481#L233-3 assume !(1 == ~z_req_up~0); 1502#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1503#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1566#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1567#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1553#L331-3 assume !(0 == ~d1_ev~0); 1492#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1493#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1504#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1522#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1549#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1487#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1488#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1515#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1528#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1589#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1581#L364-3 assume !(1 == ~d1_ev~0); 1578#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1551#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1552#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1572#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1586#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1496#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1497#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1594#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1573#L449 assume !(0 != start_simulation_~tmp~3#1); 1531#L432-2 [2024-10-13 17:43:47,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:47,219 INFO L85 PathProgramCache]: Analyzing trace with hash 2039338604, now seen corresponding path program 1 times [2024-10-13 17:43:47,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:47,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334751078] [2024-10-13 17:43:47,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:47,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:47,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:47,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:47,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:47,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334751078] [2024-10-13 17:43:47,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334751078] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:47,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:47,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:47,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325851174] [2024-10-13 17:43:47,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:47,258 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:47,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:47,258 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 6 times [2024-10-13 17:43:47,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:47,258 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315435161] [2024-10-13 17:43:47,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:47,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:47,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:47,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:47,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:47,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315435161] [2024-10-13 17:43:47,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315435161] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:47,292 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:47,292 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:43:47,292 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715989803] [2024-10-13 17:43:47,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:47,292 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:47,292 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:47,293 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:47,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:47,293 INFO L87 Difference]: Start difference. First operand 117 states and 178 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:47,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:47,300 INFO L93 Difference]: Finished difference Result 117 states and 177 transitions. [2024-10-13 17:43:47,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 177 transitions. [2024-10-13 17:43:47,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:47,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 177 transitions. [2024-10-13 17:43:47,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-10-13 17:43:47,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-10-13 17:43:47,302 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 177 transitions. [2024-10-13 17:43:47,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:43:47,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2024-10-13 17:43:47,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 177 transitions. [2024-10-13 17:43:47,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-10-13 17:43:47,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5128205128205128) internal successors, (177), 116 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:47,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 177 transitions. [2024-10-13 17:43:47,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2024-10-13 17:43:47,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:47,308 INFO L425 stractBuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2024-10-13 17:43:47,308 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-13 17:43:47,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 177 transitions. [2024-10-13 17:43:47,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-10-13 17:43:47,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:47,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:47,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:47,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:47,312 INFO L745 eck$LassoCheckResult]: Stem: 1766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1788#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1819#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1806#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1807#L137-2 ~b0_req_up~0 := 0; 1835#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1839#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1768#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1769#L152-2 ~b1_req_up~0 := 0; 1741#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1742#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1748#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1749#L167-2 ~d0_req_up~0 := 0; 1763#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1789#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 1790#L182 assume !(~d1_val~0 != ~d1_val_t~0); 1754#L182-2 ~d1_req_up~0 := 0; 1755#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 1810#L233-1 assume !(1 == ~z_req_up~0); 1812#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1743#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1744#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1813#L321 assume !(0 == ~b0_ev~0); 1814#L321-2 assume !(0 == ~b1_ev~0); 1759#L326-1 assume !(0 == ~d0_ev~0); 1760#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1728#L336-1 assume !(0 == ~z_ev~0); 1729#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1838#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1752#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1822#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1823#L390 assume !(0 != activate_threads_~tmp~1#1); 1828#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1799#L354 assume !(1 == ~b0_ev~0); 1782#L354-2 assume !(1 == ~b1_ev~0); 1783#L359-1 assume !(1 == ~d0_ev~0); 1786#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1787#L369-1 assume !(1 == ~z_ev~0); 1792#L374-1 assume { :end_inline_reset_delta_events } true; 1774#L432-2 [2024-10-13 17:43:47,313 INFO L747 eck$LassoCheckResult]: Loop: 1774#L432-2 assume !false; 1775#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1726#L295 assume !false; 1727#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1756#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1757#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1737#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1738#L290 assume !(0 != eval_~tmp___0~0#1); 1827#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1825#L212-3 assume !(1 == ~b0_req_up~0); 1778#L212-5 assume !(1 == ~b1_req_up~0); 1785#L219-3 assume !(1 == ~d0_req_up~0); 1723#L226-3 assume !(1 == ~d1_req_up~0); 1724#L233-3 assume !(1 == ~z_req_up~0); 1745#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1746#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1808#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1809#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1795#L331-3 assume !(0 == ~d1_ev~0); 1735#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1736#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1747#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1765#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1791#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1730#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1731#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1758#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1771#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1832#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1824#L364-3 assume !(1 == ~d1_ev~0); 1821#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1793#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1794#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1815#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1829#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1739#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1740#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1837#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1816#L449 assume !(0 != start_simulation_~tmp~3#1); 1774#L432-2 [2024-10-13 17:43:47,313 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:47,313 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 1 times [2024-10-13 17:43:47,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:47,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688011755] [2024-10-13 17:43:47,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:47,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:47,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:47,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:47,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:47,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688011755] [2024-10-13 17:43:47,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688011755] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:47,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:47,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-13 17:43:47,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890401492] [2024-10-13 17:43:47,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:47,353 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:47,353 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:47,353 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 7 times [2024-10-13 17:43:47,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:47,353 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206788151] [2024-10-13 17:43:47,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:47,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:47,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:47,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:47,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:47,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [206788151] [2024-10-13 17:43:47,386 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [206788151] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:47,386 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:47,386 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:43:47,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259881650] [2024-10-13 17:43:47,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:47,387 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:47,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:47,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:43:47,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:43:47,388 INFO L87 Difference]: Start difference. First operand 117 states and 177 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:47,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:47,410 INFO L93 Difference]: Finished difference Result 122 states and 182 transitions. [2024-10-13 17:43:47,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 182 transitions. [2024-10-13 17:43:47,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 76 [2024-10-13 17:43:47,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 122 states and 182 transitions. [2024-10-13 17:43:47,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122 [2024-10-13 17:43:47,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122 [2024-10-13 17:43:47,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122 states and 182 transitions. [2024-10-13 17:43:47,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:43:47,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122 states and 182 transitions. [2024-10-13 17:43:47,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states and 182 transitions. [2024-10-13 17:43:47,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 120. [2024-10-13 17:43:47,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.5) internal successors, (180), 119 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:47,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 180 transitions. [2024-10-13 17:43:47,417 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120 states and 180 transitions. [2024-10-13 17:43:47,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:43:47,419 INFO L425 stractBuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2024-10-13 17:43:47,419 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-13 17:43:47,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 180 transitions. [2024-10-13 17:43:47,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2024-10-13 17:43:47,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:47,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:47,421 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:47,421 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:47,421 INFO L745 eck$LassoCheckResult]: Stem: 2016#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 2017#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 2038#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2069#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 2056#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 2057#L137-2 ~b0_req_up~0 := 0; 2085#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 2089#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 2018#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 2019#L152-2 ~b1_req_up~0 := 0; 1990#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1991#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1997#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1998#L167-2 ~d0_req_up~0 := 0; 2013#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 2039#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 2040#L182 assume !(~d1_val~0 != ~d1_val_t~0); 2003#L182-2 ~d1_req_up~0 := 0; 2004#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 2060#L233-1 assume !(1 == ~z_req_up~0); 2062#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1992#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1993#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2063#L321 assume !(0 == ~b0_ev~0); 2064#L321-2 assume !(0 == ~b1_ev~0); 2009#L326-1 assume !(0 == ~d0_ev~0); 2010#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1977#L336-1 assume !(0 == ~z_ev~0); 1978#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2088#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2001#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2072#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2073#L390 assume !(0 != activate_threads_~tmp~1#1); 2078#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2049#L354 assume !(1 == ~b0_ev~0); 2032#L354-2 assume !(1 == ~b1_ev~0); 2033#L359-1 assume !(1 == ~d0_ev~0); 2036#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 2037#L369-1 assume !(1 == ~z_ev~0); 2042#L374-1 assume { :end_inline_reset_delta_events } true; 2024#L432-2 [2024-10-13 17:43:47,424 INFO L747 eck$LassoCheckResult]: Loop: 2024#L432-2 assume !false; 2025#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1975#L295 assume !false; 1976#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2005#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 2007#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2091#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2090#L290 assume !(0 != eval_~tmp___0~0#1); 2077#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2075#L212-3 assume !(1 == ~b0_req_up~0); 2028#L212-5 assume !(1 == ~b1_req_up~0); 2035#L219-3 assume !(1 == ~d0_req_up~0); 1972#L226-3 assume !(1 == ~d1_req_up~0); 1973#L233-3 assume !(1 == ~z_req_up~0); 1994#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1995#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 2058#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 2059#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 2045#L331-3 assume !(0 == ~d1_ev~0); 1984#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1985#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1996#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2015#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2041#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1979#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1980#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2008#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 2021#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 2082#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 2074#L364-3 assume !(1 == ~d1_ev~0); 2071#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 2043#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2044#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 2065#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2079#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1988#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1989#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2087#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 2066#L449 assume !(0 != start_simulation_~tmp~3#1); 2024#L432-2 [2024-10-13 17:43:47,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:47,424 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 2 times [2024-10-13 17:43:47,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:47,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331433221] [2024-10-13 17:43:47,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:47,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:47,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:47,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:47,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:47,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331433221] [2024-10-13 17:43:47,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1331433221] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:47,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:47,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-13 17:43:47,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327100254] [2024-10-13 17:43:47,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:47,461 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:47,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:47,461 INFO L85 PathProgramCache]: Analyzing trace with hash 356628037, now seen corresponding path program 1 times [2024-10-13 17:43:47,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:47,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872535337] [2024-10-13 17:43:47,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:47,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:47,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:47,469 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:47,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:47,490 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:47,746 INFO L204 LassoAnalysis]: Preferences: [2024-10-13 17:43:47,746 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-13 17:43:47,746 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-13 17:43:47,746 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-13 17:43:47,746 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-13 17:43:47,747 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:47,747 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-13 17:43:47,747 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-13 17:43:47,747 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2024-10-13 17:43:47,747 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-13 17:43:47,747 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-13 17:43:47,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,772 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,788 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,798 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,802 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,805 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,814 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,816 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,819 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:47,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,021 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-13 17:43:48,022 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-13 17:43:48,023 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,023 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:48,025 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:48,026 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-13 17:43:48,030 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:43:48,030 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:43:48,052 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:43:48,052 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~d1_ev~0=-8} Honda state: {~d1_ev~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:43:48,067 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-10-13 17:43:48,068 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,068 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:48,070 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:48,071 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-13 17:43:48,073 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:43:48,073 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:43:48,111 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-10-13 17:43:48,111 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,111 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:48,112 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:48,114 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-13 17:43:48,118 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-13 17:43:48,118 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:43:48,130 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-13 17:43:48,142 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-10-13 17:43:48,142 INFO L204 LassoAnalysis]: Preferences: [2024-10-13 17:43:48,142 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-13 17:43:48,142 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-13 17:43:48,142 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-13 17:43:48,142 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-13 17:43:48,142 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,142 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-13 17:43:48,142 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-13 17:43:48,143 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2024-10-13 17:43:48,143 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-13 17:43:48,143 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-13 17:43:48,144 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,150 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,153 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,155 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,166 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,168 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,170 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,174 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,177 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,179 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,181 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,182 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,184 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,185 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,188 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,193 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,198 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,202 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,206 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,207 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,209 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,211 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,213 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:48,385 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-13 17:43:48,390 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-13 17:43:48,391 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,391 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:48,396 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:48,398 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-13 17:43:48,399 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:43:48,410 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:43:48,411 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:43:48,411 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:43:48,411 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-13 17:43:48,411 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:43:48,414 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-13 17:43:48,415 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:43:48,417 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:43:48,433 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-10-13 17:43:48,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,437 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:48,438 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:48,445 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-10-13 17:43:48,446 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:43:48,456 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:43:48,456 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:43:48,456 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:43:48,457 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:43:48,457 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:43:48,458 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:43:48,458 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:43:48,461 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:43:48,472 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-10-13 17:43:48,472 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,472 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:48,473 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:48,474 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-10-13 17:43:48,477 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:43:48,486 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:43:48,487 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:43:48,487 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:43:48,487 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:43:48,487 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:43:48,487 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:43:48,487 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:43:48,490 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:43:48,506 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-10-13 17:43:48,508 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,508 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:48,509 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:48,510 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-10-13 17:43:48,511 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:43:48,521 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:43:48,521 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:43:48,521 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:43:48,521 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:43:48,521 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:43:48,523 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:43:48,523 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:43:48,525 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-13 17:43:48,527 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-13 17:43:48,527 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-13 17:43:48,528 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:48,528 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:48,529 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:48,531 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-10-13 17:43:48,531 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-13 17:43:48,532 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-13 17:43:48,532 INFO L474 LassoAnalysis]: Proved termination. [2024-10-13 17:43:48,532 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~b0_ev~0) = -1*~b0_ev~0 + 1 Supporting invariants [] [2024-10-13 17:43:48,544 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-10-13 17:43:48,547 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-13 17:43:48,564 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:48,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:48,592 INFO L255 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-13 17:43:48,593 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-13 17:43:48,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:48,659 INFO L255 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-13 17:43:48,660 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-13 17:43:48,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:48,779 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-10-13 17:43:48,781 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:48,839 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61. Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 274 states and 422 transitions. Complement of second has 5 states. [2024-10-13 17:43:48,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-13 17:43:48,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:48,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2024-10-13 17:43:48,844 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 39 letters. [2024-10-13 17:43:48,845 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:43:48,847 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 79 letters. Loop has 39 letters. [2024-10-13 17:43:48,847 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:43:48,847 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 78 letters. [2024-10-13 17:43:48,849 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:43:48,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 274 states and 422 transitions. [2024-10-13 17:43:48,854 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2024-10-13 17:43:48,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 274 states to 274 states and 422 transitions. [2024-10-13 17:43:48,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2024-10-13 17:43:48,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2024-10-13 17:43:48,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 274 states and 422 transitions. [2024-10-13 17:43:48,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:48,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 274 states and 422 transitions. [2024-10-13 17:43:48,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states and 422 transitions. [2024-10-13 17:43:48,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 271. [2024-10-13 17:43:48,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5387453874538746) internal successors, (417), 270 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:48,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 417 transitions. [2024-10-13 17:43:48,866 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 417 transitions. [2024-10-13 17:43:48,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:48,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:43:48,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:43:48,867 INFO L87 Difference]: Start difference. First operand 271 states and 417 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:48,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:48,894 INFO L93 Difference]: Finished difference Result 271 states and 416 transitions. [2024-10-13 17:43:48,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 416 transitions. [2024-10-13 17:43:48,896 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2024-10-13 17:43:48,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 416 transitions. [2024-10-13 17:43:48,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2024-10-13 17:43:48,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2024-10-13 17:43:48,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 416 transitions. [2024-10-13 17:43:48,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:48,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2024-10-13 17:43:48,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 416 transitions. [2024-10-13 17:43:48,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 271. [2024-10-13 17:43:48,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5350553505535056) internal successors, (416), 270 states have internal predecessors, (416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:48,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 416 transitions. [2024-10-13 17:43:48,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2024-10-13 17:43:48,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:43:48,904 INFO L425 stractBuchiCegarLoop]: Abstraction has 271 states and 416 transitions. [2024-10-13 17:43:48,904 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-13 17:43:48,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 416 transitions. [2024-10-13 17:43:48,905 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2024-10-13 17:43:48,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:48,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:48,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:48,905 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:48,906 INFO L745 eck$LassoCheckResult]: Stem: 3240#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3241#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3278#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3331#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3310#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3311#L137-2 ~b0_req_up~0 := 0; 3363#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 3370#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3242#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3243#L152-2 ~b1_req_up~0 := 0; 3202#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 3203#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3214#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3215#L167-2 ~d0_req_up~0 := 0; 3235#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 3281#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3282#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3225#L182-2 ~d1_req_up~0 := 0; 3226#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 3316#L233-1 assume !(1 == ~z_req_up~0); 3318#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3204#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3205#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3319#L321 assume !(0 == ~b0_ev~0); 3320#L321-2 assume !(0 == ~b1_ev~0); 3233#L326-1 assume !(0 == ~d0_ev~0); 3234#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3182#L336-1 assume !(0 == ~z_ev~0); 3183#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3369#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3217#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3339#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3340#L390 assume !(0 != activate_threads_~tmp~1#1); 3347#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3297#L354 assume !(1 == ~b0_ev~0); 3270#L354-2 assume !(1 == ~b1_ev~0); 3271#L359-1 assume !(1 == ~d0_ev~0); 3276#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3277#L369-1 assume !(1 == ~z_ev~0); 3283#L374-1 assume { :end_inline_reset_delta_events } true; 3352#L432-2 assume !false; 3255#L433 [2024-10-13 17:43:48,906 INFO L747 eck$LassoCheckResult]: Loop: 3255#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3401#L295 assume !false; 3399#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3397#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3396#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3394#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3392#L290 assume !(0 != eval_~tmp___0~0#1); 3391#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3341#L212-3 assume !(1 == ~b0_req_up~0); 3261#L212-5 assume !(1 == ~b1_req_up~0); 3273#L219-3 assume !(1 == ~d0_req_up~0); 3168#L226-3 assume !(1 == ~d1_req_up~0); 3169#L233-3 assume !(1 == ~z_req_up~0); 3206#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3207#L321-3 assume !(0 == ~b0_ev~0); 3312#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 3313#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 3288#L331-3 assume !(0 == ~d1_ev~0); 3184#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 3185#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3210#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3237#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3279#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3404#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 3403#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3244#L354-3 assume !(1 == ~b0_ev~0); 3245#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 3353#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3337#L364-3 assume !(1 == ~d1_ev~0); 3334#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 3284#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3285#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3321#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3348#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3198#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3199#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3367#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3323#L449 assume !(0 != start_simulation_~tmp~3#1); 3254#L432-2 assume !false; 3255#L433 [2024-10-13 17:43:48,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:48,907 INFO L85 PathProgramCache]: Analyzing trace with hash 750743388, now seen corresponding path program 1 times [2024-10-13 17:43:48,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:48,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238374033] [2024-10-13 17:43:48,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:48,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:48,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:48,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:48,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:48,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [238374033] [2024-10-13 17:43:48,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [238374033] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:48,946 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:48,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:48,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1405333444] [2024-10-13 17:43:48,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:48,947 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:48,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:48,951 INFO L85 PathProgramCache]: Analyzing trace with hash 618560829, now seen corresponding path program 1 times [2024-10-13 17:43:48,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:48,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694240353] [2024-10-13 17:43:48,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:48,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:48,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:48,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:48,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:48,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694240353] [2024-10-13 17:43:48,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694240353] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:48,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:48,981 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:48,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190139281] [2024-10-13 17:43:48,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:48,981 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:48,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:48,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:48,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:48,982 INFO L87 Difference]: Start difference. First operand 271 states and 416 transitions. cyclomatic complexity: 148 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:49,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:49,006 INFO L93 Difference]: Finished difference Result 313 states and 475 transitions. [2024-10-13 17:43:49,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 313 states and 475 transitions. [2024-10-13 17:43:49,008 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 159 [2024-10-13 17:43:49,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 313 states to 303 states and 459 transitions. [2024-10-13 17:43:49,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2024-10-13 17:43:49,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2024-10-13 17:43:49,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 459 transitions. [2024-10-13 17:43:49,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:49,011 INFO L218 hiAutomatonCegarLoop]: Abstraction has 303 states and 459 transitions. [2024-10-13 17:43:49,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 459 transitions. [2024-10-13 17:43:49,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2024-10-13 17:43:49,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303 states, 303 states have (on average 1.5148514851485149) internal successors, (459), 302 states have internal predecessors, (459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:49,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 459 transitions. [2024-10-13 17:43:49,018 INFO L240 hiAutomatonCegarLoop]: Abstraction has 303 states and 459 transitions. [2024-10-13 17:43:49,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:49,019 INFO L425 stractBuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2024-10-13 17:43:49,019 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-13 17:43:49,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 459 transitions. [2024-10-13 17:43:49,021 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 159 [2024-10-13 17:43:49,022 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:49,022 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:49,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:49,022 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:49,023 INFO L745 eck$LassoCheckResult]: Stem: 3832#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3833#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3924#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3900#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3901#L137-2 ~b0_req_up~0 := 0; 3965#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 3977#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3834#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3835#L152-2 ~b1_req_up~0 := 0; 3793#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 3794#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3805#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3806#L167-2 ~d0_req_up~0 := 0; 3827#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 3873#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3874#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3816#L182-2 ~d1_req_up~0 := 0; 3817#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 3906#L233-1 assume !(1 == ~z_req_up~0); 3908#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3799#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3800#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3909#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 3910#L321-2 assume !(0 == ~b1_ev~0); 3825#L326-1 assume !(0 == ~d0_ev~0); 3826#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3773#L336-1 assume !(0 == ~z_ev~0); 3774#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3972#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3963#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3935#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3936#L390 assume !(0 != activate_threads_~tmp~1#1); 3945#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3888#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 3864#L354-2 assume !(1 == ~b1_ev~0); 3865#L359-1 assume !(1 == ~d0_ev~0); 3866#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3867#L369-1 assume !(1 == ~z_ev~0); 3875#L374-1 assume { :end_inline_reset_delta_events } true; 3952#L432-2 assume !false; 3845#L433 [2024-10-13 17:43:49,026 INFO L747 eck$LassoCheckResult]: Loop: 3845#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3765#L295 assume !false; 3766#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3810#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3812#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 4004#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4005#L290 assume !(0 != eval_~tmp___0~0#1); 3942#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3943#L212-3 assume !(1 == ~b0_req_up~0); 4020#L212-5 assume !(1 == ~b1_req_up~0); 4017#L219-3 assume !(1 == ~d0_req_up~0); 4015#L226-3 assume !(1 == ~d1_req_up~0); 4012#L233-3 assume !(1 == ~z_req_up~0); 4011#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3930#L321-3 assume !(0 == ~b0_ev~0); 3931#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 4055#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 4054#L331-3 assume !(0 == ~d1_ev~0); 4053#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 4052#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 4051#L107-1 assume !(1 == ~b0_ev~0); 4048#L111-1 assume 1 == ~b1_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 4047#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 4046#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 4045#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 4044#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4043#L354-3 assume !(1 == ~b0_ev~0); 4042#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 4008#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 4041#L364-3 assume !(1 == ~d1_ev~0); 4040#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 4038#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 4037#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3973#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3946#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3789#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3790#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3976#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3915#L449 assume !(0 != start_simulation_~tmp~3#1); 3844#L432-2 assume !false; 3845#L433 [2024-10-13 17:43:49,026 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:49,026 INFO L85 PathProgramCache]: Analyzing trace with hash 969880732, now seen corresponding path program 1 times [2024-10-13 17:43:49,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:49,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176271127] [2024-10-13 17:43:49,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:49,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:49,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:49,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:49,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:49,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176271127] [2024-10-13 17:43:49,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1176271127] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:49,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:49,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:49,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723277074] [2024-10-13 17:43:49,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:49,057 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:49,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:49,060 INFO L85 PathProgramCache]: Analyzing trace with hash 571541896, now seen corresponding path program 1 times [2024-10-13 17:43:49,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:49,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808690711] [2024-10-13 17:43:49,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:49,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:49,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:49,074 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:49,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:49,082 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:49,301 INFO L204 LassoAnalysis]: Preferences: [2024-10-13 17:43:49,301 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-13 17:43:49,301 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-13 17:43:49,301 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-13 17:43:49,301 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-13 17:43:49,301 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:49,301 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-13 17:43:49,301 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-13 17:43:49,301 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration11_Loop [2024-10-13 17:43:49,302 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-13 17:43:49,302 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-13 17:43:49,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,310 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,313 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,315 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,320 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,323 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,327 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,342 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,348 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,350 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,351 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,353 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,357 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,359 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,363 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,368 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,369 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,517 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-10-13 17:43:49,552 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-13 17:43:49,553 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-13 17:43:49,553 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:49,553 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:49,558 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:49,559 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-10-13 17:43:49,564 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:43:49,564 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:43:49,602 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-10-13 17:43:49,602 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:49,602 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:49,603 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:49,605 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-10-13 17:43:49,607 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-13 17:43:49,607 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:43:49,620 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-13 17:43:49,632 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-10-13 17:43:49,633 INFO L204 LassoAnalysis]: Preferences: [2024-10-13 17:43:49,633 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-13 17:43:49,633 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-13 17:43:49,633 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-13 17:43:49,633 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-13 17:43:49,633 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:49,633 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-13 17:43:49,633 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-13 17:43:49,633 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration11_Loop [2024-10-13 17:43:49,633 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-13 17:43:49,633 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-13 17:43:49,635 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,651 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,661 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:43:49,866 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-13 17:43:49,866 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-13 17:43:49,866 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:49,866 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:49,874 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:49,875 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-10-13 17:43:49,876 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:43:49,886 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:43:49,886 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:43:49,887 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:43:49,887 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:43:49,887 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:43:49,887 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:43:49,887 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:43:49,890 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:43:49,903 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-10-13 17:43:49,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:49,903 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:49,907 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:49,908 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-10-13 17:43:49,908 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:43:49,918 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:43:49,918 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:43:49,918 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:43:49,918 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:43:49,919 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:43:49,920 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:43:49,920 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:43:49,922 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-13 17:43:49,924 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-13 17:43:49,924 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-13 17:43:49,925 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:43:49,925 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:43:49,927 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:43:49,932 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-10-13 17:43:49,933 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-13 17:43:49,933 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-13 17:43:49,933 INFO L474 LassoAnalysis]: Proved termination. [2024-10-13 17:43:49,933 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d0_ev~0) = -1*~d0_ev~0 + 1 Supporting invariants [] [2024-10-13 17:43:49,947 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-10-13 17:43:49,948 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-13 17:43:49,961 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:49,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:49,987 INFO L255 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-13 17:43:49,987 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-13 17:43:50,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:50,035 INFO L255 TraceCheckSpWp]: Trace formula consists of 85 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-13 17:43:50,036 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-13 17:43:50,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:50,115 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-10-13 17:43:50,115 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 303 states and 459 transitions. cyclomatic complexity: 159 Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,145 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 303 states and 459 transitions. cyclomatic complexity: 159. Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 810 states and 1251 transitions. Complement of second has 5 states. [2024-10-13 17:43:50,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-13 17:43:50,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2024-10-13 17:43:50,146 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 40 letters. [2024-10-13 17:43:50,146 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:43:50,146 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 81 letters. Loop has 40 letters. [2024-10-13 17:43:50,146 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:43:50,146 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 80 letters. [2024-10-13 17:43:50,147 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:43:50,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 810 states and 1251 transitions. [2024-10-13 17:43:50,150 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 318 [2024-10-13 17:43:50,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 810 states to 810 states and 1251 transitions. [2024-10-13 17:43:50,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 378 [2024-10-13 17:43:50,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2024-10-13 17:43:50,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 810 states and 1251 transitions. [2024-10-13 17:43:50,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:50,154 INFO L218 hiAutomatonCegarLoop]: Abstraction has 810 states and 1251 transitions. [2024-10-13 17:43:50,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 810 states and 1251 transitions. [2024-10-13 17:43:50,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 810 to 804. [2024-10-13 17:43:50,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 804 states, 804 states have (on average 1.5422885572139304) internal successors, (1240), 803 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 804 states to 804 states and 1240 transitions. [2024-10-13 17:43:50,163 INFO L240 hiAutomatonCegarLoop]: Abstraction has 804 states and 1240 transitions. [2024-10-13 17:43:50,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:50,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:50,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:50,164 INFO L87 Difference]: Start difference. First operand 804 states and 1240 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:50,184 INFO L93 Difference]: Finished difference Result 963 states and 1454 transitions. [2024-10-13 17:43:50,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 963 states and 1454 transitions. [2024-10-13 17:43:50,187 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 388 [2024-10-13 17:43:50,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 963 states to 963 states and 1454 transitions. [2024-10-13 17:43:50,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 448 [2024-10-13 17:43:50,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 448 [2024-10-13 17:43:50,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 963 states and 1454 transitions. [2024-10-13 17:43:50,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:50,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 963 states and 1454 transitions. [2024-10-13 17:43:50,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 963 states and 1454 transitions. [2024-10-13 17:43:50,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 963 to 963. [2024-10-13 17:43:50,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 963 states, 963 states have (on average 1.509865005192108) internal successors, (1454), 962 states have internal predecessors, (1454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1454 transitions. [2024-10-13 17:43:50,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 963 states and 1454 transitions. [2024-10-13 17:43:50,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:50,203 INFO L425 stractBuchiCegarLoop]: Abstraction has 963 states and 1454 transitions. [2024-10-13 17:43:50,203 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-13 17:43:50,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1454 transitions. [2024-10-13 17:43:50,206 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 388 [2024-10-13 17:43:50,207 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:50,207 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:50,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,207 INFO L745 eck$LassoCheckResult]: Stem: 6977#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 6978#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 7013#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7065#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 7045#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 7046#L137-2 ~b0_req_up~0 := 0; 7109#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 7121#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 6979#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 6980#L152-2 ~b1_req_up~0 := 0; 6936#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 6937#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 6948#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 6949#L167-2 ~d0_req_up~0 := 0; 6970#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 7016#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 7017#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 6959#L182-2 ~d1_req_up~0 := 0; 6960#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 7051#L233-1 assume !(1 == ~z_req_up~0); 7053#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6942#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 6943#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7054#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 7055#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 6968#L326-1 assume !(0 == ~d0_ev~0); 6969#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 6916#L336-1 assume !(0 == ~z_ev~0); 6917#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 7118#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 7119#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 7126#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 7125#L390 assume !(0 != activate_threads_~tmp~1#1); 7124#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7032#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 7009#L354-2 assume !(1 == ~b1_ev~0); 7010#L359-1 assume !(1 == ~d0_ev~0); 7011#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 7012#L369-1 assume !(1 == ~z_ev~0); 7018#L374-1 assume { :end_inline_reset_delta_events } true; 7090#L432-2 assume !false; 7338#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 7305#L295 [2024-10-13 17:43:50,208 INFO L747 eck$LassoCheckResult]: Loop: 7305#L295 assume !false; 7302#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 7296#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 7297#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 7331#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7321#L290 assume 0 != eval_~tmp___0~0#1; 7284#L290-1 assume !(0 == ~comp_m1_st~0); 7305#L295 [2024-10-13 17:43:50,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,208 INFO L85 PathProgramCache]: Analyzing trace with hash 1995676522, now seen corresponding path program 1 times [2024-10-13 17:43:50,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440494977] [2024-10-13 17:43:50,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:50,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:50,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:50,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440494977] [2024-10-13 17:43:50,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440494977] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:50,227 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:50,228 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:50,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099161974] [2024-10-13 17:43:50,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:50,228 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:50,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,228 INFO L85 PathProgramCache]: Analyzing trace with hash 829267516, now seen corresponding path program 1 times [2024-10-13 17:43:50,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523376643] [2024-10-13 17:43:50,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:50,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:50,240 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:50,240 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523376643] [2024-10-13 17:43:50,240 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1523376643] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:50,240 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:50,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:43:50,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168597633] [2024-10-13 17:43:50,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:50,240 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:43:50,241 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:50,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:50,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:50,241 INFO L87 Difference]: Start difference. First operand 963 states and 1454 transitions. cyclomatic complexity: 500 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:50,259 INFO L93 Difference]: Finished difference Result 1197 states and 1776 transitions. [2024-10-13 17:43:50,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1197 states and 1776 transitions. [2024-10-13 17:43:50,264 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 472 [2024-10-13 17:43:50,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1197 states to 1197 states and 1776 transitions. [2024-10-13 17:43:50,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 567 [2024-10-13 17:43:50,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 567 [2024-10-13 17:43:50,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1197 states and 1776 transitions. [2024-10-13 17:43:50,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:50,269 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1197 states and 1776 transitions. [2024-10-13 17:43:50,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1197 states and 1776 transitions. [2024-10-13 17:43:50,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1197 to 1197. [2024-10-13 17:43:50,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1197 states, 1197 states have (on average 1.4837092731829573) internal successors, (1776), 1196 states have internal predecessors, (1776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1197 states to 1197 states and 1776 transitions. [2024-10-13 17:43:50,282 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1197 states and 1776 transitions. [2024-10-13 17:43:50,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:50,283 INFO L425 stractBuchiCegarLoop]: Abstraction has 1197 states and 1776 transitions. [2024-10-13 17:43:50,283 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-13 17:43:50,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1197 states and 1776 transitions. [2024-10-13 17:43:50,286 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 472 [2024-10-13 17:43:50,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:50,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:50,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,287 INFO L745 eck$LassoCheckResult]: Stem: 9146#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 9147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 9187#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9244#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 9221#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 9222#L137-2 ~b0_req_up~0 := 0; 9295#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 9309#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 9148#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 9149#L152-2 ~b1_req_up~0 := 0; 9106#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 9107#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 9121#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 9122#L167-2 ~d0_req_up~0 := 0; 9141#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 9191#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 9192#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 9130#L182-2 ~d1_req_up~0 := 0; 9131#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 9227#L233-1 assume !(1 == ~z_req_up~0); 9229#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9112#L255 assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0; 9113#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9230#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 9231#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 9797#L326-1 assume !(0 == ~d0_ev~0); 9796#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 9795#L336-1 assume !(0 == ~z_ev~0); 9794#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 9793#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 9313#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 9792#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 9791#L390 assume !(0 != activate_threads_~tmp~1#1); 9267#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9756#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 9754#L354-2 assume !(1 == ~b1_ev~0); 9752#L359-1 assume !(1 == ~d0_ev~0); 9750#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 9748#L369-1 assume !(1 == ~z_ev~0); 9746#L374-1 assume { :end_inline_reset_delta_events } true; 9744#L432-2 assume !false; 9742#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 9743#L295 [2024-10-13 17:43:50,287 INFO L747 eck$LassoCheckResult]: Loop: 9743#L295 assume !false; 9906#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 9904#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 9475#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 9898#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9895#L290 assume 0 != eval_~tmp___0~0#1; 9893#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 9484#L299 assume !(0 != eval_~tmp~0#1); 9743#L295 [2024-10-13 17:43:50,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1572974696, now seen corresponding path program 1 times [2024-10-13 17:43:50,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819771378] [2024-10-13 17:43:50,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:50,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:50,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:50,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819771378] [2024-10-13 17:43:50,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1819771378] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:50,318 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:50,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-13 17:43:50,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227308587] [2024-10-13 17:43:50,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:50,319 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:50,319 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,319 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 1 times [2024-10-13 17:43:50,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,319 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033350538] [2024-10-13 17:43:50,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,322 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:50,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:50,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:50,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:43:50,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:43:50,341 INFO L87 Difference]: Start difference. First operand 1197 states and 1776 transitions. cyclomatic complexity: 588 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:50,362 INFO L93 Difference]: Finished difference Result 1174 states and 1739 transitions. [2024-10-13 17:43:50,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1174 states and 1739 transitions. [2024-10-13 17:43:50,366 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 472 [2024-10-13 17:43:50,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1174 states to 1174 states and 1739 transitions. [2024-10-13 17:43:50,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 544 [2024-10-13 17:43:50,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 544 [2024-10-13 17:43:50,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1174 states and 1739 transitions. [2024-10-13 17:43:50,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:50,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1174 states and 1739 transitions. [2024-10-13 17:43:50,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1174 states and 1739 transitions. [2024-10-13 17:43:50,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1174 to 1174. [2024-10-13 17:43:50,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1174 states, 1174 states have (on average 1.481260647359455) internal successors, (1739), 1173 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1174 states to 1174 states and 1739 transitions. [2024-10-13 17:43:50,412 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1174 states and 1739 transitions. [2024-10-13 17:43:50,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:43:50,421 INFO L425 stractBuchiCegarLoop]: Abstraction has 1174 states and 1739 transitions. [2024-10-13 17:43:50,421 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-13 17:43:50,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1174 states and 1739 transitions. [2024-10-13 17:43:50,427 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 472 [2024-10-13 17:43:50,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:50,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:50,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,431 INFO L745 eck$LassoCheckResult]: Stem: 11527#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 11528#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 11565#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11620#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 11600#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 11601#L137-2 ~b0_req_up~0 := 0; 11664#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 11676#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 11529#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 11530#L152-2 ~b1_req_up~0 := 0; 11485#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 11486#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 11496#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 11497#L167-2 ~d0_req_up~0 := 0; 11520#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 11566#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 11567#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 11505#L182-2 ~d1_req_up~0 := 0; 11506#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 11606#L233-1 assume !(1 == ~z_req_up~0); 11608#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11487#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 11488#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11609#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 11610#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 11629#L326-1 assume !(0 == ~d0_ev~0); 11521#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 11522#L336-1 assume !(0 == ~z_ev~0); 11678#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 11673#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 11660#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 11661#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 11637#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 11638#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11667#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 11557#L354-2 assume !(1 == ~b1_ev~0); 11558#L359-1 assume !(1 == ~d0_ev~0); 11563#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 11564#L369-1 assume !(1 == ~z_ev~0); 11642#L374-1 assume { :end_inline_reset_delta_events } true; 11643#L432-2 assume !false; 12086#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 11551#L295 [2024-10-13 17:43:50,431 INFO L747 eck$LassoCheckResult]: Loop: 11551#L295 assume !false; 12297#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 12295#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 12059#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 12293#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11674#L290 assume 0 != eval_~tmp___0~0#1; 11665#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 11550#L299 assume !(0 != eval_~tmp~0#1); 11551#L295 [2024-10-13 17:43:50,431 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,432 INFO L85 PathProgramCache]: Analyzing trace with hash -1906263764, now seen corresponding path program 1 times [2024-10-13 17:43:50,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12089916] [2024-10-13 17:43:50,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,431 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-10-13 17:43:50,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:50,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:50,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:50,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12089916] [2024-10-13 17:43:50,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12089916] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:50,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:50,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:50,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852915056] [2024-10-13 17:43:50,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:50,464 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:50,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,465 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 2 times [2024-10-13 17:43:50,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592220373] [2024-10-13 17:43:50,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,467 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:50,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,469 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:50,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:50,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:50,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:50,497 INFO L87 Difference]: Start difference. First operand 1174 states and 1739 transitions. cyclomatic complexity: 574 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:50,523 INFO L93 Difference]: Finished difference Result 1261 states and 1857 transitions. [2024-10-13 17:43:50,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1261 states and 1857 transitions. [2024-10-13 17:43:50,528 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 529 [2024-10-13 17:43:50,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1261 states to 1261 states and 1857 transitions. [2024-10-13 17:43:50,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 601 [2024-10-13 17:43:50,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 601 [2024-10-13 17:43:50,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1261 states and 1857 transitions. [2024-10-13 17:43:50,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:50,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1261 states and 1857 transitions. [2024-10-13 17:43:50,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1261 states and 1857 transitions. [2024-10-13 17:43:50,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1261 to 1261. [2024-10-13 17:43:50,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1261 states, 1261 states have (on average 1.4726407613005552) internal successors, (1857), 1260 states have internal predecessors, (1857), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1261 states to 1261 states and 1857 transitions. [2024-10-13 17:43:50,546 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1261 states and 1857 transitions. [2024-10-13 17:43:50,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:50,547 INFO L425 stractBuchiCegarLoop]: Abstraction has 1261 states and 1857 transitions. [2024-10-13 17:43:50,547 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-13 17:43:50,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1261 states and 1857 transitions. [2024-10-13 17:43:50,550 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 529 [2024-10-13 17:43:50,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:50,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:50,551 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,551 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,551 INFO L745 eck$LassoCheckResult]: Stem: 13969#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 13970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 14008#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14070#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 14041#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 14042#L137-2 ~b0_req_up~0 := 0; 14120#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 14133#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 13971#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 13972#L152-2 ~b1_req_up~0 := 0; 13926#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 13927#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 13937#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 13938#L167-2 ~d0_req_up~0 := 0; 13962#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 14009#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 14010#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 13946#L182-2 ~d1_req_up~0 := 0; 13947#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 14047#L233-1 assume !(1 == ~z_req_up~0); 14049#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13928#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 13929#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14050#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 14051#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 14080#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 13963#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 13964#L336-1 assume !(0 == ~z_ev~0); 14137#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 14127#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 14117#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 14118#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 14092#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 14093#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14027#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 14000#L354-2 assume !(1 == ~b1_ev~0); 14001#L359-1 assume !(1 == ~d0_ev~0); 14006#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 14007#L369-1 assume !(1 == ~z_ev~0); 14014#L374-1 assume { :end_inline_reset_delta_events } true; 14098#L432-2 assume !false; 14622#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 14573#L295 [2024-10-13 17:43:50,551 INFO L747 eck$LassoCheckResult]: Loop: 14573#L295 assume !false; 14584#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 14582#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 14248#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 14579#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14577#L290 assume 0 != eval_~tmp___0~0#1; 14574#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 14260#L299 assume !(0 != eval_~tmp~0#1); 14573#L295 [2024-10-13 17:43:50,552 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,552 INFO L85 PathProgramCache]: Analyzing trace with hash -317915862, now seen corresponding path program 1 times [2024-10-13 17:43:50,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749506093] [2024-10-13 17:43:50,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:50,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:50,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:50,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749506093] [2024-10-13 17:43:50,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749506093] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:50,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:50,575 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:50,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324099234] [2024-10-13 17:43:50,575 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:50,576 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:50,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,576 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 3 times [2024-10-13 17:43:50,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313597744] [2024-10-13 17:43:50,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,578 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:50,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,580 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:50,613 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:50,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:50,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:50,614 INFO L87 Difference]: Start difference. First operand 1261 states and 1857 transitions. cyclomatic complexity: 605 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:50,652 INFO L93 Difference]: Finished difference Result 1482 states and 2167 transitions. [2024-10-13 17:43:50,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1482 states and 2167 transitions. [2024-10-13 17:43:50,658 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 616 [2024-10-13 17:43:50,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1482 states to 1482 states and 2167 transitions. [2024-10-13 17:43:50,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2024-10-13 17:43:50,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2024-10-13 17:43:50,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1482 states and 2167 transitions. [2024-10-13 17:43:50,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:50,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1482 states and 2167 transitions. [2024-10-13 17:43:50,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1482 states and 2167 transitions. [2024-10-13 17:43:50,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1482 to 1482. [2024-10-13 17:43:50,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1482 states, 1482 states have (on average 1.4622132253711202) internal successors, (2167), 1481 states have internal predecessors, (2167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1482 states to 1482 states and 2167 transitions. [2024-10-13 17:43:50,676 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1482 states and 2167 transitions. [2024-10-13 17:43:50,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:50,678 INFO L425 stractBuchiCegarLoop]: Abstraction has 1482 states and 2167 transitions. [2024-10-13 17:43:50,678 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-13 17:43:50,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1482 states and 2167 transitions. [2024-10-13 17:43:50,682 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 616 [2024-10-13 17:43:50,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:50,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:50,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,683 INFO L745 eck$LassoCheckResult]: Stem: 16716#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 16717#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 16754#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16814#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 16789#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 16790#L137-2 ~b0_req_up~0 := 0; 16871#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 16888#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 16718#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 16719#L152-2 ~b1_req_up~0 := 0; 16675#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 16676#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 16689#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 16690#L167-2 ~d0_req_up~0 := 0; 16709#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 16755#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 16756#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 16697#L182-2 ~d1_req_up~0 := 0; 16698#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 16795#L233-1 assume !(1 == ~z_req_up~0); 16797#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16681#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 16682#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16798#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 16799#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 16707#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 16708#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 16649#L336-1 assume !(0 == ~z_ev~0); 16650#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 16882#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 16865#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 16866#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 16835#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 16836#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16875#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 16750#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 16751#L359-1 assume !(1 == ~d0_ev~0); 16752#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 16753#L369-1 assume !(1 == ~z_ev~0); 16846#L374-1 assume { :end_inline_reset_delta_events } true; 16847#L432-2 assume !false; 17016#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 17017#L295 [2024-10-13 17:43:50,683 INFO L747 eck$LassoCheckResult]: Loop: 17017#L295 assume !false; 17845#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 17843#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 17701#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 17770#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17771#L290 assume 0 != eval_~tmp___0~0#1; 16872#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 16873#L299 assume !(0 != eval_~tmp~0#1); 17017#L295 [2024-10-13 17:43:50,683 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,683 INFO L85 PathProgramCache]: Analyzing trace with hash -2092923224, now seen corresponding path program 1 times [2024-10-13 17:43:50,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135789367] [2024-10-13 17:43:50,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:43:50,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:43:50,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:43:50,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135789367] [2024-10-13 17:43:50,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135789367] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:43:50,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:43:50,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:43:50,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233065472] [2024-10-13 17:43:50,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:43:50,708 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:43:50,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,708 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 4 times [2024-10-13 17:43:50,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560890703] [2024-10-13 17:43:50,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,710 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:50,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,712 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:50,741 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:43:50,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:43:50,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:43:50,742 INFO L87 Difference]: Start difference. First operand 1482 states and 2167 transitions. cyclomatic complexity: 694 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:43:50,761 INFO L93 Difference]: Finished difference Result 1887 states and 2721 transitions. [2024-10-13 17:43:50,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1887 states and 2721 transitions. [2024-10-13 17:43:50,767 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 700 [2024-10-13 17:43:50,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1887 states to 1756 states and 2524 transitions. [2024-10-13 17:43:50,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 772 [2024-10-13 17:43:50,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 772 [2024-10-13 17:43:50,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1756 states and 2524 transitions. [2024-10-13 17:43:50,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:43:50,772 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1756 states and 2524 transitions. [2024-10-13 17:43:50,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1756 states and 2524 transitions. [2024-10-13 17:43:50,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1756 to 1756. [2024-10-13 17:43:50,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1756 states, 1756 states have (on average 1.4373576309794989) internal successors, (2524), 1755 states have internal predecessors, (2524), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:43:50,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1756 states to 1756 states and 2524 transitions. [2024-10-13 17:43:50,787 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1756 states and 2524 transitions. [2024-10-13 17:43:50,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:43:50,788 INFO L425 stractBuchiCegarLoop]: Abstraction has 1756 states and 2524 transitions. [2024-10-13 17:43:50,788 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-13 17:43:50,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1756 states and 2524 transitions. [2024-10-13 17:43:50,791 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 700 [2024-10-13 17:43:50,791 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:43:50,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:43:50,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,791 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:43:50,792 INFO L745 eck$LassoCheckResult]: Stem: 20091#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 20092#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 20129#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20192#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 20168#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 20169#L137-2 ~b0_req_up~0 := 0; 20248#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 20260#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 20093#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 20094#L152-2 ~b1_req_up~0 := 0; 20050#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 20051#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 20060#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 20061#L167-2 ~d0_req_up~0 := 0; 20084#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 20130#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 20131#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 20068#L182-2 ~d1_req_up~0 := 0; 20069#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 20174#L233-1 assume !(1 == ~z_req_up~0); 20176#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20052#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 20053#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20177#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 20178#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 20202#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 20085#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 20086#L336-1 assume !(0 == ~z_ev~0); 20263#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 20256#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 20257#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 20198#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 20199#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 20214#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20252#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 20121#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 20122#L359-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 20127#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 20128#L369-1 assume !(1 == ~z_ev~0); 20220#L374-1 assume { :end_inline_reset_delta_events } true; 20221#L432-2 assume !false; 21001#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 20755#L295 [2024-10-13 17:43:50,792 INFO L747 eck$LassoCheckResult]: Loop: 20755#L295 assume !false; 20763#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 20760#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 20747#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 20757#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20756#L290 assume 0 != eval_~tmp___0~0#1; 20438#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 20413#L299 assume !(0 != eval_~tmp~0#1); 20755#L295 [2024-10-13 17:43:50,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,792 INFO L85 PathProgramCache]: Analyzing trace with hash 2144785770, now seen corresponding path program 1 times [2024-10-13 17:43:50,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997502967] [2024-10-13 17:43:50,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,797 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:50,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,804 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:50,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,805 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 5 times [2024-10-13 17:43:50,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198173878] [2024-10-13 17:43:50,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,807 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:50,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,808 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:50,809 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:43:50,809 INFO L85 PathProgramCache]: Analyzing trace with hash 109674101, now seen corresponding path program 1 times [2024-10-13 17:43:50,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:43:50,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309397749] [2024-10-13 17:43:50,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:43:50,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:43:50,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,813 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:50,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:50,819 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:43:51,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:51,628 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:43:51,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:43:51,713 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.10 05:43:51 BoogieIcfgContainer [2024-10-13 17:43:51,713 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-10-13 17:43:51,713 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-10-13 17:43:51,713 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-10-13 17:43:51,713 INFO L274 PluginConnector]: Witness Printer initialized [2024-10-13 17:43:51,714 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:43:45" (3/4) ... [2024-10-13 17:43:51,715 INFO L136 WitnessPrinter]: Generating witness for non-termination counterexample [2024-10-13 17:43:51,758 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-10-13 17:43:51,758 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-10-13 17:43:51,758 INFO L158 Benchmark]: Toolchain (without parser) took 6646.93ms. Allocated memory was 148.9MB in the beginning and 285.2MB in the end (delta: 136.3MB). Free memory was 116.1MB in the beginning and 124.3MB in the end (delta: -8.2MB). Peak memory consumption was 130.2MB. Max. memory is 16.1GB. [2024-10-13 17:43:51,759 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 148.9MB. Free memory is still 106.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-10-13 17:43:51,759 INFO L158 Benchmark]: CACSL2BoogieTranslator took 250.13ms. Allocated memory is still 148.9MB. Free memory was 116.1MB in the beginning and 100.5MB in the end (delta: 15.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-10-13 17:43:51,759 INFO L158 Benchmark]: Boogie Procedure Inliner took 32.00ms. Allocated memory is still 148.9MB. Free memory was 100.5MB in the beginning and 97.9MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-10-13 17:43:51,759 INFO L158 Benchmark]: Boogie Preprocessor took 36.84ms. Allocated memory is still 148.9MB. Free memory was 97.9MB in the beginning and 95.3MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-10-13 17:43:51,759 INFO L158 Benchmark]: RCFGBuilder took 460.65ms. Allocated memory is still 148.9MB. Free memory was 95.3MB in the beginning and 71.1MB in the end (delta: 24.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-10-13 17:43:51,759 INFO L158 Benchmark]: BuchiAutomizer took 5817.65ms. Allocated memory was 148.9MB in the beginning and 285.2MB in the end (delta: 136.3MB). Free memory was 71.1MB in the beginning and 130.6MB in the end (delta: -59.5MB). Peak memory consumption was 77.8MB. Max. memory is 16.1GB. [2024-10-13 17:43:51,759 INFO L158 Benchmark]: Witness Printer took 45.00ms. Allocated memory is still 285.2MB. Free memory was 130.6MB in the beginning and 124.3MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-10-13 17:43:51,760 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 148.9MB. Free memory is still 106.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 250.13ms. Allocated memory is still 148.9MB. Free memory was 116.1MB in the beginning and 100.5MB in the end (delta: 15.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 32.00ms. Allocated memory is still 148.9MB. Free memory was 100.5MB in the beginning and 97.9MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 36.84ms. Allocated memory is still 148.9MB. Free memory was 97.9MB in the beginning and 95.3MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 460.65ms. Allocated memory is still 148.9MB. Free memory was 95.3MB in the beginning and 71.1MB in the end (delta: 24.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 5817.65ms. Allocated memory was 148.9MB in the beginning and 285.2MB in the end (delta: 136.3MB). Free memory was 71.1MB in the beginning and 130.6MB in the end (delta: -59.5MB). Peak memory consumption was 77.8MB. Max. memory is 16.1GB. * Witness Printer took 45.00ms. Allocated memory is still 285.2MB. Free memory was 130.6MB in the beginning and 124.3MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (16 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * b0_ev) + 1) and consists of 3 locations. One deterministic module has affine ranking function (((long long) -1 * d0_ev) + 1) and consists of 3 locations. 16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1756 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.7s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 4.2s. Construction of modules took 0.2s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 10. Automata minimization 0.2s AutomataMinimizationTime, 18 MinimizatonAttempts, 11 StatesRemovedByMinimization, 3 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 742 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 740 mSDsluCounter, 6929 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3745 mSDsCounter, 48 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 231 IncrementalHoareTripleChecker+Invalid, 279 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 48 mSolverCounterUnsat, 3184 mSDtfsCounter, 231 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN4 SILU0 SILI10 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital62 mio100 ax100 hnf100 lsp16 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 27ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 1 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-10-13 17:43:51,783 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)