./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a046e57d Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-mul-div-a046e57-m [2024-10-13 17:44:52,627 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-13 17:44:52,680 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-13 17:44:52,685 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-13 17:44:52,686 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-13 17:44:52,719 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-13 17:44:52,721 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-13 17:44:52,722 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-13 17:44:52,722 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-13 17:44:52,723 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-13 17:44:52,723 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-13 17:44:52,723 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-13 17:44:52,724 INFO L153 SettingsManager]: * Use SBE=true [2024-10-13 17:44:52,725 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-13 17:44:52,726 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-13 17:44:52,726 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-13 17:44:52,726 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-13 17:44:52,726 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-13 17:44:52,726 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-13 17:44:52,727 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-13 17:44:52,727 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-13 17:44:52,728 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-13 17:44:52,729 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-13 17:44:52,730 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-13 17:44:52,730 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-13 17:44:52,731 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-13 17:44:52,731 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-13 17:44:52,731 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-13 17:44:52,731 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-13 17:44:52,731 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-13 17:44:52,731 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-13 17:44:52,732 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-13 17:44:52,732 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-13 17:44:52,732 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-13 17:44:52,732 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-13 17:44:52,732 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-13 17:44:52,732 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-13 17:44:52,732 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-13 17:44:52,733 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-13 17:44:52,733 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 [2024-10-13 17:44:52,956 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-13 17:44:52,972 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-13 17:44:52,977 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-13 17:44:52,978 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-13 17:44:52,979 INFO L274 PluginConnector]: CDTParser initialized [2024-10-13 17:44:52,980 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2024-10-13 17:44:54,145 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-13 17:44:54,330 INFO L384 CDTParser]: Found 1 translation units. [2024-10-13 17:44:54,331 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2024-10-13 17:44:54,339 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a9a86e2b4/131f50002cbd4f708016de8b2ac28c8a/FLAG508df3589 [2024-10-13 17:44:54,725 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a9a86e2b4/131f50002cbd4f708016de8b2ac28c8a [2024-10-13 17:44:54,728 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-13 17:44:54,729 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-13 17:44:54,729 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-13 17:44:54,729 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-13 17:44:54,735 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-13 17:44:54,736 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:44:54" (1/1) ... [2024-10-13 17:44:54,737 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7975d004 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:54, skipping insertion in model container [2024-10-13 17:44:54,738 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:44:54" (1/1) ... [2024-10-13 17:44:54,770 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-13 17:44:55,003 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:44:55,014 INFO L200 MainTranslator]: Completed pre-run [2024-10-13 17:44:55,067 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:44:55,084 INFO L204 MainTranslator]: Completed translation [2024-10-13 17:44:55,084 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55 WrapperNode [2024-10-13 17:44:55,085 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-13 17:44:55,085 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-13 17:44:55,085 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-13 17:44:55,085 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-13 17:44:55,090 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,098 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,141 INFO L138 Inliner]: procedures = 46, calls = 60, calls flagged for inlining = 55, calls inlined = 185, statements flattened = 2792 [2024-10-13 17:44:55,141 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-13 17:44:55,142 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-13 17:44:55,142 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-13 17:44:55,142 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-13 17:44:55,155 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,156 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,172 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,205 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-13 17:44:55,205 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,205 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,229 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,250 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,254 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,264 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,273 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-13 17:44:55,274 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-13 17:44:55,274 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-13 17:44:55,274 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-13 17:44:55,275 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (1/1) ... [2024-10-13 17:44:55,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:44:55,288 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:44:55,302 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:44:55,304 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-13 17:44:55,342 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-13 17:44:55,342 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-13 17:44:55,343 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-13 17:44:55,343 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-13 17:44:55,438 INFO L238 CfgBuilder]: Building ICFG [2024-10-13 17:44:55,440 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-13 17:44:56,923 INFO L? ?]: Removed 568 outVars from TransFormulas that were not future-live. [2024-10-13 17:44:56,924 INFO L287 CfgBuilder]: Performing block encoding [2024-10-13 17:44:56,959 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-13 17:44:56,962 INFO L314 CfgBuilder]: Removed 12 assume(true) statements. [2024-10-13 17:44:56,962 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:44:56 BoogieIcfgContainer [2024-10-13 17:44:56,962 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-13 17:44:56,963 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-13 17:44:56,963 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-13 17:44:56,966 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-13 17:44:56,966 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:44:56,967 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 05:44:54" (1/3) ... [2024-10-13 17:44:56,968 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@28e86390 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:44:56, skipping insertion in model container [2024-10-13 17:44:56,968 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:44:56,968 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:44:55" (2/3) ... [2024-10-13 17:44:56,969 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@28e86390 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:44:56, skipping insertion in model container [2024-10-13 17:44:56,969 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:44:56,969 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:44:56" (3/3) ... [2024-10-13 17:44:56,970 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-2.c [2024-10-13 17:44:57,027 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-13 17:44:57,027 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-13 17:44:57,027 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-13 17:44:57,028 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-13 17:44:57,028 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-13 17:44:57,028 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-13 17:44:57,028 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-13 17:44:57,028 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-13 17:44:57,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:57,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1064 [2024-10-13 17:44:57,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:57,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:57,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:57,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:57,111 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-13 17:44:57,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:57,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1064 [2024-10-13 17:44:57,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:57,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:57,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:57,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:57,142 INFO L745 eck$LassoCheckResult]: Stem: 181#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1095#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 882#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1093#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 521#L670true assume !(1 == ~m_i~0);~m_st~0 := 2; 305#L670-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 841#L675-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 926#L680-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1032#L685-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 906#L690-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1182#L695-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 397#L700-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L705-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 538#L710-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 255#L715-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 779#L951true assume !(0 == ~M_E~0); 112#L951-2true assume !(0 == ~T1_E~0); 194#L956-1true assume !(0 == ~T2_E~0); 1151#L961-1true assume !(0 == ~T3_E~0); 537#L966-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 657#L971-1true assume !(0 == ~T5_E~0); 1084#L976-1true assume !(0 == ~T6_E~0); 632#L981-1true assume !(0 == ~T7_E~0); 422#L986-1true assume !(0 == ~T8_E~0); 224#L991-1true assume !(0 == ~T9_E~0); 1125#L996-1true assume !(0 == ~E_M~0); 1004#L1001-1true assume !(0 == ~E_1~0); 585#L1006-1true assume 0 == ~E_2~0;~E_2~0 := 1; 927#L1011-1true assume !(0 == ~E_3~0); 962#L1016-1true assume !(0 == ~E_4~0); 1097#L1021-1true assume !(0 == ~E_5~0); 17#L1026-1true assume !(0 == ~E_6~0); 1161#L1031-1true assume !(0 == ~E_7~0); 545#L1036-1true assume !(0 == ~E_8~0); 542#L1041-1true assume !(0 == ~E_9~0); 853#L1046-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1086#L472true assume 1 == ~m_pc~0; 1041#L473true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 568#L483true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 754#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 578#L1179true assume !(0 != activate_threads_~tmp~1#1); 21#L1179-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 898#L491true assume 1 == ~t1_pc~0; 584#L492true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 644#L502true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9#L1187true assume !(0 != activate_threads_~tmp___0~0#1); 18#L1187-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 835#L510true assume !(1 == ~t2_pc~0); 4#L510-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1001#L521true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 298#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1160#L1195true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 137#L1195-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428#L529true assume 1 == ~t3_pc~0; 361#L530true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 769#L540true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1075#L1203true assume !(0 != activate_threads_~tmp___2~0#1); 100#L1203-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1126#L548true assume !(1 == ~t4_pc~0); 315#L548-2true is_transmit4_triggered_~__retres1~4#1 := 0; 201#L559true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67#L1211true assume !(0 != activate_threads_~tmp___3~0#1); 642#L1211-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45#L567true assume 1 == ~t5_pc~0; 894#L568true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1100#L578true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 756#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030#L1219true assume !(0 != activate_threads_~tmp___4~0#1); 831#L1219-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105#L586true assume !(1 == ~t6_pc~0); 139#L586-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1027#L597true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 289#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1186#L1227true assume !(0 != activate_threads_~tmp___5~0#1); 824#L1227-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1123#L605true assume 1 == ~t7_pc~0; 761#L606true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 570#L616true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1116#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1107#L1235true assume !(0 != activate_threads_~tmp___6~0#1); 1096#L1235-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 514#L624true assume !(1 == ~t8_pc~0); 1060#L624-2true is_transmit8_triggered_~__retres1~8#1 := 0; 619#L635true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 684#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 790#L1243true assume !(0 != activate_threads_~tmp___7~0#1); 1169#L1243-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29#L643true assume 1 == ~t9_pc~0; 861#L644true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 716#L654true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 336#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 227#L1251true assume !(0 != activate_threads_~tmp___8~0#1); 1122#L1251-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127#L1059true assume !(1 == ~M_E~0); 1189#L1059-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 212#L1064-1true assume !(1 == ~T2_E~0); 725#L1069-1true assume !(1 == ~T3_E~0); 1083#L1074-1true assume !(1 == ~T4_E~0); 786#L1079-1true assume !(1 == ~T5_E~0); 760#L1084-1true assume !(1 == ~T6_E~0); 935#L1089-1true assume !(1 == ~T7_E~0); 815#L1094-1true assume !(1 == ~T8_E~0); 450#L1099-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 951#L1104-1true assume !(1 == ~E_M~0); 623#L1109-1true assume !(1 == ~E_1~0); 299#L1114-1true assume !(1 == ~E_2~0); 1130#L1119-1true assume !(1 == ~E_3~0); 344#L1124-1true assume !(1 == ~E_4~0); 27#L1129-1true assume !(1 == ~E_5~0); 524#L1134-1true assume !(1 == ~E_6~0); 192#L1139-1true assume 1 == ~E_7~0;~E_7~0 := 2; 311#L1144-1true assume !(1 == ~E_8~0); 1173#L1149-1true assume !(1 == ~E_9~0); 108#L1154-1true assume { :end_inline_reset_delta_events } true; 174#L1440-2true [2024-10-13 17:44:57,143 INFO L747 eck$LassoCheckResult]: Loop: 174#L1440-2true assume !false; 987#L1441true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 876#L926-1true assume false; 690#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 457#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 246#L951-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1162#L951-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 673#L956-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 516#L961-3true assume !(0 == ~T3_E~0); 332#L966-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 946#L971-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 562#L976-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 39#L981-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 237#L986-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 28#L991-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 651#L996-3true assume 0 == ~E_M~0;~E_M~0 := 1; 783#L1001-3true assume !(0 == ~E_1~0); 310#L1006-3true assume 0 == ~E_2~0;~E_2~0 := 1; 681#L1011-3true assume 0 == ~E_3~0;~E_3~0 := 1; 923#L1016-3true assume 0 == ~E_4~0;~E_4~0 := 1; 734#L1021-3true assume 0 == ~E_5~0;~E_5~0 := 1; 462#L1026-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1078#L1031-3true assume 0 == ~E_7~0;~E_7~0 := 1; 648#L1036-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1137#L1041-3true assume !(0 == ~E_9~0); 720#L1046-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 671#L472-33true assume !(1 == ~m_pc~0); 79#L472-35true is_master_triggered_~__retres1~0#1 := 0; 932#L483-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 705#is_master_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 678#L1179-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 339#L1179-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1063#L491-33true assume 1 == ~t1_pc~0; 579#L492-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 982#L502-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1079#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1020#L1187-33true assume !(0 != activate_threads_~tmp___0~0#1); 1082#L1187-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 627#L510-33true assume 1 == ~t2_pc~0; 682#L511-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1006#L521-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 660#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 740#L1195-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2#L1195-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152#L529-33true assume !(1 == ~t3_pc~0); 208#L529-35true is_transmit3_triggered_~__retres1~3#1 := 0; 143#L540-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1028#L1203-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59#L1203-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183#L548-33true assume !(1 == ~t4_pc~0); 1181#L548-35true is_transmit4_triggered_~__retres1~4#1 := 0; 592#L559-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 940#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 281#L1211-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148#L1211-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 937#L567-33true assume 1 == ~t5_pc~0; 435#L568-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 367#L578-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1026#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1048#L1219-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1138#L1219-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 536#L586-33true assume 1 == ~t6_pc~0; 503#L587-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 572#L597-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 379#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1157#L1227-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 158#L1227-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 261#L605-33true assume !(1 == ~t7_pc~0); 555#L605-35true is_transmit7_triggered_~__retres1~7#1 := 0; 123#L616-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 775#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1127#L1235-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64#L1235-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 142#L624-33true assume !(1 == ~t8_pc~0); 146#L624-35true is_transmit8_triggered_~__retres1~8#1 := 0; 1057#L635-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 515#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 270#L1243-33true assume !(0 != activate_threads_~tmp___7~0#1); 1174#L1243-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124#L643-33true assume !(1 == ~t9_pc~0); 165#L643-35true is_transmit9_triggered_~__retres1~9#1 := 0; 484#L654-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 664#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 448#L1251-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 809#L1251-35true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60#L1059-3true assume !(1 == ~M_E~0); 352#L1059-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1184#L1064-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 394#L1069-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 633#L1074-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 886#L1079-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 546#L1084-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 483#L1089-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 595#L1094-3true assume !(1 == ~T8_E~0); 415#L1099-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 653#L1104-3true assume 1 == ~E_M~0;~E_M~0 := 2; 958#L1109-3true assume 1 == ~E_1~0;~E_1~0 := 2; 641#L1114-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1049#L1119-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1183#L1124-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1080#L1129-3true assume 1 == ~E_5~0;~E_5~0 := 2; 216#L1134-3true assume !(1 == ~E_6~0); 500#L1139-3true assume 1 == ~E_7~0;~E_7~0 := 2; 328#L1144-3true assume 1 == ~E_8~0;~E_8~0 := 2; 451#L1149-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1177#L1154-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1114#L728-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 751#L780-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 268#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12#L1459true assume !(0 == start_simulation_~tmp~3#1); 736#L1459-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 919#L728-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 552#L780-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 243#L1414true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 355#L1421true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 473#stop_simulation_returnLabel#1true start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 732#L1472true assume !(0 != start_simulation_~tmp___0~1#1); 174#L1440-2true [2024-10-13 17:44:57,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:57,155 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2024-10-13 17:44:57,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:57,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409936726] [2024-10-13 17:44:57,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:57,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:57,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:57,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:57,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:57,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409936726] [2024-10-13 17:44:57,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409936726] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:57,425 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:57,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:57,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807827815] [2024-10-13 17:44:57,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:57,431 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:57,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:57,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1748189105, now seen corresponding path program 1 times [2024-10-13 17:44:57,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:57,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25796774] [2024-10-13 17:44:57,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:57,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:57,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:57,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:57,485 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:57,485 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25796774] [2024-10-13 17:44:57,486 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25796774] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:57,486 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:57,486 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:44:57,486 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719546989] [2024-10-13 17:44:57,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:57,487 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:57,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:57,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:57,512 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:57,515 INFO L87 Difference]: Start difference. First operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:57,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:57,583 INFO L93 Difference]: Finished difference Result 1191 states and 1767 transitions. [2024-10-13 17:44:57,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1191 states and 1767 transitions. [2024-10-13 17:44:57,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:57,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1191 states to 1185 states and 1761 transitions. [2024-10-13 17:44:57,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2024-10-13 17:44:57,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2024-10-13 17:44:57,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1761 transitions. [2024-10-13 17:44:57,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:57,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2024-10-13 17:44:57,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1761 transitions. [2024-10-13 17:44:57,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2024-10-13 17:44:57,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4860759493670885) internal successors, (1761), 1184 states have internal predecessors, (1761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:57,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1761 transitions. [2024-10-13 17:44:57,680 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2024-10-13 17:44:57,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:57,683 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2024-10-13 17:44:57,683 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-13 17:44:57,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1761 transitions. [2024-10-13 17:44:57,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:57,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:57,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:57,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:57,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:57,693 INFO L745 eck$LassoCheckResult]: Stem: 2773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3517#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3518#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3241#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2967#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2968#L675-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3496#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3530#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3523#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3524#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3095#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3082#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3083#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2892#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2893#L951 assume !(0 == ~M_E~0); 2637#L951-2 assume !(0 == ~T1_E~0); 2638#L956-1 assume !(0 == ~T2_E~0); 2792#L961-1 assume !(0 == ~T3_E~0); 3260#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3261#L971-1 assume !(0 == ~T5_E~0); 3384#L976-1 assume !(0 == ~T6_E~0); 3359#L981-1 assume !(0 == ~T7_E~0); 3131#L986-1 assume !(0 == ~T8_E~0); 2842#L991-1 assume !(0 == ~T9_E~0); 2843#L996-1 assume !(0 == ~E_M~0); 3553#L1001-1 assume !(0 == ~E_1~0); 3311#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3312#L1011-1 assume !(0 == ~E_3~0); 3531#L1016-1 assume !(0 == ~E_4~0); 3540#L1021-1 assume !(0 == ~E_5~0); 2431#L1026-1 assume !(0 == ~E_6~0); 2432#L1031-1 assume !(0 == ~E_7~0); 3267#L1036-1 assume !(0 == ~E_8~0); 3263#L1041-1 assume !(0 == ~E_9~0); 3264#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3503#L472 assume 1 == ~m_pc~0; 3569#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3292#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3293#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3301#L1179 assume !(0 != activate_threads_~tmp~1#1); 2439#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2440#L491 assume 1 == ~t1_pc~0; 3310#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2937#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2464#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2411#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2412#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2435#L510 assume !(1 == ~t2_pc~0); 2400#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2401#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2959#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2960#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2692#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2693#L529 assume 1 == ~t3_pc~0; 3044#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3045#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2409#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2410#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2612#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2613#L548 assume !(1 == ~t4_pc~0); 2506#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2505#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2548#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2549#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2493#L567 assume 1 == ~t5_pc~0; 2494#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2550#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3451#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3452#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 3491#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2623#L586 assume !(1 == ~t6_pc~0); 2624#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2696#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2943#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 3485#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3486#L605 assume 1 == ~t7_pc~0; 3459#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3118#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3294#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3578#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 3577#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3235#L624 assume !(1 == ~t8_pc~0); 2687#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2686#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3403#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 3469#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2456#L643 assume 1 == ~t9_pc~0; 2457#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3423#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3009#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2849#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2850#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2669#L1059 assume !(1 == ~M_E~0); 2670#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2820#L1064-1 assume !(1 == ~T2_E~0); 2821#L1069-1 assume !(1 == ~T3_E~0); 3430#L1074-1 assume !(1 == ~T4_E~0); 3467#L1079-1 assume !(1 == ~T5_E~0); 3457#L1084-1 assume !(1 == ~T6_E~0); 3458#L1089-1 assume !(1 == ~T7_E~0); 3481#L1094-1 assume !(1 == ~T8_E~0); 3169#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3170#L1104-1 assume !(1 == ~E_M~0); 3346#L1109-1 assume !(1 == ~E_1~0); 2961#L1114-1 assume !(1 == ~E_2~0); 2962#L1119-1 assume !(1 == ~E_3~0); 3019#L1124-1 assume !(1 == ~E_4~0); 2452#L1129-1 assume !(1 == ~E_5~0); 2453#L1134-1 assume !(1 == ~E_6~0); 2788#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2789#L1144-1 assume !(1 == ~E_8~0); 2977#L1149-1 assume !(1 == ~E_9~0); 2629#L1154-1 assume { :end_inline_reset_delta_events } true; 2630#L1440-2 [2024-10-13 17:44:57,693 INFO L747 eck$LassoCheckResult]: Loop: 2630#L1440-2 assume !false; 2758#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3333#L926-1 assume !false; 3021#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3022#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2717#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2718#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2725#L795 assume !(0 != eval_~tmp~0#1); 2726#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2876#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2877#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3394#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3237#L961-3 assume !(0 == ~T3_E~0); 3004#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3005#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3286#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2479#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2480#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2454#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2455#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3381#L1001-3 assume !(0 == ~E_1~0); 2973#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2974#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3402#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3437#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3182#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3183#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3375#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3376#L1041-3 assume !(0 == ~E_9~0); 3428#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3392#L472-33 assume 1 == ~m_pc~0; 3393#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2575#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3419#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3399#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3012#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3013#L491-33 assume !(1 == ~t1_pc~0); 2513#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2514#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3546#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3561#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 3562#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3353#L510-33 assume !(1 == ~t2_pc~0); 3347#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3348#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3386#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3387#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2395#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2396#L529-33 assume 1 == ~t3_pc~0; 2420#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2422#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2587#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2588#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2527#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2528#L548-33 assume 1 == ~t4_pc~0; 2776#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2894#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3318#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2931#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2712#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2713#L567-33 assume !(1 == ~t5_pc~0); 2815#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2816#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3055#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3566#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3571#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3259#L586-33 assume !(1 == ~t6_pc~0); 2832#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2833#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3071#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3072#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2729#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2730#L605-33 assume 1 == ~t7_pc~0; 2898#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2654#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2655#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3462#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2539#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2540#L624-33 assume !(1 == ~t8_pc~0); 2701#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2709#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3236#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2913#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 2914#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2656#L643-33 assume 1 == ~t9_pc~0; 2657#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2743#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3209#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3165#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3166#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2529#L1059-3 assume !(1 == ~M_E~0); 2530#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3033#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3091#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3092#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3360#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3268#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3207#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3208#L1094-3 assume !(1 == ~T8_E~0); 3124#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3125#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3382#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3366#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3367#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3572#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3576#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2827#L1134-3 assume !(1 == ~E_6~0); 2828#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2990#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2991#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3171#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3579#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2532#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2909#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2417#L1459 assume !(0 == start_simulation_~tmp~3#1); 2418#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3438#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2715#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2460#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2873#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3034#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3194#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2630#L1440-2 [2024-10-13 17:44:57,693 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:57,694 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2024-10-13 17:44:57,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:57,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039106106] [2024-10-13 17:44:57,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:57,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:57,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:57,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:57,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:57,764 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039106106] [2024-10-13 17:44:57,764 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039106106] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:57,764 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:57,764 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:57,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018433655] [2024-10-13 17:44:57,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:57,764 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:57,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:57,765 INFO L85 PathProgramCache]: Analyzing trace with hash 1812965149, now seen corresponding path program 1 times [2024-10-13 17:44:57,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:57,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930546938] [2024-10-13 17:44:57,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:57,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:57,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:57,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:57,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:57,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930546938] [2024-10-13 17:44:57,868 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930546938] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:57,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:57,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:57,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [941756177] [2024-10-13 17:44:57,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:57,869 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:57,869 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:57,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:57,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:57,870 INFO L87 Difference]: Start difference. First operand 1185 states and 1761 transitions. cyclomatic complexity: 577 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:57,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:57,888 INFO L93 Difference]: Finished difference Result 1185 states and 1760 transitions. [2024-10-13 17:44:57,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1760 transitions. [2024-10-13 17:44:57,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:57,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1760 transitions. [2024-10-13 17:44:57,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2024-10-13 17:44:57,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2024-10-13 17:44:57,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1760 transitions. [2024-10-13 17:44:57,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:57,915 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2024-10-13 17:44:57,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1760 transitions. [2024-10-13 17:44:57,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2024-10-13 17:44:57,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4852320675105486) internal successors, (1760), 1184 states have internal predecessors, (1760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:57,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1760 transitions. [2024-10-13 17:44:57,929 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2024-10-13 17:44:57,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:57,932 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2024-10-13 17:44:57,934 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-13 17:44:57,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1760 transitions. [2024-10-13 17:44:57,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:57,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:57,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:57,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:57,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:57,941 INFO L745 eck$LassoCheckResult]: Stem: 5153#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5894#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5895#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5618#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 5344#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5345#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5873#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5907#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5900#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5901#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5472#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5459#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5460#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5270#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5271#L951 assume !(0 == ~M_E~0); 5014#L951-2 assume !(0 == ~T1_E~0); 5015#L956-1 assume !(0 == ~T2_E~0); 5169#L961-1 assume !(0 == ~T3_E~0); 5637#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5638#L971-1 assume !(0 == ~T5_E~0); 5761#L976-1 assume !(0 == ~T6_E~0); 5736#L981-1 assume !(0 == ~T7_E~0); 5511#L986-1 assume !(0 == ~T8_E~0); 5219#L991-1 assume !(0 == ~T9_E~0); 5220#L996-1 assume !(0 == ~E_M~0); 5930#L1001-1 assume !(0 == ~E_1~0); 5688#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5689#L1011-1 assume !(0 == ~E_3~0); 5908#L1016-1 assume !(0 == ~E_4~0); 5917#L1021-1 assume !(0 == ~E_5~0); 4808#L1026-1 assume !(0 == ~E_6~0); 4809#L1031-1 assume !(0 == ~E_7~0); 5644#L1036-1 assume !(0 == ~E_8~0); 5642#L1041-1 assume !(0 == ~E_9~0); 5643#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5880#L472 assume 1 == ~m_pc~0; 5946#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5669#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5670#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5678#L1179 assume !(0 != activate_threads_~tmp~1#1); 4816#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4817#L491 assume 1 == ~t1_pc~0; 5687#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5316#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4841#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4788#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4789#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4812#L510 assume !(1 == ~t2_pc~0); 4777#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4778#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5337#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5069#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5070#L529 assume 1 == ~t3_pc~0; 5421#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5422#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4786#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4787#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4989#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4990#L548 assume !(1 == ~t4_pc~0); 4883#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4882#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4954#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4925#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4926#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4875#L567 assume 1 == ~t5_pc~0; 4876#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4927#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5829#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 5868#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5000#L586 assume !(1 == ~t6_pc~0); 5001#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5075#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5322#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5323#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 5862#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5863#L605 assume 1 == ~t7_pc~0; 5836#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5496#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5672#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5955#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 5954#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5612#L624 assume !(1 == ~t8_pc~0); 5064#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5063#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5721#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5780#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 5846#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4833#L643 assume 1 == ~t9_pc~0; 4834#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5800#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5386#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5226#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 5227#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5046#L1059 assume !(1 == ~M_E~0); 5047#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5197#L1064-1 assume !(1 == ~T2_E~0); 5198#L1069-1 assume !(1 == ~T3_E~0); 5807#L1074-1 assume !(1 == ~T4_E~0); 5845#L1079-1 assume !(1 == ~T5_E~0); 5834#L1084-1 assume !(1 == ~T6_E~0); 5835#L1089-1 assume !(1 == ~T7_E~0); 5858#L1094-1 assume !(1 == ~T8_E~0); 5546#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5547#L1104-1 assume !(1 == ~E_M~0); 5725#L1109-1 assume !(1 == ~E_1~0); 5338#L1114-1 assume !(1 == ~E_2~0); 5339#L1119-1 assume !(1 == ~E_3~0); 5396#L1124-1 assume !(1 == ~E_4~0); 4829#L1129-1 assume !(1 == ~E_5~0); 4830#L1134-1 assume !(1 == ~E_6~0); 5165#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5166#L1144-1 assume !(1 == ~E_8~0); 5354#L1149-1 assume !(1 == ~E_9~0); 5006#L1154-1 assume { :end_inline_reset_delta_events } true; 5007#L1440-2 [2024-10-13 17:44:57,941 INFO L747 eck$LassoCheckResult]: Loop: 5007#L1440-2 assume !false; 5137#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5710#L926-1 assume !false; 5398#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5399#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5094#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5095#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5102#L795 assume !(0 != eval_~tmp~0#1); 5103#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5255#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5256#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5771#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5614#L961-3 assume !(0 == ~T3_E~0); 5382#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5383#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5663#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4856#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4857#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4831#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4832#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5758#L1001-3 assume !(0 == ~E_1~0); 5350#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5351#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5779#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5814#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5560#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5561#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5752#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5753#L1041-3 assume !(0 == ~E_9~0); 5805#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5769#L472-33 assume !(1 == ~m_pc~0); 4951#L472-35 is_master_triggered_~__retres1~0#1 := 0; 4952#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5796#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5776#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5389#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5390#L491-33 assume !(1 == ~t1_pc~0); 4887#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 4888#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5923#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5938#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 5939#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5726#L510-33 assume !(1 == ~t2_pc~0); 5723#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5724#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5763#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5764#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4772#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4773#L529-33 assume 1 == ~t3_pc~0; 4797#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4799#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4962#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4963#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4904#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4905#L548-33 assume 1 == ~t4_pc~0; 5149#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5269#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5695#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5308#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5089#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5090#L567-33 assume 1 == ~t5_pc~0; 5527#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5193#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5431#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5943#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5948#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5636#L586-33 assume 1 == ~t6_pc~0; 5602#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5211#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5448#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5449#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5108#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5109#L605-33 assume 1 == ~t7_pc~0; 5278#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5031#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5839#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4916#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4917#L624-33 assume !(1 == ~t8_pc~0); 5078#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 5086#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5613#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5290#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 5291#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5033#L643-33 assume 1 == ~t9_pc~0; 5034#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5120#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5586#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5542#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5543#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4906#L1059-3 assume !(1 == ~M_E~0); 4907#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5410#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5468#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5469#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5737#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5645#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5584#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5585#L1094-3 assume !(1 == ~T8_E~0); 5501#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5502#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5759#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5743#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5744#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5949#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5953#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5204#L1134-3 assume !(1 == ~E_6~0); 5205#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5370#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5371#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5548#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5956#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4909#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5288#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4794#L1459 assume !(0 == start_simulation_~tmp~3#1); 4795#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5815#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5092#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4836#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 4837#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5250#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5412#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5571#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 5007#L1440-2 [2024-10-13 17:44:57,941 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:57,942 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2024-10-13 17:44:57,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:57,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235028259] [2024-10-13 17:44:57,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:57,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:57,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:57,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:57,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:57,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235028259] [2024-10-13 17:44:57,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235028259] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:57,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:57,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:57,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109853899] [2024-10-13 17:44:57,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:57,975 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:57,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:57,975 INFO L85 PathProgramCache]: Analyzing trace with hash 2112954140, now seen corresponding path program 1 times [2024-10-13 17:44:57,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:57,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304108128] [2024-10-13 17:44:57,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:57,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:57,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304108128] [2024-10-13 17:44:58,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1304108128] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82281267] [2024-10-13 17:44:58,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,032 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:58,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:58,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:58,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:58,033 INFO L87 Difference]: Start difference. First operand 1185 states and 1760 transitions. cyclomatic complexity: 576 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:58,052 INFO L93 Difference]: Finished difference Result 1185 states and 1759 transitions. [2024-10-13 17:44:58,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1759 transitions. [2024-10-13 17:44:58,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1759 transitions. [2024-10-13 17:44:58,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2024-10-13 17:44:58,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2024-10-13 17:44:58,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1759 transitions. [2024-10-13 17:44:58,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:58,062 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2024-10-13 17:44:58,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1759 transitions. [2024-10-13 17:44:58,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2024-10-13 17:44:58,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4843881856540084) internal successors, (1759), 1184 states have internal predecessors, (1759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1759 transitions. [2024-10-13 17:44:58,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2024-10-13 17:44:58,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:58,075 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2024-10-13 17:44:58,075 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-13 17:44:58,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1759 transitions. [2024-10-13 17:44:58,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:58,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:58,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,081 INFO L745 eck$LassoCheckResult]: Stem: 7530#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7531#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7995#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 7723#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7724#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8250#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8284#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8277#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8278#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7849#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7836#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7837#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7647#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7648#L951 assume !(0 == ~M_E~0); 7393#L951-2 assume !(0 == ~T1_E~0); 7394#L956-1 assume !(0 == ~T2_E~0); 7546#L961-1 assume !(0 == ~T3_E~0); 8014#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8015#L971-1 assume !(0 == ~T5_E~0); 8138#L976-1 assume !(0 == ~T6_E~0); 8113#L981-1 assume !(0 == ~T7_E~0); 7888#L986-1 assume !(0 == ~T8_E~0); 7596#L991-1 assume !(0 == ~T9_E~0); 7597#L996-1 assume !(0 == ~E_M~0); 8307#L1001-1 assume !(0 == ~E_1~0); 8065#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8066#L1011-1 assume !(0 == ~E_3~0); 8286#L1016-1 assume !(0 == ~E_4~0); 8294#L1021-1 assume !(0 == ~E_5~0); 7185#L1026-1 assume !(0 == ~E_6~0); 7186#L1031-1 assume !(0 == ~E_7~0); 8021#L1036-1 assume !(0 == ~E_8~0); 8019#L1041-1 assume !(0 == ~E_9~0); 8020#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8257#L472 assume 1 == ~m_pc~0; 8323#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8046#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8047#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8055#L1179 assume !(0 != activate_threads_~tmp~1#1); 7193#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7194#L491 assume 1 == ~t1_pc~0; 8064#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7693#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7165#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 7166#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7189#L510 assume !(1 == ~t2_pc~0); 7154#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7155#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7713#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7714#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7446#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7447#L529 assume 1 == ~t3_pc~0; 7798#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7799#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7164#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 7366#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7367#L548 assume !(1 == ~t4_pc~0); 7261#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7260#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7331#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7302#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 7303#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7252#L567 assume 1 == ~t5_pc~0; 7253#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7304#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8205#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8206#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 8245#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7377#L586 assume !(1 == ~t6_pc~0); 7378#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7452#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7699#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7700#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 8239#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8240#L605 assume 1 == ~t7_pc~0; 8213#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7876#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8049#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8332#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 8331#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7989#L624 assume !(1 == ~t8_pc~0); 7441#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7440#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8098#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8158#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 8223#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7210#L643 assume 1 == ~t9_pc~0; 7211#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8177#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7763#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7603#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 7604#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7423#L1059 assume !(1 == ~M_E~0); 7424#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7574#L1064-1 assume !(1 == ~T2_E~0); 7575#L1069-1 assume !(1 == ~T3_E~0); 8184#L1074-1 assume !(1 == ~T4_E~0); 8222#L1079-1 assume !(1 == ~T5_E~0); 8211#L1084-1 assume !(1 == ~T6_E~0); 8212#L1089-1 assume !(1 == ~T7_E~0); 8235#L1094-1 assume !(1 == ~T8_E~0); 7923#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7924#L1104-1 assume !(1 == ~E_M~0); 8102#L1109-1 assume !(1 == ~E_1~0); 7715#L1114-1 assume !(1 == ~E_2~0); 7716#L1119-1 assume !(1 == ~E_3~0); 7774#L1124-1 assume !(1 == ~E_4~0); 7208#L1129-1 assume !(1 == ~E_5~0); 7209#L1134-1 assume !(1 == ~E_6~0); 7544#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7545#L1144-1 assume !(1 == ~E_8~0); 7731#L1149-1 assume !(1 == ~E_9~0); 7383#L1154-1 assume { :end_inline_reset_delta_events } true; 7384#L1440-2 [2024-10-13 17:44:58,081 INFO L747 eck$LassoCheckResult]: Loop: 7384#L1440-2 assume !false; 7514#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8087#L926-1 assume !false; 7775#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7776#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7471#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7472#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7479#L795 assume !(0 != eval_~tmp~0#1); 7480#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7932#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7632#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7633#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8149#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7992#L961-3 assume !(0 == ~T3_E~0); 7755#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7756#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8040#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7230#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7231#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7206#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7207#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8135#L1001-3 assume !(0 == ~E_1~0); 7727#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7728#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8156#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8191#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7936#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7937#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8129#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8130#L1041-3 assume !(0 == ~E_9~0); 8182#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8146#L472-33 assume !(1 == ~m_pc~0); 7328#L472-35 is_master_triggered_~__retres1~0#1 := 0; 7329#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8173#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8153#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7766#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7767#L491-33 assume !(1 == ~t1_pc~0); 7267#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7268#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8300#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8315#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 8316#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8106#L510-33 assume !(1 == ~t2_pc~0); 8100#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 8101#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8140#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8141#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7149#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7150#L529-33 assume 1 == ~t3_pc~0; 7174#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7176#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7341#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7342#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7281#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7282#L548-33 assume 1 == ~t4_pc~0; 7526#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7646#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8072#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7685#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7466#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7467#L567-33 assume !(1 == ~t5_pc~0); 7569#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7570#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7808#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8320#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8325#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8013#L586-33 assume !(1 == ~t6_pc~0); 7587#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 7588#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7826#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7827#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7485#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7486#L605-33 assume 1 == ~t7_pc~0; 7655#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7415#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7416#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8216#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7293#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7294#L624-33 assume 1 == ~t8_pc~0; 7456#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7463#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7990#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7667#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 7668#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7417#L643-33 assume 1 == ~t9_pc~0; 7418#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7497#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7963#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7919#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7920#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7283#L1059-3 assume !(1 == ~M_E~0); 7284#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7787#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7846#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7847#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8114#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8022#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7961#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7962#L1094-3 assume !(1 == ~T8_E~0); 7878#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7879#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8136#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8122#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8123#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8326#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8330#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7581#L1134-3 assume !(1 == ~E_6~0); 7582#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7749#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7750#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7925#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8333#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7288#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7665#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7171#L1459 assume !(0 == start_simulation_~tmp~3#1); 7172#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8192#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7469#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7213#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7214#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7627#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7789#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 7948#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 7384#L1440-2 [2024-10-13 17:44:58,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2024-10-13 17:44:58,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136601554] [2024-10-13 17:44:58,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136601554] [2024-10-13 17:44:58,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136601554] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137372716] [2024-10-13 17:44:58,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,124 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:58,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,125 INFO L85 PathProgramCache]: Analyzing trace with hash -491339491, now seen corresponding path program 1 times [2024-10-13 17:44:58,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409682502] [2024-10-13 17:44:58,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409682502] [2024-10-13 17:44:58,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409682502] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592458354] [2024-10-13 17:44:58,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,170 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:58,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:58,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:58,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:58,170 INFO L87 Difference]: Start difference. First operand 1185 states and 1759 transitions. cyclomatic complexity: 575 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:58,186 INFO L93 Difference]: Finished difference Result 1185 states and 1758 transitions. [2024-10-13 17:44:58,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1758 transitions. [2024-10-13 17:44:58,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1758 transitions. [2024-10-13 17:44:58,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2024-10-13 17:44:58,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2024-10-13 17:44:58,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1758 transitions. [2024-10-13 17:44:58,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:58,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2024-10-13 17:44:58,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1758 transitions. [2024-10-13 17:44:58,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2024-10-13 17:44:58,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4835443037974683) internal successors, (1758), 1184 states have internal predecessors, (1758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1758 transitions. [2024-10-13 17:44:58,213 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2024-10-13 17:44:58,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:58,215 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2024-10-13 17:44:58,215 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-13 17:44:58,215 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1758 transitions. [2024-10-13 17:44:58,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:58,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:58,220 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,221 INFO L745 eck$LassoCheckResult]: Stem: 9902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 9903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10646#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10647#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10372#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 10098#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10099#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10627#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10661#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10654#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10655#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10226#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10213#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10214#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10023#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10024#L951 assume !(0 == ~M_E~0); 9768#L951-2 assume !(0 == ~T1_E~0); 9769#L956-1 assume !(0 == ~T2_E~0); 9923#L961-1 assume !(0 == ~T3_E~0); 10391#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10392#L971-1 assume !(0 == ~T5_E~0); 10515#L976-1 assume !(0 == ~T6_E~0); 10490#L981-1 assume !(0 == ~T7_E~0); 10262#L986-1 assume !(0 == ~T8_E~0); 9973#L991-1 assume !(0 == ~T9_E~0); 9974#L996-1 assume !(0 == ~E_M~0); 10683#L1001-1 assume !(0 == ~E_1~0); 10442#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10443#L1011-1 assume !(0 == ~E_3~0); 10662#L1016-1 assume !(0 == ~E_4~0); 10671#L1021-1 assume !(0 == ~E_5~0); 9562#L1026-1 assume !(0 == ~E_6~0); 9563#L1031-1 assume !(0 == ~E_7~0); 10398#L1036-1 assume !(0 == ~E_8~0); 10394#L1041-1 assume !(0 == ~E_9~0); 10395#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10634#L472 assume 1 == ~m_pc~0; 10700#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10423#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10424#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10432#L1179 assume !(0 != activate_threads_~tmp~1#1); 9570#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9571#L491 assume 1 == ~t1_pc~0; 10441#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10068#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9595#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9542#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 9543#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9564#L510 assume !(1 == ~t2_pc~0); 9531#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9532#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10090#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10091#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9823#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9824#L529 assume 1 == ~t3_pc~0; 10175#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10176#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9540#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9541#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 9743#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9744#L548 assume !(1 == ~t4_pc~0); 9637#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9636#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9708#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9677#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 9678#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9624#L567 assume 1 == ~t5_pc~0; 9625#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9679#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10583#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 10622#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9754#L586 assume !(1 == ~t6_pc~0); 9755#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9827#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10073#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10074#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 10616#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10617#L605 assume 1 == ~t7_pc~0; 10590#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10246#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10425#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10709#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 10708#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10366#L624 assume !(1 == ~t8_pc~0); 9818#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9817#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10475#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10534#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 10600#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9587#L643 assume 1 == ~t9_pc~0; 9588#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10554#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10138#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9978#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 9979#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9800#L1059 assume !(1 == ~M_E~0); 9801#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9951#L1064-1 assume !(1 == ~T2_E~0); 9952#L1069-1 assume !(1 == ~T3_E~0); 10561#L1074-1 assume !(1 == ~T4_E~0); 10598#L1079-1 assume !(1 == ~T5_E~0); 10588#L1084-1 assume !(1 == ~T6_E~0); 10589#L1089-1 assume !(1 == ~T7_E~0); 10612#L1094-1 assume !(1 == ~T8_E~0); 10300#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10301#L1104-1 assume !(1 == ~E_M~0); 10477#L1109-1 assume !(1 == ~E_1~0); 10092#L1114-1 assume !(1 == ~E_2~0); 10093#L1119-1 assume !(1 == ~E_3~0); 10150#L1124-1 assume !(1 == ~E_4~0); 9583#L1129-1 assume !(1 == ~E_5~0); 9584#L1134-1 assume !(1 == ~E_6~0); 9919#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9920#L1144-1 assume !(1 == ~E_8~0); 10106#L1149-1 assume !(1 == ~E_9~0); 9760#L1154-1 assume { :end_inline_reset_delta_events } true; 9761#L1440-2 [2024-10-13 17:44:58,224 INFO L747 eck$LassoCheckResult]: Loop: 9761#L1440-2 assume !false; 9889#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10464#L926-1 assume !false; 10152#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10153#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9845#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9846#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9855#L795 assume !(0 != eval_~tmp~0#1); 9856#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10309#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10007#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10008#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10525#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10368#L961-3 assume !(0 == ~T3_E~0); 10132#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10133#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10417#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9607#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9608#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9585#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9586#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10512#L1001-3 assume !(0 == ~E_1~0); 10104#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10105#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10533#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10568#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10313#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10314#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10506#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10507#L1041-3 assume !(0 == ~E_9~0); 10559#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10523#L472-33 assume !(1 == ~m_pc~0); 9705#L472-35 is_master_triggered_~__retres1~0#1 := 0; 9706#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10550#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10530#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10143#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10144#L491-33 assume 1 == ~t1_pc~0; 10433#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9645#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10677#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10692#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 10693#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10483#L510-33 assume 1 == ~t2_pc~0; 10484#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10479#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10517#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10518#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9526#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9527#L529-33 assume !(1 == ~t3_pc~0); 9552#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 9553#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9718#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9719#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9658#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9659#L548-33 assume 1 == ~t4_pc~0; 9905#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10025#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10449#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10062#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9843#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9844#L567-33 assume !(1 == ~t5_pc~0); 9946#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 9947#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10185#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10697#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10702#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10390#L586-33 assume 1 == ~t6_pc~0; 10356#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9965#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10203#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10204#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9862#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9863#L605-33 assume 1 == ~t7_pc~0; 10032#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9792#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9793#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10593#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9670#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9671#L624-33 assume !(1 == ~t8_pc~0); 9832#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 9840#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10367#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10044#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 10045#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9794#L643-33 assume 1 == ~t9_pc~0; 9795#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9874#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10340#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10296#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10297#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9660#L1059-3 assume !(1 == ~M_E~0); 9661#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10164#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10223#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10224#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10491#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10399#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10338#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10339#L1094-3 assume !(1 == ~T8_E~0); 10255#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10256#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10513#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10499#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10500#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10703#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10707#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9958#L1134-3 assume !(1 == ~E_6~0); 9959#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10126#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10127#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10302#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10710#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9665#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10042#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 9548#L1459 assume !(0 == start_simulation_~tmp~3#1); 9549#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10569#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9848#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9590#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 9591#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 10004#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10168#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10328#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 9761#L1440-2 [2024-10-13 17:44:58,224 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,224 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2024-10-13 17:44:58,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316531528] [2024-10-13 17:44:58,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316531528] [2024-10-13 17:44:58,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [316531528] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352083739] [2024-10-13 17:44:58,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,253 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:58,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,254 INFO L85 PathProgramCache]: Analyzing trace with hash -1438738724, now seen corresponding path program 1 times [2024-10-13 17:44:58,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111659379] [2024-10-13 17:44:58,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,329 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111659379] [2024-10-13 17:44:58,329 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111659379] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1831272174] [2024-10-13 17:44:58,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,330 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:58,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:58,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:58,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:58,331 INFO L87 Difference]: Start difference. First operand 1185 states and 1758 transitions. cyclomatic complexity: 574 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:58,350 INFO L93 Difference]: Finished difference Result 1185 states and 1757 transitions. [2024-10-13 17:44:58,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1757 transitions. [2024-10-13 17:44:58,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1757 transitions. [2024-10-13 17:44:58,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2024-10-13 17:44:58,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2024-10-13 17:44:58,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1757 transitions. [2024-10-13 17:44:58,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:58,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2024-10-13 17:44:58,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1757 transitions. [2024-10-13 17:44:58,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2024-10-13 17:44:58,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4827004219409283) internal successors, (1757), 1184 states have internal predecessors, (1757), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1757 transitions. [2024-10-13 17:44:58,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2024-10-13 17:44:58,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:58,377 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2024-10-13 17:44:58,377 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-13 17:44:58,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1757 transitions. [2024-10-13 17:44:58,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:58,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:58,383 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,383 INFO L745 eck$LassoCheckResult]: Stem: 12279#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 13023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12749#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 12475#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12476#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13004#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13038#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13031#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13032#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12603#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12590#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12591#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12400#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12401#L951 assume !(0 == ~M_E~0); 12145#L951-2 assume !(0 == ~T1_E~0); 12146#L956-1 assume !(0 == ~T2_E~0); 12300#L961-1 assume !(0 == ~T3_E~0); 12768#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12769#L971-1 assume !(0 == ~T5_E~0); 12892#L976-1 assume !(0 == ~T6_E~0); 12867#L981-1 assume !(0 == ~T7_E~0); 12639#L986-1 assume !(0 == ~T8_E~0); 12350#L991-1 assume !(0 == ~T9_E~0); 12351#L996-1 assume !(0 == ~E_M~0); 13060#L1001-1 assume !(0 == ~E_1~0); 12819#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12820#L1011-1 assume !(0 == ~E_3~0); 13039#L1016-1 assume !(0 == ~E_4~0); 13048#L1021-1 assume !(0 == ~E_5~0); 11939#L1026-1 assume !(0 == ~E_6~0); 11940#L1031-1 assume !(0 == ~E_7~0); 12775#L1036-1 assume !(0 == ~E_8~0); 12771#L1041-1 assume !(0 == ~E_9~0); 12772#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13011#L472 assume 1 == ~m_pc~0; 13077#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12800#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12801#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12809#L1179 assume !(0 != activate_threads_~tmp~1#1); 11947#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11948#L491 assume 1 == ~t1_pc~0; 12818#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12445#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11972#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11919#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 11920#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11941#L510 assume !(1 == ~t2_pc~0); 11908#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11909#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12468#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12200#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12201#L529 assume 1 == ~t3_pc~0; 12552#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12553#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11917#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11918#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 12120#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12121#L548 assume !(1 == ~t4_pc~0); 12014#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12013#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12085#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12054#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 12055#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12001#L567 assume 1 == ~t5_pc~0; 12002#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12056#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12959#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12960#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 12999#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12131#L586 assume !(1 == ~t6_pc~0); 12132#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12204#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12450#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12451#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 12993#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12994#L605 assume 1 == ~t7_pc~0; 12967#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12623#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12802#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13086#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 13085#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12743#L624 assume !(1 == ~t8_pc~0); 12195#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12194#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12852#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12911#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 12977#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11964#L643 assume 1 == ~t9_pc~0; 11965#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12931#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12515#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12355#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 12356#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12177#L1059 assume !(1 == ~M_E~0); 12178#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12328#L1064-1 assume !(1 == ~T2_E~0); 12329#L1069-1 assume !(1 == ~T3_E~0); 12938#L1074-1 assume !(1 == ~T4_E~0); 12975#L1079-1 assume !(1 == ~T5_E~0); 12965#L1084-1 assume !(1 == ~T6_E~0); 12966#L1089-1 assume !(1 == ~T7_E~0); 12989#L1094-1 assume !(1 == ~T8_E~0); 12677#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12678#L1104-1 assume !(1 == ~E_M~0); 12854#L1109-1 assume !(1 == ~E_1~0); 12469#L1114-1 assume !(1 == ~E_2~0); 12470#L1119-1 assume !(1 == ~E_3~0); 12527#L1124-1 assume !(1 == ~E_4~0); 11960#L1129-1 assume !(1 == ~E_5~0); 11961#L1134-1 assume !(1 == ~E_6~0); 12296#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12297#L1144-1 assume !(1 == ~E_8~0); 12483#L1149-1 assume !(1 == ~E_9~0); 12137#L1154-1 assume { :end_inline_reset_delta_events } true; 12138#L1440-2 [2024-10-13 17:44:58,384 INFO L747 eck$LassoCheckResult]: Loop: 12138#L1440-2 assume !false; 12266#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12841#L926-1 assume !false; 12529#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12530#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12222#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12223#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12232#L795 assume !(0 != eval_~tmp~0#1); 12233#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12686#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12384#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12385#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12902#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12745#L961-3 assume !(0 == ~T3_E~0); 12509#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12510#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12794#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11984#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11985#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11962#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11963#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12889#L1001-3 assume !(0 == ~E_1~0); 12481#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12482#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12910#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12945#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12690#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12691#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12883#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12884#L1041-3 assume !(0 == ~E_9~0); 12936#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12900#L472-33 assume !(1 == ~m_pc~0); 12082#L472-35 is_master_triggered_~__retres1~0#1 := 0; 12083#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12927#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12907#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12520#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12521#L491-33 assume !(1 == ~t1_pc~0); 12021#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12022#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13054#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13069#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 13070#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12860#L510-33 assume !(1 == ~t2_pc~0); 12855#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 12856#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12894#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12895#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11903#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11904#L529-33 assume 1 == ~t3_pc~0; 11928#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11930#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12095#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12096#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12035#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12036#L548-33 assume 1 == ~t4_pc~0; 12282#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12402#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12826#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12439#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12220#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12221#L567-33 assume !(1 == ~t5_pc~0); 12323#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 12324#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12562#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13074#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13079#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12767#L586-33 assume !(1 == ~t6_pc~0); 12341#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 12342#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12580#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12581#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12239#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12240#L605-33 assume 1 == ~t7_pc~0; 12409#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12169#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12170#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12970#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12047#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12048#L624-33 assume !(1 == ~t8_pc~0); 12209#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 12217#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12744#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12421#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 12422#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12171#L643-33 assume 1 == ~t9_pc~0; 12172#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12251#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12717#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12673#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12674#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12037#L1059-3 assume !(1 == ~M_E~0); 12038#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12541#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12600#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12601#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12868#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12776#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12715#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12716#L1094-3 assume !(1 == ~T8_E~0); 12632#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12633#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12890#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12876#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12877#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13080#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13084#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12335#L1134-3 assume !(1 == ~E_6~0); 12336#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12503#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12504#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12679#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 13087#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12042#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12419#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 11925#L1459 assume !(0 == start_simulation_~tmp~3#1); 11926#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12946#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12225#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11967#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 11968#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 12381#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12545#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 12705#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 12138#L1440-2 [2024-10-13 17:44:58,384 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,385 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2024-10-13 17:44:58,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457454372] [2024-10-13 17:44:58,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457454372] [2024-10-13 17:44:58,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [457454372] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1322894242] [2024-10-13 17:44:58,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,425 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:58,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1364817186, now seen corresponding path program 1 times [2024-10-13 17:44:58,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765993153] [2024-10-13 17:44:58,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765993153] [2024-10-13 17:44:58,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765993153] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579107003] [2024-10-13 17:44:58,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,468 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:58,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:58,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:58,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:58,469 INFO L87 Difference]: Start difference. First operand 1185 states and 1757 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:58,485 INFO L93 Difference]: Finished difference Result 1185 states and 1756 transitions. [2024-10-13 17:44:58,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1756 transitions. [2024-10-13 17:44:58,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1756 transitions. [2024-10-13 17:44:58,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2024-10-13 17:44:58,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2024-10-13 17:44:58,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1756 transitions. [2024-10-13 17:44:58,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:58,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2024-10-13 17:44:58,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1756 transitions. [2024-10-13 17:44:58,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2024-10-13 17:44:58,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4818565400843882) internal successors, (1756), 1184 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1756 transitions. [2024-10-13 17:44:58,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2024-10-13 17:44:58,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:58,512 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2024-10-13 17:44:58,512 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-13 17:44:58,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1756 transitions. [2024-10-13 17:44:58,517 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:58,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:58,518 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,518 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,519 INFO L745 eck$LassoCheckResult]: Stem: 14656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15400#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15401#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15126#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 14852#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14853#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15381#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15415#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15408#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15409#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14980#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14967#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14968#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14777#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14778#L951 assume !(0 == ~M_E~0); 14522#L951-2 assume !(0 == ~T1_E~0); 14523#L956-1 assume !(0 == ~T2_E~0); 14677#L961-1 assume !(0 == ~T3_E~0); 15145#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15146#L971-1 assume !(0 == ~T5_E~0); 15269#L976-1 assume !(0 == ~T6_E~0); 15244#L981-1 assume !(0 == ~T7_E~0); 15016#L986-1 assume !(0 == ~T8_E~0); 14727#L991-1 assume !(0 == ~T9_E~0); 14728#L996-1 assume !(0 == ~E_M~0); 15437#L1001-1 assume !(0 == ~E_1~0); 15196#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15197#L1011-1 assume !(0 == ~E_3~0); 15416#L1016-1 assume !(0 == ~E_4~0); 15425#L1021-1 assume !(0 == ~E_5~0); 14316#L1026-1 assume !(0 == ~E_6~0); 14317#L1031-1 assume !(0 == ~E_7~0); 15152#L1036-1 assume !(0 == ~E_8~0); 15148#L1041-1 assume !(0 == ~E_9~0); 15149#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15388#L472 assume 1 == ~m_pc~0; 15454#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15177#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15178#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15186#L1179 assume !(0 != activate_threads_~tmp~1#1); 14324#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14325#L491 assume 1 == ~t1_pc~0; 15195#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14822#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14349#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14296#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 14297#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14318#L510 assume !(1 == ~t2_pc~0); 14285#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14286#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14844#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14845#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14577#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14578#L529 assume 1 == ~t3_pc~0; 14929#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14930#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14294#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14295#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 14497#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14498#L548 assume !(1 == ~t4_pc~0); 14391#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14390#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14462#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14431#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 14432#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14378#L567 assume 1 == ~t5_pc~0; 14379#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14433#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15336#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15337#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 15376#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14508#L586 assume !(1 == ~t6_pc~0); 14509#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14581#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14827#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14828#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 15370#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15371#L605 assume 1 == ~t7_pc~0; 15344#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15000#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15463#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 15462#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15120#L624 assume !(1 == ~t8_pc~0); 14572#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14571#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15229#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15288#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 15354#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14341#L643 assume 1 == ~t9_pc~0; 14342#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15308#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14892#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14732#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 14733#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14554#L1059 assume !(1 == ~M_E~0); 14555#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14705#L1064-1 assume !(1 == ~T2_E~0); 14706#L1069-1 assume !(1 == ~T3_E~0); 15315#L1074-1 assume !(1 == ~T4_E~0); 15352#L1079-1 assume !(1 == ~T5_E~0); 15342#L1084-1 assume !(1 == ~T6_E~0); 15343#L1089-1 assume !(1 == ~T7_E~0); 15366#L1094-1 assume !(1 == ~T8_E~0); 15054#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15055#L1104-1 assume !(1 == ~E_M~0); 15231#L1109-1 assume !(1 == ~E_1~0); 14846#L1114-1 assume !(1 == ~E_2~0); 14847#L1119-1 assume !(1 == ~E_3~0); 14904#L1124-1 assume !(1 == ~E_4~0); 14337#L1129-1 assume !(1 == ~E_5~0); 14338#L1134-1 assume !(1 == ~E_6~0); 14673#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14674#L1144-1 assume !(1 == ~E_8~0); 14860#L1149-1 assume !(1 == ~E_9~0); 14514#L1154-1 assume { :end_inline_reset_delta_events } true; 14515#L1440-2 [2024-10-13 17:44:58,520 INFO L747 eck$LassoCheckResult]: Loop: 14515#L1440-2 assume !false; 14643#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15218#L926-1 assume !false; 14906#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14907#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14599#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14600#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14609#L795 assume !(0 != eval_~tmp~0#1); 14610#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14761#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14762#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15279#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15122#L961-3 assume !(0 == ~T3_E~0); 14886#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14887#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15171#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14361#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14362#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14339#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14340#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15266#L1001-3 assume !(0 == ~E_1~0); 14858#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14859#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15287#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15322#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15067#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15068#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15260#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15261#L1041-3 assume !(0 == ~E_9~0); 15313#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15277#L472-33 assume !(1 == ~m_pc~0); 14459#L472-35 is_master_triggered_~__retres1~0#1 := 0; 14460#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15304#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15284#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14897#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14898#L491-33 assume 1 == ~t1_pc~0; 15187#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14399#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15431#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15446#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 15447#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15237#L510-33 assume !(1 == ~t2_pc~0); 15232#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15233#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15271#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15272#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14280#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14281#L529-33 assume 1 == ~t3_pc~0; 14305#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14307#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14472#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14473#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14412#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14413#L548-33 assume 1 == ~t4_pc~0; 14659#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14779#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15203#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14816#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14597#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14598#L567-33 assume !(1 == ~t5_pc~0); 14700#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 14701#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14939#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15451#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15456#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15144#L586-33 assume 1 == ~t6_pc~0; 15110#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14719#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14957#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14958#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14616#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14617#L605-33 assume 1 == ~t7_pc~0; 14786#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14546#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14547#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15347#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14424#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14425#L624-33 assume !(1 == ~t8_pc~0); 14586#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 14594#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15121#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14798#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 14799#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14548#L643-33 assume 1 == ~t9_pc~0; 14549#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14628#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15094#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15050#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15051#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14414#L1059-3 assume !(1 == ~M_E~0); 14415#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14918#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14977#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14978#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15245#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15153#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15092#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15093#L1094-3 assume !(1 == ~T8_E~0); 15009#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15010#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15267#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15253#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15254#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15457#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15461#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14712#L1134-3 assume !(1 == ~E_6~0); 14713#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14880#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14881#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15056#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15464#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14419#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14796#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14302#L1459 assume !(0 == start_simulation_~tmp~3#1); 14303#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15323#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14602#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14344#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 14345#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 14758#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14922#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 15082#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 14515#L1440-2 [2024-10-13 17:44:58,520 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2024-10-13 17:44:58,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,521 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1695237487] [2024-10-13 17:44:58,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,551 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,551 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1695237487] [2024-10-13 17:44:58,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1695237487] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792543321] [2024-10-13 17:44:58,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,552 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:58,552 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,553 INFO L85 PathProgramCache]: Analyzing trace with hash -119844324, now seen corresponding path program 1 times [2024-10-13 17:44:58,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160089674] [2024-10-13 17:44:58,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160089674] [2024-10-13 17:44:58,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160089674] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,602 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061824935] [2024-10-13 17:44:58,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,603 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:58,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:58,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:58,603 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:58,603 INFO L87 Difference]: Start difference. First operand 1185 states and 1756 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:58,619 INFO L93 Difference]: Finished difference Result 1185 states and 1755 transitions. [2024-10-13 17:44:58,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1755 transitions. [2024-10-13 17:44:58,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1755 transitions. [2024-10-13 17:44:58,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2024-10-13 17:44:58,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2024-10-13 17:44:58,628 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1755 transitions. [2024-10-13 17:44:58,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:58,629 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2024-10-13 17:44:58,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1755 transitions. [2024-10-13 17:44:58,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2024-10-13 17:44:58,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.481012658227848) internal successors, (1755), 1184 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1755 transitions. [2024-10-13 17:44:58,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2024-10-13 17:44:58,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:58,645 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2024-10-13 17:44:58,645 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-13 17:44:58,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1755 transitions. [2024-10-13 17:44:58,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:58,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:58,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,651 INFO L745 eck$LassoCheckResult]: Stem: 17035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17779#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17780#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17503#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 17229#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17230#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17758#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17792#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17785#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17786#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17357#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17344#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17345#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17154#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17155#L951 assume !(0 == ~M_E~0); 16899#L951-2 assume !(0 == ~T1_E~0); 16900#L956-1 assume !(0 == ~T2_E~0); 17054#L961-1 assume !(0 == ~T3_E~0); 17522#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17523#L971-1 assume !(0 == ~T5_E~0); 17646#L976-1 assume !(0 == ~T6_E~0); 17621#L981-1 assume !(0 == ~T7_E~0); 17393#L986-1 assume !(0 == ~T8_E~0); 17104#L991-1 assume !(0 == ~T9_E~0); 17105#L996-1 assume !(0 == ~E_M~0); 17814#L1001-1 assume !(0 == ~E_1~0); 17573#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17574#L1011-1 assume !(0 == ~E_3~0); 17793#L1016-1 assume !(0 == ~E_4~0); 17802#L1021-1 assume !(0 == ~E_5~0); 16693#L1026-1 assume !(0 == ~E_6~0); 16694#L1031-1 assume !(0 == ~E_7~0); 17529#L1036-1 assume !(0 == ~E_8~0); 17525#L1041-1 assume !(0 == ~E_9~0); 17526#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17765#L472 assume 1 == ~m_pc~0; 17831#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17554#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17555#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17563#L1179 assume !(0 != activate_threads_~tmp~1#1); 16701#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16702#L491 assume 1 == ~t1_pc~0; 17572#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17199#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16726#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16673#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 16674#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16697#L510 assume !(1 == ~t2_pc~0); 16662#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16663#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17221#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17222#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16954#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16955#L529 assume 1 == ~t3_pc~0; 17306#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17307#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16671#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16672#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 16874#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16875#L548 assume !(1 == ~t4_pc~0); 16768#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16767#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16839#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16810#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 16811#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16755#L567 assume 1 == ~t5_pc~0; 16756#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16812#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17713#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17714#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 17753#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16885#L586 assume !(1 == ~t6_pc~0); 16886#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16958#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17204#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17205#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 17747#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17748#L605 assume 1 == ~t7_pc~0; 17721#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17379#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17556#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17840#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 17839#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17497#L624 assume !(1 == ~t8_pc~0); 16949#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16948#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17606#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17665#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 17731#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16718#L643 assume 1 == ~t9_pc~0; 16719#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17685#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17271#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17111#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 17112#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16931#L1059 assume !(1 == ~M_E~0); 16932#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17082#L1064-1 assume !(1 == ~T2_E~0); 17083#L1069-1 assume !(1 == ~T3_E~0); 17692#L1074-1 assume !(1 == ~T4_E~0); 17729#L1079-1 assume !(1 == ~T5_E~0); 17719#L1084-1 assume !(1 == ~T6_E~0); 17720#L1089-1 assume !(1 == ~T7_E~0); 17743#L1094-1 assume !(1 == ~T8_E~0); 17431#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17432#L1104-1 assume !(1 == ~E_M~0); 17608#L1109-1 assume !(1 == ~E_1~0); 17223#L1114-1 assume !(1 == ~E_2~0); 17224#L1119-1 assume !(1 == ~E_3~0); 17281#L1124-1 assume !(1 == ~E_4~0); 16714#L1129-1 assume !(1 == ~E_5~0); 16715#L1134-1 assume !(1 == ~E_6~0); 17050#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17051#L1144-1 assume !(1 == ~E_8~0); 17239#L1149-1 assume !(1 == ~E_9~0); 16891#L1154-1 assume { :end_inline_reset_delta_events } true; 16892#L1440-2 [2024-10-13 17:44:58,651 INFO L747 eck$LassoCheckResult]: Loop: 16892#L1440-2 assume !false; 17020#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17595#L926-1 assume !false; 17283#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17284#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16979#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16980#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16987#L795 assume !(0 != eval_~tmp~0#1); 16988#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17440#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17138#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17139#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17656#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17499#L961-3 assume !(0 == ~T3_E~0); 17264#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17265#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17548#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16741#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16742#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16716#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16717#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17643#L1001-3 assume !(0 == ~E_1~0); 17235#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17236#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17664#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17699#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17444#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17445#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17637#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17638#L1041-3 assume !(0 == ~E_9~0); 17690#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17654#L472-33 assume !(1 == ~m_pc~0); 16836#L472-35 is_master_triggered_~__retres1~0#1 := 0; 16837#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17681#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17661#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17274#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17275#L491-33 assume !(1 == ~t1_pc~0); 16775#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16776#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17808#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17823#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 17824#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17614#L510-33 assume !(1 == ~t2_pc~0); 17609#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 17610#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17648#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17649#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16657#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16658#L529-33 assume 1 == ~t3_pc~0; 16682#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16684#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16849#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16850#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16789#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16790#L548-33 assume 1 == ~t4_pc~0; 17038#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17156#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17580#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17193#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16974#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16975#L567-33 assume !(1 == ~t5_pc~0); 17077#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 17078#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17317#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17828#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17834#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17521#L586-33 assume !(1 == ~t6_pc~0); 17095#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 17096#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17333#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17334#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16991#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16992#L605-33 assume 1 == ~t7_pc~0; 17160#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16916#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16917#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17724#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16801#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16802#L624-33 assume !(1 == ~t8_pc~0); 16961#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 16968#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17498#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17175#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 17176#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16918#L643-33 assume 1 == ~t9_pc~0; 16919#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17005#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17471#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17427#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17428#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16791#L1059-3 assume !(1 == ~M_E~0); 16792#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17295#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17353#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17354#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17622#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17530#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17469#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17470#L1094-3 assume !(1 == ~T8_E~0); 17386#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17387#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17644#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17628#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17629#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17833#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17838#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17089#L1134-3 assume !(1 == ~E_6~0); 17090#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17252#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17253#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17433#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17841#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16794#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16679#L1459 assume !(0 == start_simulation_~tmp~3#1); 16680#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17700#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16977#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 16722#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17135#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17296#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17456#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 16892#L1440-2 [2024-10-13 17:44:58,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,651 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2024-10-13 17:44:58,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259412657] [2024-10-13 17:44:58,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259412657] [2024-10-13 17:44:58,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259412657] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,680 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428908170] [2024-10-13 17:44:58,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,682 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:58,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,682 INFO L85 PathProgramCache]: Analyzing trace with hash -1364817186, now seen corresponding path program 2 times [2024-10-13 17:44:58,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232151579] [2024-10-13 17:44:58,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232151579] [2024-10-13 17:44:58,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1232151579] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,732 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,732 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063854788] [2024-10-13 17:44:58,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,733 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:58,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:58,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:58,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:58,733 INFO L87 Difference]: Start difference. First operand 1185 states and 1755 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:58,749 INFO L93 Difference]: Finished difference Result 1185 states and 1754 transitions. [2024-10-13 17:44:58,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1754 transitions. [2024-10-13 17:44:58,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1754 transitions. [2024-10-13 17:44:58,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2024-10-13 17:44:58,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2024-10-13 17:44:58,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1754 transitions. [2024-10-13 17:44:58,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:58,758 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2024-10-13 17:44:58,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1754 transitions. [2024-10-13 17:44:58,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2024-10-13 17:44:58,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.480168776371308) internal successors, (1754), 1184 states have internal predecessors, (1754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1754 transitions. [2024-10-13 17:44:58,773 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2024-10-13 17:44:58,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:58,775 INFO L425 stractBuchiCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2024-10-13 17:44:58,775 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-13 17:44:58,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1754 transitions. [2024-10-13 17:44:58,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2024-10-13 17:44:58,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:58,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:58,779 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,779 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:58,779 INFO L745 eck$LassoCheckResult]: Stem: 19414#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20156#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20157#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19880#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 19606#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19607#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20135#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20169#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20162#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20163#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19734#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19721#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19722#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19532#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19533#L951 assume !(0 == ~M_E~0); 19276#L951-2 assume !(0 == ~T1_E~0); 19277#L956-1 assume !(0 == ~T2_E~0); 19431#L961-1 assume !(0 == ~T3_E~0); 19899#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19900#L971-1 assume !(0 == ~T5_E~0); 20023#L976-1 assume !(0 == ~T6_E~0); 19998#L981-1 assume !(0 == ~T7_E~0); 19773#L986-1 assume !(0 == ~T8_E~0); 19481#L991-1 assume !(0 == ~T9_E~0); 19482#L996-1 assume !(0 == ~E_M~0); 20192#L1001-1 assume !(0 == ~E_1~0); 19950#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19951#L1011-1 assume !(0 == ~E_3~0); 20170#L1016-1 assume !(0 == ~E_4~0); 20179#L1021-1 assume !(0 == ~E_5~0); 19070#L1026-1 assume !(0 == ~E_6~0); 19071#L1031-1 assume !(0 == ~E_7~0); 19906#L1036-1 assume !(0 == ~E_8~0); 19904#L1041-1 assume !(0 == ~E_9~0); 19905#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20142#L472 assume 1 == ~m_pc~0; 20208#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19931#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19932#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19940#L1179 assume !(0 != activate_threads_~tmp~1#1); 19078#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19079#L491 assume 1 == ~t1_pc~0; 19949#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19576#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19103#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19050#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 19051#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19074#L510 assume !(1 == ~t2_pc~0); 19039#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19040#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19598#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19599#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19331#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19332#L529 assume 1 == ~t3_pc~0; 19683#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19684#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19049#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 19251#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19252#L548 assume !(1 == ~t4_pc~0); 19145#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19144#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19187#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 19188#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19132#L567 assume 1 == ~t5_pc~0; 19133#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19189#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20090#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20091#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 20130#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19262#L586 assume !(1 == ~t6_pc~0); 19263#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19337#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19585#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 20124#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20125#L605 assume 1 == ~t7_pc~0; 20098#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19757#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19934#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20217#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 20216#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19874#L624 assume !(1 == ~t8_pc~0); 19326#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19325#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19983#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20042#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 20108#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19095#L643 assume 1 == ~t9_pc~0; 19096#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20062#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19648#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19488#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 19489#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19308#L1059 assume !(1 == ~M_E~0); 19309#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19459#L1064-1 assume !(1 == ~T2_E~0); 19460#L1069-1 assume !(1 == ~T3_E~0); 20069#L1074-1 assume !(1 == ~T4_E~0); 20107#L1079-1 assume !(1 == ~T5_E~0); 20096#L1084-1 assume !(1 == ~T6_E~0); 20097#L1089-1 assume !(1 == ~T7_E~0); 20120#L1094-1 assume !(1 == ~T8_E~0); 19808#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19809#L1104-1 assume !(1 == ~E_M~0); 19987#L1109-1 assume !(1 == ~E_1~0); 19600#L1114-1 assume !(1 == ~E_2~0); 19601#L1119-1 assume !(1 == ~E_3~0); 19658#L1124-1 assume !(1 == ~E_4~0); 19091#L1129-1 assume !(1 == ~E_5~0); 19092#L1134-1 assume !(1 == ~E_6~0); 19427#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19428#L1144-1 assume !(1 == ~E_8~0); 19616#L1149-1 assume !(1 == ~E_9~0); 19268#L1154-1 assume { :end_inline_reset_delta_events } true; 19269#L1440-2 [2024-10-13 17:44:58,780 INFO L747 eck$LassoCheckResult]: Loop: 19269#L1440-2 assume !false; 19399#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19972#L926-1 assume !false; 19660#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19661#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19356#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19357#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19364#L795 assume !(0 != eval_~tmp~0#1); 19365#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19817#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19515#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19516#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20033#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19876#L961-3 assume !(0 == ~T3_E~0); 19644#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19645#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19925#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19118#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19119#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19093#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19094#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20020#L1001-3 assume !(0 == ~E_1~0); 19612#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19613#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20041#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20076#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19822#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19823#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20014#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20015#L1041-3 assume !(0 == ~E_9~0); 20067#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20031#L472-33 assume 1 == ~m_pc~0; 20032#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19214#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20058#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20038#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19651#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19652#L491-33 assume !(1 == ~t1_pc~0); 19152#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19153#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20185#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20200#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 20201#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19992#L510-33 assume !(1 == ~t2_pc~0); 19985#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19986#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20025#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20026#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19034#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19035#L529-33 assume 1 == ~t3_pc~0; 19059#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19061#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19224#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19225#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19166#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19167#L548-33 assume 1 == ~t4_pc~0; 19410#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19531#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19957#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19568#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19351#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19352#L567-33 assume 1 == ~t5_pc~0; 19789#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19455#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19693#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20205#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20210#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19898#L586-33 assume !(1 == ~t6_pc~0); 19472#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 19473#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19710#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19711#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19370#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19371#L605-33 assume 1 == ~t7_pc~0; 19540#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19293#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19294#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20101#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19178#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19179#L624-33 assume !(1 == ~t8_pc~0); 19340#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 19348#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19875#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19552#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 19553#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19295#L643-33 assume 1 == ~t9_pc~0; 19296#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19382#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19848#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19804#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19805#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19168#L1059-3 assume !(1 == ~M_E~0); 19169#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19672#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19730#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19731#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19999#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19907#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19846#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19847#L1094-3 assume !(1 == ~T8_E~0); 19763#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19764#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20021#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20005#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20006#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20211#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20215#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19466#L1134-3 assume !(1 == ~E_6~0); 19467#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19632#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19633#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19810#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20218#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19171#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19550#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19056#L1459 assume !(0 == start_simulation_~tmp~3#1); 19057#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20077#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19354#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 19099#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 19512#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19674#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19833#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 19269#L1440-2 [2024-10-13 17:44:58,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2024-10-13 17:44:58,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257694942] [2024-10-13 17:44:58,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,839 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,839 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257694942] [2024-10-13 17:44:58,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257694942] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,839 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921340116] [2024-10-13 17:44:58,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,839 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:58,839 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:58,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1236036508, now seen corresponding path program 1 times [2024-10-13 17:44:58,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:58,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044916939] [2024-10-13 17:44:58,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:58,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:58,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:58,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:58,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:58,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044916939] [2024-10-13 17:44:58,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044916939] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:58,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:58,872 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:58,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458061100] [2024-10-13 17:44:58,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:58,873 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:58,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:58,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:44:58,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:44:58,873 INFO L87 Difference]: Start difference. First operand 1185 states and 1754 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:58,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:58,967 INFO L93 Difference]: Finished difference Result 2171 states and 3201 transitions. [2024-10-13 17:44:58,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2171 states and 3201 transitions. [2024-10-13 17:44:58,975 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2024-10-13 17:44:58,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2171 states to 2171 states and 3201 transitions. [2024-10-13 17:44:58,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2171 [2024-10-13 17:44:58,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2171 [2024-10-13 17:44:58,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2171 states and 3201 transitions. [2024-10-13 17:44:58,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:58,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2024-10-13 17:44:58,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2171 states and 3201 transitions. [2024-10-13 17:44:59,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2171 to 2171. [2024-10-13 17:44:59,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2171 states, 2171 states have (on average 1.4744357438968216) internal successors, (3201), 2170 states have internal predecessors, (3201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:59,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2171 states to 2171 states and 3201 transitions. [2024-10-13 17:44:59,018 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2024-10-13 17:44:59,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:44:59,020 INFO L425 stractBuchiCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2024-10-13 17:44:59,020 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-13 17:44:59,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2171 states and 3201 transitions. [2024-10-13 17:44:59,025 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2024-10-13 17:44:59,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:59,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:59,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:59,026 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:59,026 INFO L745 eck$LassoCheckResult]: Stem: 22784#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22785#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23263#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 22979#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22980#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23552#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23587#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23580#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23581#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23107#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23094#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 23095#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22902#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22903#L951 assume !(0 == ~M_E~0); 22645#L951-2 assume !(0 == ~T1_E~0); 22646#L956-1 assume !(0 == ~T2_E~0); 22800#L961-1 assume !(0 == ~T3_E~0); 23284#L966-1 assume !(0 == ~T4_E~0); 23285#L971-1 assume !(0 == ~T5_E~0); 23417#L976-1 assume !(0 == ~T6_E~0); 23391#L981-1 assume !(0 == ~T7_E~0); 23148#L986-1 assume !(0 == ~T8_E~0); 22851#L991-1 assume !(0 == ~T9_E~0); 22852#L996-1 assume !(0 == ~E_M~0); 23617#L1001-1 assume !(0 == ~E_1~0); 23338#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 23339#L1011-1 assume !(0 == ~E_3~0); 23589#L1016-1 assume !(0 == ~E_4~0); 23598#L1021-1 assume !(0 == ~E_5~0); 22436#L1026-1 assume !(0 == ~E_6~0); 22437#L1031-1 assume !(0 == ~E_7~0); 23291#L1036-1 assume !(0 == ~E_8~0); 23289#L1041-1 assume !(0 == ~E_9~0); 23290#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23559#L472 assume 1 == ~m_pc~0; 23634#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23319#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23320#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23328#L1179 assume !(0 != activate_threads_~tmp~1#1); 22444#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22445#L491 assume 1 == ~t1_pc~0; 23337#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22949#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22416#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 22417#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22440#L510 assume !(1 == ~t2_pc~0); 22405#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22406#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22969#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22970#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22699#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22700#L529 assume 1 == ~t3_pc~0; 23056#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23057#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22414#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22415#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 22618#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22619#L548 assume !(1 == ~t4_pc~0); 22512#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22511#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22583#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22554#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 22555#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22503#L567 assume 1 == ~t5_pc~0; 22504#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22556#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23496#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23497#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 23546#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22629#L586 assume !(1 == ~t6_pc~0); 22630#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22705#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22955#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22956#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 23538#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23539#L605 assume 1 == ~t7_pc~0; 23504#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23135#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23322#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23648#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 23647#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23257#L624 assume !(1 == ~t8_pc~0); 22694#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22693#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23375#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23441#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 23516#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22461#L643 assume 1 == ~t9_pc~0; 22462#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23463#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23021#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22858#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 22859#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22675#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 22676#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23657#L1064-1 assume !(1 == ~T2_E~0); 23690#L1069-1 assume !(1 == ~T3_E~0); 23689#L1074-1 assume !(1 == ~T4_E~0); 23643#L1079-1 assume !(1 == ~T5_E~0); 23688#L1084-1 assume !(1 == ~T6_E~0); 23687#L1089-1 assume !(1 == ~T7_E~0); 23686#L1094-1 assume !(1 == ~T8_E~0); 23685#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23684#L1104-1 assume !(1 == ~E_M~0); 23683#L1109-1 assume !(1 == ~E_1~0); 23682#L1114-1 assume !(1 == ~E_2~0); 23681#L1119-1 assume !(1 == ~E_3~0); 23680#L1124-1 assume !(1 == ~E_4~0); 23679#L1129-1 assume !(1 == ~E_5~0); 23678#L1134-1 assume !(1 == ~E_6~0); 23677#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23676#L1144-1 assume !(1 == ~E_8~0); 23675#L1149-1 assume !(1 == ~E_9~0); 23674#L1154-1 assume { :end_inline_reset_delta_events } true; 23672#L1440-2 [2024-10-13 17:44:59,027 INFO L747 eck$LassoCheckResult]: Loop: 23672#L1440-2 assume !false; 23671#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23670#L926-1 assume !false; 23669#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23667#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22724#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22725#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22732#L795 assume !(0 != eval_~tmp~0#1); 22733#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23195#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23196#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23655#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23431#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23260#L961-3 assume !(0 == ~T3_E~0); 23013#L966-3 assume !(0 == ~T4_E~0); 23014#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23311#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22481#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22482#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22457#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22458#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23414#L1001-3 assume !(0 == ~E_1~0); 22983#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22984#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23438#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23478#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23201#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23202#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23408#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23409#L1041-3 assume !(0 == ~E_9~0); 23468#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23427#L472-33 assume 1 == ~m_pc~0; 23428#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24130#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24129#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24128#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24127#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24126#L491-33 assume 1 == ~t1_pc~0; 24124#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23606#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23607#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23625#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 23626#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23383#L510-33 assume 1 == ~t2_pc~0; 23384#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24119#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24118#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24117#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24116#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24115#L529-33 assume !(1 == ~t3_pc~0); 24113#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 24112#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24111#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24110#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24109#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24108#L548-33 assume 1 == ~t4_pc~0; 24106#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24105#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24104#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24103#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24102#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24101#L567-33 assume !(1 == ~t5_pc~0); 24099#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 24098#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24097#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24096#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24095#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23281#L586-33 assume 1 == ~t6_pc~0; 23282#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24094#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24093#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24092#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24091#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24090#L605-33 assume !(1 == ~t7_pc~0); 24088#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 24087#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24086#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24085#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24084#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24083#L624-33 assume 1 == ~t8_pc~0; 24081#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24080#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24079#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24078#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 24077#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24076#L643-33 assume 1 == ~t9_pc~0; 24074#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24073#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24072#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24071#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24070#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24069#L1059-3 assume !(1 == ~M_E~0); 22536#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24068#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24067#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24066#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23392#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24065#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24064#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24063#L1094-3 assume !(1 == ~T8_E~0); 24062#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24061#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24060#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24059#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24058#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24057#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24056#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24055#L1134-3 assume !(1 == ~E_6~0); 24054#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24053#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23185#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23186#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23656#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23710#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23709#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23708#L1459 assume !(0 == start_simulation_~tmp~3#1); 23563#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23704#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23695#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23693#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 23692#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23691#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23673#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 23672#L1440-2 [2024-10-13 17:44:59,027 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:59,027 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2024-10-13 17:44:59,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:59,028 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39655023] [2024-10-13 17:44:59,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:59,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:59,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:59,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:59,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:59,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39655023] [2024-10-13 17:44:59,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39655023] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:59,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:59,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:44:59,074 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76111879] [2024-10-13 17:44:59,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:59,074 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:59,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:59,074 INFO L85 PathProgramCache]: Analyzing trace with hash -1619670631, now seen corresponding path program 1 times [2024-10-13 17:44:59,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:59,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359987465] [2024-10-13 17:44:59,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:59,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:59,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:59,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:59,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:59,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359987465] [2024-10-13 17:44:59,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359987465] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:59,110 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:59,110 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:59,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037172582] [2024-10-13 17:44:59,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:59,111 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:59,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:59,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:59,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:59,112 INFO L87 Difference]: Start difference. First operand 2171 states and 3201 transitions. cyclomatic complexity: 1032 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:59,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:59,192 INFO L93 Difference]: Finished difference Result 2171 states and 3171 transitions. [2024-10-13 17:44:59,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2171 states and 3171 transitions. [2024-10-13 17:44:59,199 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2024-10-13 17:44:59,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2171 states to 2171 states and 3171 transitions. [2024-10-13 17:44:59,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2171 [2024-10-13 17:44:59,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2171 [2024-10-13 17:44:59,207 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2171 states and 3171 transitions. [2024-10-13 17:44:59,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:59,209 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2024-10-13 17:44:59,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2171 states and 3171 transitions. [2024-10-13 17:44:59,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2171 to 2171. [2024-10-13 17:44:59,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2171 states, 2171 states have (on average 1.460617227084293) internal successors, (3171), 2170 states have internal predecessors, (3171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:59,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2171 states to 2171 states and 3171 transitions. [2024-10-13 17:44:59,238 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2024-10-13 17:44:59,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:59,239 INFO L425 stractBuchiCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2024-10-13 17:44:59,239 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-13 17:44:59,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2171 states and 3171 transitions. [2024-10-13 17:44:59,244 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2024-10-13 17:44:59,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:59,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:59,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:59,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:59,246 INFO L745 eck$LassoCheckResult]: Stem: 27127#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 27128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27921#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27922#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27615#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 27326#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27327#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27897#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27938#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27930#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27931#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27457#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27444#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27445#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27250#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27251#L951 assume !(0 == ~M_E~0); 26990#L951-2 assume !(0 == ~T1_E~0); 26991#L956-1 assume !(0 == ~T2_E~0); 27148#L961-1 assume !(0 == ~T3_E~0); 27634#L966-1 assume !(0 == ~T4_E~0); 27635#L971-1 assume !(0 == ~T5_E~0); 27769#L976-1 assume !(0 == ~T6_E~0); 27744#L981-1 assume !(0 == ~T7_E~0); 27497#L986-1 assume !(0 == ~T8_E~0); 27200#L991-1 assume !(0 == ~T9_E~0); 27201#L996-1 assume !(0 == ~E_M~0); 27968#L1001-1 assume !(0 == ~E_1~0); 27687#L1006-1 assume !(0 == ~E_2~0); 27688#L1011-1 assume !(0 == ~E_3~0); 27939#L1016-1 assume !(0 == ~E_4~0); 27948#L1021-1 assume !(0 == ~E_5~0); 26784#L1026-1 assume !(0 == ~E_6~0); 26785#L1031-1 assume !(0 == ~E_7~0); 27643#L1036-1 assume !(0 == ~E_8~0); 27639#L1041-1 assume !(0 == ~E_9~0); 27640#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27904#L472 assume 1 == ~m_pc~0; 27987#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 27668#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27669#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27677#L1179 assume !(0 != activate_threads_~tmp~1#1); 26792#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26793#L491 assume 1 == ~t1_pc~0; 27686#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27296#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26818#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26765#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 26766#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26786#L510 assume !(1 == ~t2_pc~0); 26754#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26755#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27318#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27319#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27046#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27047#L529 assume 1 == ~t3_pc~0; 27406#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27407#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26763#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26764#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 26965#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26966#L548 assume !(1 == ~t4_pc~0); 26860#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26859#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26900#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 26901#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26847#L567 assume 1 == ~t5_pc~0; 26848#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26902#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27849#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 27891#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26976#L586 assume !(1 == ~t6_pc~0); 26977#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27050#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27301#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27302#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 27885#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27886#L605 assume 1 == ~t7_pc~0; 27856#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27478#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27670#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27996#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 27995#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27609#L624 assume !(1 == ~t8_pc~0); 27041#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27040#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27728#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27791#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 27867#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26809#L643 assume 1 == ~t9_pc~0; 26810#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27814#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27369#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27205#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 27206#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27022#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 27023#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27176#L1064-1 assume !(1 == ~T2_E~0); 27177#L1069-1 assume !(1 == ~T3_E~0); 27823#L1074-1 assume !(1 == ~T4_E~0); 27865#L1079-1 assume !(1 == ~T5_E~0); 27854#L1084-1 assume !(1 == ~T6_E~0); 27855#L1089-1 assume !(1 == ~T7_E~0); 27880#L1094-1 assume !(1 == ~T8_E~0); 27534#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27535#L1104-1 assume !(1 == ~E_M~0); 27730#L1109-1 assume !(1 == ~E_1~0); 27320#L1114-1 assume !(1 == ~E_2~0); 27321#L1119-1 assume !(1 == ~E_3~0); 27381#L1124-1 assume !(1 == ~E_4~0); 26805#L1129-1 assume !(1 == ~E_5~0); 26806#L1134-1 assume !(1 == ~E_6~0); 27144#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27145#L1144-1 assume !(1 == ~E_8~0); 27334#L1149-1 assume !(1 == ~E_9~0); 26982#L1154-1 assume { :end_inline_reset_delta_events } true; 26983#L1440-2 [2024-10-13 17:44:59,246 INFO L747 eck$LassoCheckResult]: Loop: 26983#L1440-2 assume !false; 27963#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27716#L926-1 assume !false; 27383#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27384#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27068#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27069#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28008#L795 assume !(0 != eval_~tmp~0#1); 27795#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27796#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28006#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28007#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28889#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28888#L961-3 assume !(0 == ~T3_E~0); 28887#L966-3 assume !(0 == ~T4_E~0); 28886#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28885#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28884#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28883#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28882#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28881#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28880#L1001-3 assume !(0 == ~E_1~0); 28879#L1006-3 assume !(0 == ~E_2~0); 28878#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28877#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28876#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28875#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28874#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28873#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28872#L1041-3 assume !(0 == ~E_9~0); 28871#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28870#L472-33 assume !(1 == ~m_pc~0); 28868#L472-35 is_master_triggered_~__retres1~0#1 := 0; 28867#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28866#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28865#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28864#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28863#L491-33 assume 1 == ~t1_pc~0; 28861#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28860#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28859#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28858#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 28857#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28856#L510-33 assume !(1 == ~t2_pc~0); 28854#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 28853#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28852#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28851#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28850#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28849#L529-33 assume 1 == ~t3_pc~0; 28848#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28846#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28845#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28844#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28843#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28842#L548-33 assume 1 == ~t4_pc~0; 28840#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28839#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28838#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28837#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28836#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28835#L567-33 assume !(1 == ~t5_pc~0); 28833#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 28832#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28831#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28830#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28829#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28828#L586-33 assume 1 == ~t6_pc~0; 28826#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28825#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28824#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28652#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28651#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28650#L605-33 assume !(1 == ~t7_pc~0); 28647#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 28644#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28642#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28640#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28638#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28636#L624-33 assume 1 == ~t8_pc~0; 28633#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28630#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28628#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28626#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 28624#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27015#L643-33 assume 1 == ~t9_pc~0; 27016#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27097#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27575#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27530#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27531#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26883#L1059-3 assume !(1 == ~M_E~0); 26884#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27395#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27454#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27455#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27745#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27644#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27573#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27574#L1094-3 assume !(1 == ~T8_E~0); 27488#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27489#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27767#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27753#L1114-3 assume !(1 == ~E_2~0); 27754#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27990#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27994#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27184#L1134-3 assume !(1 == ~E_6~0); 27185#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27357#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27358#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27536#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27997#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26888#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28161#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28160#L1459 assume !(0 == start_simulation_~tmp~3#1); 27909#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28045#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28035#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28034#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28033#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 28032#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28031#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 27828#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 26983#L1440-2 [2024-10-13 17:44:59,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:59,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2024-10-13 17:44:59,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:59,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318264733] [2024-10-13 17:44:59,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:59,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:59,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:59,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:59,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:59,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318264733] [2024-10-13 17:44:59,286 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318264733] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:59,287 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:59,287 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:44:59,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502152546] [2024-10-13 17:44:59,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:59,287 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:59,287 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:59,288 INFO L85 PathProgramCache]: Analyzing trace with hash -627598118, now seen corresponding path program 1 times [2024-10-13 17:44:59,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:59,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972632169] [2024-10-13 17:44:59,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:59,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:59,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:59,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:59,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:59,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [972632169] [2024-10-13 17:44:59,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [972632169] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:59,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:59,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:59,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244660344] [2024-10-13 17:44:59,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:59,327 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:59,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:59,329 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:59,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:59,329 INFO L87 Difference]: Start difference. First operand 2171 states and 3171 transitions. cyclomatic complexity: 1002 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:59,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:59,419 INFO L93 Difference]: Finished difference Result 4157 states and 6014 transitions. [2024-10-13 17:44:59,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4157 states and 6014 transitions. [2024-10-13 17:44:59,431 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4007 [2024-10-13 17:44:59,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4157 states to 4157 states and 6014 transitions. [2024-10-13 17:44:59,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4157 [2024-10-13 17:44:59,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4157 [2024-10-13 17:44:59,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4157 states and 6014 transitions. [2024-10-13 17:44:59,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:59,449 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4157 states and 6014 transitions. [2024-10-13 17:44:59,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4157 states and 6014 transitions. [2024-10-13 17:44:59,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4157 to 4019. [2024-10-13 17:44:59,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4019 states, 4019 states have (on average 1.4486190594675292) internal successors, (5822), 4018 states have internal predecessors, (5822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:59,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4019 states to 4019 states and 5822 transitions. [2024-10-13 17:44:59,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4019 states and 5822 transitions. [2024-10-13 17:44:59,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:59,502 INFO L425 stractBuchiCegarLoop]: Abstraction has 4019 states and 5822 transitions. [2024-10-13 17:44:59,502 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-13 17:44:59,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4019 states and 5822 transitions. [2024-10-13 17:44:59,511 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3869 [2024-10-13 17:44:59,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:59,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:59,512 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:59,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:59,512 INFO L745 eck$LassoCheckResult]: Stem: 33470#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33471#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 34329#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34330#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33985#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 33684#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33685#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34289#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34361#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34346#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34347#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33826#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33811#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33812#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33598#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33599#L951 assume !(0 == ~M_E~0); 33328#L951-2 assume !(0 == ~T1_E~0); 33329#L956-1 assume !(0 == ~T2_E~0); 33492#L961-1 assume !(0 == ~T3_E~0); 34004#L966-1 assume !(0 == ~T4_E~0); 34005#L971-1 assume !(0 == ~T5_E~0); 34148#L976-1 assume !(0 == ~T6_E~0); 34120#L981-1 assume !(0 == ~T7_E~0); 33867#L986-1 assume !(0 == ~T8_E~0); 33546#L991-1 assume !(0 == ~T9_E~0); 33547#L996-1 assume !(0 == ~E_M~0); 34402#L1001-1 assume !(0 == ~E_1~0); 34058#L1006-1 assume !(0 == ~E_2~0); 34059#L1011-1 assume !(0 == ~E_3~0); 34362#L1016-1 assume !(0 == ~E_4~0); 34377#L1021-1 assume !(0 == ~E_5~0); 33119#L1026-1 assume !(0 == ~E_6~0); 33120#L1031-1 assume !(0 == ~E_7~0); 34012#L1036-1 assume !(0 == ~E_8~0); 34007#L1041-1 assume !(0 == ~E_9~0); 34008#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34303#L472 assume !(1 == ~m_pc~0); 34247#L472-2 is_master_triggered_~__retres1~0#1 := 0; 34038#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34039#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34048#L1179 assume !(0 != activate_threads_~tmp~1#1); 33127#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33128#L491 assume 1 == ~t1_pc~0; 34057#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33648#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33153#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33100#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 33101#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33121#L510 assume !(1 == ~t2_pc~0); 33089#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33090#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33671#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33672#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33383#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33384#L529 assume 1 == ~t3_pc~0; 33770#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33771#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33098#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33099#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 33303#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33304#L548 assume !(1 == ~t4_pc~0); 33194#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33193#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33267#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33236#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 33237#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33181#L567 assume 1 == ~t5_pc~0; 33182#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33238#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34231#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34232#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 34282#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33314#L586 assume !(1 == ~t6_pc~0); 33315#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33387#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33653#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33654#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 34274#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34275#L605 assume 1 == ~t7_pc~0; 34239#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33847#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34041#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34450#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 34446#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33979#L624 assume !(1 == ~t8_pc~0); 33378#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33377#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34103#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34172#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 34251#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33144#L643 assume 1 == ~t9_pc~0; 33145#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34195#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33733#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33553#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 33554#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33360#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 33361#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36365#L1064-1 assume !(1 == ~T2_E~0); 36364#L1069-1 assume !(1 == ~T3_E~0); 36363#L1074-1 assume !(1 == ~T4_E~0); 34442#L1079-1 assume !(1 == ~T5_E~0); 36362#L1084-1 assume !(1 == ~T6_E~0); 36361#L1089-1 assume !(1 == ~T7_E~0); 36360#L1094-1 assume !(1 == ~T8_E~0); 36359#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36358#L1104-1 assume !(1 == ~E_M~0); 36357#L1109-1 assume !(1 == ~E_1~0); 36356#L1114-1 assume !(1 == ~E_2~0); 36355#L1119-1 assume !(1 == ~E_3~0); 36354#L1124-1 assume !(1 == ~E_4~0); 36353#L1129-1 assume !(1 == ~E_5~0); 36352#L1134-1 assume !(1 == ~E_6~0); 36351#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 36350#L1144-1 assume !(1 == ~E_8~0); 36349#L1149-1 assume !(1 == ~E_9~0); 36348#L1154-1 assume { :end_inline_reset_delta_events } true; 34909#L1440-2 [2024-10-13 17:44:59,513 INFO L747 eck$LassoCheckResult]: Loop: 34909#L1440-2 assume !false; 34910#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34323#L926-1 assume !false; 34324#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34155#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33457#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33700#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33701#L795 assume !(0 != eval_~tmp~0#1); 36288#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36860#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36859#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36858#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36857#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36856#L961-3 assume !(0 == ~T3_E~0); 36855#L966-3 assume !(0 == ~T4_E~0); 36854#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36853#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36852#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36851#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36850#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36849#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36848#L1001-3 assume !(0 == ~E_1~0); 36847#L1006-3 assume !(0 == ~E_2~0); 36846#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36845#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36844#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36843#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36842#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36841#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36840#L1041-3 assume !(0 == ~E_9~0); 36839#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36838#L472-33 assume !(1 == ~m_pc~0); 36837#L472-35 is_master_triggered_~__retres1~0#1 := 0; 36836#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36835#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36834#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36833#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36832#L491-33 assume 1 == ~t1_pc~0; 36830#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36829#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36828#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36827#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 36826#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36825#L510-33 assume !(1 == ~t2_pc~0); 36823#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 36822#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36821#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36820#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36819#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36818#L529-33 assume !(1 == ~t3_pc~0); 36816#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 36815#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36814#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36813#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36812#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36811#L548-33 assume 1 == ~t4_pc~0; 36809#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36808#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36807#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36806#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36805#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36804#L567-33 assume !(1 == ~t5_pc~0); 36802#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 36801#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36800#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36799#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36798#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36797#L586-33 assume 1 == ~t6_pc~0; 36795#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36794#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36793#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36792#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36791#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36790#L605-33 assume !(1 == ~t7_pc~0); 36788#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 36787#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36786#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36785#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36784#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36783#L624-33 assume 1 == ~t8_pc~0; 36781#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36780#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36779#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36778#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 36777#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36776#L643-33 assume 1 == ~t9_pc~0; 36774#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36773#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36772#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36771#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36770#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36769#L1059-3 assume !(1 == ~M_E~0); 33220#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36768#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36767#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36766#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34121#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36765#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36764#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36763#L1094-3 assume !(1 == ~T8_E~0); 36762#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36761#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36760#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36759#L1114-3 assume !(1 == ~E_2~0); 36758#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36757#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36756#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36755#L1134-3 assume !(1 == ~E_6~0); 36754#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36753#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36752#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36751#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 36749#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36740#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36739#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 36738#L1459 assume !(0 == start_simulation_~tmp~3#1); 35012#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 36736#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36727#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36726#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 36725#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 36724#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36723#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 36347#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 34909#L1440-2 [2024-10-13 17:44:59,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:59,513 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2024-10-13 17:44:59,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:59,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936535152] [2024-10-13 17:44:59,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:59,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:59,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:59,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:59,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:59,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936535152] [2024-10-13 17:44:59,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936535152] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:59,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:59,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:44:59,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35010815] [2024-10-13 17:44:59,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:59,546 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:59,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:59,547 INFO L85 PathProgramCache]: Analyzing trace with hash -486498597, now seen corresponding path program 1 times [2024-10-13 17:44:59,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:59,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28729047] [2024-10-13 17:44:59,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:59,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:59,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:59,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:59,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:59,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [28729047] [2024-10-13 17:44:59,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [28729047] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:59,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:59,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:59,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022799451] [2024-10-13 17:44:59,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:59,616 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:59,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:59,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:44:59,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:44:59,617 INFO L87 Difference]: Start difference. First operand 4019 states and 5822 transitions. cyclomatic complexity: 1807 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:59,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:44:59,702 INFO L93 Difference]: Finished difference Result 7561 states and 10882 transitions. [2024-10-13 17:44:59,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7561 states and 10882 transitions. [2024-10-13 17:44:59,728 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7400 [2024-10-13 17:44:59,748 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7561 states to 7561 states and 10882 transitions. [2024-10-13 17:44:59,748 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7561 [2024-10-13 17:44:59,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7561 [2024-10-13 17:44:59,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7561 states and 10882 transitions. [2024-10-13 17:44:59,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:44:59,760 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7561 states and 10882 transitions. [2024-10-13 17:44:59,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7561 states and 10882 transitions. [2024-10-13 17:44:59,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7561 to 7553. [2024-10-13 17:44:59,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7553 states, 7553 states have (on average 1.4396928372831987) internal successors, (10874), 7552 states have internal predecessors, (10874), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:44:59,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7553 states to 7553 states and 10874 transitions. [2024-10-13 17:44:59,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7553 states and 10874 transitions. [2024-10-13 17:44:59,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:44:59,855 INFO L425 stractBuchiCegarLoop]: Abstraction has 7553 states and 10874 transitions. [2024-10-13 17:44:59,855 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-13 17:44:59,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7553 states and 10874 transitions. [2024-10-13 17:44:59,873 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7392 [2024-10-13 17:44:59,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:44:59,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:44:59,874 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:59,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:44:59,875 INFO L745 eck$LassoCheckResult]: Stem: 45051#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 45052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 45865#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45536#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 45252#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45253#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45840#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45893#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45876#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45877#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45388#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45373#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45374#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45173#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45174#L951 assume !(0 == ~M_E~0); 44912#L951-2 assume !(0 == ~T1_E~0); 44913#L956-1 assume !(0 == ~T2_E~0); 45072#L961-1 assume !(0 == ~T3_E~0); 45560#L966-1 assume !(0 == ~T4_E~0); 45561#L971-1 assume !(0 == ~T5_E~0); 45693#L976-1 assume !(0 == ~T6_E~0); 45667#L981-1 assume !(0 == ~T7_E~0); 45425#L986-1 assume !(0 == ~T8_E~0); 45123#L991-1 assume !(0 == ~T9_E~0); 45124#L996-1 assume !(0 == ~E_M~0); 45929#L1001-1 assume !(0 == ~E_1~0); 45616#L1006-1 assume !(0 == ~E_2~0); 45617#L1011-1 assume !(0 == ~E_3~0); 45894#L1016-1 assume !(0 == ~E_4~0); 45909#L1021-1 assume !(0 == ~E_5~0); 44706#L1026-1 assume !(0 == ~E_6~0); 44707#L1031-1 assume !(0 == ~E_7~0); 45569#L1036-1 assume !(0 == ~E_8~0); 45565#L1041-1 assume !(0 == ~E_9~0); 45566#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45851#L472 assume !(1 == ~m_pc~0); 45797#L472-2 is_master_triggered_~__retres1~0#1 := 0; 45596#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45597#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45605#L1179 assume !(0 != activate_threads_~tmp~1#1); 44714#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44715#L491 assume !(1 == ~t1_pc~0); 45218#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45219#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44740#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44687#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 44688#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44708#L510 assume !(1 == ~t2_pc~0); 44676#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44677#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45241#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45242#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44967#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44968#L529 assume 1 == ~t3_pc~0; 45333#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45334#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44685#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44686#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 44887#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44888#L548 assume !(1 == ~t4_pc~0); 44781#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44780#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44852#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44821#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 44822#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44768#L567 assume 1 == ~t5_pc~0; 44769#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44823#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45780#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45781#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 45834#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44898#L586 assume !(1 == ~t6_pc~0); 44899#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 44971#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45224#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45225#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 45824#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45825#L605 assume 1 == ~t7_pc~0; 45788#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45408#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45598#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45968#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 45967#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45530#L624 assume !(1 == ~t8_pc~0); 44962#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44961#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45651#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45717#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 45802#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44731#L643 assume 1 == ~t9_pc~0; 44732#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45743#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45295#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45128#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 45129#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44944#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 44945#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45100#L1064-1 assume !(1 == ~T2_E~0); 45101#L1069-1 assume !(1 == ~T3_E~0); 45751#L1074-1 assume !(1 == ~T4_E~0); 45800#L1079-1 assume !(1 == ~T5_E~0); 45786#L1084-1 assume !(1 == ~T6_E~0); 45787#L1089-1 assume !(1 == ~T7_E~0); 45818#L1094-1 assume !(1 == ~T8_E~0); 45464#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45465#L1104-1 assume !(1 == ~E_M~0); 45653#L1109-1 assume !(1 == ~E_1~0); 45654#L1114-1 assume !(1 == ~E_2~0); 48599#L1119-1 assume !(1 == ~E_3~0); 48597#L1124-1 assume !(1 == ~E_4~0); 48596#L1129-1 assume !(1 == ~E_5~0); 48595#L1134-1 assume !(1 == ~E_6~0); 45068#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 45069#L1144-1 assume !(1 == ~E_8~0); 45260#L1149-1 assume !(1 == ~E_9~0); 48565#L1154-1 assume { :end_inline_reset_delta_events } true; 48557#L1440-2 [2024-10-13 17:44:59,875 INFO L747 eck$LassoCheckResult]: Loop: 48557#L1440-2 assume !false; 48551#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48547#L926-1 assume !false; 48546#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 48544#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 48535#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 48534#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48531#L795 assume !(0 != eval_~tmp~0#1); 48532#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51210#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50442#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50432#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50417#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50404#L961-3 assume !(0 == ~T3_E~0); 50403#L966-3 assume !(0 == ~T4_E~0); 50401#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50398#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50396#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50394#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50393#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50392#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50390#L1001-3 assume !(0 == ~E_1~0); 50388#L1006-3 assume !(0 == ~E_2~0); 50385#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50383#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50381#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50379#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50378#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50377#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49790#L1041-3 assume !(0 == ~E_9~0); 49789#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49787#L472-33 assume !(1 == ~m_pc~0); 49785#L472-35 is_master_triggered_~__retres1~0#1 := 0; 49784#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49783#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49638#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49635#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49633#L491-33 assume !(1 == ~t1_pc~0); 49631#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 49629#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49627#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49625#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 49624#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49621#L510-33 assume !(1 == ~t2_pc~0); 49618#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 49616#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49614#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49612#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49610#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49609#L529-33 assume !(1 == ~t3_pc~0); 49607#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 44978#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44861#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44862#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44802#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44803#L548-33 assume 1 == ~t4_pc~0; 45053#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45175#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45623#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45898#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49359#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49358#L567-33 assume !(1 == ~t5_pc~0); 49356#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 49355#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49353#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49351#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49349#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49347#L586-33 assume 1 == ~t6_pc~0; 49344#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49342#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49340#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49338#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49336#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49334#L605-33 assume !(1 == ~t7_pc~0); 49331#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 49329#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49326#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49324#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49322#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49320#L624-33 assume 1 == ~t8_pc~0; 49317#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49315#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49313#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49310#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 49308#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49306#L643-33 assume 1 == ~t9_pc~0; 45562#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45022#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45504#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45460#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45461#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44804#L1059-3 assume !(1 == ~M_E~0); 44805#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45321#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45385#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45386#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45668#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45570#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45502#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45503#L1094-3 assume !(1 == ~T8_E~0); 45417#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45418#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45691#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45677#L1114-3 assume !(1 == ~E_2~0); 45678#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45953#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49248#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49244#L1134-3 assume !(1 == ~E_6~0); 49241#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49238#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49235#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49232#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 48730#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 48719#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 48717#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 48715#L1459 assume !(0 == start_simulation_~tmp~3#1); 48712#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 48691#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 48681#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 48594#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 48593#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 48591#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48573#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 48564#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 48557#L1440-2 [2024-10-13 17:44:59,876 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:59,876 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2024-10-13 17:44:59,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:59,876 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468641542] [2024-10-13 17:44:59,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:59,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:59,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:59,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:59,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:59,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [468641542] [2024-10-13 17:44:59,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [468641542] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:59,920 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:59,920 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:44:59,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075798270] [2024-10-13 17:44:59,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:59,920 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:44:59,921 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:44:59,921 INFO L85 PathProgramCache]: Analyzing trace with hash -1971738788, now seen corresponding path program 1 times [2024-10-13 17:44:59,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:44:59,921 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036008558] [2024-10-13 17:44:59,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:44:59,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:44:59,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:44:59,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:44:59,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:44:59,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036008558] [2024-10-13 17:44:59,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036008558] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:44:59,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:44:59,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:44:59,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557328445] [2024-10-13 17:44:59,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:44:59,951 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:44:59,951 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:44:59,951 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:44:59,951 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:44:59,951 INFO L87 Difference]: Start difference. First operand 7553 states and 10874 transitions. cyclomatic complexity: 3329 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:00,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:00,151 INFO L93 Difference]: Finished difference Result 7565 states and 10805 transitions. [2024-10-13 17:45:00,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7565 states and 10805 transitions. [2024-10-13 17:45:00,180 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7404 [2024-10-13 17:45:00,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7565 states to 7565 states and 10805 transitions. [2024-10-13 17:45:00,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7565 [2024-10-13 17:45:00,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7565 [2024-10-13 17:45:00,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7565 states and 10805 transitions. [2024-10-13 17:45:00,211 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:00,211 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7565 states and 10805 transitions. [2024-10-13 17:45:00,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7565 states and 10805 transitions. [2024-10-13 17:45:00,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7565 to 7565. [2024-10-13 17:45:00,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7565 states, 7565 states have (on average 1.4282881692002645) internal successors, (10805), 7564 states have internal predecessors, (10805), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:00,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7565 states to 7565 states and 10805 transitions. [2024-10-13 17:45:00,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7565 states and 10805 transitions. [2024-10-13 17:45:00,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:45:00,317 INFO L425 stractBuchiCegarLoop]: Abstraction has 7565 states and 10805 transitions. [2024-10-13 17:45:00,318 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-13 17:45:00,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7565 states and 10805 transitions. [2024-10-13 17:45:00,341 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7404 [2024-10-13 17:45:00,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:00,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:00,343 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:00,343 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:00,343 INFO L745 eck$LassoCheckResult]: Stem: 60176#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 60177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 60959#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60960#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60656#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 60375#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60376#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60939#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60983#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60968#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60969#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60507#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60494#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60495#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60297#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60298#L951 assume !(0 == ~M_E~0); 60038#L951-2 assume !(0 == ~T1_E~0); 60039#L956-1 assume !(0 == ~T2_E~0); 60197#L961-1 assume !(0 == ~T3_E~0); 60679#L966-1 assume !(0 == ~T4_E~0); 60680#L971-1 assume !(0 == ~T5_E~0); 60807#L976-1 assume !(0 == ~T6_E~0); 60781#L981-1 assume !(0 == ~T7_E~0); 60544#L986-1 assume !(0 == ~T8_E~0); 60247#L991-1 assume !(0 == ~T9_E~0); 60248#L996-1 assume !(0 == ~E_M~0); 61012#L1001-1 assume !(0 == ~E_1~0); 60732#L1006-1 assume !(0 == ~E_2~0); 60733#L1011-1 assume !(0 == ~E_3~0); 60984#L1016-1 assume !(0 == ~E_4~0); 60994#L1021-1 assume !(0 == ~E_5~0); 59833#L1026-1 assume !(0 == ~E_6~0); 59834#L1031-1 assume !(0 == ~E_7~0); 60687#L1036-1 assume !(0 == ~E_8~0); 60683#L1041-1 assume !(0 == ~E_9~0); 60684#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60946#L472 assume !(1 == ~m_pc~0); 60901#L472-2 is_master_triggered_~__retres1~0#1 := 0; 60711#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60712#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 60721#L1179 assume !(0 != activate_threads_~tmp~1#1); 59841#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59842#L491 assume !(1 == ~t1_pc~0); 60343#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60344#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59814#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 59815#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59835#L510 assume !(1 == ~t2_pc~0); 59803#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59804#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60366#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60367#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 60094#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60095#L529 assume 1 == ~t3_pc~0; 60455#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60456#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59812#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59813#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 60013#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60014#L548 assume !(1 == ~t4_pc~0); 59908#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59907#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59980#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59948#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 59949#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59895#L567 assume 1 == ~t5_pc~0; 59896#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59950#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60887#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60888#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 60933#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60024#L586 assume !(1 == ~t6_pc~0); 60025#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 60098#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60349#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60350#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 60924#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60925#L605 assume 1 == ~t7_pc~0; 60895#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 60527#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60714#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61048#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 61046#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60649#L624 assume !(1 == ~t8_pc~0); 60089#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 60088#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60765#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60829#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 60906#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59858#L643 assume 1 == ~t9_pc~0; 59859#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60854#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60417#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60252#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 60253#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60070#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 60071#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63904#L1064-1 assume !(1 == ~T2_E~0); 60862#L1069-1 assume !(1 == ~T3_E~0); 60863#L1074-1 assume !(1 == ~T4_E~0); 61045#L1079-1 assume !(1 == ~T5_E~0); 60893#L1084-1 assume !(1 == ~T6_E~0); 60894#L1089-1 assume !(1 == ~T7_E~0); 60920#L1094-1 assume !(1 == ~T8_E~0); 60581#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60582#L1104-1 assume !(1 == ~E_M~0); 60990#L1109-1 assume !(1 == ~E_1~0); 60368#L1114-1 assume !(1 == ~E_2~0); 60369#L1119-1 assume !(1 == ~E_3~0); 60429#L1124-1 assume !(1 == ~E_4~0); 59854#L1129-1 assume !(1 == ~E_5~0); 59855#L1134-1 assume !(1 == ~E_6~0); 60193#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 60194#L1144-1 assume !(1 == ~E_8~0); 60383#L1149-1 assume !(1 == ~E_9~0); 60030#L1154-1 assume { :end_inline_reset_delta_events } true; 60031#L1440-2 [2024-10-13 17:45:00,344 INFO L747 eck$LassoCheckResult]: Loop: 60031#L1440-2 assume !false; 64304#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64300#L926-1 assume !false; 64299#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64297#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64288#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64287#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 64285#L795 assume !(0 != eval_~tmp~0#1); 64284#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64283#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64282#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64281#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64280#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64279#L961-3 assume !(0 == ~T3_E~0); 64278#L966-3 assume !(0 == ~T4_E~0); 64277#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64276#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64275#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64274#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64273#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64272#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64271#L1001-3 assume !(0 == ~E_1~0); 64270#L1006-3 assume !(0 == ~E_2~0); 64269#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64268#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 64267#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64266#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64265#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64264#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64263#L1041-3 assume !(0 == ~E_9~0); 64262#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64261#L472-33 assume !(1 == ~m_pc~0); 64260#L472-35 is_master_triggered_~__retres1~0#1 := 0; 64259#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64258#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64257#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 64256#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64255#L491-33 assume !(1 == ~t1_pc~0); 64254#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 64253#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64252#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64251#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 64250#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64249#L510-33 assume !(1 == ~t2_pc~0); 64247#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 64246#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64245#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64244#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 64243#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64242#L529-33 assume !(1 == ~t3_pc~0); 64240#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 64239#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64238#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64237#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64236#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64235#L548-33 assume 1 == ~t4_pc~0; 64233#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64232#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64231#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64230#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64229#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64228#L567-33 assume !(1 == ~t5_pc~0); 64226#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 64224#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64222#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64219#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64216#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64213#L586-33 assume 1 == ~t6_pc~0; 64209#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64206#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64202#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64199#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64195#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64192#L605-33 assume !(1 == ~t7_pc~0); 64188#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 64184#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64181#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64177#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64174#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64171#L624-33 assume 1 == ~t8_pc~0; 64167#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64163#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64158#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64154#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 64149#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64145#L643-33 assume !(1 == ~t9_pc~0); 60145#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 60146#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60622#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60577#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60578#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59931#L1059-3 assume !(1 == ~M_E~0); 59932#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60443#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60504#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60505#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60782#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60688#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60620#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60621#L1094-3 assume !(1 == ~T8_E~0); 60536#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60537#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 60805#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60791#L1114-3 assume !(1 == ~E_2~0); 60792#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61035#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61042#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60232#L1134-3 assume !(1 == ~E_6~0); 60233#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60405#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60406#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60583#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 61049#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 59936#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 60317#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 59820#L1459 assume !(0 == start_simulation_~tmp~3#1); 59821#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64428#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64418#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 64347#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 64335#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64324#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 64316#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 60031#L1440-2 [2024-10-13 17:45:00,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:00,344 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2024-10-13 17:45:00,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:00,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160191824] [2024-10-13 17:45:00,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:00,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:00,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:00,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:00,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:00,391 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160191824] [2024-10-13 17:45:00,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160191824] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:00,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:00,392 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:00,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170120290] [2024-10-13 17:45:00,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:00,392 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:00,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:00,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1393365727, now seen corresponding path program 1 times [2024-10-13 17:45:00,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:00,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269232248] [2024-10-13 17:45:00,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:00,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:00,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:00,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:00,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:00,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269232248] [2024-10-13 17:45:00,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1269232248] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:00,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:00,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:00,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1724451838] [2024-10-13 17:45:00,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:00,424 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:00,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:00,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:00,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:00,424 INFO L87 Difference]: Start difference. First operand 7565 states and 10805 transitions. cyclomatic complexity: 3248 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:00,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:00,525 INFO L93 Difference]: Finished difference Result 14324 states and 20346 transitions. [2024-10-13 17:45:00,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14324 states and 20346 transitions. [2024-10-13 17:45:00,574 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14140 [2024-10-13 17:45:00,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14324 states to 14324 states and 20346 transitions. [2024-10-13 17:45:00,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14324 [2024-10-13 17:45:00,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14324 [2024-10-13 17:45:00,671 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14324 states and 20346 transitions. [2024-10-13 17:45:00,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:00,678 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14324 states and 20346 transitions. [2024-10-13 17:45:00,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14324 states and 20346 transitions. [2024-10-13 17:45:00,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14324 to 14308. [2024-10-13 17:45:00,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14308 states, 14308 states have (on average 1.4208834218618955) internal successors, (20330), 14307 states have internal predecessors, (20330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:00,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14308 states to 14308 states and 20330 transitions. [2024-10-13 17:45:00,837 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14308 states and 20330 transitions. [2024-10-13 17:45:00,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:00,838 INFO L425 stractBuchiCegarLoop]: Abstraction has 14308 states and 20330 transitions. [2024-10-13 17:45:00,838 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-13 17:45:00,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14308 states and 20330 transitions. [2024-10-13 17:45:00,870 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14124 [2024-10-13 17:45:00,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:00,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:00,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:00,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:00,871 INFO L745 eck$LassoCheckResult]: Stem: 82072#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 82073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 82893#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82576#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 82282#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82283#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82868#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82917#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82905#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82906#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82416#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82402#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82403#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82199#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82200#L951 assume !(0 == ~M_E~0); 81935#L951-2 assume !(0 == ~T1_E~0); 81936#L956-1 assume !(0 == ~T2_E~0); 82097#L961-1 assume !(0 == ~T3_E~0); 82597#L966-1 assume !(0 == ~T4_E~0); 82598#L971-1 assume !(0 == ~T5_E~0); 82729#L976-1 assume !(0 == ~T6_E~0); 82703#L981-1 assume !(0 == ~T7_E~0); 82457#L986-1 assume !(0 == ~T8_E~0); 82147#L991-1 assume !(0 == ~T9_E~0); 82148#L996-1 assume !(0 == ~E_M~0); 82948#L1001-1 assume !(0 == ~E_1~0); 82648#L1006-1 assume !(0 == ~E_2~0); 82649#L1011-1 assume !(0 == ~E_3~0); 82918#L1016-1 assume !(0 == ~E_4~0); 82930#L1021-1 assume !(0 == ~E_5~0); 81729#L1026-1 assume !(0 == ~E_6~0); 81730#L1031-1 assume !(0 == ~E_7~0); 82604#L1036-1 assume !(0 == ~E_8~0); 82600#L1041-1 assume !(0 == ~E_9~0); 82601#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82876#L472 assume !(1 == ~m_pc~0); 82826#L472-2 is_master_triggered_~__retres1~0#1 := 0; 82629#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82630#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82639#L1179 assume !(0 != activate_threads_~tmp~1#1); 81737#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81738#L491 assume !(1 == ~t1_pc~0); 82248#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82249#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81763#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81710#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 81711#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81731#L510 assume !(1 == ~t2_pc~0); 81699#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81700#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82271#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82272#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 81990#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81991#L529 assume !(1 == ~t3_pc~0); 82466#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82756#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81708#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81709#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 81910#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81911#L548 assume !(1 == ~t4_pc~0); 81804#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81803#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81877#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81845#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 81846#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81791#L567 assume 1 == ~t5_pc~0; 81792#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 81847#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82809#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82810#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 82861#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81921#L586 assume !(1 == ~t6_pc~0); 81922#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 81994#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82254#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82255#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 82852#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82853#L605 assume 1 == ~t7_pc~0; 82816#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82436#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82632#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82995#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 82993#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82569#L624 assume !(1 == ~t8_pc~0); 81985#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 81984#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82687#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82752#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 82831#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81754#L643 assume 1 == ~t9_pc~0; 81755#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82776#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82328#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82152#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 82153#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81967#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 81968#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86726#L1064-1 assume !(1 == ~T2_E~0); 86725#L1069-1 assume !(1 == ~T3_E~0); 86724#L1074-1 assume !(1 == ~T4_E~0); 82989#L1079-1 assume !(1 == ~T5_E~0); 86723#L1084-1 assume !(1 == ~T6_E~0); 86722#L1089-1 assume !(1 == ~T7_E~0); 86721#L1094-1 assume !(1 == ~T8_E~0); 86720#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86719#L1104-1 assume !(1 == ~E_M~0); 86718#L1109-1 assume !(1 == ~E_1~0); 86717#L1114-1 assume !(1 == ~E_2~0); 86716#L1119-1 assume !(1 == ~E_3~0); 86715#L1124-1 assume !(1 == ~E_4~0); 86714#L1129-1 assume !(1 == ~E_5~0); 86713#L1134-1 assume !(1 == ~E_6~0); 86712#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 86711#L1144-1 assume !(1 == ~E_8~0); 83004#L1149-1 assume !(1 == ~E_9~0); 81927#L1154-1 assume { :end_inline_reset_delta_events } true; 81928#L1440-2 [2024-10-13 17:45:00,872 INFO L747 eck$LassoCheckResult]: Loop: 81928#L1440-2 assume !false; 85297#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85189#L926-1 assume !false; 85190#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 85055#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 85047#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 85026#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 85027#L795 assume !(0 != eval_~tmp~0#1); 86677#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86675#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86672#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 86673#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87257#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87256#L961-3 assume !(0 == ~T3_E~0); 87255#L966-3 assume !(0 == ~T4_E~0); 87254#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87253#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 87252#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 87251#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 87250#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 87249#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87248#L1001-3 assume !(0 == ~E_1~0); 87247#L1006-3 assume !(0 == ~E_2~0); 87246#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87245#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87244#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 87243#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 87242#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 87241#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 87240#L1041-3 assume !(0 == ~E_9~0); 87239#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87238#L472-33 assume !(1 == ~m_pc~0); 87237#L472-35 is_master_triggered_~__retres1~0#1 := 0; 87236#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87235#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 87234#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 87233#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87232#L491-33 assume !(1 == ~t1_pc~0); 87231#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 87230#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87229#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87228#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 87227#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87226#L510-33 assume !(1 == ~t2_pc~0); 87224#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 87223#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87222#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87221#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 87220#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87219#L529-33 assume !(1 == ~t3_pc~0); 87218#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 87217#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87216#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87215#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87214#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87213#L548-33 assume 1 == ~t4_pc~0; 87211#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 87210#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87209#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87208#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87207#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87206#L567-33 assume 1 == ~t5_pc~0; 87205#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87203#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87202#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87201#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87200#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87199#L586-33 assume 1 == ~t6_pc~0; 87197#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 87196#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87195#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87194#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87193#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87192#L605-33 assume 1 == ~t7_pc~0; 87191#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 87189#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87188#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87187#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 87186#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87185#L624-33 assume !(1 == ~t8_pc~0); 87184#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 87182#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87181#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87180#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 87179#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87178#L643-33 assume !(1 == ~t9_pc~0); 87177#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 87175#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87174#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87173#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 87172#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87171#L1059-3 assume !(1 == ~M_E~0); 86430#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87170#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87169#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87168#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86420#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87167#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 87166#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87165#L1094-3 assume !(1 == ~T8_E~0); 87164#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 87163#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87162#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87161#L1114-3 assume !(1 == ~E_2~0); 87160#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87159#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87158#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87157#L1134-3 assume !(1 == ~E_6~0); 87156#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87155#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 87154#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86339#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 86340#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 86318#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 86319#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 85335#L1459 assume !(0 == start_simulation_~tmp~3#1); 85334#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 85322#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 85312#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 85310#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 85307#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 85308#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86694#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 85299#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 81928#L1440-2 [2024-10-13 17:45:00,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:00,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2024-10-13 17:45:00,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:00,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773013149] [2024-10-13 17:45:00,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:00,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:00,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:00,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:00,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:00,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773013149] [2024-10-13 17:45:00,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773013149] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:00,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:00,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:00,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860877565] [2024-10-13 17:45:00,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:00,904 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:00,904 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:00,905 INFO L85 PathProgramCache]: Analyzing trace with hash 2043800606, now seen corresponding path program 1 times [2024-10-13 17:45:00,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:00,905 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135682914] [2024-10-13 17:45:00,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:00,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:00,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:00,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:00,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:00,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135682914] [2024-10-13 17:45:00,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135682914] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:00,933 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:00,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:00,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210316917] [2024-10-13 17:45:00,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:00,933 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:00,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:00,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:00,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:00,934 INFO L87 Difference]: Start difference. First operand 14308 states and 20330 transitions. cyclomatic complexity: 6038 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:01,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:01,068 INFO L93 Difference]: Finished difference Result 27183 states and 38443 transitions. [2024-10-13 17:45:01,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27183 states and 38443 transitions. [2024-10-13 17:45:01,268 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26928 [2024-10-13 17:45:01,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27183 states to 27183 states and 38443 transitions. [2024-10-13 17:45:01,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27183 [2024-10-13 17:45:01,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27183 [2024-10-13 17:45:01,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27183 states and 38443 transitions. [2024-10-13 17:45:01,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:01,366 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27183 states and 38443 transitions. [2024-10-13 17:45:01,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27183 states and 38443 transitions. [2024-10-13 17:45:01,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27183 to 27151. [2024-10-13 17:45:01,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27151 states, 27151 states have (on average 1.414717689956171) internal successors, (38411), 27150 states have internal predecessors, (38411), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:01,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27151 states to 27151 states and 38411 transitions. [2024-10-13 17:45:01,753 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27151 states and 38411 transitions. [2024-10-13 17:45:01,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:01,753 INFO L425 stractBuchiCegarLoop]: Abstraction has 27151 states and 38411 transitions. [2024-10-13 17:45:01,754 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-13 17:45:01,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27151 states and 38411 transitions. [2024-10-13 17:45:01,824 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26896 [2024-10-13 17:45:01,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:01,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:01,826 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:01,826 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:01,826 INFO L745 eck$LassoCheckResult]: Stem: 123569#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 123570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 124384#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 124385#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 124060#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 123767#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 123768#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124351#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124407#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124397#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 124398#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123903#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 123888#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 123889#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123689#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123690#L951 assume !(0 == ~M_E~0); 123432#L951-2 assume !(0 == ~T1_E~0); 123433#L956-1 assume !(0 == ~T2_E~0); 123590#L961-1 assume !(0 == ~T3_E~0); 124080#L966-1 assume !(0 == ~T4_E~0); 124081#L971-1 assume !(0 == ~T5_E~0); 124208#L976-1 assume !(0 == ~T6_E~0); 124183#L981-1 assume !(0 == ~T7_E~0); 123939#L986-1 assume !(0 == ~T8_E~0); 123640#L991-1 assume !(0 == ~T9_E~0); 123641#L996-1 assume !(0 == ~E_M~0); 124438#L1001-1 assume !(0 == ~E_1~0); 124131#L1006-1 assume !(0 == ~E_2~0); 124132#L1011-1 assume !(0 == ~E_3~0); 124408#L1016-1 assume !(0 == ~E_4~0); 124424#L1021-1 assume !(0 == ~E_5~0); 123227#L1026-1 assume !(0 == ~E_6~0); 123228#L1031-1 assume !(0 == ~E_7~0); 124087#L1036-1 assume !(0 == ~E_8~0); 124083#L1041-1 assume !(0 == ~E_9~0); 124084#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124365#L472 assume !(1 == ~m_pc~0); 124308#L472-2 is_master_triggered_~__retres1~0#1 := 0; 124113#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124114#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124122#L1179 assume !(0 != activate_threads_~tmp~1#1); 123235#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123236#L491 assume !(1 == ~t1_pc~0); 123735#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123736#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123260#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123208#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 123209#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123229#L510 assume !(1 == ~t2_pc~0); 123197#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 123198#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123758#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123759#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 123488#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123489#L529 assume !(1 == ~t3_pc~0); 123948#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 124234#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123206#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123207#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 123407#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123408#L548 assume !(1 == ~t4_pc~0); 123299#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 123298#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123372#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123339#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 123340#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123287#L567 assume !(1 == ~t5_pc~0); 123288#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 123341#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124293#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124294#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 124345#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123418#L586 assume !(1 == ~t6_pc~0); 123419#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 123492#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123741#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 123742#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 124337#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124338#L605 assume 1 == ~t7_pc~0; 124300#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 123922#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124115#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124478#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 124476#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 124052#L624 assume !(1 == ~t8_pc~0); 123483#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 123482#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124168#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124229#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 124312#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123251#L643 assume 1 == ~t9_pc~0; 123252#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 124260#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123814#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123645#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 123646#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123464#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 123465#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124488#L1064-1 assume !(1 == ~T2_E~0); 134226#L1069-1 assume !(1 == ~T3_E~0); 134224#L1074-1 assume !(1 == ~T4_E~0); 124310#L1079-1 assume !(1 == ~T5_E~0); 124298#L1084-1 assume !(1 == ~T6_E~0); 124299#L1089-1 assume !(1 == ~T7_E~0); 124411#L1094-1 assume !(1 == ~T8_E~0); 134214#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 134211#L1104-1 assume !(1 == ~E_M~0); 134209#L1109-1 assume !(1 == ~E_1~0); 134207#L1114-1 assume !(1 == ~E_2~0); 134205#L1119-1 assume !(1 == ~E_3~0); 134203#L1124-1 assume !(1 == ~E_4~0); 134201#L1129-1 assume !(1 == ~E_5~0); 124064#L1134-1 assume !(1 == ~E_6~0); 123586#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 123587#L1144-1 assume !(1 == ~E_8~0); 123780#L1149-1 assume !(1 == ~E_9~0); 123424#L1154-1 assume { :end_inline_reset_delta_events } true; 123425#L1440-2 [2024-10-13 17:45:01,827 INFO L747 eck$LassoCheckResult]: Loop: 123425#L1440-2 assume !false; 137683#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 137675#L926-1 assume !false; 137668#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 137634#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 137619#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 137615#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 137608#L795 assume !(0 != eval_~tmp~0#1); 137609#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 149886#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 149885#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 149884#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 149883#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 149882#L961-3 assume !(0 == ~T3_E~0); 149881#L966-3 assume !(0 == ~T4_E~0); 149880#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 149879#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 149878#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 149877#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 149876#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 149874#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 149872#L1001-3 assume !(0 == ~E_1~0); 149870#L1006-3 assume !(0 == ~E_2~0); 149868#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 149865#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 149863#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 149861#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 149859#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 149857#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 149855#L1041-3 assume !(0 == ~E_9~0); 124265#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124217#L472-33 assume !(1 == ~m_pc~0); 123364#L472-35 is_master_triggered_~__retres1~0#1 := 0; 123365#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124251#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124225#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123819#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123820#L491-33 assume !(1 == ~t1_pc~0); 124463#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 149875#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 149873#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 149871#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 149869#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 149867#L510-33 assume !(1 == ~t2_pc~0); 149864#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 149862#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149860#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 149858#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 149856#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149854#L529-33 assume !(1 == ~t3_pc~0); 149853#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 149852#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149851#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 149850#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 149849#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 149848#L548-33 assume 1 == ~t4_pc~0; 149846#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 149845#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 149844#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 149842#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 149841#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 149840#L567-33 assume !(1 == ~t5_pc~0); 149839#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 149838#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 149835#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 149834#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 149828#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 149826#L586-33 assume !(1 == ~t6_pc~0); 149824#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 149821#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 149820#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 149818#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 149815#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 149813#L605-33 assume !(1 == ~t7_pc~0); 149810#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 149808#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 149806#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 149804#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 149801#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 149799#L624-33 assume 1 == ~t8_pc~0; 149796#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 149794#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 149792#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 149789#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 149787#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 149785#L643-33 assume 1 == ~t9_pc~0; 149782#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 149780#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 149778#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 149776#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 149775#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149774#L1059-3 assume !(1 == ~M_E~0); 134370#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 149773#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 149772#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 149770#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 134360#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 149766#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 149764#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 149762#L1094-3 assume !(1 == ~T8_E~0); 149760#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 149758#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 149757#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 149756#L1114-3 assume !(1 == ~E_2~0); 149755#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 149754#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 149753#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 149752#L1134-3 assume !(1 == ~E_6~0); 149751#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 149750#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 149749#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 149748#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 149746#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 149737#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 149736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 123214#L1459 assume !(0 == start_simulation_~tmp~3#1); 123215#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 137778#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 137744#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 137734#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 137721#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 137720#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 137719#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 137701#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 123425#L1440-2 [2024-10-13 17:45:01,827 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:01,827 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2024-10-13 17:45:01,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:01,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622557367] [2024-10-13 17:45:01,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:01,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:01,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:01,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:01,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:01,994 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622557367] [2024-10-13 17:45:01,994 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622557367] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:01,994 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:01,994 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:01,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338643712] [2024-10-13 17:45:01,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:01,994 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:01,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:01,995 INFO L85 PathProgramCache]: Analyzing trace with hash -1704405857, now seen corresponding path program 1 times [2024-10-13 17:45:01,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:01,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171946222] [2024-10-13 17:45:01,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:01,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:02,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:02,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:02,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:02,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171946222] [2024-10-13 17:45:02,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171946222] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:02,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:02,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:02,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795578093] [2024-10-13 17:45:02,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:02,032 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:02,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:02,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:02,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:02,033 INFO L87 Difference]: Start difference. First operand 27151 states and 38411 transitions. cyclomatic complexity: 11292 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:02,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:02,365 INFO L93 Difference]: Finished difference Result 63866 states and 89780 transitions. [2024-10-13 17:45:02,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63866 states and 89780 transitions. [2024-10-13 17:45:02,788 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63340 [2024-10-13 17:45:03,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63866 states to 63866 states and 89780 transitions. [2024-10-13 17:45:03,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63866 [2024-10-13 17:45:03,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63866 [2024-10-13 17:45:03,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63866 states and 89780 transitions. [2024-10-13 17:45:03,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:03,169 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63866 states and 89780 transitions. [2024-10-13 17:45:03,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63866 states and 89780 transitions. [2024-10-13 17:45:03,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63866 to 51550. [2024-10-13 17:45:03,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51550 states, 51550 states have (on average 1.4092725509214354) internal successors, (72648), 51549 states have internal predecessors, (72648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:03,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51550 states to 51550 states and 72648 transitions. [2024-10-13 17:45:03,939 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51550 states and 72648 transitions. [2024-10-13 17:45:03,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:03,939 INFO L425 stractBuchiCegarLoop]: Abstraction has 51550 states and 72648 transitions. [2024-10-13 17:45:03,940 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-13 17:45:03,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51550 states and 72648 transitions. [2024-10-13 17:45:04,078 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 51184 [2024-10-13 17:45:04,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:04,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:04,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:04,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:04,080 INFO L745 eck$LassoCheckResult]: Stem: 214592#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 214593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 215423#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 215424#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 215097#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 214798#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 214799#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 215390#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 215452#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215439#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215440#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 214932#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 214919#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 214920#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 214717#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 214718#L951 assume !(0 == ~M_E~0); 214455#L951-2 assume !(0 == ~T1_E~0); 214456#L956-1 assume !(0 == ~T2_E~0); 214617#L961-1 assume !(0 == ~T3_E~0); 215120#L966-1 assume !(0 == ~T4_E~0); 215121#L971-1 assume !(0 == ~T5_E~0); 215254#L976-1 assume !(0 == ~T6_E~0); 215227#L981-1 assume !(0 == ~T7_E~0); 214971#L986-1 assume !(0 == ~T8_E~0); 214669#L991-1 assume !(0 == ~T9_E~0); 214670#L996-1 assume !(0 == ~E_M~0); 215488#L1001-1 assume !(0 == ~E_1~0); 215173#L1006-1 assume !(0 == ~E_2~0); 215174#L1011-1 assume !(0 == ~E_3~0); 215453#L1016-1 assume !(0 == ~E_4~0); 215472#L1021-1 assume !(0 == ~E_5~0); 214254#L1026-1 assume !(0 == ~E_6~0); 214255#L1031-1 assume !(0 == ~E_7~0); 215127#L1036-1 assume !(0 == ~E_8~0); 215123#L1041-1 assume !(0 == ~E_9~0); 215124#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 215404#L472 assume !(1 == ~m_pc~0); 215352#L472-2 is_master_triggered_~__retres1~0#1 := 0; 215155#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 215156#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215164#L1179 assume !(0 != activate_threads_~tmp~1#1); 214262#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 214263#L491 assume !(1 == ~t1_pc~0); 214764#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 214765#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 214287#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214235#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 214236#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 214256#L510 assume !(1 == ~t2_pc~0); 214224#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 214225#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214787#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 214788#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 214511#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214512#L529 assume !(1 == ~t3_pc~0); 214980#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 215282#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214233#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 214234#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 214430#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214431#L548 assume !(1 == ~t4_pc~0); 214326#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 214325#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214397#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 214365#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 214366#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 214314#L567 assume !(1 == ~t5_pc~0); 214315#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 214367#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 215340#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215341#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 215384#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 214441#L586 assume !(1 == ~t6_pc~0); 214442#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 214515#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 214770#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 214771#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 215378#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 215379#L605 assume !(1 == ~t7_pc~0); 214950#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 214951#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 215157#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 215536#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 215535#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 215090#L624 assume !(1 == ~t8_pc~0); 214506#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 214505#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 215211#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 215277#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 215358#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 214278#L643 assume 1 == ~t9_pc~0; 214279#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 215305#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 214844#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 214674#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 214675#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 214487#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 214488#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 214646#L1064-1 assume !(1 == ~T2_E~0); 214647#L1069-1 assume !(1 == ~T3_E~0); 215529#L1074-1 assume !(1 == ~T4_E~0); 215530#L1079-1 assume !(1 == ~T5_E~0); 215345#L1084-1 assume !(1 == ~T6_E~0); 215346#L1089-1 assume !(1 == ~T7_E~0); 215372#L1094-1 assume !(1 == ~T8_E~0); 215373#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 215466#L1104-1 assume !(1 == ~E_M~0); 215467#L1109-1 assume !(1 == ~E_1~0); 214789#L1114-1 assume !(1 == ~E_2~0); 214790#L1119-1 assume !(1 == ~E_3~0); 214857#L1124-1 assume !(1 == ~E_4~0); 214858#L1129-1 assume !(1 == ~E_5~0); 215101#L1134-1 assume !(1 == ~E_6~0); 215102#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 214809#L1144-1 assume !(1 == ~E_8~0); 214810#L1149-1 assume !(1 == ~E_9~0); 214447#L1154-1 assume { :end_inline_reset_delta_events } true; 214448#L1440-2 [2024-10-13 17:45:04,081 INFO L747 eck$LassoCheckResult]: Loop: 214448#L1440-2 assume !false; 252143#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 252138#L926-1 assume !false; 252136#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 252128#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 252118#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 251505#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 251495#L795 assume !(0 != eval_~tmp~0#1); 251496#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 252405#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 252403#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 252401#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 252399#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 252397#L961-3 assume !(0 == ~T3_E~0); 252395#L966-3 assume !(0 == ~T4_E~0); 252393#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 252391#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 252389#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 252387#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 252385#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 252383#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 252381#L1001-3 assume !(0 == ~E_1~0); 252379#L1006-3 assume !(0 == ~E_2~0); 252377#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 252375#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 252373#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 252371#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 252369#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 252367#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 252365#L1041-3 assume !(0 == ~E_9~0); 252363#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252361#L472-33 assume !(1 == ~m_pc~0); 252359#L472-35 is_master_triggered_~__retres1~0#1 := 0; 252357#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252355#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 252353#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 252351#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 252349#L491-33 assume !(1 == ~t1_pc~0); 252347#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 252345#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252343#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 252341#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 252339#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 252337#L510-33 assume !(1 == ~t2_pc~0); 252333#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 252331#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252329#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 252327#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 252325#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 252323#L529-33 assume !(1 == ~t3_pc~0); 252321#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 252319#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 252317#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 252315#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 252313#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252311#L548-33 assume !(1 == ~t4_pc~0); 252309#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 252305#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252303#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 252301#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 252299#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 252297#L567-33 assume !(1 == ~t5_pc~0); 252295#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 252293#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 252291#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 252289#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 252287#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 252285#L586-33 assume !(1 == ~t6_pc~0); 252283#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 252279#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252277#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 252275#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 252273#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 252271#L605-33 assume !(1 == ~t7_pc~0); 225767#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 252269#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 252267#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 252265#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 252263#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 252261#L624-33 assume !(1 == ~t8_pc~0); 252259#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 252255#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 252253#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 252251#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 252249#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 252247#L643-33 assume !(1 == ~t9_pc~0); 252245#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 252241#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 252239#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 252237#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 252235#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 252232#L1059-3 assume !(1 == ~M_E~0); 252230#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 252228#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 252226#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 252225#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 252222#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 252221#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 252220#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 252219#L1094-3 assume !(1 == ~T8_E~0); 252218#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 252217#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 252216#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 252214#L1114-3 assume !(1 == ~E_2~0); 252212#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 252210#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 252208#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 252206#L1134-3 assume !(1 == ~E_6~0); 252204#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 252202#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 252200#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 252198#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 252192#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 252182#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 252179#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 252176#L1459 assume !(0 == start_simulation_~tmp~3#1); 252173#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 252167#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 252157#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 252155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 252153#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 252151#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 252149#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 252147#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 214448#L1440-2 [2024-10-13 17:45:04,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:04,081 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2024-10-13 17:45:04,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:04,082 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183197138] [2024-10-13 17:45:04,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:04,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:04,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:04,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:04,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:04,132 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183197138] [2024-10-13 17:45:04,132 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183197138] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:04,132 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:04,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:04,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361591484] [2024-10-13 17:45:04,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:04,133 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:04,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:04,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1897784226, now seen corresponding path program 1 times [2024-10-13 17:45:04,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:04,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387729175] [2024-10-13 17:45:04,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:04,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:04,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:04,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:04,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:04,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387729175] [2024-10-13 17:45:04,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387729175] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:04,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:04,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:04,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648436076] [2024-10-13 17:45:04,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:04,278 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:04,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:04,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:04,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:04,278 INFO L87 Difference]: Start difference. First operand 51550 states and 72648 transitions. cyclomatic complexity: 21130 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:04,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:04,542 INFO L93 Difference]: Finished difference Result 97933 states and 137493 transitions. [2024-10-13 17:45:04,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97933 states and 137493 transitions. [2024-10-13 17:45:05,049 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 97216 [2024-10-13 17:45:05,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97933 states to 97933 states and 137493 transitions. [2024-10-13 17:45:05,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97933 [2024-10-13 17:45:05,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97933 [2024-10-13 17:45:05,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97933 states and 137493 transitions. [2024-10-13 17:45:05,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:05,576 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97933 states and 137493 transitions. [2024-10-13 17:45:05,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97933 states and 137493 transitions. [2024-10-13 17:45:06,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97933 to 97805. [2024-10-13 17:45:06,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97805 states, 97805 states have (on average 1.404478298655488) internal successors, (137365), 97804 states have internal predecessors, (137365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97805 states to 97805 states and 137365 transitions. [2024-10-13 17:45:06,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97805 states and 137365 transitions. [2024-10-13 17:45:06,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:06,896 INFO L425 stractBuchiCegarLoop]: Abstraction has 97805 states and 137365 transitions. [2024-10-13 17:45:06,896 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-13 17:45:06,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97805 states and 137365 transitions. [2024-10-13 17:45:07,111 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 97088 [2024-10-13 17:45:07,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:07,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:07,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:07,113 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:07,114 INFO L745 eck$LassoCheckResult]: Stem: 364082#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 364083#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 364957#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 364958#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 364603#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 364289#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364290#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 364925#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 364991#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 364975#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 364976#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 364432#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 364414#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 364415#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 364207#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 364208#L951 assume !(0 == ~M_E~0); 363946#L951-2 assume !(0 == ~T1_E~0); 363947#L956-1 assume !(0 == ~T2_E~0); 364105#L961-1 assume !(0 == ~T3_E~0); 364622#L966-1 assume !(0 == ~T4_E~0); 364623#L971-1 assume !(0 == ~T5_E~0); 364766#L976-1 assume !(0 == ~T6_E~0); 364739#L981-1 assume !(0 == ~T7_E~0); 364477#L986-1 assume !(0 == ~T8_E~0); 364158#L991-1 assume !(0 == ~T9_E~0); 364159#L996-1 assume !(0 == ~E_M~0); 365032#L1001-1 assume !(0 == ~E_1~0); 364679#L1006-1 assume !(0 == ~E_2~0); 364680#L1011-1 assume !(0 == ~E_3~0); 364992#L1016-1 assume !(0 == ~E_4~0); 365011#L1021-1 assume !(0 == ~E_5~0); 363744#L1026-1 assume !(0 == ~E_6~0); 363745#L1031-1 assume !(0 == ~E_7~0); 364632#L1036-1 assume !(0 == ~E_8~0); 364628#L1041-1 assume !(0 == ~E_9~0); 364629#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 364936#L472 assume !(1 == ~m_pc~0); 364882#L472-2 is_master_triggered_~__retres1~0#1 := 0; 364658#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 364659#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 364668#L1179 assume !(0 != activate_threads_~tmp~1#1); 363752#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 363753#L491 assume !(1 == ~t1_pc~0); 364253#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 364254#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 363777#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 363725#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 363726#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 363746#L510 assume !(1 == ~t2_pc~0); 363714#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 363715#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 364276#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 364277#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 364001#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 364002#L529 assume !(1 == ~t3_pc~0); 364486#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 364797#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 363723#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 363724#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 363921#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363922#L548 assume !(1 == ~t4_pc~0); 363817#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 363816#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 363888#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 363858#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 363859#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 363805#L567 assume !(1 == ~t5_pc~0); 363806#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 363857#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 364867#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 364868#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 364919#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 363932#L586 assume !(1 == ~t6_pc~0); 363933#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 364005#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364259#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 364260#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 364910#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 364911#L605 assume !(1 == ~t7_pc~0); 364452#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 364453#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 364661#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 365089#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 365083#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 364595#L624 assume !(1 == ~t8_pc~0); 363996#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 363995#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 364719#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 364793#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 364887#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 363769#L643 assume !(1 == ~t9_pc~0); 363770#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 364826#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 364337#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 364163#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 364164#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363977#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 363978#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 364135#L1064-1 assume !(1 == ~T2_E~0); 364136#L1069-1 assume !(1 == ~T3_E~0); 364836#L1074-1 assume !(1 == ~T4_E~0); 364884#L1079-1 assume !(1 == ~T5_E~0); 364872#L1084-1 assume !(1 == ~T6_E~0); 364873#L1089-1 assume !(1 == ~T7_E~0); 364905#L1094-1 assume !(1 == ~T8_E~0); 364518#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 364519#L1104-1 assume !(1 == ~E_M~0); 364724#L1109-1 assume !(1 == ~E_1~0); 364278#L1114-1 assume !(1 == ~E_2~0); 364279#L1119-1 assume !(1 == ~E_3~0); 364350#L1124-1 assume !(1 == ~E_4~0); 363765#L1129-1 assume !(1 == ~E_5~0); 363766#L1134-1 assume !(1 == ~E_6~0); 364101#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 364102#L1144-1 assume !(1 == ~E_8~0); 364301#L1149-1 assume !(1 == ~E_9~0); 363938#L1154-1 assume { :end_inline_reset_delta_events } true; 363939#L1440-2 [2024-10-13 17:45:07,114 INFO L747 eck$LassoCheckResult]: Loop: 363939#L1440-2 assume !false; 428356#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 428347#L926-1 assume !false; 428287#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 427561#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 427550#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 427548#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 427545#L795 assume !(0 != eval_~tmp~0#1); 427546#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 428807#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 428805#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 428803#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 428801#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 428799#L961-3 assume !(0 == ~T3_E~0); 428797#L966-3 assume !(0 == ~T4_E~0); 428795#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 428793#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 428791#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 428788#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 428786#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 428784#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 428782#L1001-3 assume !(0 == ~E_1~0); 428780#L1006-3 assume !(0 == ~E_2~0); 428778#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 428775#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 428773#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 428771#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 428768#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 428766#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 428764#L1041-3 assume !(0 == ~E_9~0); 428761#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 428759#L472-33 assume !(1 == ~m_pc~0); 428757#L472-35 is_master_triggered_~__retres1~0#1 := 0; 428755#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 428753#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 428751#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 428748#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 428746#L491-33 assume !(1 == ~t1_pc~0); 428692#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 428654#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 428649#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 428643#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 428637#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 428632#L510-33 assume !(1 == ~t2_pc~0); 428629#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 428626#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 428624#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 428622#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 428620#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428618#L529-33 assume !(1 == ~t3_pc~0); 428616#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 428614#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 428612#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 428610#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 428608#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 428606#L548-33 assume !(1 == ~t4_pc~0); 428604#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 428601#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 428599#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 428597#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 428595#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 428593#L567-33 assume !(1 == ~t5_pc~0); 428591#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 428589#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 428587#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 428585#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 428583#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 428581#L586-33 assume !(1 == ~t6_pc~0); 428572#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 428569#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 428567#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 428565#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 428563#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 428561#L605-33 assume !(1 == ~t7_pc~0); 413020#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 428558#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 428556#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 428554#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 428551#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 428549#L624-33 assume 1 == ~t8_pc~0; 428546#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 428544#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 428542#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 428540#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 428538#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 428536#L643-33 assume !(1 == ~t9_pc~0); 428534#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 428532#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 428530#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 428528#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 428526#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 428523#L1059-3 assume !(1 == ~M_E~0); 409905#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 428520#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 428518#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 428516#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 409896#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 428513#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 428511#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 428509#L1094-3 assume !(1 == ~T8_E~0); 428507#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 428505#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 428503#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 428500#L1114-3 assume !(1 == ~E_2~0); 428498#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 428496#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 428494#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 428492#L1134-3 assume !(1 == ~E_6~0); 428490#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 428489#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 428487#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 428485#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 428472#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 428458#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 428452#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 428447#L1459 assume !(0 == start_simulation_~tmp~3#1); 428442#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 428380#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 428371#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 428367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 428365#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 428363#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 428362#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 428359#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 363939#L1440-2 [2024-10-13 17:45:07,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:07,114 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2024-10-13 17:45:07,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:07,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048743457] [2024-10-13 17:45:07,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:07,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:07,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:07,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:07,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:07,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048743457] [2024-10-13 17:45:07,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048743457] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:07,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:07,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:07,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483866380] [2024-10-13 17:45:07,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:07,154 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:07,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:07,155 INFO L85 PathProgramCache]: Analyzing trace with hash -1523705375, now seen corresponding path program 1 times [2024-10-13 17:45:07,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:07,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000857670] [2024-10-13 17:45:07,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:07,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:07,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:07,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:07,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:07,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000857670] [2024-10-13 17:45:07,183 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2000857670] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:07,183 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:07,183 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:07,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218758489] [2024-10-13 17:45:07,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:07,184 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:07,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:07,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:07,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:07,185 INFO L87 Difference]: Start difference. First operand 97805 states and 137365 transitions. cyclomatic complexity: 39624 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:07,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:07,803 INFO L93 Difference]: Finished difference Result 145065 states and 204044 transitions. [2024-10-13 17:45:07,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145065 states and 204044 transitions. [2024-10-13 17:45:08,630 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144064 [2024-10-13 17:45:08,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145065 states to 145065 states and 204044 transitions. [2024-10-13 17:45:08,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145065 [2024-10-13 17:45:08,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145065 [2024-10-13 17:45:08,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145065 states and 204044 transitions. [2024-10-13 17:45:09,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:09,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145065 states and 204044 transitions. [2024-10-13 17:45:09,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145065 states and 204044 transitions. [2024-10-13 17:45:10,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145065 to 99065. [2024-10-13 17:45:10,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.4101246656235804) internal successors, (139694), 99064 states have internal predecessors, (139694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:10,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 139694 transitions. [2024-10-13 17:45:10,900 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139694 transitions. [2024-10-13 17:45:10,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:10,905 INFO L425 stractBuchiCegarLoop]: Abstraction has 99065 states and 139694 transitions. [2024-10-13 17:45:10,906 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-13 17:45:10,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 139694 transitions. [2024-10-13 17:45:11,097 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2024-10-13 17:45:11,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:11,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:11,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:11,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:11,099 INFO L745 eck$LassoCheckResult]: Stem: 606964#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 606965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 607791#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 607792#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 607457#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 607171#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 607172#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 607759#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 607815#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 607803#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 607804#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 607301#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 607287#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 607288#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 607087#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 607088#L951 assume !(0 == ~M_E~0); 606825#L951-2 assume !(0 == ~T1_E~0); 606826#L956-1 assume !(0 == ~T2_E~0); 606984#L961-1 assume !(0 == ~T3_E~0); 607476#L966-1 assume !(0 == ~T4_E~0); 607477#L971-1 assume !(0 == ~T5_E~0); 607613#L976-1 assume !(0 == ~T6_E~0); 607585#L981-1 assume !(0 == ~T7_E~0); 607342#L986-1 assume !(0 == ~T8_E~0); 607036#L991-1 assume !(0 == ~T9_E~0); 607037#L996-1 assume !(0 == ~E_M~0); 607857#L1001-1 assume !(0 == ~E_1~0); 607532#L1006-1 assume !(0 == ~E_2~0); 607533#L1011-1 assume !(0 == ~E_3~0); 607817#L1016-1 assume !(0 == ~E_4~0); 607836#L1021-1 assume !(0 == ~E_5~0); 606621#L1026-1 assume !(0 == ~E_6~0); 606622#L1031-1 assume !(0 == ~E_7~0); 607483#L1036-1 assume !(0 == ~E_8~0); 607481#L1041-1 assume !(0 == ~E_9~0); 607482#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607773#L472 assume !(1 == ~m_pc~0); 607712#L472-2 is_master_triggered_~__retres1~0#1 := 0; 607512#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 607513#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 607521#L1179 assume !(0 != activate_threads_~tmp~1#1); 606629#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 606630#L491 assume !(1 == ~t1_pc~0); 607137#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 607138#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 606653#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 606602#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 606603#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 606625#L510 assume !(1 == ~t2_pc~0); 606591#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 606592#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 607159#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 606877#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 606878#L529 assume !(1 == ~t3_pc~0); 607350#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 607639#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 606600#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606601#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 606798#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 606799#L548 assume !(1 == ~t4_pc~0); 606693#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 606692#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 606763#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 606734#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 606735#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 606685#L567 assume !(1 == ~t5_pc~0); 606686#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 606733#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 607698#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 607699#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 607753#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 606809#L586 assume !(1 == ~t6_pc~0); 606810#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 606883#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 607144#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 607145#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 607746#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 607747#L605 assume !(1 == ~t7_pc~0); 607326#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 607327#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 607515#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 607903#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 607900#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 607450#L624 assume !(1 == ~t8_pc~0); 606872#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 606871#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 607570#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 607636#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 607717#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 606645#L643 assume !(1 == ~t9_pc~0); 606646#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 607662#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 607212#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 607043#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 607044#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 606857#L1059 assume !(1 == ~M_E~0); 606858#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 607013#L1064-1 assume !(1 == ~T2_E~0); 607014#L1069-1 assume !(1 == ~T3_E~0); 607671#L1074-1 assume !(1 == ~T4_E~0); 607715#L1079-1 assume !(1 == ~T5_E~0); 607703#L1084-1 assume !(1 == ~T6_E~0); 607704#L1089-1 assume !(1 == ~T7_E~0); 607738#L1094-1 assume !(1 == ~T8_E~0); 607378#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 607379#L1104-1 assume !(1 == ~E_M~0); 607574#L1109-1 assume !(1 == ~E_1~0); 607161#L1114-1 assume !(1 == ~E_2~0); 607162#L1119-1 assume !(1 == ~E_3~0); 607223#L1124-1 assume !(1 == ~E_4~0); 606643#L1129-1 assume !(1 == ~E_5~0); 606644#L1134-1 assume !(1 == ~E_6~0); 606982#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 606983#L1144-1 assume !(1 == ~E_8~0); 607180#L1149-1 assume !(1 == ~E_9~0); 606815#L1154-1 assume { :end_inline_reset_delta_events } true; 606816#L1440-2 [2024-10-13 17:45:11,099 INFO L747 eck$LassoCheckResult]: Loop: 606816#L1440-2 assume !false; 657967#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 657806#L926-1 assume !false; 657966#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 657960#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 657950#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 657948#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 657945#L795 assume !(0 != eval_~tmp~0#1); 657946#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 704123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 704121#L951-3 assume !(0 == ~M_E~0); 704119#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 704117#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 704115#L961-3 assume !(0 == ~T3_E~0); 704113#L966-3 assume !(0 == ~T4_E~0); 704111#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 704109#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 704107#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 704105#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 704103#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 704101#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 704099#L1001-3 assume !(0 == ~E_1~0); 704097#L1006-3 assume !(0 == ~E_2~0); 704095#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 704093#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 704091#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 704089#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 704087#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 704085#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 704083#L1041-3 assume !(0 == ~E_9~0); 704080#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 704078#L472-33 assume !(1 == ~m_pc~0); 704076#L472-35 is_master_triggered_~__retres1~0#1 := 0; 704074#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 704072#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 704070#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 704068#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 704066#L491-33 assume !(1 == ~t1_pc~0); 704064#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 704062#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 704060#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 704058#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 704056#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 704053#L510-33 assume !(1 == ~t2_pc~0); 704050#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 704048#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 704046#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 704044#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 704042#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 704039#L529-33 assume !(1 == ~t3_pc~0); 704037#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 704035#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 704033#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 704031#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 704029#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 704028#L548-33 assume 1 == ~t4_pc~0; 704026#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 704025#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 704024#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 704022#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 704019#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 704017#L567-33 assume !(1 == ~t5_pc~0); 704014#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 704012#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 704010#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 704008#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 704006#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 704004#L586-33 assume 1 == ~t6_pc~0; 704002#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 704000#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 703998#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 703996#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 703994#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 703992#L605-33 assume !(1 == ~t7_pc~0); 633732#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 703988#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 703986#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 703984#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 703982#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 703980#L624-33 assume 1 == ~t8_pc~0; 703976#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 703974#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 703972#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 703970#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 703968#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 703966#L643-33 assume !(1 == ~t9_pc~0); 703965#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 703963#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 703961#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 703959#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 703957#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 703955#L1059-3 assume !(1 == ~M_E~0); 626084#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 703952#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 703950#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 703948#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 703946#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 703944#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 703942#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 703940#L1094-3 assume !(1 == ~T8_E~0); 703938#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 703936#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 703934#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 703932#L1114-3 assume !(1 == ~E_2~0); 703930#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 703928#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 703927#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 703926#L1134-3 assume !(1 == ~E_6~0); 703925#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 703924#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 703922#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 703921#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 668927#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 668918#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 668917#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 624172#L1459 assume !(0 == start_simulation_~tmp~3#1); 624173#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 657983#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 657973#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 657972#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 657971#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 657970#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 657969#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 657968#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 606816#L1440-2 [2024-10-13 17:45:11,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:11,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2024-10-13 17:45:11,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:11,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383473435] [2024-10-13 17:45:11,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:11,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:11,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:11,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:11,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:11,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383473435] [2024-10-13 17:45:11,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [383473435] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:11,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:11,137 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:11,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905865094] [2024-10-13 17:45:11,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:11,137 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:11,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:11,138 INFO L85 PathProgramCache]: Analyzing trace with hash -899715299, now seen corresponding path program 1 times [2024-10-13 17:45:11,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:11,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331558101] [2024-10-13 17:45:11,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:11,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:11,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:11,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:11,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:11,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331558101] [2024-10-13 17:45:11,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1331558101] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:11,168 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:11,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:11,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760594244] [2024-10-13 17:45:11,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:11,168 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:11,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:11,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:11,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:11,169 INFO L87 Difference]: Start difference. First operand 99065 states and 139694 transitions. cyclomatic complexity: 40661 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:11,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:11,418 INFO L93 Difference]: Finished difference Result 99065 states and 139308 transitions. [2024-10-13 17:45:11,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99065 states and 139308 transitions. [2024-10-13 17:45:11,797 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2024-10-13 17:45:12,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99065 states to 99065 states and 139308 transitions. [2024-10-13 17:45:12,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99065 [2024-10-13 17:45:12,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99065 [2024-10-13 17:45:12,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99065 states and 139308 transitions. [2024-10-13 17:45:12,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:12,596 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2024-10-13 17:45:12,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99065 states and 139308 transitions. [2024-10-13 17:45:13,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99065 to 99065. [2024-10-13 17:45:13,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.4062282339877858) internal successors, (139308), 99064 states have internal predecessors, (139308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:13,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 139308 transitions. [2024-10-13 17:45:13,784 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2024-10-13 17:45:13,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:13,784 INFO L425 stractBuchiCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2024-10-13 17:45:13,785 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-13 17:45:13,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 139308 transitions. [2024-10-13 17:45:14,023 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2024-10-13 17:45:14,023 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:14,023 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:14,028 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:14,028 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:14,029 INFO L745 eck$LassoCheckResult]: Stem: 805095#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 805096#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 805905#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 805906#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 805581#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 805293#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 805294#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 805881#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 805928#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 805918#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 805919#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 805426#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 805411#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 805412#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 805215#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 805216#L951 assume !(0 == ~M_E~0); 804962#L951-2 assume !(0 == ~T1_E~0); 804963#L956-1 assume !(0 == ~T2_E~0); 805115#L961-1 assume !(0 == ~T3_E~0); 805600#L966-1 assume !(0 == ~T4_E~0); 805601#L971-1 assume !(0 == ~T5_E~0); 805736#L976-1 assume !(0 == ~T6_E~0); 805710#L981-1 assume !(0 == ~T7_E~0); 805467#L986-1 assume !(0 == ~T8_E~0); 805165#L991-1 assume !(0 == ~T9_E~0); 805166#L996-1 assume !(0 == ~E_M~0); 805966#L1001-1 assume !(0 == ~E_1~0); 805656#L1006-1 assume !(0 == ~E_2~0); 805657#L1011-1 assume !(0 == ~E_3~0); 805930#L1016-1 assume !(0 == ~E_4~0); 805943#L1021-1 assume !(0 == ~E_5~0); 804758#L1026-1 assume !(0 == ~E_6~0); 804759#L1031-1 assume !(0 == ~E_7~0); 805607#L1036-1 assume !(0 == ~E_8~0); 805605#L1041-1 assume !(0 == ~E_9~0); 805606#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 805889#L472 assume !(1 == ~m_pc~0); 805842#L472-2 is_master_triggered_~__retres1~0#1 := 0; 805636#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 805637#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 805645#L1179 assume !(0 != activate_threads_~tmp~1#1); 804766#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 804767#L491 assume !(1 == ~t1_pc~0); 805262#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 805263#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804791#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 804739#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 804740#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 804762#L510 assume !(1 == ~t2_pc~0); 804728#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 804729#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 805283#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 805284#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 805014#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 805015#L529 assume !(1 == ~t3_pc~0); 805473#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 805765#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 804737#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 804738#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 804935#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 804936#L548 assume !(1 == ~t4_pc~0); 804833#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 804832#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 804900#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 804874#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 804875#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 804822#L567 assume !(1 == ~t5_pc~0); 804823#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 804873#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 805828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 805829#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 805875#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 804946#L586 assume !(1 == ~t6_pc~0); 804947#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 805020#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 805266#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 805267#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 805867#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 805868#L605 assume !(1 == ~t7_pc~0); 805448#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 805449#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 805639#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 805998#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 805996#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 805575#L624 assume !(1 == ~t8_pc~0); 805009#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 805008#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 805695#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 805762#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 805849#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 804783#L643 assume !(1 == ~t9_pc~0); 804784#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 805792#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 805336#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 805170#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 805171#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 804994#L1059 assume !(1 == ~M_E~0); 804995#L1059-2 assume !(1 == ~T1_E~0); 805143#L1064-1 assume !(1 == ~T2_E~0); 805144#L1069-1 assume !(1 == ~T3_E~0); 805800#L1074-1 assume !(1 == ~T4_E~0); 805846#L1079-1 assume !(1 == ~T5_E~0); 805833#L1084-1 assume !(1 == ~T6_E~0); 805834#L1089-1 assume !(1 == ~T7_E~0); 805862#L1094-1 assume !(1 == ~T8_E~0); 805502#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 805503#L1104-1 assume !(1 == ~E_M~0); 805699#L1109-1 assume !(1 == ~E_1~0); 805285#L1114-1 assume !(1 == ~E_2~0); 805286#L1119-1 assume !(1 == ~E_3~0); 805349#L1124-1 assume !(1 == ~E_4~0); 804781#L1129-1 assume !(1 == ~E_5~0); 804782#L1134-1 assume !(1 == ~E_6~0); 805113#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 805114#L1144-1 assume !(1 == ~E_8~0); 805301#L1149-1 assume !(1 == ~E_9~0); 804952#L1154-1 assume { :end_inline_reset_delta_events } true; 804953#L1440-2 [2024-10-13 17:45:14,029 INFO L747 eck$LassoCheckResult]: Loop: 804953#L1440-2 assume !false; 829697#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 819039#L926-1 assume !false; 829694#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 829688#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 829678#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 829676#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 829674#L795 assume !(0 != eval_~tmp~0#1); 829675#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 837806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 837804#L951-3 assume !(0 == ~M_E~0); 837802#L951-5 assume !(0 == ~T1_E~0); 837800#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 837798#L961-3 assume !(0 == ~T3_E~0); 837796#L966-3 assume !(0 == ~T4_E~0); 837794#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 837792#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 837790#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 837788#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 837784#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 837782#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 837766#L1001-3 assume !(0 == ~E_1~0); 837763#L1006-3 assume !(0 == ~E_2~0); 837758#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 837754#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 837750#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 837734#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 837716#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 837712#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 837710#L1041-3 assume !(0 == ~E_9~0); 837708#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 837707#L472-33 assume !(1 == ~m_pc~0); 837704#L472-35 is_master_triggered_~__retres1~0#1 := 0; 837703#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 837702#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 837700#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 837696#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 837692#L491-33 assume !(1 == ~t1_pc~0); 837688#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 837684#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 837680#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 837676#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 837671#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 829923#L510-33 assume !(1 == ~t2_pc~0); 829920#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 829918#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 829916#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 829914#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 829912#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 829910#L529-33 assume !(1 == ~t3_pc~0); 829908#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 829906#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 829904#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 829902#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 829900#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 829898#L548-33 assume !(1 == ~t4_pc~0); 829896#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 829893#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 829890#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 829888#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 829886#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 829884#L567-33 assume !(1 == ~t5_pc~0); 829882#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 829880#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 829878#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 829876#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 829874#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 829872#L586-33 assume 1 == ~t6_pc~0; 829869#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 829867#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 829865#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 829862#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 829860#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 829858#L605-33 assume !(1 == ~t7_pc~0); 813528#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 829855#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 829853#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 829851#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 829849#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 829847#L624-33 assume 1 == ~t8_pc~0; 829844#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 829842#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 829840#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 829837#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 829835#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 829833#L643-33 assume !(1 == ~t9_pc~0); 829831#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 829829#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 829827#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 829826#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 829824#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 829793#L1059-3 assume !(1 == ~M_E~0); 829790#L1059-5 assume !(1 == ~T1_E~0); 829788#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 829786#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 829784#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 829782#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 829780#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 829778#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 829776#L1094-3 assume !(1 == ~T8_E~0); 829774#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 829772#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 829770#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 829768#L1114-3 assume !(1 == ~E_2~0); 829766#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 829763#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 829761#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 829759#L1134-3 assume !(1 == ~E_6~0); 829757#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 829755#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 829753#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 829751#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 829745#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 829735#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 829732#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 829729#L1459 assume !(0 == start_simulation_~tmp~3#1); 829726#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 829721#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 829711#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 829709#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 829707#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 829705#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 829703#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 829700#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 804953#L1440-2 [2024-10-13 17:45:14,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:14,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2024-10-13 17:45:14,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:14,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735070941] [2024-10-13 17:45:14,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:14,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:14,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:14,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:14,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:14,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735070941] [2024-10-13 17:45:14,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735070941] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:14,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:14,074 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:14,074 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295235800] [2024-10-13 17:45:14,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:14,075 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:14,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:14,075 INFO L85 PathProgramCache]: Analyzing trace with hash -2055149154, now seen corresponding path program 1 times [2024-10-13 17:45:14,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:14,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563824192] [2024-10-13 17:45:14,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:14,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:14,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:14,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:14,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:14,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563824192] [2024-10-13 17:45:14,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563824192] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:14,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:14,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:14,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467731119] [2024-10-13 17:45:14,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:14,103 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:14,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:14,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:14,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:14,104 INFO L87 Difference]: Start difference. First operand 99065 states and 139308 transitions. cyclomatic complexity: 40275 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:14,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:14,911 INFO L93 Difference]: Finished difference Result 156409 states and 219637 transitions. [2024-10-13 17:45:14,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156409 states and 219637 transitions. [2024-10-13 17:45:15,529 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 155328 [2024-10-13 17:45:15,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156409 states to 156409 states and 219637 transitions. [2024-10-13 17:45:15,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156409 [2024-10-13 17:45:16,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156409 [2024-10-13 17:45:16,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156409 states and 219637 transitions. [2024-10-13 17:45:16,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:16,104 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156409 states and 219637 transitions. [2024-10-13 17:45:16,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156409 states and 219637 transitions. [2024-10-13 17:45:17,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156409 to 110414. [2024-10-13 17:45:17,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110414 states, 110414 states have (on average 1.4082362743854946) internal successors, (155489), 110413 states have internal predecessors, (155489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:17,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110414 states to 110414 states and 155489 transitions. [2024-10-13 17:45:17,669 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110414 states and 155489 transitions. [2024-10-13 17:45:17,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:17,670 INFO L425 stractBuchiCegarLoop]: Abstraction has 110414 states and 155489 transitions. [2024-10-13 17:45:17,670 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-13 17:45:17,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110414 states and 155489 transitions. [2024-10-13 17:45:18,361 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109632 [2024-10-13 17:45:18,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:18,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:18,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:18,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:18,363 INFO L745 eck$LassoCheckResult]: Stem: 1060588#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1060589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1061450#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1061451#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1061091#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1060796#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1060797#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1061424#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1061477#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1061464#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1061465#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1060932#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1060918#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1060919#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1060715#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1060716#L951 assume !(0 == ~M_E~0); 1060453#L951-2 assume !(0 == ~T1_E~0); 1060454#L956-1 assume !(0 == ~T2_E~0); 1060610#L961-1 assume !(0 == ~T3_E~0); 1061110#L966-1 assume !(0 == ~T4_E~0); 1061111#L971-1 assume !(0 == ~T5_E~0); 1061263#L976-1 assume !(0 == ~T6_E~0); 1061231#L981-1 assume !(0 == ~T7_E~0); 1060973#L986-1 assume !(0 == ~T8_E~0); 1060663#L991-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1060664#L996-1 assume !(0 == ~E_M~0); 1061628#L1001-1 assume !(0 == ~E_1~0); 1061174#L1006-1 assume !(0 == ~E_2~0); 1061175#L1011-1 assume !(0 == ~E_3~0); 1061496#L1016-1 assume !(0 == ~E_4~0); 1061497#L1021-1 assume !(0 == ~E_5~0); 1060242#L1026-1 assume !(0 == ~E_6~0); 1060243#L1031-1 assume !(0 == ~E_7~0); 1061120#L1036-1 assume !(0 == ~E_8~0); 1061121#L1041-1 assume !(0 == ~E_9~0); 1061434#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1061435#L472 assume !(1 == ~m_pc~0); 1061374#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1061375#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1061353#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1061354#L1179 assume !(0 != activate_threads_~tmp~1#1); 1060251#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1060252#L491 assume !(1 == ~t1_pc~0); 1060766#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1060767#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1060277#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1060278#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1060246#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1060247#L510 assume !(1 == ~t2_pc~0); 1060212#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1060213#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1061517#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1061599#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1061600#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1060979#L529 assume !(1 == ~t3_pc~0); 1060980#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1061365#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1061366#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1061560#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1061561#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1061587#L548 assume !(1 == ~t4_pc~0); 1061588#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1060621#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1060622#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1060360#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1060361#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1060307#L567 assume !(1 == ~t5_pc~0); 1060308#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1061573#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1061574#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1061625#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1061417#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1061418#L586 assume !(1 == ~t6_pc~0); 1060511#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1060512#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1061541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1061611#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1061612#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1061585#L605 assume !(1 == ~t7_pc~0); 1061586#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1061155#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1061156#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1061576#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1061577#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1061623#L624 assume !(1 == ~t8_pc~0); 1060500#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1060499#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1061285#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1061286#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1061606#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1060269#L643 assume !(1 == ~t9_pc~0); 1060270#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1061536#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1060842#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1060843#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1061584#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1060482#L1059 assume !(1 == ~M_E~0); 1060483#L1059-2 assume !(1 == ~T1_E~0); 1060640#L1064-1 assume !(1 == ~T2_E~0); 1060641#L1069-1 assume !(1 == ~T3_E~0); 1061563#L1074-1 assume !(1 == ~T4_E~0); 1061564#L1079-1 assume !(1 == ~T5_E~0); 1061361#L1084-1 assume !(1 == ~T6_E~0); 1061362#L1089-1 assume !(1 == ~T7_E~0); 1061403#L1094-1 assume !(1 == ~T8_E~0); 1061404#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1061011#L1104-1 assume !(1 == ~E_M~0); 1061220#L1109-1 assume !(1 == ~E_1~0); 1060789#L1114-1 assume !(1 == ~E_2~0); 1060790#L1119-1 assume !(1 == ~E_3~0); 1060855#L1124-1 assume !(1 == ~E_4~0); 1060264#L1129-1 assume !(1 == ~E_5~0); 1060265#L1134-1 assume !(1 == ~E_6~0); 1060606#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1060607#L1144-1 assume !(1 == ~E_8~0); 1060808#L1149-1 assume !(1 == ~E_9~0); 1060443#L1154-1 assume { :end_inline_reset_delta_events } true; 1060444#L1440-2 [2024-10-13 17:45:18,367 INFO L747 eck$LassoCheckResult]: Loop: 1060444#L1440-2 assume !false; 1120005#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1119999#L926-1 assume !false; 1119997#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1119983#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1119973#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1119971#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1119968#L795 assume !(0 != eval_~tmp~0#1); 1119969#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1169266#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1169263#L951-3 assume !(0 == ~M_E~0); 1169257#L951-5 assume !(0 == ~T1_E~0); 1169256#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1169254#L961-3 assume !(0 == ~T3_E~0); 1169253#L966-3 assume !(0 == ~T4_E~0); 1169252#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1169251#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1060290#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1060291#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1151227#L991-3 assume !(0 == ~T9_E~0); 1151229#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1168470#L1001-3 assume !(0 == ~E_1~0); 1168471#L1006-3 assume !(0 == ~E_2~0); 1168464#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1168465#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1168458#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1168459#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1168452#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1168453#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1168446#L1041-3 assume !(0 == ~E_9~0); 1168447#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1168439#L472-33 assume !(1 == ~m_pc~0); 1168440#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1168433#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1168434#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1168427#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1168428#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1168421#L491-33 assume !(1 == ~t1_pc~0); 1168422#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1168415#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1168416#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1168409#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 1168410#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1168403#L510-33 assume !(1 == ~t2_pc~0); 1168402#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1168395#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1168396#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1168389#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1168390#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1168382#L529-33 assume !(1 == ~t3_pc~0); 1168383#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1168376#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1168377#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1168370#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1168371#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1168362#L548-33 assume 1 == ~t4_pc~0; 1168363#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1168355#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1168356#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1168349#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1168350#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1168342#L567-33 assume !(1 == ~t5_pc~0); 1168343#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1168336#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1168337#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1168330#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1168331#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1168322#L586-33 assume 1 == ~t6_pc~0; 1168323#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1168315#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1168316#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1168309#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1168310#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1151039#L605-33 assume !(1 == ~t7_pc~0); 1151037#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1151035#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1151033#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1151032#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1151030#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1151028#L624-33 assume 1 == ~t8_pc~0; 1151025#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1151023#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1151021#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1151019#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 1151017#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1151016#L643-33 assume !(1 == ~t9_pc~0); 1151015#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1151013#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1151011#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1151009#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1151007#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1151005#L1059-3 assume !(1 == ~M_E~0); 1095272#L1059-5 assume !(1 == ~T1_E~0); 1151002#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1151000#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1150998#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1150996#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1150994#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1150992#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1150990#L1094-3 assume !(1 == ~T8_E~0); 1150988#L1099-3 assume !(1 == ~T9_E~0); 1150985#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1150983#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1150981#L1114-3 assume !(1 == ~E_2~0); 1150979#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1150978#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1150977#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1150976#L1134-3 assume !(1 == ~E_6~0); 1150975#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1150974#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1150973#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1150972#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1150970#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1150961#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1150960#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1094978#L1459 assume !(0 == start_simulation_~tmp~3#1); 1094979#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1120029#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1120019#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1120017#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1120014#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1120012#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1120010#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1120008#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1060444#L1440-2 [2024-10-13 17:45:18,368 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:18,368 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2024-10-13 17:45:18,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:18,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752543960] [2024-10-13 17:45:18,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:18,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:18,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:18,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:18,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:18,438 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752543960] [2024-10-13 17:45:18,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752543960] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:18,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:18,439 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:18,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339143531] [2024-10-13 17:45:18,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:18,439 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:18,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:18,440 INFO L85 PathProgramCache]: Analyzing trace with hash 1086617245, now seen corresponding path program 1 times [2024-10-13 17:45:18,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:18,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333110441] [2024-10-13 17:45:18,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:18,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:18,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:18,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:18,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:18,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333110441] [2024-10-13 17:45:18,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333110441] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:18,469 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:18,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:18,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610554635] [2024-10-13 17:45:18,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:18,469 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:18,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:18,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:18,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:18,470 INFO L87 Difference]: Start difference. First operand 110414 states and 155489 transitions. cyclomatic complexity: 45107 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:18,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:18,838 INFO L93 Difference]: Finished difference Result 145049 states and 202986 transitions. [2024-10-13 17:45:18,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145049 states and 202986 transitions. [2024-10-13 17:45:19,416 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144064 [2024-10-13 17:45:20,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145049 states to 145049 states and 202986 transitions. [2024-10-13 17:45:20,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145049 [2024-10-13 17:45:20,328 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145049 [2024-10-13 17:45:20,328 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145049 states and 202986 transitions. [2024-10-13 17:45:20,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:20,399 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145049 states and 202986 transitions. [2024-10-13 17:45:20,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145049 states and 202986 transitions. [2024-10-13 17:45:21,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145049 to 99065. [2024-10-13 17:45:21,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.402331802351991) internal successors, (138922), 99064 states have internal predecessors, (138922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:21,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 138922 transitions. [2024-10-13 17:45:21,957 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 138922 transitions. [2024-10-13 17:45:21,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:21,958 INFO L425 stractBuchiCegarLoop]: Abstraction has 99065 states and 138922 transitions. [2024-10-13 17:45:21,958 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-13 17:45:21,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 138922 transitions. [2024-10-13 17:45:22,235 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2024-10-13 17:45:22,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:22,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:22,237 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:22,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:22,237 INFO L745 eck$LassoCheckResult]: Stem: 1316053#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1316054#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1316941#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1316942#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1316576#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1316268#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1316269#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1316904#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1316973#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1316958#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1316959#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1316412#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1316398#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1316399#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1316179#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1316180#L951 assume !(0 == ~M_E~0); 1315916#L951-2 assume !(0 == ~T1_E~0); 1315917#L956-1 assume !(0 == ~T2_E~0); 1316077#L961-1 assume !(0 == ~T3_E~0); 1316597#L966-1 assume !(0 == ~T4_E~0); 1316598#L971-1 assume !(0 == ~T5_E~0); 1316746#L976-1 assume !(0 == ~T6_E~0); 1316717#L981-1 assume !(0 == ~T7_E~0); 1316450#L986-1 assume !(0 == ~T8_E~0); 1316129#L991-1 assume !(0 == ~T9_E~0); 1316130#L996-1 assume !(0 == ~E_M~0); 1317020#L1001-1 assume !(0 == ~E_1~0); 1316655#L1006-1 assume !(0 == ~E_2~0); 1316656#L1011-1 assume !(0 == ~E_3~0); 1316974#L1016-1 assume !(0 == ~E_4~0); 1317000#L1021-1 assume !(0 == ~E_5~0); 1315715#L1026-1 assume !(0 == ~E_6~0); 1315716#L1031-1 assume !(0 == ~E_7~0); 1316607#L1036-1 assume !(0 == ~E_8~0); 1316603#L1041-1 assume !(0 == ~E_9~0); 1316604#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1316916#L472 assume !(1 == ~m_pc~0); 1316857#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1316636#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1316637#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1316646#L1179 assume !(0 != activate_threads_~tmp~1#1); 1315723#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1315724#L491 assume !(1 == ~t1_pc~0); 1316229#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1316230#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1315747#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1315696#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1315697#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1315719#L510 assume !(1 == ~t2_pc~0); 1315685#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1315686#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1316253#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1316254#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1315971#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1315972#L529 assume !(1 == ~t3_pc~0); 1316459#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1316778#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1315694#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1315695#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1315891#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1315892#L548 assume !(1 == ~t4_pc~0); 1315787#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1315786#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1315858#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1315829#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1315830#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1315775#L567 assume !(1 == ~t5_pc~0); 1315776#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1315831#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1316844#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1316845#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1316896#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1315902#L586 assume !(1 == ~t6_pc~0); 1315903#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1315975#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1316235#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1316236#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1316890#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1316891#L605 assume !(1 == ~t7_pc~0); 1316432#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1316433#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1316638#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1317070#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1317066#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1316568#L624 assume !(1 == ~t8_pc~0); 1315966#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1315965#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1316701#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1316774#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1316865#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1315739#L643 assume !(1 == ~t9_pc~0); 1315740#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1316804#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1316315#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1316134#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1316135#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1315947#L1059 assume !(1 == ~M_E~0); 1315948#L1059-2 assume !(1 == ~T1_E~0); 1316106#L1064-1 assume !(1 == ~T2_E~0); 1316107#L1069-1 assume !(1 == ~T3_E~0); 1316812#L1074-1 assume !(1 == ~T4_E~0); 1316861#L1079-1 assume !(1 == ~T5_E~0); 1316849#L1084-1 assume !(1 == ~T6_E~0); 1316850#L1089-1 assume !(1 == ~T7_E~0); 1316885#L1094-1 assume !(1 == ~T8_E~0); 1316489#L1099-1 assume !(1 == ~T9_E~0); 1316490#L1104-1 assume !(1 == ~E_M~0); 1316703#L1109-1 assume !(1 == ~E_1~0); 1316255#L1114-1 assume !(1 == ~E_2~0); 1316256#L1119-1 assume !(1 == ~E_3~0); 1316327#L1124-1 assume !(1 == ~E_4~0); 1315735#L1129-1 assume !(1 == ~E_5~0); 1315736#L1134-1 assume !(1 == ~E_6~0); 1316073#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1316074#L1144-1 assume !(1 == ~E_8~0); 1316278#L1149-1 assume !(1 == ~E_9~0); 1315908#L1154-1 assume { :end_inline_reset_delta_events } true; 1315909#L1440-2 [2024-10-13 17:45:22,238 INFO L747 eck$LassoCheckResult]: Loop: 1315909#L1440-2 assume !false; 1365114#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1365109#L926-1 assume !false; 1365107#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1365101#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1365091#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1365089#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1365087#L795 assume !(0 != eval_~tmp~0#1); 1365088#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1414691#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1414688#L951-3 assume !(0 == ~M_E~0); 1414686#L951-5 assume !(0 == ~T1_E~0); 1414684#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1414682#L961-3 assume !(0 == ~T3_E~0); 1414680#L966-3 assume !(0 == ~T4_E~0); 1414679#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1414678#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1315759#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1315760#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1316151#L991-3 assume !(0 == ~T9_E~0); 1414520#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1414519#L1001-3 assume !(0 == ~E_1~0); 1414518#L1006-3 assume !(0 == ~E_2~0); 1414517#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1414515#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1414513#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1414511#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1414509#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1414507#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1414505#L1041-3 assume !(0 == ~E_9~0); 1414503#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1414501#L472-33 assume !(1 == ~m_pc~0); 1414499#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1414497#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1414495#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1414493#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1414491#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1414489#L491-33 assume !(1 == ~t1_pc~0); 1414487#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1414485#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1414483#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1414481#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 1414479#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1414477#L510-33 assume !(1 == ~t2_pc~0); 1414474#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1414472#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1414470#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1414468#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1414466#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1414464#L529-33 assume !(1 == ~t3_pc~0); 1414462#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1414460#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1414458#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1414455#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1414453#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1414452#L548-33 assume !(1 == ~t4_pc~0); 1414451#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1414449#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1414448#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1414447#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1414446#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1414445#L567-33 assume !(1 == ~t5_pc~0); 1414444#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1414443#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1414442#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1414441#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1414440#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1414439#L586-33 assume 1 == ~t6_pc~0; 1414437#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1414329#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1414330#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1412802#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1412801#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1398609#L605-33 assume !(1 == ~t7_pc~0); 1398607#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1398605#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1398603#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1398601#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1398599#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1398597#L624-33 assume 1 == ~t8_pc~0; 1398485#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1398483#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1398480#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1398478#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 1398476#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1398474#L643-33 assume !(1 == ~t9_pc~0); 1398472#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1398470#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1398468#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1398466#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1398464#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1398462#L1059-3 assume !(1 == ~M_E~0); 1333202#L1059-5 assume !(1 == ~T1_E~0); 1398460#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1398455#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1398453#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1398451#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1398450#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1398447#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1398445#L1094-3 assume !(1 == ~T8_E~0); 1398443#L1099-3 assume !(1 == ~T9_E~0); 1398441#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1398439#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1398437#L1114-3 assume !(1 == ~E_2~0); 1398435#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1398433#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1398432#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1398234#L1134-3 assume !(1 == ~E_6~0); 1398230#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1398216#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1398206#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1398204#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1397992#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1397976#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1397971#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1333396#L1459 assume !(0 == start_simulation_~tmp~3#1); 1333397#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1365138#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1365128#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1365126#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1365124#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1365122#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1365120#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1365117#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1315909#L1440-2 [2024-10-13 17:45:22,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:22,238 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times [2024-10-13 17:45:22,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:22,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050873493] [2024-10-13 17:45:22,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:22,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:22,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:22,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:22,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:22,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1050873493] [2024-10-13 17:45:22,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1050873493] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:22,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:22,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:22,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1013416548] [2024-10-13 17:45:22,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:22,291 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:22,291 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:22,291 INFO L85 PathProgramCache]: Analyzing trace with hash -2070721186, now seen corresponding path program 1 times [2024-10-13 17:45:22,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:22,291 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166157201] [2024-10-13 17:45:22,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:22,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:22,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:22,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:22,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:22,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1166157201] [2024-10-13 17:45:22,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1166157201] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:22,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:22,325 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:22,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947333729] [2024-10-13 17:45:22,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:22,325 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:22,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:22,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:22,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:22,326 INFO L87 Difference]: Start difference. First operand 99065 states and 138922 transitions. cyclomatic complexity: 39889 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:22,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:22,811 INFO L93 Difference]: Finished difference Result 153169 states and 213971 transitions. [2024-10-13 17:45:22,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153169 states and 213971 transitions. [2024-10-13 17:45:23,959 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 152032 [2024-10-13 17:45:24,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153169 states to 153169 states and 213971 transitions. [2024-10-13 17:45:24,251 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153169 [2024-10-13 17:45:24,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153169 [2024-10-13 17:45:24,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153169 states and 213971 transitions. [2024-10-13 17:45:24,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:24,389 INFO L218 hiAutomatonCegarLoop]: Abstraction has 153169 states and 213971 transitions. [2024-10-13 17:45:24,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153169 states and 213971 transitions. [2024-10-13 17:45:25,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153169 to 110350. [2024-10-13 17:45:25,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110350 states, 110350 states have (on average 1.3991662890801995) internal successors, (154398), 110349 states have internal predecessors, (154398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:25,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110350 states to 110350 states and 154398 transitions. [2024-10-13 17:45:25,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110350 states and 154398 transitions. [2024-10-13 17:45:25,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:25,848 INFO L425 stractBuchiCegarLoop]: Abstraction has 110350 states and 154398 transitions. [2024-10-13 17:45:25,849 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-13 17:45:25,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110350 states and 154398 transitions. [2024-10-13 17:45:26,137 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109568 [2024-10-13 17:45:26,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:26,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:26,139 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:26,139 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:26,139 INFO L745 eck$LassoCheckResult]: Stem: 1568303#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1568304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1569172#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1569173#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1568809#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1568507#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1568508#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1569141#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1569214#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1569194#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1569195#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1568647#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1568633#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1568634#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1568429#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1568430#L951 assume !(0 == ~M_E~0); 1568164#L951-2 assume !(0 == ~T1_E~0); 1568165#L956-1 assume !(0 == ~T2_E~0); 1568326#L961-1 assume !(0 == ~T3_E~0); 1568829#L966-1 assume !(0 == ~T4_E~0); 1568830#L971-1 assume !(0 == ~T5_E~0); 1568978#L976-1 assume !(0 == ~T6_E~0); 1568948#L981-1 assume !(0 == ~T7_E~0); 1568685#L986-1 assume !(0 == ~T8_E~0); 1568376#L991-1 assume !(0 == ~T9_E~0); 1568377#L996-1 assume !(0 == ~E_M~0); 1569261#L1001-1 assume !(0 == ~E_1~0); 1568888#L1006-1 assume !(0 == ~E_2~0); 1568889#L1011-1 assume !(0 == ~E_3~0); 1569215#L1016-1 assume !(0 == ~E_4~0); 1569237#L1021-1 assume !(0 == ~E_5~0); 1567959#L1026-1 assume !(0 == ~E_6~0); 1567960#L1031-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1568842#L1036-1 assume !(0 == ~E_8~0); 1568843#L1041-1 assume !(0 == ~E_9~0); 1569406#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1569313#L472 assume !(1 == ~m_pc~0); 1569091#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1569092#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1569074#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1569075#L1179 assume !(0 != activate_threads_~tmp~1#1); 1569404#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1569403#L491 assume !(1 == ~t1_pc~0); 1568475#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1568476#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1567993#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1567994#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1567961#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1567962#L510 assume !(1 == ~t2_pc~0); 1567929#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1567930#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1569259#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1569343#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1569344#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1569398#L529 assume !(1 == ~t3_pc~0); 1569397#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1569396#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1569395#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1569304#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1568139#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1568140#L548 assume !(1 == ~t4_pc~0); 1569393#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1569391#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1569390#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1568072#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1568073#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1569389#L567 assume !(1 == ~t5_pc~0); 1568074#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1568075#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1569388#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1569387#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1569386#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1569385#L586 assume !(1 == ~t6_pc~0); 1568222#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1568223#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1569281#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1569354#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1569125#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1569126#L605 assume !(1 == ~t7_pc~0); 1569382#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1568871#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1568872#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1569317#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1569318#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1569381#L624 assume !(1 == ~t8_pc~0); 1568213#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1568212#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1569380#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1569379#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1569348#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1567985#L643 assume !(1 == ~t9_pc~0); 1567986#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1569033#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1568551#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1568381#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1568382#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1569373#L1059 assume !(1 == ~M_E~0); 1569355#L1059-2 assume !(1 == ~T1_E~0); 1568355#L1064-1 assume !(1 == ~T2_E~0); 1568356#L1069-1 assume !(1 == ~T3_E~0); 1569042#L1074-1 assume !(1 == ~T4_E~0); 1569370#L1079-1 assume !(1 == ~T5_E~0); 1569369#L1084-1 assume !(1 == ~T6_E~0); 1569368#L1089-1 assume !(1 == ~T7_E~0); 1569367#L1094-1 assume !(1 == ~T8_E~0); 1569366#L1099-1 assume !(1 == ~T9_E~0); 1569365#L1104-1 assume !(1 == ~E_M~0); 1568934#L1109-1 assume !(1 == ~E_1~0); 1568935#L1114-1 assume !(1 == ~E_2~0); 1569331#L1119-1 assume !(1 == ~E_3~0); 1568563#L1124-1 assume !(1 == ~E_4~0); 1567981#L1129-1 assume !(1 == ~E_5~0); 1567982#L1134-1 assume !(1 == ~E_6~0); 1569362#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1568323#L1144-1 assume !(1 == ~E_8~0); 1568515#L1149-1 assume !(1 == ~E_9~0); 1568156#L1154-1 assume { :end_inline_reset_delta_events } true; 1568157#L1440-2 [2024-10-13 17:45:26,140 INFO L747 eck$LassoCheckResult]: Loop: 1568157#L1440-2 assume !false; 1606126#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1606120#L926-1 assume !false; 1606118#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1606112#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1606101#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1606099#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1606096#L795 assume !(0 != eval_~tmp~0#1); 1606097#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1618878#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1618876#L951-3 assume !(0 == ~M_E~0); 1618874#L951-5 assume !(0 == ~T1_E~0); 1618872#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1618870#L961-3 assume !(0 == ~T3_E~0); 1618868#L966-3 assume !(0 == ~T4_E~0); 1618867#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1618865#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1618863#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1618861#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1618859#L991-3 assume !(0 == ~T9_E~0); 1618857#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1618855#L1001-3 assume !(0 == ~E_1~0); 1618853#L1006-3 assume !(0 == ~E_2~0); 1618851#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1618850#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1618849#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1618848#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1618846#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1618845#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1618844#L1041-3 assume !(0 == ~E_9~0); 1618843#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1618842#L472-33 assume !(1 == ~m_pc~0); 1618841#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1618840#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1618839#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1618838#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1618837#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1618836#L491-33 assume !(1 == ~t1_pc~0); 1618835#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1618834#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1618833#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1618832#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 1618831#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1618830#L510-33 assume !(1 == ~t2_pc~0); 1618828#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1618827#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1618826#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1618825#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1618824#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1618823#L529-33 assume !(1 == ~t3_pc~0); 1618822#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1618821#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1618820#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1618819#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1618818#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1618817#L548-33 assume 1 == ~t4_pc~0; 1618815#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1618814#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1618813#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1618812#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1618811#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1618810#L567-33 assume !(1 == ~t5_pc~0); 1618809#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1618808#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1618807#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1618806#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1618805#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1618804#L586-33 assume 1 == ~t6_pc~0; 1618802#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1618801#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1618800#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1618799#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1618798#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1618797#L605-33 assume !(1 == ~t7_pc~0); 1612180#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1618796#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1618795#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1618794#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1618793#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1618792#L624-33 assume 1 == ~t8_pc~0; 1618790#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1618789#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1618788#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1618787#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 1618786#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1618785#L643-33 assume !(1 == ~t9_pc~0); 1618784#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1618783#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1618782#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1618781#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1618780#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1618779#L1059-3 assume !(1 == ~M_E~0); 1581485#L1059-5 assume !(1 == ~T1_E~0); 1618778#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1618777#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1618776#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1618775#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1618774#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1618773#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1618772#L1094-3 assume !(1 == ~T8_E~0); 1618771#L1099-3 assume !(1 == ~T9_E~0); 1618770#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1618769#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1618768#L1114-3 assume !(1 == ~E_2~0); 1618767#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1618766#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1618765#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1618764#L1134-3 assume !(1 == ~E_6~0); 1618762#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1618761#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1618760#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1618759#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1618649#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1618639#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1609565#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1582051#L1459 assume !(0 == start_simulation_~tmp~3#1); 1582052#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1606149#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1606139#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1606137#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1606135#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1606133#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1606131#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1606129#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1568157#L1440-2 [2024-10-13 17:45:26,140 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:26,140 INFO L85 PathProgramCache]: Analyzing trace with hash 19846661, now seen corresponding path program 1 times [2024-10-13 17:45:26,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:26,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68296143] [2024-10-13 17:45:26,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:26,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:26,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:26,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:26,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:26,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68296143] [2024-10-13 17:45:26,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68296143] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:26,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:26,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:26,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144473382] [2024-10-13 17:45:26,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:26,177 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:26,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:26,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1086617245, now seen corresponding path program 2 times [2024-10-13 17:45:26,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:26,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552762163] [2024-10-13 17:45:26,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:26,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:26,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:26,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:26,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:26,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552762163] [2024-10-13 17:45:26,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552762163] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:26,201 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:26,201 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:26,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749594064] [2024-10-13 17:45:26,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:26,201 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:26,201 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:26,201 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:26,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:26,202 INFO L87 Difference]: Start difference. First operand 110350 states and 154398 transitions. cyclomatic complexity: 44080 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:26,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:26,604 INFO L93 Difference]: Finished difference Result 140697 states and 195960 transitions. [2024-10-13 17:45:26,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140697 states and 195960 transitions. [2024-10-13 17:45:27,628 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 139648 [2024-10-13 17:45:27,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140697 states to 140697 states and 195960 transitions. [2024-10-13 17:45:27,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 140697 [2024-10-13 17:45:27,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 140697 [2024-10-13 17:45:27,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140697 states and 195960 transitions. [2024-10-13 17:45:28,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:28,023 INFO L218 hiAutomatonCegarLoop]: Abstraction has 140697 states and 195960 transitions. [2024-10-13 17:45:28,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140697 states and 195960 transitions. [2024-10-13 17:45:29,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140697 to 99065. [2024-10-13 17:45:29,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.3932670468884065) internal successors, (138024), 99064 states have internal predecessors, (138024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:29,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 138024 transitions. [2024-10-13 17:45:29,526 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 138024 transitions. [2024-10-13 17:45:29,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:29,526 INFO L425 stractBuchiCegarLoop]: Abstraction has 99065 states and 138024 transitions. [2024-10-13 17:45:29,527 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-13 17:45:29,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 138024 transitions. [2024-10-13 17:45:29,835 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2024-10-13 17:45:29,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:29,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:29,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:29,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:29,838 INFO L745 eck$LassoCheckResult]: Stem: 1819351#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1819352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1820234#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1820235#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1819869#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1819563#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1819564#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1820201#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1820266#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1820253#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1820254#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1819701#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1819687#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1819688#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1819477#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1819478#L951 assume !(0 == ~M_E~0); 1819215#L951-2 assume !(0 == ~T1_E~0); 1819216#L956-1 assume !(0 == ~T2_E~0); 1819376#L961-1 assume !(0 == ~T3_E~0); 1819889#L966-1 assume !(0 == ~T4_E~0); 1819890#L971-1 assume !(0 == ~T5_E~0); 1820037#L976-1 assume !(0 == ~T6_E~0); 1820012#L981-1 assume !(0 == ~T7_E~0); 1819740#L986-1 assume !(0 == ~T8_E~0); 1819428#L991-1 assume !(0 == ~T9_E~0); 1819429#L996-1 assume !(0 == ~E_M~0); 1820308#L1001-1 assume !(0 == ~E_1~0); 1819949#L1006-1 assume !(0 == ~E_2~0); 1819950#L1011-1 assume !(0 == ~E_3~0); 1820267#L1016-1 assume !(0 == ~E_4~0); 1820289#L1021-1 assume !(0 == ~E_5~0); 1819016#L1026-1 assume !(0 == ~E_6~0); 1819017#L1031-1 assume !(0 == ~E_7~0); 1819900#L1036-1 assume !(0 == ~E_8~0); 1819896#L1041-1 assume !(0 == ~E_9~0); 1819897#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1820213#L472 assume !(1 == ~m_pc~0); 1820155#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1819927#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1819928#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1819938#L1179 assume !(0 != activate_threads_~tmp~1#1); 1819024#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1819025#L491 assume !(1 == ~t1_pc~0); 1819526#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1819527#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1819048#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1818997#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1818998#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1819018#L510 assume !(1 == ~t2_pc~0); 1818986#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1818987#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1819549#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1819550#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1819269#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1819270#L529 assume !(1 == ~t3_pc~0); 1819749#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1820066#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1818995#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1818996#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1819190#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1819191#L548 assume !(1 == ~t4_pc~0); 1819088#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1819087#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1819157#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1819128#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1819129#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1819076#L567 assume !(1 == ~t5_pc~0); 1819077#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1819127#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1820138#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1820139#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1820195#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1819201#L586 assume !(1 == ~t6_pc~0); 1819202#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1819273#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1819532#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1819533#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1820189#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1820190#L605 assume !(1 == ~t7_pc~0); 1819719#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1819720#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1819929#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1820362#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1820361#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1819862#L624 assume !(1 == ~t8_pc~0); 1819263#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1819262#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1819997#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1820062#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1820162#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1819040#L643 assume !(1 == ~t9_pc~0); 1819041#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1820097#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1819607#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1819433#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1819434#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1819246#L1059 assume !(1 == ~M_E~0); 1819247#L1059-2 assume !(1 == ~T1_E~0); 1819406#L1064-1 assume !(1 == ~T2_E~0); 1819407#L1069-1 assume !(1 == ~T3_E~0); 1820107#L1074-1 assume !(1 == ~T4_E~0); 1820158#L1079-1 assume !(1 == ~T5_E~0); 1820143#L1084-1 assume !(1 == ~T6_E~0); 1820144#L1089-1 assume !(1 == ~T7_E~0); 1820181#L1094-1 assume !(1 == ~T8_E~0); 1819787#L1099-1 assume !(1 == ~T9_E~0); 1819788#L1104-1 assume !(1 == ~E_M~0); 1819999#L1109-1 assume !(1 == ~E_1~0); 1819551#L1114-1 assume !(1 == ~E_2~0); 1819552#L1119-1 assume !(1 == ~E_3~0); 1819620#L1124-1 assume !(1 == ~E_4~0); 1819036#L1129-1 assume !(1 == ~E_5~0); 1819037#L1134-1 assume !(1 == ~E_6~0); 1819372#L1139-1 assume !(1 == ~E_7~0); 1819373#L1144-1 assume !(1 == ~E_8~0); 1819573#L1149-1 assume !(1 == ~E_9~0); 1819207#L1154-1 assume { :end_inline_reset_delta_events } true; 1819208#L1440-2 [2024-10-13 17:45:29,838 INFO L747 eck$LassoCheckResult]: Loop: 1819208#L1440-2 assume !false; 1879458#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1879453#L926-1 assume !false; 1879451#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1879442#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1879432#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1879430#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1879426#L795 assume !(0 != eval_~tmp~0#1); 1879427#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1896554#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1896553#L951-3 assume !(0 == ~M_E~0); 1896552#L951-5 assume !(0 == ~T1_E~0); 1896548#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1896546#L961-3 assume !(0 == ~T3_E~0); 1896544#L966-3 assume !(0 == ~T4_E~0); 1896543#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1896540#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1896539#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1896538#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1896535#L991-3 assume !(0 == ~T9_E~0); 1896532#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1896529#L1001-3 assume !(0 == ~E_1~0); 1896528#L1006-3 assume !(0 == ~E_2~0); 1896527#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1896526#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1896525#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1896524#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1896523#L1031-3 assume !(0 == ~E_7~0); 1896522#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1896521#L1041-3 assume !(0 == ~E_9~0); 1896520#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1896519#L472-33 assume !(1 == ~m_pc~0); 1896518#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1896514#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1896513#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1896512#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1896511#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1896510#L491-33 assume !(1 == ~t1_pc~0); 1896509#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1896508#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1896507#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1896506#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 1896505#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1896504#L510-33 assume !(1 == ~t2_pc~0); 1896502#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1896501#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1896500#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1896499#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1896497#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1896495#L529-33 assume !(1 == ~t3_pc~0); 1896493#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1896490#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1896488#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1896486#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1896484#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1896482#L548-33 assume 1 == ~t4_pc~0; 1896479#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1896477#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1896475#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1896473#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1896471#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1896469#L567-33 assume !(1 == ~t5_pc~0); 1896466#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1896464#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1896462#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1896460#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1896458#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1896456#L586-33 assume 1 == ~t6_pc~0; 1896453#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1896450#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1896448#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1896446#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1896444#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1896442#L605-33 assume !(1 == ~t7_pc~0); 1874621#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1896438#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1896436#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1896434#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1896432#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1896430#L624-33 assume !(1 == ~t8_pc~0); 1896428#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1896425#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1896423#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1896421#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 1896419#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1896417#L643-33 assume !(1 == ~t9_pc~0); 1896415#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1896412#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1896410#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1896408#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1896406#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1896404#L1059-3 assume !(1 == ~M_E~0); 1840051#L1059-5 assume !(1 == ~T1_E~0); 1896400#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1896398#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1896396#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1896394#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1896392#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1896390#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1896388#L1094-3 assume !(1 == ~T8_E~0); 1896385#L1099-3 assume !(1 == ~T9_E~0); 1896383#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1896381#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1896379#L1114-3 assume !(1 == ~E_2~0); 1896377#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1896375#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1896372#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1896370#L1134-3 assume !(1 == ~E_6~0); 1896368#L1139-3 assume !(1 == ~E_7~0); 1896366#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1896364#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1896363#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1873211#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1873202#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1873200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1840167#L1459 assume !(0 == start_simulation_~tmp~3#1); 1840168#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1879482#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1879472#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1879470#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1879468#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1879465#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1879463#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1879461#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1819208#L1440-2 [2024-10-13 17:45:29,838 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:29,839 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 1 times [2024-10-13 17:45:29,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:29,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276740369] [2024-10-13 17:45:29,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:29,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:29,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:45:29,851 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:45:29,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:45:29,909 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:45:29,910 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:29,910 INFO L85 PathProgramCache]: Analyzing trace with hash 793142302, now seen corresponding path program 1 times [2024-10-13 17:45:29,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:29,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497423482] [2024-10-13 17:45:29,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:29,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:29,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:29,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:29,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:29,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1497423482] [2024-10-13 17:45:29,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1497423482] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:29,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:29,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:29,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1469311804] [2024-10-13 17:45:29,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:29,949 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:29,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:29,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:29,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:29,950 INFO L87 Difference]: Start difference. First operand 99065 states and 138024 transitions. cyclomatic complexity: 38991 Second operand has 3 states, 3 states have (on average 41.333333333333336) internal successors, (124), 3 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:30,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:30,278 INFO L93 Difference]: Finished difference Result 110414 states and 154011 transitions. [2024-10-13 17:45:30,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110414 states and 154011 transitions. [2024-10-13 17:45:31,325 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109632 [2024-10-13 17:45:31,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110414 states to 110414 states and 154011 transitions. [2024-10-13 17:45:31,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110414 [2024-10-13 17:45:31,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110414 [2024-10-13 17:45:31,566 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110414 states and 154011 transitions. [2024-10-13 17:45:31,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:31,614 INFO L218 hiAutomatonCegarLoop]: Abstraction has 110414 states and 154011 transitions. [2024-10-13 17:45:31,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110414 states and 154011 transitions. [2024-10-13 17:45:32,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110414 to 110414. [2024-10-13 17:45:32,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110414 states, 110414 states have (on average 1.3948502907240024) internal successors, (154011), 110413 states have internal predecessors, (154011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:33,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110414 states to 110414 states and 154011 transitions. [2024-10-13 17:45:33,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110414 states and 154011 transitions. [2024-10-13 17:45:33,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:33,083 INFO L425 stractBuchiCegarLoop]: Abstraction has 110414 states and 154011 transitions. [2024-10-13 17:45:33,083 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-10-13 17:45:33,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110414 states and 154011 transitions. [2024-10-13 17:45:33,303 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109632 [2024-10-13 17:45:33,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:33,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:33,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:33,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:33,306 INFO L745 eck$LassoCheckResult]: Stem: 2028839#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2028840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2029722#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2029723#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2029354#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2029047#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2029048#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2029689#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2029749#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2029735#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2029736#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2029187#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2029172#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2029173#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2028967#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2028968#L951 assume !(0 == ~M_E~0); 2028704#L951-2 assume !(0 == ~T1_E~0); 2028705#L956-1 assume !(0 == ~T2_E~0); 2028863#L961-1 assume !(0 == ~T3_E~0); 2029375#L966-1 assume !(0 == ~T4_E~0); 2029376#L971-1 assume !(0 == ~T5_E~0); 2029523#L976-1 assume !(0 == ~T6_E~0); 2029492#L981-1 assume !(0 == ~T7_E~0); 2029226#L986-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2029227#L991-1 assume !(0 == ~T9_E~0); 2029862#L996-1 assume !(0 == ~E_M~0); 2029792#L1001-1 assume !(0 == ~E_1~0); 2029793#L1006-1 assume !(0 == ~E_2~0); 2029935#L1011-1 assume !(0 == ~E_3~0); 2029934#L1016-1 assume !(0 == ~E_4~0); 2029851#L1021-1 assume !(0 == ~E_5~0); 2029852#L1026-1 assume !(0 == ~E_6~0); 2029874#L1031-1 assume !(0 == ~E_7~0); 2029875#L1036-1 assume !(0 == ~E_8~0); 2029378#L1041-1 assume !(0 == ~E_9~0); 2029379#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2029700#L472 assume !(1 == ~m_pc~0); 2029932#L472-2 is_master_triggered_~__retres1~0#1 := 0; 2029409#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2029410#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2029420#L1179 assume !(0 != activate_threads_~tmp~1#1); 2029421#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2029931#L491 assume !(1 == ~t1_pc~0); 2029013#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2029014#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2028534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2028482#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2028483#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2029929#L510 assume !(1 == ~t2_pc~0); 2029927#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2029926#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2029037#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2029038#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 2028758#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2028759#L529 assume !(1 == ~t3_pc~0); 2029236#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2029553#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2028480#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2028481#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2029921#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2029863#L548 assume !(1 == ~t4_pc~0); 2028574#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2028573#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2028645#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2028646#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2029506#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2028562#L567 assume !(1 == ~t5_pc~0); 2028563#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2029854#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2029623#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2029624#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 2029681#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2028690#L586 assume !(1 == ~t6_pc~0); 2028691#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2029911#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2029019#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2029020#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 2029672#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2029673#L605 assume !(1 == ~t7_pc~0); 2029908#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2029411#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2029412#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2029855#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 2029850#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2029347#L624 assume !(1 == ~t8_pc~0); 2028753#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2028752#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2029476#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2029548#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 2029647#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2028526#L643 assume !(1 == ~t9_pc~0); 2028527#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2029580#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2029094#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2028920#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2028921#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2028736#L1059 assume !(1 == ~M_E~0); 2028737#L1059-2 assume !(1 == ~T1_E~0); 2028893#L1064-1 assume !(1 == ~T2_E~0); 2028894#L1069-1 assume !(1 == ~T3_E~0); 2029591#L1074-1 assume !(1 == ~T4_E~0); 2029643#L1079-1 assume !(1 == ~T5_E~0); 2029628#L1084-1 assume !(1 == ~T6_E~0); 2029629#L1089-1 assume !(1 == ~T7_E~0); 2029664#L1094-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2029269#L1099-1 assume !(1 == ~T9_E~0); 2029270#L1104-1 assume !(1 == ~E_M~0); 2029479#L1109-1 assume !(1 == ~E_1~0); 2029039#L1114-1 assume !(1 == ~E_2~0); 2029040#L1119-1 assume !(1 == ~E_3~0); 2029106#L1124-1 assume !(1 == ~E_4~0); 2028522#L1129-1 assume !(1 == ~E_5~0); 2028523#L1134-1 assume !(1 == ~E_6~0); 2028859#L1139-1 assume !(1 == ~E_7~0); 2028860#L1144-1 assume !(1 == ~E_8~0); 2029059#L1149-1 assume !(1 == ~E_9~0); 2028696#L1154-1 assume { :end_inline_reset_delta_events } true; 2028697#L1440-2 [2024-10-13 17:45:33,307 INFO L747 eck$LassoCheckResult]: Loop: 2028697#L1440-2 assume !false; 2047652#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2047648#L926-1 assume !false; 2047647#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2047645#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2047626#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2047624#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2047621#L795 assume !(0 != eval_~tmp~0#1); 2047622#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2048589#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2048587#L951-3 assume !(0 == ~M_E~0); 2048585#L951-5 assume !(0 == ~T1_E~0); 2048583#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2048581#L961-3 assume !(0 == ~T3_E~0); 2048579#L966-3 assume !(0 == ~T4_E~0); 2048577#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2048575#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2048573#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2048569#L986-3 assume !(0 == ~T8_E~0); 2048570#L991-3 assume !(0 == ~T9_E~0); 2048627#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2048625#L1001-3 assume !(0 == ~E_1~0); 2048623#L1006-3 assume !(0 == ~E_2~0); 2048621#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2048619#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2048617#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2048615#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2048613#L1031-3 assume !(0 == ~E_7~0); 2048611#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2048609#L1041-3 assume !(0 == ~E_9~0); 2048608#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2048607#L472-33 assume !(1 == ~m_pc~0); 2048606#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2048605#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2048604#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2048603#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2048602#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2048601#L491-33 assume !(1 == ~t1_pc~0); 2048600#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2048599#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2048598#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2048597#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 2048596#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2048595#L510-33 assume !(1 == ~t2_pc~0); 2048593#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2048592#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2048591#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2048590#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 2048588#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2048586#L529-33 assume !(1 == ~t3_pc~0); 2048584#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2048582#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2048580#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2048578#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2048576#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2048574#L548-33 assume !(1 == ~t4_pc~0); 2048572#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 2048568#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2048566#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2048564#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2048562#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2048560#L567-33 assume !(1 == ~t5_pc~0); 2048558#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2048556#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2048554#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2048552#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2048550#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2048548#L586-33 assume !(1 == ~t6_pc~0); 2048546#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2048543#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2048541#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2048539#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2048537#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2048535#L605-33 assume !(1 == ~t7_pc~0); 2044619#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2048532#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2048530#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2048528#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2048526#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2048524#L624-33 assume !(1 == ~t8_pc~0); 2048522#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2048519#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2048516#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2048514#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 2048512#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2048510#L643-33 assume !(1 == ~t9_pc~0); 2048508#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2048506#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2048504#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2048502#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2048500#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2048498#L1059-3 assume !(1 == ~M_E~0); 2047946#L1059-5 assume !(1 == ~T1_E~0); 2048495#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2048493#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2048490#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2048488#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2048486#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2048484#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2047725#L1094-3 assume !(1 == ~T8_E~0); 2047723#L1099-3 assume !(1 == ~T9_E~0); 2047721#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2047719#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2047717#L1114-3 assume !(1 == ~E_2~0); 2047715#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2047713#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2047711#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2047709#L1134-3 assume !(1 == ~E_6~0); 2047707#L1139-3 assume !(1 == ~E_7~0); 2047705#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2047703#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2047701#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2047695#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2047685#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2047683#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2047681#L1459 assume !(0 == start_simulation_~tmp~3#1); 2047679#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2047677#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2047668#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2047664#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2047662#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2047660#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2047659#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2047656#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2028697#L1440-2 [2024-10-13 17:45:33,307 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:33,307 INFO L85 PathProgramCache]: Analyzing trace with hash -192797307, now seen corresponding path program 1 times [2024-10-13 17:45:33,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:33,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263601056] [2024-10-13 17:45:33,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:33,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:33,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:33,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:33,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:33,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263601056] [2024-10-13 17:45:33,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1263601056] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:33,348 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:33,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:33,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047569855] [2024-10-13 17:45:33,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:33,348 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:33,349 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:33,349 INFO L85 PathProgramCache]: Analyzing trace with hash 1547756894, now seen corresponding path program 1 times [2024-10-13 17:45:33,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:33,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070916939] [2024-10-13 17:45:33,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:33,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:33,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:33,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:33,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:33,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070916939] [2024-10-13 17:45:33,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070916939] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:33,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:33,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:33,372 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657978140] [2024-10-13 17:45:33,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:33,373 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:33,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:33,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:33,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:33,373 INFO L87 Difference]: Start difference. First operand 110414 states and 154011 transitions. cyclomatic complexity: 43629 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:33,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:33,729 INFO L93 Difference]: Finished difference Result 145061 states and 201547 transitions. [2024-10-13 17:45:33,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145061 states and 201547 transitions. [2024-10-13 17:45:34,812 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144064 [2024-10-13 17:45:35,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145061 states to 145061 states and 201547 transitions. [2024-10-13 17:45:35,055 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145061 [2024-10-13 17:45:35,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145061 [2024-10-13 17:45:35,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145061 states and 201547 transitions. [2024-10-13 17:45:35,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:35,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145061 states and 201547 transitions. [2024-10-13 17:45:35,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145061 states and 201547 transitions. [2024-10-13 17:45:35,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145061 to 99065.