./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a046e57d Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-mul-div-a046e57-m [2024-10-13 17:44:59,223 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-13 17:44:59,276 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-13 17:44:59,280 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-13 17:44:59,284 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-13 17:44:59,303 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-13 17:44:59,304 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-13 17:44:59,304 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-13 17:44:59,305 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-13 17:44:59,308 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-13 17:44:59,309 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-13 17:44:59,309 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-13 17:44:59,309 INFO L153 SettingsManager]: * Use SBE=true [2024-10-13 17:44:59,309 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-13 17:44:59,309 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-13 17:44:59,310 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-13 17:44:59,310 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-13 17:44:59,310 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-13 17:44:59,311 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-13 17:44:59,312 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-13 17:44:59,312 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-13 17:44:59,312 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-13 17:44:59,312 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-13 17:44:59,313 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-13 17:44:59,313 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-13 17:44:59,313 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-13 17:44:59,313 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-13 17:44:59,313 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-13 17:44:59,314 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-13 17:44:59,315 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-13 17:44:59,315 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-13 17:44:59,315 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-13 17:44:59,315 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-13 17:44:59,315 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-13 17:44:59,316 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-13 17:44:59,316 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-13 17:44:59,316 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-13 17:44:59,317 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-13 17:44:59,317 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-13 17:44:59,317 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 [2024-10-13 17:44:59,587 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-13 17:44:59,603 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-13 17:44:59,605 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-13 17:44:59,607 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-13 17:44:59,607 INFO L274 PluginConnector]: CDTParser initialized [2024-10-13 17:44:59,608 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2024-10-13 17:45:00,962 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-13 17:45:01,181 INFO L384 CDTParser]: Found 1 translation units. [2024-10-13 17:45:01,182 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2024-10-13 17:45:01,202 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/53ff3a0e5/4f1befe9898141438e00a8d157029fcc/FLAGc41ce53a7 [2024-10-13 17:45:01,219 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/53ff3a0e5/4f1befe9898141438e00a8d157029fcc [2024-10-13 17:45:01,222 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-13 17:45:01,223 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-13 17:45:01,224 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-13 17:45:01,225 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-13 17:45:01,230 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-13 17:45:01,230 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:01,231 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@469e1987 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01, skipping insertion in model container [2024-10-13 17:45:01,233 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:01,275 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-13 17:45:01,675 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:45:01,718 INFO L200 MainTranslator]: Completed pre-run [2024-10-13 17:45:01,838 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:45:01,896 INFO L204 MainTranslator]: Completed translation [2024-10-13 17:45:01,902 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01 WrapperNode [2024-10-13 17:45:01,903 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-13 17:45:01,904 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-13 17:45:01,905 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-13 17:45:01,906 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-13 17:45:01,913 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:01,926 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,073 INFO L138 Inliner]: procedures = 48, calls = 62, calls flagged for inlining = 57, calls inlined = 210, statements flattened = 3209 [2024-10-13 17:45:02,073 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-13 17:45:02,078 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-13 17:45:02,078 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-13 17:45:02,078 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-13 17:45:02,092 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,096 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,106 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,154 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-13 17:45:02,154 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,158 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,190 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,224 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,230 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,236 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,251 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-13 17:45:02,252 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-13 17:45:02,252 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-13 17:45:02,252 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-13 17:45:02,253 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (1/1) ... [2024-10-13 17:45:02,257 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:45:02,267 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:45:02,280 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:45:02,283 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-13 17:45:02,318 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-13 17:45:02,318 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-13 17:45:02,318 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-13 17:45:02,318 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-13 17:45:02,415 INFO L238 CfgBuilder]: Building ICFG [2024-10-13 17:45:02,417 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-13 17:45:04,320 INFO L? ?]: Removed 662 outVars from TransFormulas that were not future-live. [2024-10-13 17:45:04,320 INFO L287 CfgBuilder]: Performing block encoding [2024-10-13 17:45:04,357 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-13 17:45:04,358 INFO L314 CfgBuilder]: Removed 13 assume(true) statements. [2024-10-13 17:45:04,358 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:45:04 BoogieIcfgContainer [2024-10-13 17:45:04,358 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-13 17:45:04,359 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-13 17:45:04,359 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-13 17:45:04,367 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-13 17:45:04,367 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:04,367 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 05:45:01" (1/3) ... [2024-10-13 17:45:04,368 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c76ae9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:45:04, skipping insertion in model container [2024-10-13 17:45:04,368 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:04,369 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:01" (2/3) ... [2024-10-13 17:45:04,369 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c76ae9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:45:04, skipping insertion in model container [2024-10-13 17:45:04,369 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:04,369 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:45:04" (3/3) ... [2024-10-13 17:45:04,374 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-2.c [2024-10-13 17:45:04,509 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-13 17:45:04,510 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-13 17:45:04,510 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-13 17:45:04,510 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-13 17:45:04,510 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-13 17:45:04,510 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-13 17:45:04,510 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-13 17:45:04,510 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-13 17:45:04,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:04,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1236 [2024-10-13 17:45:04,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:04,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:04,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:04,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:04,597 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-13 17:45:04,601 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:04,613 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1236 [2024-10-13 17:45:04,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:04,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:04,616 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:04,616 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:04,623 INFO L745 eck$LassoCheckResult]: Stem: 188#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1260#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 998#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1256#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 589#L719true assume !(1 == ~m_i~0);~m_st~0 := 2; 358#L719-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 563#L724-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 730#L729-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1246#L734-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 477#L739-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 848#L744-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 392#L749-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 683#L754-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 869#L759-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 639#L764-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 571#L769-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 857#L1024true assume !(0 == ~M_E~0); 960#L1024-2true assume !(0 == ~T1_E~0); 186#L1029-1true assume !(0 == ~T2_E~0); 245#L1034-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1328#L1039-1true assume !(0 == ~T4_E~0); 1035#L1044-1true assume !(0 == ~T5_E~0); 407#L1049-1true assume !(0 == ~T6_E~0); 1342#L1054-1true assume !(0 == ~T7_E~0); 588#L1059-1true assume !(0 == ~T8_E~0); 214#L1064-1true assume !(0 == ~T9_E~0); 822#L1069-1true assume !(0 == ~T10_E~0); 1239#L1074-1true assume 0 == ~E_M~0;~E_M~0 := 1; 899#L1079-1true assume !(0 == ~E_1~0); 860#L1084-1true assume !(0 == ~E_2~0); 1059#L1089-1true assume !(0 == ~E_3~0); 933#L1094-1true assume !(0 == ~E_4~0); 469#L1099-1true assume !(0 == ~E_5~0); 1074#L1104-1true assume !(0 == ~E_6~0); 702#L1109-1true assume !(0 == ~E_7~0); 320#L1114-1true assume 0 == ~E_8~0;~E_8~0 := 1; 1291#L1119-1true assume !(0 == ~E_9~0); 365#L1124-1true assume !(0 == ~E_10~0); 39#L1129-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 721#L502true assume 1 == ~m_pc~0; 586#L503true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100#L513true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 636#L1273true assume !(0 != activate_threads_~tmp~1#1); 1378#L1273-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1143#L521true assume !(1 == ~t1_pc~0); 1070#L521-2true is_transmit1_triggered_~__retres1~1#1 := 0; 63#L532true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 652#L1281true assume !(0 != activate_threads_~tmp___0~0#1); 56#L1281-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 875#L540true assume 1 == ~t2_pc~0; 1125#L541true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 879#L551true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 318#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1240#L1289true assume !(0 != activate_threads_~tmp___1~0#1); 968#L1289-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203#L559true assume 1 == ~t3_pc~0; 1044#L560true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 377#L570true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 665#L1297true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1297-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1267#L578true assume !(1 == ~t4_pc~0); 828#L578-2true is_transmit4_triggered_~__retres1~4#1 := 0; 854#L589true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1111#L1305true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 619#L1305-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1179#L597true assume 1 == ~t5_pc~0; 1347#L598true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73#L608true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 855#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1366#L1313true assume !(0 != activate_threads_~tmp___4~0#1); 572#L1313-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 633#L616true assume !(1 == ~t6_pc~0); 1191#L616-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1087#L627true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 304#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 509#L1321true assume !(0 != activate_threads_~tmp___5~0#1); 462#L1321-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 697#L635true assume 1 == ~t7_pc~0; 622#L636true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 255#L646true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1276#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 928#L1329true assume !(0 != activate_threads_~tmp___6~0#1); 567#L1329-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 816#L654true assume !(1 == ~t8_pc~0); 426#L654-2true is_transmit8_triggered_~__retres1~8#1 := 0; 969#L665true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 764#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 819#L1337true assume !(0 != activate_threads_~tmp___7~0#1); 1021#L1337-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185#L673true assume 1 == ~t9_pc~0; 1038#L674true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1215#L684true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 355#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 768#L1345true assume !(0 != activate_threads_~tmp___8~0#1); 715#L1345-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 888#L692true assume !(1 == ~t10_pc~0); 701#L692-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1028#L703true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 464#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 472#L1353true assume !(0 != activate_threads_~tmp___9~0#1); 792#L1353-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1325#L1142true assume !(1 == ~M_E~0); 138#L1142-2true assume !(1 == ~T1_E~0); 769#L1147-1true assume !(1 == ~T2_E~0); 1324#L1152-1true assume !(1 == ~T3_E~0); 382#L1157-1true assume !(1 == ~T4_E~0); 868#L1162-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 491#L1167-1true assume !(1 == ~T6_E~0); 952#L1172-1true assume !(1 == ~T7_E~0); 982#L1177-1true assume !(1 == ~T8_E~0); 604#L1182-1true assume !(1 == ~T9_E~0); 708#L1187-1true assume !(1 == ~T10_E~0); 758#L1192-1true assume !(1 == ~E_M~0); 288#L1197-1true assume !(1 == ~E_1~0); 773#L1202-1true assume 1 == ~E_2~0;~E_2~0 := 2; 555#L1207-1true assume !(1 == ~E_3~0); 539#L1212-1true assume !(1 == ~E_4~0); 66#L1217-1true assume !(1 == ~E_5~0); 1380#L1222-1true assume !(1 == ~E_6~0); 536#L1227-1true assume !(1 == ~E_7~0); 601#L1232-1true assume !(1 == ~E_8~0); 7#L1237-1true assume !(1 == ~E_9~0); 1079#L1242-1true assume 1 == ~E_10~0;~E_10~0 := 2; 587#L1247-1true assume { :end_inline_reset_delta_events } true; 88#L1553-2true [2024-10-13 17:45:04,625 INFO L747 eck$LassoCheckResult]: Loop: 88#L1553-2true assume !false; 755#L1554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235#L999-1true assume false; 779#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 481#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1305#L1024-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1025#L1024-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 459#L1029-3true assume !(0 == ~T2_E~0); 435#L1034-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 735#L1039-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 788#L1044-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 183#L1049-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 664#L1054-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 64#L1059-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1350#L1064-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 415#L1069-3true assume !(0 == ~T10_E~0); 710#L1074-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1001#L1079-3true assume 0 == ~E_1~0;~E_1~0 := 1; 595#L1084-3true assume 0 == ~E_2~0;~E_2~0 := 1; 504#L1089-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1094-3true assume 0 == ~E_4~0;~E_4~0 := 1; 448#L1099-3true assume 0 == ~E_5~0;~E_5~0 := 1; 733#L1104-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1085#L1109-3true assume !(0 == ~E_7~0); 719#L1114-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1204#L1119-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1344#L1124-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1237#L1129-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1118#L502-36true assume 1 == ~m_pc~0; 736#L503-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2#L513-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1003#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215#L1273-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 703#L1273-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394#L521-36true assume !(1 == ~t1_pc~0); 1098#L521-38true is_transmit1_triggered_~__retres1~1#1 := 0; 528#L532-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 999#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1209#L1281-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 826#L1281-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1128#L540-36true assume !(1 == ~t2_pc~0); 42#L540-38true is_transmit2_triggered_~__retres1~2#1 := 0; 258#L551-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 827#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1351#L1289-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 488#L1289-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6#L559-36true assume 1 == ~t3_pc~0; 726#L560-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 756#L570-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606#L1297-36true assume !(0 != activate_threads_~tmp___2~0#1); 894#L1297-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1250#L578-36true assume 1 == ~t4_pc~0; 579#L579-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1259#L589-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 496#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1323#L1305-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 419#L1305-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 594#L597-36true assume !(1 == ~t5_pc~0); 1141#L597-38true is_transmit5_triggered_~__retres1~5#1 := 0; 1078#L608-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 967#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 556#L1313-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 289#L1313-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1130#L616-36true assume 1 == ~t6_pc~0; 1349#L617-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37#L627-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 338#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 456#L1321-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 754#L1321-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1362#L635-36true assume 1 == ~t7_pc~0; 1030#L636-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 838#L646-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 932#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1284#L1329-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 446#L1329-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1297#L654-36true assume 1 == ~t8_pc~0; 1218#L655-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1346#L665-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 576#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1190#L1337-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1145#L1337-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 231#L673-36true assume !(1 == ~t9_pc~0); 740#L673-38true is_transmit9_triggered_~__retres1~9#1 := 0; 478#L684-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 380#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1050#L1345-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10#L1345-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1201#L692-36true assume !(1 == ~t10_pc~0); 112#L692-38true is_transmit10_triggered_~__retres1~10#1 := 0; 455#L703-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 278#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 212#L1353-36true assume !(0 != activate_threads_~tmp___9~0#1); 454#L1353-38true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 573#L1142-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1185#L1142-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1034#L1147-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1090#L1152-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 513#L1157-3true assume !(1 == ~T4_E~0); 834#L1162-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1088#L1167-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1011#L1172-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 444#L1177-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 374#L1182-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 867#L1187-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 384#L1192-3true assume 1 == ~E_M~0;~E_M~0 := 2; 266#L1197-3true assume !(1 == ~E_1~0); 433#L1202-3true assume 1 == ~E_2~0;~E_2~0 := 2; 522#L1207-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1126#L1212-3true assume 1 == ~E_4~0;~E_4~0 := 2; 731#L1217-3true assume 1 == ~E_5~0;~E_5~0 := 2; 207#L1222-3true assume 1 == ~E_6~0;~E_6~0 := 2; 48#L1227-3true assume 1 == ~E_7~0;~E_7~0 := 2; 900#L1232-3true assume 1 == ~E_8~0;~E_8~0 := 2; 870#L1237-3true assume !(1 == ~E_9~0); 1310#L1242-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1264#L1247-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 945#L782-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 120#L839-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 271#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 580#L1572true assume !(0 == start_simulation_~tmp~3#1); 395#L1572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1231#L782-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1103#L839-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 43#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1301#L1527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4#L1534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 499#stop_simulation_returnLabel#1true start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1371#L1585true assume !(0 != start_simulation_~tmp___0~1#1); 88#L1553-2true [2024-10-13 17:45:04,630 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:04,631 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2024-10-13 17:45:04,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:04,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095972880] [2024-10-13 17:45:04,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:04,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:04,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:04,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:04,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:04,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095972880] [2024-10-13 17:45:04,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095972880] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:04,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:04,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:04,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617609718] [2024-10-13 17:45:04,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:04,937 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:04,938 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:04,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1194100893, now seen corresponding path program 1 times [2024-10-13 17:45:04,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:04,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391268300] [2024-10-13 17:45:04,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:04,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:04,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391268300] [2024-10-13 17:45:05,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [391268300] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:05,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893504090] [2024-10-13 17:45:05,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,015 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:05,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:05,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:05,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:05,043 INFO L87 Difference]: Start difference. First operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:05,108 INFO L93 Difference]: Finished difference Result 1377 states and 2039 transitions. [2024-10-13 17:45:05,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2039 transitions. [2024-10-13 17:45:05,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1372 states and 2034 transitions. [2024-10-13 17:45:05,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:05,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:05,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2034 transitions. [2024-10-13 17:45:05,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:05,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2024-10-13 17:45:05,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2034 transitions. [2024-10-13 17:45:05,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:05,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4825072886297377) internal successors, (2034), 1371 states have internal predecessors, (2034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2034 transitions. [2024-10-13 17:45:05,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2024-10-13 17:45:05,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:05,203 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2024-10-13 17:45:05,204 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-13 17:45:05,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2034 transitions. [2024-10-13 17:45:05,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:05,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:05,214 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:05,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:05,215 INFO L745 eck$LassoCheckResult]: Stem: 3147#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3729#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3418#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3419#L724-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3699#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3869#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3587#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3588#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3469#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3470#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3823#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3783#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3707#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3708#L1024 assume !(0 == ~M_E~0); 3963#L1024-2 assume !(0 == ~T1_E~0); 3143#L1029-1 assume !(0 == ~T2_E~0); 3144#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3246#L1039-1 assume !(0 == ~T4_E~0); 4073#L1044-1 assume !(0 == ~T5_E~0); 3491#L1049-1 assume !(0 == ~T6_E~0); 3492#L1054-1 assume !(0 == ~T7_E~0); 3728#L1059-1 assume !(0 == ~T8_E~0); 3193#L1064-1 assume !(0 == ~T9_E~0); 3194#L1069-1 assume !(0 == ~T10_E~0); 3932#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3992#L1079-1 assume !(0 == ~E_1~0); 3965#L1084-1 assume !(0 == ~E_2~0); 3966#L1089-1 assume !(0 == ~E_3~0); 4010#L1094-1 assume !(0 == ~E_4~0); 3577#L1099-1 assume !(0 == ~E_5~0); 3578#L1104-1 assume !(0 == ~E_6~0); 3841#L1109-1 assume !(0 == ~E_7~0); 3360#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3361#L1119-1 assume !(0 == ~E_9~0); 3431#L1124-1 assume !(0 == ~E_10~0); 2847#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2848#L502 assume 1 == ~m_pc~0; 3726#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2973#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2974#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3779#L1273 assume !(0 != activate_threads_~tmp~1#1); 3780#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4103#L521 assume !(1 == ~t1_pc~0); 4038#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2898#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2864#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2884#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2885#L540 assume 1 == ~t2_pc~0; 3976#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3688#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3356#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3357#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4034#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3171#L559 assume 1 == ~t3_pc~0; 3172#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3449#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2800#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2801#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2991#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2992#L578 assume !(1 == ~t4_pc~0); 3115#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3114#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2932#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3760#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3761#L597 assume 1 == ~t5_pc~0; 4119#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2918#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2919#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3961#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3709#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3710#L616 assume !(1 == ~t6_pc~0); 3725#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3724#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3332#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3333#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3567#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3568#L635 assume 1 == ~t7_pc~0; 3764#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2887#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4006#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3701#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3702#L654 assume !(1 == ~t8_pc~0); 3518#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3519#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3894#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3895#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3930#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3141#L673 assume 1 == ~t9_pc~0; 3142#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2838#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3413#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3414#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3853#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3854#L692 assume !(1 == ~t10_pc~0); 3798#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3797#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3569#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3570#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3581#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3909#L1142 assume !(1 == ~M_E~0); 3052#L1142-2 assume !(1 == ~T1_E~0); 3053#L1147-1 assume !(1 == ~T2_E~0); 3898#L1152-1 assume !(1 == ~T3_E~0); 3455#L1157-1 assume !(1 == ~T4_E~0); 3456#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3605#L1167-1 assume !(1 == ~T6_E~0); 3606#L1172-1 assume !(1 == ~T7_E~0); 4028#L1177-1 assume !(1 == ~T8_E~0); 3746#L1182-1 assume !(1 == ~T9_E~0); 3747#L1187-1 assume !(1 == ~T10_E~0); 3846#L1192-1 assume !(1 == ~E_M~0); 3312#L1197-1 assume !(1 == ~E_1~0); 3313#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3691#L1207-1 assume !(1 == ~E_3~0); 3666#L1212-1 assume !(1 == ~E_4~0); 2903#L1217-1 assume !(1 == ~E_5~0); 2904#L1222-1 assume !(1 == ~E_6~0); 3663#L1227-1 assume !(1 == ~E_7~0); 3664#L1232-1 assume !(1 == ~E_8~0); 2777#L1237-1 assume !(1 == ~E_9~0); 2778#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3727#L1247-1 assume { :end_inline_reset_delta_events } true; 2948#L1553-2 [2024-10-13 17:45:05,216 INFO L747 eck$LassoCheckResult]: Loop: 2948#L1553-2 assume !false; 2949#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3088#L999-1 assume !false; 3229#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3036#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2921#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3393#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3394#L854 assume !(0 != eval_~tmp~0#1); 3803#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3590#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3591#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4063#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3563#L1029-3 assume !(0 == ~T2_E~0); 3531#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3532#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3874#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3137#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3138#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2899#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2900#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3501#L1069-3 assume !(0 == ~T10_E~0); 3502#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3848#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3739#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3624#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3625#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3550#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3551#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3872#L1109-3 assume !(0 == ~E_7~0); 3860#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3861#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4124#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4131#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4097#L502-36 assume !(1 == ~m_pc~0); 3280#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2765#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2766#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3195#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3196#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3474#L521-36 assume 1 == ~t1_pc~0; 3475#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3485#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3655#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4051#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3934#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3935#L540-36 assume !(1 == ~t2_pc~0); 2849#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2850#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3267#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3936#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3600#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2771#L559-36 assume !(1 == ~t3_pc~0); 2772#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3230#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3408#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3409#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 3748#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3988#L578-36 assume 1 == ~t4_pc~0; 3717#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3673#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3611#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3612#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3507#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3508#L597-36 assume !(1 == ~t5_pc~0); 3736#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4089#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4033#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3690#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3310#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3311#L616-36 assume 1 == ~t6_pc~0; 4100#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2843#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2844#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3388#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3560#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3889#L635-36 assume 1 == ~t7_pc~0; 4064#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3946#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3947#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4009#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3546#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3547#L654-36 assume !(1 == ~t8_pc~0); 4069#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4070#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3713#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3714#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4104#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3221#L673-36 assume 1 == ~t9_pc~0; 3222#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3586#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3451#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3452#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2784#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2785#L692-36 assume !(1 == ~t10_pc~0); 2999#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3000#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3294#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3188#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 3189#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3557#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3706#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4071#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4072#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3637#L1157-3 assume !(1 == ~T4_E~0); 3638#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3942#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4055#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3545#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3443#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3444#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3458#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3277#L1197-3 assume !(1 == ~E_1~0); 3278#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3528#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3646#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3870#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3181#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2868#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2869#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3971#L1237-3 assume !(1 == ~E_9~0); 3972#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4134#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4020#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3019#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3284#L1572 assume !(0 == start_simulation_~tmp~3#1); 3315#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3477#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2798#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2856#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 2857#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2769#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2770#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3617#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2948#L1553-2 [2024-10-13 17:45:05,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:05,219 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2024-10-13 17:45:05,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:05,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521468511] [2024-10-13 17:45:05,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:05,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:05,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [521468511] [2024-10-13 17:45:05,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [521468511] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:05,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91842298] [2024-10-13 17:45:05,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,318 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:05,318 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:05,318 INFO L85 PathProgramCache]: Analyzing trace with hash 1542473243, now seen corresponding path program 1 times [2024-10-13 17:45:05,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:05,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850691164] [2024-10-13 17:45:05,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:05,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:05,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,446 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850691164] [2024-10-13 17:45:05,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [850691164] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,447 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,447 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:05,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [727897912] [2024-10-13 17:45:05,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,448 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:05,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:05,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:05,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:05,449 INFO L87 Difference]: Start difference. First operand 1372 states and 2034 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:05,466 INFO L93 Difference]: Finished difference Result 1372 states and 2033 transitions. [2024-10-13 17:45:05,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2033 transitions. [2024-10-13 17:45:05,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2033 transitions. [2024-10-13 17:45:05,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:05,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:05,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2033 transitions. [2024-10-13 17:45:05,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:05,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2024-10-13 17:45:05,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2033 transitions. [2024-10-13 17:45:05,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:05,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4817784256559767) internal successors, (2033), 1371 states have internal predecessors, (2033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2033 transitions. [2024-10-13 17:45:05,497 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2024-10-13 17:45:05,498 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:05,498 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2024-10-13 17:45:05,498 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-13 17:45:05,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2033 transitions. [2024-10-13 17:45:05,504 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,504 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:05,504 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:05,505 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:05,506 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:05,507 INFO L745 eck$LassoCheckResult]: Stem: 5898#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6480#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6168#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6169#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6450#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6620#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6337#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6338#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6220#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6221#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6574#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6534#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6457#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6458#L1024 assume !(0 == ~M_E~0); 6714#L1024-2 assume !(0 == ~T1_E~0); 5894#L1029-1 assume !(0 == ~T2_E~0); 5895#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5997#L1039-1 assume !(0 == ~T4_E~0); 6824#L1044-1 assume !(0 == ~T5_E~0); 6240#L1049-1 assume !(0 == ~T6_E~0); 6241#L1054-1 assume !(0 == ~T7_E~0); 6479#L1059-1 assume !(0 == ~T8_E~0); 5944#L1064-1 assume !(0 == ~T9_E~0); 5945#L1069-1 assume !(0 == ~T10_E~0); 6683#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6743#L1079-1 assume !(0 == ~E_1~0); 6716#L1084-1 assume !(0 == ~E_2~0); 6717#L1089-1 assume !(0 == ~E_3~0); 6761#L1094-1 assume !(0 == ~E_4~0); 6328#L1099-1 assume !(0 == ~E_5~0); 6329#L1104-1 assume !(0 == ~E_6~0); 6592#L1109-1 assume !(0 == ~E_7~0); 6111#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6112#L1119-1 assume !(0 == ~E_9~0); 6178#L1124-1 assume !(0 == ~E_10~0); 5598#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5599#L502 assume 1 == ~m_pc~0; 6477#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5724#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5725#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6528#L1273 assume !(0 != activate_threads_~tmp~1#1); 6529#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6854#L521 assume !(1 == ~t1_pc~0); 6789#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5649#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5614#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5615#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5635#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5636#L540 assume 1 == ~t2_pc~0; 6727#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6439#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6107#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6108#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6785#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5922#L559 assume 1 == ~t3_pc~0; 5923#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6199#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5551#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5552#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5742#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5743#L578 assume !(1 == ~t4_pc~0); 5861#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5860#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5681#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5682#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6509#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6510#L597 assume 1 == ~t5_pc~0; 6869#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5669#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6712#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6459#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6460#L616 assume !(1 == ~t6_pc~0); 6474#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6473#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6084#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6317#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6318#L635 assume 1 == ~t7_pc~0; 6514#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5638#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6013#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6757#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6452#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6453#L654 assume !(1 == ~t8_pc~0); 6269#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6270#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6642#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6643#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6681#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5892#L673 assume 1 == ~t9_pc~0; 5893#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5589#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6162#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6163#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6604#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6605#L692 assume !(1 == ~t10_pc~0); 6549#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6548#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6320#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6321#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6332#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6660#L1142 assume !(1 == ~M_E~0); 5803#L1142-2 assume !(1 == ~T1_E~0); 5804#L1147-1 assume !(1 == ~T2_E~0); 6649#L1152-1 assume !(1 == ~T3_E~0); 6206#L1157-1 assume !(1 == ~T4_E~0); 6207#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6356#L1167-1 assume !(1 == ~T6_E~0); 6357#L1172-1 assume !(1 == ~T7_E~0); 6778#L1177-1 assume !(1 == ~T8_E~0); 6497#L1182-1 assume !(1 == ~T9_E~0); 6498#L1187-1 assume !(1 == ~T10_E~0); 6597#L1192-1 assume !(1 == ~E_M~0); 6061#L1197-1 assume !(1 == ~E_1~0); 6062#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6441#L1207-1 assume !(1 == ~E_3~0); 6417#L1212-1 assume !(1 == ~E_4~0); 5654#L1217-1 assume !(1 == ~E_5~0); 5655#L1222-1 assume !(1 == ~E_6~0); 6414#L1227-1 assume !(1 == ~E_7~0); 6415#L1232-1 assume !(1 == ~E_8~0); 5528#L1237-1 assume !(1 == ~E_9~0); 5529#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 6478#L1247-1 assume { :end_inline_reset_delta_events } true; 5699#L1553-2 [2024-10-13 17:45:05,507 INFO L747 eck$LassoCheckResult]: Loop: 5699#L1553-2 assume !false; 5700#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5839#L999-1 assume !false; 5980#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5787#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5672#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6144#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6145#L854 assume !(0 != eval_~tmp~0#1); 6554#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6341#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6342#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6814#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6314#L1029-3 assume !(0 == ~T2_E~0); 6282#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6283#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6625#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5888#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5889#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5650#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5651#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6252#L1069-3 assume !(0 == ~T10_E~0); 6253#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6599#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6489#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6375#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6376#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6301#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6302#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6623#L1109-3 assume !(0 == ~E_7~0); 6611#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6612#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6875#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6882#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6848#L502-36 assume 1 == ~m_pc~0; 6626#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5516#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5517#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5946#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5947#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6225#L521-36 assume 1 == ~t1_pc~0; 6226#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6236#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6406#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6802#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6685#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6686#L540-36 assume 1 == ~t2_pc~0; 6850#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5606#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6018#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6687#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6351#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5525#L559-36 assume !(1 == ~t3_pc~0); 5526#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5984#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6159#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6160#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 6499#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6739#L578-36 assume 1 == ~t4_pc~0; 6468#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6427#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6363#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6364#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6260#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6261#L597-36 assume !(1 == ~t5_pc~0); 6487#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6840#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6784#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6442#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6063#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6064#L616-36 assume 1 == ~t6_pc~0; 6851#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5594#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5595#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6139#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6311#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6640#L635-36 assume !(1 == ~t7_pc~0); 6816#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6697#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6698#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6760#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6297#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6298#L654-36 assume !(1 == ~t8_pc~0); 6820#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6821#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6464#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6465#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6855#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5972#L673-36 assume 1 == ~t9_pc~0; 5973#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6339#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6202#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6203#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5535#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5536#L692-36 assume !(1 == ~t10_pc~0); 5750#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5751#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6045#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5939#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 5940#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6310#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6461#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6822#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6823#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6388#L1157-3 assume !(1 == ~T4_E~0); 6389#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6693#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6806#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6296#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6194#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6195#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6209#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6028#L1197-3 assume !(1 == ~E_1~0); 6029#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6279#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6397#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6621#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5932#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5619#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5620#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6722#L1237-3 assume !(1 == ~E_9~0); 6723#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6885#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6771#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5770#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5771#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6035#L1572 assume !(0 == start_simulation_~tmp~3#1); 6066#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6228#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5549#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5607#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 5608#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5520#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5521#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6368#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5699#L1553-2 [2024-10-13 17:45:05,508 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:05,511 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2024-10-13 17:45:05,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:05,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539594] [2024-10-13 17:45:05,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:05,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:05,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,556 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539594] [2024-10-13 17:45:05,556 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539594] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,556 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,556 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:05,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393967116] [2024-10-13 17:45:05,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,557 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:05,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:05,557 INFO L85 PathProgramCache]: Analyzing trace with hash -1367151846, now seen corresponding path program 1 times [2024-10-13 17:45:05,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:05,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248526349] [2024-10-13 17:45:05,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:05,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:05,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248526349] [2024-10-13 17:45:05,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248526349] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:05,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045252989] [2024-10-13 17:45:05,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,642 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:05,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:05,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:05,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:05,642 INFO L87 Difference]: Start difference. First operand 1372 states and 2033 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:05,661 INFO L93 Difference]: Finished difference Result 1372 states and 2032 transitions. [2024-10-13 17:45:05,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2032 transitions. [2024-10-13 17:45:05,668 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,672 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2032 transitions. [2024-10-13 17:45:05,672 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:05,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:05,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2032 transitions. [2024-10-13 17:45:05,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:05,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2024-10-13 17:45:05,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2032 transitions. [2024-10-13 17:45:05,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:05,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4810495626822158) internal successors, (2032), 1371 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2032 transitions. [2024-10-13 17:45:05,689 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2024-10-13 17:45:05,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:05,691 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2024-10-13 17:45:05,691 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-13 17:45:05,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2032 transitions. [2024-10-13 17:45:05,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:05,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:05,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:05,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:05,697 INFO L745 eck$LassoCheckResult]: Stem: 8649#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9551#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9552#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9231#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8919#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8920#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9201#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9371#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9088#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9089#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8971#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8972#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9325#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9285#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9208#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9209#L1024 assume !(0 == ~M_E~0); 9465#L1024-2 assume !(0 == ~T1_E~0); 8645#L1029-1 assume !(0 == ~T2_E~0); 8646#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8748#L1039-1 assume !(0 == ~T4_E~0); 9575#L1044-1 assume !(0 == ~T5_E~0); 8991#L1049-1 assume !(0 == ~T6_E~0); 8992#L1054-1 assume !(0 == ~T7_E~0); 9230#L1059-1 assume !(0 == ~T8_E~0); 8695#L1064-1 assume !(0 == ~T9_E~0); 8696#L1069-1 assume !(0 == ~T10_E~0); 9434#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 9494#L1079-1 assume !(0 == ~E_1~0); 9467#L1084-1 assume !(0 == ~E_2~0); 9468#L1089-1 assume !(0 == ~E_3~0); 9512#L1094-1 assume !(0 == ~E_4~0); 9079#L1099-1 assume !(0 == ~E_5~0); 9080#L1104-1 assume !(0 == ~E_6~0); 9343#L1109-1 assume !(0 == ~E_7~0); 8862#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8863#L1119-1 assume !(0 == ~E_9~0); 8929#L1124-1 assume !(0 == ~E_10~0); 8349#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8350#L502 assume 1 == ~m_pc~0; 9228#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8475#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8476#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9279#L1273 assume !(0 != activate_threads_~tmp~1#1); 9280#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9605#L521 assume !(1 == ~t1_pc~0); 9540#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8400#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8365#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8366#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 8386#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8387#L540 assume 1 == ~t2_pc~0; 9478#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9190#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8858#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8859#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 9536#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8673#L559 assume 1 == ~t3_pc~0; 8674#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8950#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8302#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8303#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8493#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8494#L578 assume !(1 == ~t4_pc~0); 8614#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8613#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8433#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8434#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9262#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9263#L597 assume 1 == ~t5_pc~0; 9620#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8420#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8421#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9463#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 9210#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9211#L616 assume !(1 == ~t6_pc~0); 9225#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9224#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8834#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8835#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 9068#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9069#L635 assume 1 == ~t7_pc~0; 9265#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8389#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8764#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9508#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 9203#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9204#L654 assume !(1 == ~t8_pc~0); 9020#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9021#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9395#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9396#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 9432#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8643#L673 assume 1 == ~t9_pc~0; 8644#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8340#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8915#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8916#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 9355#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9356#L692 assume !(1 == ~t10_pc~0); 9300#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9299#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9072#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 9083#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9411#L1142 assume !(1 == ~M_E~0); 8554#L1142-2 assume !(1 == ~T1_E~0); 8555#L1147-1 assume !(1 == ~T2_E~0); 9400#L1152-1 assume !(1 == ~T3_E~0); 8957#L1157-1 assume !(1 == ~T4_E~0); 8958#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9107#L1167-1 assume !(1 == ~T6_E~0); 9108#L1172-1 assume !(1 == ~T7_E~0); 9529#L1177-1 assume !(1 == ~T8_E~0); 9248#L1182-1 assume !(1 == ~T9_E~0); 9249#L1187-1 assume !(1 == ~T10_E~0); 9348#L1192-1 assume !(1 == ~E_M~0); 8812#L1197-1 assume !(1 == ~E_1~0); 8813#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9192#L1207-1 assume !(1 == ~E_3~0); 9168#L1212-1 assume !(1 == ~E_4~0); 8405#L1217-1 assume !(1 == ~E_5~0); 8406#L1222-1 assume !(1 == ~E_6~0); 9165#L1227-1 assume !(1 == ~E_7~0); 9166#L1232-1 assume !(1 == ~E_8~0); 8279#L1237-1 assume !(1 == ~E_9~0); 8280#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9229#L1247-1 assume { :end_inline_reset_delta_events } true; 8450#L1553-2 [2024-10-13 17:45:05,698 INFO L747 eck$LassoCheckResult]: Loop: 8450#L1553-2 assume !false; 8451#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8590#L999-1 assume !false; 8731#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8538#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8423#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8895#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8896#L854 assume !(0 != eval_~tmp~0#1); 9305#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9093#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9565#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9065#L1029-3 assume !(0 == ~T2_E~0); 9033#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9034#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9376#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8639#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8640#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8401#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8402#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9003#L1069-3 assume !(0 == ~T10_E~0); 9004#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9350#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9240#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9126#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9127#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9052#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9053#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9374#L1109-3 assume !(0 == ~E_7~0); 9362#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9363#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9626#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9633#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9599#L502-36 assume 1 == ~m_pc~0; 9377#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8267#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8268#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8697#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8698#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8976#L521-36 assume 1 == ~t1_pc~0; 8977#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8987#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9157#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9553#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9436#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9437#L540-36 assume 1 == ~t2_pc~0; 9601#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8357#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8769#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9438#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9102#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8276#L559-36 assume !(1 == ~t3_pc~0); 8277#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 8735#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8910#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8911#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 9250#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9490#L578-36 assume 1 == ~t4_pc~0; 9219#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9178#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9114#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9115#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9011#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9012#L597-36 assume !(1 == ~t5_pc~0); 9238#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9591#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9535#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9193#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8814#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L616-36 assume 1 == ~t6_pc~0; 9602#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8345#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8346#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8890#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9062#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9391#L635-36 assume 1 == ~t7_pc~0; 9566#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9448#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9449#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9511#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9048#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9049#L654-36 assume !(1 == ~t8_pc~0); 9571#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9572#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9215#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9216#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9606#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8723#L673-36 assume 1 == ~t9_pc~0; 8724#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9090#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8953#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8954#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8286#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8287#L692-36 assume !(1 == ~t10_pc~0); 8501#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8502#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8796#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8690#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 8691#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9061#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9212#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9573#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9574#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9139#L1157-3 assume !(1 == ~T4_E~0); 9140#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9444#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9557#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9047#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8947#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8948#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8960#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8779#L1197-3 assume !(1 == ~E_1~0); 8780#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9030#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9148#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9372#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8683#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8370#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8371#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9473#L1237-3 assume !(1 == ~E_9~0); 9474#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9636#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9522#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8521#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8522#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8786#L1572 assume !(0 == start_simulation_~tmp~3#1); 8817#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8979#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8300#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 8359#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8271#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8272#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9119#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 8450#L1553-2 [2024-10-13 17:45:05,698 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:05,698 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2024-10-13 17:45:05,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:05,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616300813] [2024-10-13 17:45:05,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:05,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:05,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616300813] [2024-10-13 17:45:05,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616300813] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:05,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460622384] [2024-10-13 17:45:05,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,748 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:05,748 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:05,748 INFO L85 PathProgramCache]: Analyzing trace with hash -335821031, now seen corresponding path program 1 times [2024-10-13 17:45:05,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:05,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210105945] [2024-10-13 17:45:05,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:05,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:05,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,799 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210105945] [2024-10-13 17:45:05,800 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1210105945] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:05,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621204621] [2024-10-13 17:45:05,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,801 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:05,801 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:05,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:05,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:05,801 INFO L87 Difference]: Start difference. First operand 1372 states and 2032 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:05,818 INFO L93 Difference]: Finished difference Result 1372 states and 2031 transitions. [2024-10-13 17:45:05,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2031 transitions. [2024-10-13 17:45:05,825 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2031 transitions. [2024-10-13 17:45:05,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:05,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:05,831 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2031 transitions. [2024-10-13 17:45:05,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:05,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2024-10-13 17:45:05,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2031 transitions. [2024-10-13 17:45:05,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:05,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4803206997084548) internal successors, (2031), 1371 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2031 transitions. [2024-10-13 17:45:05,850 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2024-10-13 17:45:05,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:05,851 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2024-10-13 17:45:05,852 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-13 17:45:05,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2031 transitions. [2024-10-13 17:45:05,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:05,858 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:05,859 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:05,860 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:05,860 INFO L745 eck$LassoCheckResult]: Stem: 11400#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12303#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12304#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11982#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 11671#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11672#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11952#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12122#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11840#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11841#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11722#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11723#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12076#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12036#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11960#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11961#L1024 assume !(0 == ~M_E~0); 12216#L1024-2 assume !(0 == ~T1_E~0); 11396#L1029-1 assume !(0 == ~T2_E~0); 11397#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11499#L1039-1 assume !(0 == ~T4_E~0); 12326#L1044-1 assume !(0 == ~T5_E~0); 11744#L1049-1 assume !(0 == ~T6_E~0); 11745#L1054-1 assume !(0 == ~T7_E~0); 11981#L1059-1 assume !(0 == ~T8_E~0); 11446#L1064-1 assume !(0 == ~T9_E~0); 11447#L1069-1 assume !(0 == ~T10_E~0); 12185#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 12245#L1079-1 assume !(0 == ~E_1~0); 12218#L1084-1 assume !(0 == ~E_2~0); 12219#L1089-1 assume !(0 == ~E_3~0); 12263#L1094-1 assume !(0 == ~E_4~0); 11830#L1099-1 assume !(0 == ~E_5~0); 11831#L1104-1 assume !(0 == ~E_6~0); 12094#L1109-1 assume !(0 == ~E_7~0); 11613#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11614#L1119-1 assume !(0 == ~E_9~0); 11684#L1124-1 assume !(0 == ~E_10~0); 11100#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11101#L502 assume 1 == ~m_pc~0; 11979#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11226#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11227#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12032#L1273 assume !(0 != activate_threads_~tmp~1#1); 12033#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12356#L521 assume !(1 == ~t1_pc~0); 12291#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11151#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11116#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11117#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 11137#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11138#L540 assume 1 == ~t2_pc~0; 12229#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11941#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11610#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 12287#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11424#L559 assume 1 == ~t3_pc~0; 11425#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11702#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11054#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 11244#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11245#L578 assume !(1 == ~t4_pc~0); 11368#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11367#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11184#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11185#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12013#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12014#L597 assume 1 == ~t5_pc~0; 12372#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11171#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11172#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12214#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 11962#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11963#L616 assume !(1 == ~t6_pc~0); 11978#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11977#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11585#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11586#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 11820#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11821#L635 assume 1 == ~t7_pc~0; 12017#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11140#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11517#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12259#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 11954#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11955#L654 assume !(1 == ~t8_pc~0); 11771#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11772#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12147#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12148#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 12183#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11394#L673 assume 1 == ~t9_pc~0; 11395#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11091#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11666#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11667#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 12106#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12107#L692 assume !(1 == ~t10_pc~0); 12051#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12050#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11822#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11823#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 11834#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12162#L1142 assume !(1 == ~M_E~0); 11305#L1142-2 assume !(1 == ~T1_E~0); 11306#L1147-1 assume !(1 == ~T2_E~0); 12151#L1152-1 assume !(1 == ~T3_E~0); 11708#L1157-1 assume !(1 == ~T4_E~0); 11709#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11858#L1167-1 assume !(1 == ~T6_E~0); 11859#L1172-1 assume !(1 == ~T7_E~0); 12281#L1177-1 assume !(1 == ~T8_E~0); 11999#L1182-1 assume !(1 == ~T9_E~0); 12000#L1187-1 assume !(1 == ~T10_E~0); 12099#L1192-1 assume !(1 == ~E_M~0); 11565#L1197-1 assume !(1 == ~E_1~0); 11566#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11944#L1207-1 assume !(1 == ~E_3~0); 11919#L1212-1 assume !(1 == ~E_4~0); 11156#L1217-1 assume !(1 == ~E_5~0); 11157#L1222-1 assume !(1 == ~E_6~0); 11916#L1227-1 assume !(1 == ~E_7~0); 11917#L1232-1 assume !(1 == ~E_8~0); 11030#L1237-1 assume !(1 == ~E_9~0); 11031#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11980#L1247-1 assume { :end_inline_reset_delta_events } true; 11201#L1553-2 [2024-10-13 17:45:05,861 INFO L747 eck$LassoCheckResult]: Loop: 11201#L1553-2 assume !false; 11202#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11341#L999-1 assume !false; 11482#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11289#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11174#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11646#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11647#L854 assume !(0 != eval_~tmp~0#1); 12056#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11844#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12316#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11816#L1029-3 assume !(0 == ~T2_E~0); 11784#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11785#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12127#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11390#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11391#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11152#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11153#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11754#L1069-3 assume !(0 == ~T10_E~0); 11755#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12101#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11992#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11877#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11878#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11803#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11804#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12125#L1109-3 assume !(0 == ~E_7~0); 12113#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12114#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12377#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12384#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12350#L502-36 assume 1 == ~m_pc~0; 12128#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11018#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11019#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11448#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11449#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11727#L521-36 assume 1 == ~t1_pc~0; 11728#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11738#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11908#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12302#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12187#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12188#L540-36 assume 1 == ~t2_pc~0; 12352#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11103#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11520#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12189#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11853#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11024#L559-36 assume !(1 == ~t3_pc~0); 11025#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 11483#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11661#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11662#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 12001#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12241#L578-36 assume 1 == ~t4_pc~0; 11970#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11927#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11865#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11866#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11762#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11763#L597-36 assume !(1 == ~t5_pc~0); 11989#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 12342#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12286#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11943#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11563#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11564#L616-36 assume 1 == ~t6_pc~0; 12353#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11096#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11097#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11641#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11813#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12142#L635-36 assume 1 == ~t7_pc~0; 12317#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12199#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12200#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12262#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11799#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11800#L654-36 assume !(1 == ~t8_pc~0); 12322#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12323#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11966#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11967#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12357#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11474#L673-36 assume 1 == ~t9_pc~0; 11475#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11839#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11704#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11705#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11037#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11038#L692-36 assume !(1 == ~t10_pc~0); 11252#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 11253#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11547#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11441#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 11442#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11810#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11959#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12324#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12325#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11890#L1157-3 assume !(1 == ~T4_E~0); 11891#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12195#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12308#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11798#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11696#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11697#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11711#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11530#L1197-3 assume !(1 == ~E_1~0); 11531#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11781#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11899#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12123#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11434#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11121#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11122#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12224#L1237-3 assume !(1 == ~E_9~0); 12225#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12387#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12273#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11272#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 11537#L1572 assume !(0 == start_simulation_~tmp~3#1); 11568#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11730#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11051#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 11110#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11022#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11023#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11870#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 11201#L1553-2 [2024-10-13 17:45:05,861 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:05,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2024-10-13 17:45:05,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:05,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739060352] [2024-10-13 17:45:05,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:05,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:05,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [739060352] [2024-10-13 17:45:05,895 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [739060352] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,895 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:05,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971098573] [2024-10-13 17:45:05,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,896 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:05,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:05,896 INFO L85 PathProgramCache]: Analyzing trace with hash -335821031, now seen corresponding path program 2 times [2024-10-13 17:45:05,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:05,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221490070] [2024-10-13 17:45:05,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:05,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:05,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:05,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:05,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:05,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221490070] [2024-10-13 17:45:05,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221490070] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:05,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:05,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:05,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425550136] [2024-10-13 17:45:05,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:05,960 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:05,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:05,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:05,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:05,961 INFO L87 Difference]: Start difference. First operand 1372 states and 2031 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:05,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:05,979 INFO L93 Difference]: Finished difference Result 1372 states and 2030 transitions. [2024-10-13 17:45:05,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2030 transitions. [2024-10-13 17:45:05,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:05,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2030 transitions. [2024-10-13 17:45:05,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:05,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:05,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2030 transitions. [2024-10-13 17:45:05,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:05,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2024-10-13 17:45:05,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2030 transitions. [2024-10-13 17:45:06,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:06,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4795918367346939) internal successors, (2030), 1371 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2030 transitions. [2024-10-13 17:45:06,005 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2024-10-13 17:45:06,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:06,007 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2024-10-13 17:45:06,007 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-13 17:45:06,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2030 transitions. [2024-10-13 17:45:06,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:06,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:06,013 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,013 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,013 INFO L745 eck$LassoCheckResult]: Stem: 14151#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 15053#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15054#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14733#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 14421#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14422#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14703#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14873#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14590#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14591#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14473#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14474#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14827#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14787#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14710#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14711#L1024 assume !(0 == ~M_E~0); 14967#L1024-2 assume !(0 == ~T1_E~0); 14147#L1029-1 assume !(0 == ~T2_E~0); 14148#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14250#L1039-1 assume !(0 == ~T4_E~0); 15077#L1044-1 assume !(0 == ~T5_E~0); 14493#L1049-1 assume !(0 == ~T6_E~0); 14494#L1054-1 assume !(0 == ~T7_E~0); 14732#L1059-1 assume !(0 == ~T8_E~0); 14197#L1064-1 assume !(0 == ~T9_E~0); 14198#L1069-1 assume !(0 == ~T10_E~0); 14936#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14996#L1079-1 assume !(0 == ~E_1~0); 14969#L1084-1 assume !(0 == ~E_2~0); 14970#L1089-1 assume !(0 == ~E_3~0); 15014#L1094-1 assume !(0 == ~E_4~0); 14581#L1099-1 assume !(0 == ~E_5~0); 14582#L1104-1 assume !(0 == ~E_6~0); 14845#L1109-1 assume !(0 == ~E_7~0); 14364#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14365#L1119-1 assume !(0 == ~E_9~0); 14431#L1124-1 assume !(0 == ~E_10~0); 13851#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13852#L502 assume 1 == ~m_pc~0; 14730#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13977#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13978#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14781#L1273 assume !(0 != activate_threads_~tmp~1#1); 14782#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15107#L521 assume !(1 == ~t1_pc~0); 15042#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13902#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13868#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 13888#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13889#L540 assume 1 == ~t2_pc~0; 14980#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14692#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14360#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14361#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 15038#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14175#L559 assume 1 == ~t3_pc~0; 14176#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14452#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13804#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13805#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 13995#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13996#L578 assume !(1 == ~t4_pc~0); 14114#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14113#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13934#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13935#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14762#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14763#L597 assume 1 == ~t5_pc~0; 15122#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13922#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13923#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14965#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 14712#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14713#L616 assume !(1 == ~t6_pc~0); 14727#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14726#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14336#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14337#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 14570#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14571#L635 assume 1 == ~t7_pc~0; 14767#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13891#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14266#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15010#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 14705#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14706#L654 assume !(1 == ~t8_pc~0); 14522#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14523#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14896#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 14934#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14145#L673 assume 1 == ~t9_pc~0; 14146#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13842#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14415#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14416#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 14857#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14858#L692 assume !(1 == ~t10_pc~0); 14802#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14801#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14573#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14574#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 14585#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14913#L1142 assume !(1 == ~M_E~0); 14056#L1142-2 assume !(1 == ~T1_E~0); 14057#L1147-1 assume !(1 == ~T2_E~0); 14902#L1152-1 assume !(1 == ~T3_E~0); 14459#L1157-1 assume !(1 == ~T4_E~0); 14460#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14609#L1167-1 assume !(1 == ~T6_E~0); 14610#L1172-1 assume !(1 == ~T7_E~0); 15031#L1177-1 assume !(1 == ~T8_E~0); 14750#L1182-1 assume !(1 == ~T9_E~0); 14751#L1187-1 assume !(1 == ~T10_E~0); 14850#L1192-1 assume !(1 == ~E_M~0); 14314#L1197-1 assume !(1 == ~E_1~0); 14315#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14694#L1207-1 assume !(1 == ~E_3~0); 14670#L1212-1 assume !(1 == ~E_4~0); 13907#L1217-1 assume !(1 == ~E_5~0); 13908#L1222-1 assume !(1 == ~E_6~0); 14667#L1227-1 assume !(1 == ~E_7~0); 14668#L1232-1 assume !(1 == ~E_8~0); 13781#L1237-1 assume !(1 == ~E_9~0); 13782#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14731#L1247-1 assume { :end_inline_reset_delta_events } true; 13952#L1553-2 [2024-10-13 17:45:06,014 INFO L747 eck$LassoCheckResult]: Loop: 13952#L1553-2 assume !false; 13953#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14092#L999-1 assume !false; 14233#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14040#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13925#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14397#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14398#L854 assume !(0 != eval_~tmp~0#1); 14807#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14594#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14595#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15067#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14567#L1029-3 assume !(0 == ~T2_E~0); 14535#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14536#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14878#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14141#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14142#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13903#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13904#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14505#L1069-3 assume !(0 == ~T10_E~0); 14506#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14852#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14742#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14628#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14629#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14554#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14555#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14876#L1109-3 assume !(0 == ~E_7~0); 14864#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14865#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15128#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15135#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15101#L502-36 assume !(1 == ~m_pc~0); 14284#L502-38 is_master_triggered_~__retres1~0#1 := 0; 13769#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13770#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14199#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14200#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14478#L521-36 assume !(1 == ~t1_pc~0); 14480#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 14489#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14659#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15055#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14938#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14939#L540-36 assume !(1 == ~t2_pc~0); 13858#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 13859#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14271#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14940#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14604#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13778#L559-36 assume !(1 == ~t3_pc~0); 13779#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 14237#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14412#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14413#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 14752#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14992#L578-36 assume 1 == ~t4_pc~0; 14721#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14680#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14616#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14617#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14513#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14514#L597-36 assume !(1 == ~t5_pc~0); 14740#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 15093#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15037#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14695#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14316#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14317#L616-36 assume 1 == ~t6_pc~0; 15104#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13847#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13848#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14392#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14564#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14893#L635-36 assume 1 == ~t7_pc~0; 15068#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14950#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14951#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15013#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14550#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14551#L654-36 assume !(1 == ~t8_pc~0); 15073#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 15074#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14717#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14718#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15108#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14225#L673-36 assume 1 == ~t9_pc~0; 14226#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14592#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14455#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14456#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13788#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13789#L692-36 assume !(1 == ~t10_pc~0); 14003#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14004#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14298#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14192#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 14193#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14563#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14714#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15075#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14641#L1157-3 assume !(1 == ~T4_E~0); 14642#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14946#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15059#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14549#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14447#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14448#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14462#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14281#L1197-3 assume !(1 == ~E_1~0); 14282#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14532#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14650#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14874#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14185#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13872#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13873#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14975#L1237-3 assume !(1 == ~E_9~0); 14976#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15138#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 15024#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14023#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14024#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14288#L1572 assume !(0 == start_simulation_~tmp~3#1); 14319#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14481#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13802#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13860#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 13861#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13773#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13774#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14621#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 13952#L1553-2 [2024-10-13 17:45:06,014 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,015 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2024-10-13 17:45:06,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805860206] [2024-10-13 17:45:06,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805860206] [2024-10-13 17:45:06,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1805860206] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,052 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,052 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206541337] [2024-10-13 17:45:06,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,052 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:06,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,053 INFO L85 PathProgramCache]: Analyzing trace with hash 1415396764, now seen corresponding path program 1 times [2024-10-13 17:45:06,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875462699] [2024-10-13 17:45:06,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875462699] [2024-10-13 17:45:06,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875462699] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757348135] [2024-10-13 17:45:06,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,101 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:06,101 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:06,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:06,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:06,102 INFO L87 Difference]: Start difference. First operand 1372 states and 2030 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:06,118 INFO L93 Difference]: Finished difference Result 1372 states and 2029 transitions. [2024-10-13 17:45:06,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2029 transitions. [2024-10-13 17:45:06,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2029 transitions. [2024-10-13 17:45:06,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:06,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:06,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2029 transitions. [2024-10-13 17:45:06,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:06,133 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2024-10-13 17:45:06,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2029 transitions. [2024-10-13 17:45:06,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:06,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.478862973760933) internal successors, (2029), 1371 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2029 transitions. [2024-10-13 17:45:06,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2024-10-13 17:45:06,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:06,153 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2024-10-13 17:45:06,153 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-13 17:45:06,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2029 transitions. [2024-10-13 17:45:06,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:06,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:06,164 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,164 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,164 INFO L745 eck$LassoCheckResult]: Stem: 16902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 16903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17805#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17484#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 17172#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17173#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17454#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17624#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17341#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17342#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17224#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17225#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17578#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17538#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17461#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17462#L1024 assume !(0 == ~M_E~0); 17718#L1024-2 assume !(0 == ~T1_E~0); 16898#L1029-1 assume !(0 == ~T2_E~0); 16899#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17001#L1039-1 assume !(0 == ~T4_E~0); 17828#L1044-1 assume !(0 == ~T5_E~0); 17244#L1049-1 assume !(0 == ~T6_E~0); 17245#L1054-1 assume !(0 == ~T7_E~0); 17483#L1059-1 assume !(0 == ~T8_E~0); 16948#L1064-1 assume !(0 == ~T9_E~0); 16949#L1069-1 assume !(0 == ~T10_E~0); 17687#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17747#L1079-1 assume !(0 == ~E_1~0); 17720#L1084-1 assume !(0 == ~E_2~0); 17721#L1089-1 assume !(0 == ~E_3~0); 17765#L1094-1 assume !(0 == ~E_4~0); 17332#L1099-1 assume !(0 == ~E_5~0); 17333#L1104-1 assume !(0 == ~E_6~0); 17596#L1109-1 assume !(0 == ~E_7~0); 17115#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17116#L1119-1 assume !(0 == ~E_9~0); 17182#L1124-1 assume !(0 == ~E_10~0); 16602#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16603#L502 assume 1 == ~m_pc~0; 17481#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16728#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16729#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17532#L1273 assume !(0 != activate_threads_~tmp~1#1); 17533#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17858#L521 assume !(1 == ~t1_pc~0); 17793#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16653#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16619#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 16639#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16640#L540 assume 1 == ~t2_pc~0; 17731#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17443#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17111#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17112#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 17789#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16926#L559 assume 1 == ~t3_pc~0; 16927#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17203#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16555#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16556#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 16746#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16747#L578 assume !(1 == ~t4_pc~0); 16868#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16867#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16686#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16687#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17515#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17516#L597 assume 1 == ~t5_pc~0; 17873#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16673#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16674#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17716#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 17463#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17464#L616 assume !(1 == ~t6_pc~0); 17478#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17477#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17087#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17088#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 17321#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17322#L635 assume 1 == ~t7_pc~0; 17518#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16642#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17017#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17761#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 17456#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17457#L654 assume !(1 == ~t8_pc~0); 17273#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17274#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17648#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17649#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 17685#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16896#L673 assume 1 == ~t9_pc~0; 16897#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16593#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17168#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17169#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 17608#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17609#L692 assume !(1 == ~t10_pc~0); 17553#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17552#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17324#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17325#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 17336#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17664#L1142 assume !(1 == ~M_E~0); 16807#L1142-2 assume !(1 == ~T1_E~0); 16808#L1147-1 assume !(1 == ~T2_E~0); 17653#L1152-1 assume !(1 == ~T3_E~0); 17210#L1157-1 assume !(1 == ~T4_E~0); 17211#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17360#L1167-1 assume !(1 == ~T6_E~0); 17361#L1172-1 assume !(1 == ~T7_E~0); 17782#L1177-1 assume !(1 == ~T8_E~0); 17501#L1182-1 assume !(1 == ~T9_E~0); 17502#L1187-1 assume !(1 == ~T10_E~0); 17601#L1192-1 assume !(1 == ~E_M~0); 17065#L1197-1 assume !(1 == ~E_1~0); 17066#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17445#L1207-1 assume !(1 == ~E_3~0); 17421#L1212-1 assume !(1 == ~E_4~0); 16658#L1217-1 assume !(1 == ~E_5~0); 16659#L1222-1 assume !(1 == ~E_6~0); 17418#L1227-1 assume !(1 == ~E_7~0); 17419#L1232-1 assume !(1 == ~E_8~0); 16532#L1237-1 assume !(1 == ~E_9~0); 16533#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 17482#L1247-1 assume { :end_inline_reset_delta_events } true; 16703#L1553-2 [2024-10-13 17:45:06,165 INFO L747 eck$LassoCheckResult]: Loop: 16703#L1553-2 assume !false; 16704#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16843#L999-1 assume !false; 16984#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16791#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16676#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17148#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17149#L854 assume !(0 != eval_~tmp~0#1); 17558#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17345#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17346#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17818#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17318#L1029-3 assume !(0 == ~T2_E~0); 17286#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17287#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17629#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16892#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16893#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16654#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16655#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17256#L1069-3 assume !(0 == ~T10_E~0); 17257#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17603#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17493#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17379#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17380#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17305#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17306#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17627#L1109-3 assume !(0 == ~E_7~0); 17615#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17616#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17879#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17886#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17852#L502-36 assume !(1 == ~m_pc~0); 17035#L502-38 is_master_triggered_~__retres1~0#1 := 0; 16520#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16521#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16950#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16951#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17229#L521-36 assume 1 == ~t1_pc~0; 17230#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17240#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17410#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17806#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17689#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17690#L540-36 assume !(1 == ~t2_pc~0); 16609#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 16610#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17022#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17691#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17355#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16529#L559-36 assume !(1 == ~t3_pc~0); 16530#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 16988#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17163#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17164#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 17503#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17743#L578-36 assume 1 == ~t4_pc~0; 17473#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17431#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17367#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17368#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17264#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17265#L597-36 assume !(1 == ~t5_pc~0); 17491#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 17844#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17788#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17446#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17067#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17068#L616-36 assume !(1 == ~t6_pc~0); 17814#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 16598#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16599#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17143#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17315#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17644#L635-36 assume 1 == ~t7_pc~0; 17819#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17701#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17702#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17764#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17301#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17302#L654-36 assume !(1 == ~t8_pc~0); 17824#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 17825#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17468#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17469#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17859#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16976#L673-36 assume 1 == ~t9_pc~0; 16977#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17343#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17206#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17207#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16539#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16540#L692-36 assume !(1 == ~t10_pc~0); 16754#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 16755#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17049#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16943#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 16944#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17314#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17465#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17826#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17827#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17392#L1157-3 assume !(1 == ~T4_E~0); 17393#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17697#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17811#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17300#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17200#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17201#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17213#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17032#L1197-3 assume !(1 == ~E_1~0); 17033#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17283#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17401#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17626#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16936#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16623#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16624#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17726#L1237-3 assume !(1 == ~E_9~0); 17727#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17889#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17775#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16774#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16775#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17039#L1572 assume !(0 == start_simulation_~tmp~3#1); 17070#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17232#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16553#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 16612#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16524#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16525#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17372#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 16703#L1553-2 [2024-10-13 17:45:06,165 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,166 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2024-10-13 17:45:06,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531714352] [2024-10-13 17:45:06,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,214 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531714352] [2024-10-13 17:45:06,214 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531714352] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,214 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,214 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789180248] [2024-10-13 17:45:06,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,215 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:06,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,215 INFO L85 PathProgramCache]: Analyzing trace with hash 1920116060, now seen corresponding path program 1 times [2024-10-13 17:45:06,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031955420] [2024-10-13 17:45:06,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,284 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1031955420] [2024-10-13 17:45:06,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1031955420] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,284 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,284 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [823791074] [2024-10-13 17:45:06,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,285 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:06,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:06,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:06,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:06,285 INFO L87 Difference]: Start difference. First operand 1372 states and 2029 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:06,320 INFO L93 Difference]: Finished difference Result 1372 states and 2028 transitions. [2024-10-13 17:45:06,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2028 transitions. [2024-10-13 17:45:06,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2028 transitions. [2024-10-13 17:45:06,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:06,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:06,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2028 transitions. [2024-10-13 17:45:06,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:06,345 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2024-10-13 17:45:06,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2028 transitions. [2024-10-13 17:45:06,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:06,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.478134110787172) internal successors, (2028), 1371 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2028 transitions. [2024-10-13 17:45:06,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2024-10-13 17:45:06,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:06,382 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2024-10-13 17:45:06,382 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-13 17:45:06,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2028 transitions. [2024-10-13 17:45:06,390 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:06,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:06,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,392 INFO L745 eck$LassoCheckResult]: Stem: 19653#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20556#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20557#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20235#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 19924#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19925#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20206#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20375#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20093#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20094#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19978#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19979#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20329#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20289#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20213#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20214#L1024 assume !(0 == ~M_E~0); 20469#L1024-2 assume !(0 == ~T1_E~0); 19649#L1029-1 assume !(0 == ~T2_E~0); 19650#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19752#L1039-1 assume !(0 == ~T4_E~0); 20579#L1044-1 assume !(0 == ~T5_E~0); 19997#L1049-1 assume !(0 == ~T6_E~0); 19998#L1054-1 assume !(0 == ~T7_E~0); 20234#L1059-1 assume !(0 == ~T8_E~0); 19699#L1064-1 assume !(0 == ~T9_E~0); 19700#L1069-1 assume !(0 == ~T10_E~0); 20438#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20498#L1079-1 assume !(0 == ~E_1~0); 20471#L1084-1 assume !(0 == ~E_2~0); 20472#L1089-1 assume !(0 == ~E_3~0); 20516#L1094-1 assume !(0 == ~E_4~0); 20083#L1099-1 assume !(0 == ~E_5~0); 20084#L1104-1 assume !(0 == ~E_6~0); 20347#L1109-1 assume !(0 == ~E_7~0); 19866#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19867#L1119-1 assume !(0 == ~E_9~0); 19937#L1124-1 assume !(0 == ~E_10~0); 19353#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19354#L502 assume 1 == ~m_pc~0; 20232#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19479#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19480#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20285#L1273 assume !(0 != activate_threads_~tmp~1#1); 20286#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20609#L521 assume !(1 == ~t1_pc~0); 20544#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19404#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19370#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 19390#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19391#L540 assume 1 == ~t2_pc~0; 20482#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20194#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19864#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19865#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 20540#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19677#L559 assume 1 == ~t3_pc~0; 19678#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19955#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19306#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19307#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 19497#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19498#L578 assume !(1 == ~t4_pc~0); 19621#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19620#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19438#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20266#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20267#L597 assume 1 == ~t5_pc~0; 20625#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19424#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19425#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20467#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 20215#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20216#L616 assume !(1 == ~t6_pc~0); 20231#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20230#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19838#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19839#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 20073#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20074#L635 assume 1 == ~t7_pc~0; 20270#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19393#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19770#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20512#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 20207#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20208#L654 assume !(1 == ~t8_pc~0); 20024#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20025#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20400#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20401#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 20436#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19647#L673 assume 1 == ~t9_pc~0; 19648#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19344#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19919#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19920#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 20359#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20360#L692 assume !(1 == ~t10_pc~0); 20304#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20303#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20075#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20076#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 20087#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20415#L1142 assume !(1 == ~M_E~0); 19558#L1142-2 assume !(1 == ~T1_E~0); 19559#L1147-1 assume !(1 == ~T2_E~0); 20404#L1152-1 assume !(1 == ~T3_E~0); 19961#L1157-1 assume !(1 == ~T4_E~0); 19962#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20111#L1167-1 assume !(1 == ~T6_E~0); 20112#L1172-1 assume !(1 == ~T7_E~0); 20534#L1177-1 assume !(1 == ~T8_E~0); 20252#L1182-1 assume !(1 == ~T9_E~0); 20253#L1187-1 assume !(1 == ~T10_E~0); 20352#L1192-1 assume !(1 == ~E_M~0); 19818#L1197-1 assume !(1 == ~E_1~0); 19819#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20197#L1207-1 assume !(1 == ~E_3~0); 20172#L1212-1 assume !(1 == ~E_4~0); 19409#L1217-1 assume !(1 == ~E_5~0); 19410#L1222-1 assume !(1 == ~E_6~0); 20169#L1227-1 assume !(1 == ~E_7~0); 20170#L1232-1 assume !(1 == ~E_8~0); 19283#L1237-1 assume !(1 == ~E_9~0); 19284#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20233#L1247-1 assume { :end_inline_reset_delta_events } true; 19454#L1553-2 [2024-10-13 17:45:06,392 INFO L747 eck$LassoCheckResult]: Loop: 19454#L1553-2 assume !false; 19455#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19594#L999-1 assume !false; 19735#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19542#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19427#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19899#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19900#L854 assume !(0 != eval_~tmp~0#1); 20309#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20097#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20569#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20069#L1029-3 assume !(0 == ~T2_E~0); 20037#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20038#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20380#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19643#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19644#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19405#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19406#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20007#L1069-3 assume !(0 == ~T10_E~0); 20008#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20354#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20245#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20130#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20131#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20056#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20057#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20378#L1109-3 assume !(0 == ~E_7~0); 20366#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20367#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20630#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20637#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20603#L502-36 assume !(1 == ~m_pc~0); 19786#L502-38 is_master_triggered_~__retres1~0#1 := 0; 19271#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19272#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19701#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19702#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19975#L521-36 assume 1 == ~t1_pc~0; 19976#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19991#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20161#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20555#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20440#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20441#L540-36 assume 1 == ~t2_pc~0; 20605#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19358#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19773#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20442#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20106#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19277#L559-36 assume !(1 == ~t3_pc~0); 19278#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 19739#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19914#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19915#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 20254#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20494#L578-36 assume !(1 == ~t4_pc~0); 20179#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20180#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20118#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20119#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20015#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20016#L597-36 assume !(1 == ~t5_pc~0); 20242#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 20595#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20539#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20196#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19816#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19817#L616-36 assume !(1 == ~t6_pc~0); 20565#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 19349#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19350#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19894#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20066#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20395#L635-36 assume 1 == ~t7_pc~0; 20570#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20452#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20453#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20515#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20052#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20053#L654-36 assume 1 == ~t8_pc~0; 20633#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20576#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20219#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20220#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20610#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19727#L673-36 assume 1 == ~t9_pc~0; 19728#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20092#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19957#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19958#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19290#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19291#L692-36 assume !(1 == ~t10_pc~0); 19505#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 19506#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19800#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19694#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 19695#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20063#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20212#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20577#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20578#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20143#L1157-3 assume !(1 == ~T4_E~0); 20144#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20448#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20561#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20051#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19949#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19950#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19964#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19783#L1197-3 assume !(1 == ~E_1~0); 19784#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20034#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20152#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20376#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19687#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19374#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19375#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20477#L1237-3 assume !(1 == ~E_9~0); 20478#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20640#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20526#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19525#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19526#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19790#L1572 assume !(0 == start_simulation_~tmp~3#1); 19821#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19983#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19304#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19362#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 19363#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19275#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19276#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20123#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 19454#L1553-2 [2024-10-13 17:45:06,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,394 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2024-10-13 17:45:06,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054273536] [2024-10-13 17:45:06,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054273536] [2024-10-13 17:45:06,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054273536] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,447 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,447 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1813887977] [2024-10-13 17:45:06,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,448 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:06,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,448 INFO L85 PathProgramCache]: Analyzing trace with hash 1738262043, now seen corresponding path program 1 times [2024-10-13 17:45:06,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,450 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977715220] [2024-10-13 17:45:06,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977715220] [2024-10-13 17:45:06,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977715220] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787558431] [2024-10-13 17:45:06,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,545 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:06,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:06,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:06,546 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:06,546 INFO L87 Difference]: Start difference. First operand 1372 states and 2028 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:06,568 INFO L93 Difference]: Finished difference Result 1372 states and 2027 transitions. [2024-10-13 17:45:06,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2027 transitions. [2024-10-13 17:45:06,574 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2027 transitions. [2024-10-13 17:45:06,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:06,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:06,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2027 transitions. [2024-10-13 17:45:06,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:06,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2024-10-13 17:45:06,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2027 transitions. [2024-10-13 17:45:06,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:06,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.477405247813411) internal successors, (2027), 1371 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2027 transitions. [2024-10-13 17:45:06,599 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2024-10-13 17:45:06,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:06,600 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2024-10-13 17:45:06,600 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-13 17:45:06,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2027 transitions. [2024-10-13 17:45:06,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:06,605 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:06,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,606 INFO L745 eck$LassoCheckResult]: Stem: 22404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22986#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 22674#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22675#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22956#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23126#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22843#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22844#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22726#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22727#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 23080#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23040#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22963#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22964#L1024 assume !(0 == ~M_E~0); 23220#L1024-2 assume !(0 == ~T1_E~0); 22400#L1029-1 assume !(0 == ~T2_E~0); 22401#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22503#L1039-1 assume !(0 == ~T4_E~0); 23330#L1044-1 assume !(0 == ~T5_E~0); 22746#L1049-1 assume !(0 == ~T6_E~0); 22747#L1054-1 assume !(0 == ~T7_E~0); 22985#L1059-1 assume !(0 == ~T8_E~0); 22450#L1064-1 assume !(0 == ~T9_E~0); 22451#L1069-1 assume !(0 == ~T10_E~0); 23189#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 23249#L1079-1 assume !(0 == ~E_1~0); 23222#L1084-1 assume !(0 == ~E_2~0); 23223#L1089-1 assume !(0 == ~E_3~0); 23267#L1094-1 assume !(0 == ~E_4~0); 22834#L1099-1 assume !(0 == ~E_5~0); 22835#L1104-1 assume !(0 == ~E_6~0); 23098#L1109-1 assume !(0 == ~E_7~0); 22617#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22618#L1119-1 assume !(0 == ~E_9~0); 22684#L1124-1 assume !(0 == ~E_10~0); 22104#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22105#L502 assume 1 == ~m_pc~0; 22983#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22230#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22231#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23034#L1273 assume !(0 != activate_threads_~tmp~1#1); 23035#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23360#L521 assume !(1 == ~t1_pc~0); 23295#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22155#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22120#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22121#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 22141#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22142#L540 assume 1 == ~t2_pc~0; 23233#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22945#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22613#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22614#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 23291#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22428#L559 assume 1 == ~t3_pc~0; 22429#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22705#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22057#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22058#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 22248#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22249#L578 assume !(1 == ~t4_pc~0); 22367#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22366#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22188#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23015#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23016#L597 assume 1 == ~t5_pc~0; 23375#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22175#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22176#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23218#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 22965#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22966#L616 assume !(1 == ~t6_pc~0); 22980#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22979#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22589#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22590#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 22823#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22824#L635 assume 1 == ~t7_pc~0; 23020#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22144#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22519#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23263#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 22958#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22959#L654 assume !(1 == ~t8_pc~0); 22775#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22776#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23148#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23149#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 23187#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22398#L673 assume 1 == ~t9_pc~0; 22399#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22095#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22668#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22669#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 23110#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23111#L692 assume !(1 == ~t10_pc~0); 23055#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23054#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22826#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22827#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 22838#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23166#L1142 assume !(1 == ~M_E~0); 22309#L1142-2 assume !(1 == ~T1_E~0); 22310#L1147-1 assume !(1 == ~T2_E~0); 23155#L1152-1 assume !(1 == ~T3_E~0); 22712#L1157-1 assume !(1 == ~T4_E~0); 22713#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22862#L1167-1 assume !(1 == ~T6_E~0); 22863#L1172-1 assume !(1 == ~T7_E~0); 23284#L1177-1 assume !(1 == ~T8_E~0); 23003#L1182-1 assume !(1 == ~T9_E~0); 23004#L1187-1 assume !(1 == ~T10_E~0); 23103#L1192-1 assume !(1 == ~E_M~0); 22567#L1197-1 assume !(1 == ~E_1~0); 22568#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22947#L1207-1 assume !(1 == ~E_3~0); 22923#L1212-1 assume !(1 == ~E_4~0); 22160#L1217-1 assume !(1 == ~E_5~0); 22161#L1222-1 assume !(1 == ~E_6~0); 22920#L1227-1 assume !(1 == ~E_7~0); 22921#L1232-1 assume !(1 == ~E_8~0); 22034#L1237-1 assume !(1 == ~E_9~0); 22035#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22984#L1247-1 assume { :end_inline_reset_delta_events } true; 22205#L1553-2 [2024-10-13 17:45:06,607 INFO L747 eck$LassoCheckResult]: Loop: 22205#L1553-2 assume !false; 22206#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22345#L999-1 assume !false; 22486#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22293#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22178#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22650#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22651#L854 assume !(0 != eval_~tmp~0#1); 23060#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22847#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22848#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23320#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22820#L1029-3 assume !(0 == ~T2_E~0); 22788#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22789#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23131#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22394#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22395#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22156#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22157#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22758#L1069-3 assume !(0 == ~T10_E~0); 22759#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23105#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22995#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22881#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22882#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22807#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22808#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23129#L1109-3 assume !(0 == ~E_7~0); 23117#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23118#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23381#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23388#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23354#L502-36 assume !(1 == ~m_pc~0); 22537#L502-38 is_master_triggered_~__retres1~0#1 := 0; 22022#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22023#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22452#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22453#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22731#L521-36 assume 1 == ~t1_pc~0; 22732#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22742#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22912#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23308#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23191#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23192#L540-36 assume 1 == ~t2_pc~0; 23356#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22112#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22524#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23193#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22857#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22031#L559-36 assume !(1 == ~t3_pc~0); 22032#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 22490#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22665#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22666#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 23005#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23245#L578-36 assume !(1 == ~t4_pc~0); 22932#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 22933#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22869#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22870#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22766#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22767#L597-36 assume !(1 == ~t5_pc~0); 22993#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 23346#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23290#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22948#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22569#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22570#L616-36 assume !(1 == ~t6_pc~0); 23316#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 22100#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22101#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22645#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22817#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23146#L635-36 assume 1 == ~t7_pc~0; 23321#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23203#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23204#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23266#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22803#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22804#L654-36 assume 1 == ~t8_pc~0; 23384#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23327#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22970#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22971#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23361#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22478#L673-36 assume !(1 == ~t9_pc~0); 22480#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 22845#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22708#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22709#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22041#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22042#L692-36 assume !(1 == ~t10_pc~0); 22256#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 22257#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22551#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22445#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 22446#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22816#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22967#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23328#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23329#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22894#L1157-3 assume !(1 == ~T4_E~0); 22895#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23199#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23312#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22802#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22700#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22701#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22715#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22534#L1197-3 assume !(1 == ~E_1~0); 22535#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22785#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22903#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23127#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22438#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22125#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22126#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23228#L1237-3 assume !(1 == ~E_9~0); 23229#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23391#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23277#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22276#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 22541#L1572 assume !(0 == start_simulation_~tmp~3#1); 22572#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22734#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22055#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 22114#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22026#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22027#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22874#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 22205#L1553-2 [2024-10-13 17:45:06,607 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,608 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2024-10-13 17:45:06,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159166012] [2024-10-13 17:45:06,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159166012] [2024-10-13 17:45:06,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159166012] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844559662] [2024-10-13 17:45:06,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,641 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:06,641 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,641 INFO L85 PathProgramCache]: Analyzing trace with hash -155180132, now seen corresponding path program 1 times [2024-10-13 17:45:06,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416193230] [2024-10-13 17:45:06,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416193230] [2024-10-13 17:45:06,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416193230] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451550750] [2024-10-13 17:45:06,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,688 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:06,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:06,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:06,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:06,689 INFO L87 Difference]: Start difference. First operand 1372 states and 2027 transitions. cyclomatic complexity: 656 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:06,711 INFO L93 Difference]: Finished difference Result 1372 states and 2026 transitions. [2024-10-13 17:45:06,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2026 transitions. [2024-10-13 17:45:06,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2026 transitions. [2024-10-13 17:45:06,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-10-13 17:45:06,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-10-13 17:45:06,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2026 transitions. [2024-10-13 17:45:06,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:06,729 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2024-10-13 17:45:06,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2026 transitions. [2024-10-13 17:45:06,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-10-13 17:45:06,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4766763848396502) internal successors, (2026), 1371 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2026 transitions. [2024-10-13 17:45:06,748 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2024-10-13 17:45:06,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:06,749 INFO L425 stractBuchiCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2024-10-13 17:45:06,749 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-13 17:45:06,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2026 transitions. [2024-10-13 17:45:06,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-10-13 17:45:06,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:06,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:06,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:06,755 INFO L745 eck$LassoCheckResult]: Stem: 25155#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26057#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26058#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25737#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 25425#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25426#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25707#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25877#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25595#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25596#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25477#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25478#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25831#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25791#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 25715#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25716#L1024 assume !(0 == ~M_E~0); 25971#L1024-2 assume !(0 == ~T1_E~0); 25151#L1029-1 assume !(0 == ~T2_E~0); 25152#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25254#L1039-1 assume !(0 == ~T4_E~0); 26081#L1044-1 assume !(0 == ~T5_E~0); 25497#L1049-1 assume !(0 == ~T6_E~0); 25498#L1054-1 assume !(0 == ~T7_E~0); 25736#L1059-1 assume !(0 == ~T8_E~0); 25201#L1064-1 assume !(0 == ~T9_E~0); 25202#L1069-1 assume !(0 == ~T10_E~0); 25940#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 26000#L1079-1 assume !(0 == ~E_1~0); 25973#L1084-1 assume !(0 == ~E_2~0); 25974#L1089-1 assume !(0 == ~E_3~0); 26018#L1094-1 assume !(0 == ~E_4~0); 25585#L1099-1 assume !(0 == ~E_5~0); 25586#L1104-1 assume !(0 == ~E_6~0); 25849#L1109-1 assume !(0 == ~E_7~0); 25368#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25369#L1119-1 assume !(0 == ~E_9~0); 25435#L1124-1 assume !(0 == ~E_10~0); 24855#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24856#L502 assume 1 == ~m_pc~0; 25734#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24981#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24982#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25785#L1273 assume !(0 != activate_threads_~tmp~1#1); 25786#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26111#L521 assume !(1 == ~t1_pc~0); 26046#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24906#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24871#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24872#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 24892#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24893#L540 assume 1 == ~t2_pc~0; 25984#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25696#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25364#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25365#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 26042#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25179#L559 assume 1 == ~t3_pc~0; 25180#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25456#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24808#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24809#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 24999#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25000#L578 assume !(1 == ~t4_pc~0); 25121#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25120#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24939#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24940#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25768#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25769#L597 assume 1 == ~t5_pc~0; 26126#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24926#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25969#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 25717#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25718#L616 assume !(1 == ~t6_pc~0); 25731#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25730#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25341#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 25574#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25575#L635 assume 1 == ~t7_pc~0; 25771#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24895#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25270#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26014#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 25709#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25710#L654 assume !(1 == ~t8_pc~0); 25526#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25527#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25901#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25902#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 25938#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25149#L673 assume 1 == ~t9_pc~0; 25150#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24846#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25421#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25422#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 25861#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25862#L692 assume !(1 == ~t10_pc~0); 25806#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25805#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25577#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25578#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 25589#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25917#L1142 assume !(1 == ~M_E~0); 25060#L1142-2 assume !(1 == ~T1_E~0); 25061#L1147-1 assume !(1 == ~T2_E~0); 25906#L1152-1 assume !(1 == ~T3_E~0); 25463#L1157-1 assume !(1 == ~T4_E~0); 25464#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25613#L1167-1 assume !(1 == ~T6_E~0); 25614#L1172-1 assume !(1 == ~T7_E~0); 26035#L1177-1 assume !(1 == ~T8_E~0); 25754#L1182-1 assume !(1 == ~T9_E~0); 25755#L1187-1 assume !(1 == ~T10_E~0); 25854#L1192-1 assume !(1 == ~E_M~0); 25318#L1197-1 assume !(1 == ~E_1~0); 25319#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25698#L1207-1 assume !(1 == ~E_3~0); 25674#L1212-1 assume !(1 == ~E_4~0); 24911#L1217-1 assume !(1 == ~E_5~0); 24912#L1222-1 assume !(1 == ~E_6~0); 25671#L1227-1 assume !(1 == ~E_7~0); 25672#L1232-1 assume !(1 == ~E_8~0); 24785#L1237-1 assume !(1 == ~E_9~0); 24786#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25735#L1247-1 assume { :end_inline_reset_delta_events } true; 24956#L1553-2 [2024-10-13 17:45:06,756 INFO L747 eck$LassoCheckResult]: Loop: 24956#L1553-2 assume !false; 24957#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25096#L999-1 assume !false; 25237#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25044#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24929#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25401#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25402#L854 assume !(0 != eval_~tmp~0#1); 25811#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25598#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25599#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26071#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25571#L1029-3 assume !(0 == ~T2_E~0); 25539#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25540#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25882#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25145#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25146#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24907#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24908#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25509#L1069-3 assume !(0 == ~T10_E~0); 25510#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25856#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25747#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25632#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25633#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25558#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25559#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25880#L1109-3 assume !(0 == ~E_7~0); 25868#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25869#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26132#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26139#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26105#L502-36 assume !(1 == ~m_pc~0); 25288#L502-38 is_master_triggered_~__retres1~0#1 := 0; 24773#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24774#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25203#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25204#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25482#L521-36 assume 1 == ~t1_pc~0; 25483#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25493#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25663#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26059#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25942#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25943#L540-36 assume 1 == ~t2_pc~0; 26107#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24863#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25275#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25944#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25608#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24782#L559-36 assume 1 == ~t3_pc~0; 24784#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25241#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25416#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25417#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 25756#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25996#L578-36 assume !(1 == ~t4_pc~0); 25683#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25684#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25620#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25621#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25517#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25518#L597-36 assume !(1 == ~t5_pc~0); 25744#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 26097#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26041#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25699#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25320#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25321#L616-36 assume !(1 == ~t6_pc~0); 26067#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 24851#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24852#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25396#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25568#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25897#L635-36 assume 1 == ~t7_pc~0; 26072#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25954#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25955#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26017#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25554#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25555#L654-36 assume 1 == ~t8_pc~0; 26135#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26080#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25721#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25722#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26112#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25226#L673-36 assume 1 == ~t9_pc~0; 25227#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25594#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25459#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25460#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24792#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24793#L692-36 assume 1 == ~t10_pc~0; 25746#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25005#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25302#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25194#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 25195#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25565#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25714#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26075#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25645#L1157-3 assume !(1 == ~T4_E~0); 25646#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25950#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26062#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25551#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25451#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25452#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25466#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25284#L1197-3 assume !(1 == ~E_1~0); 25285#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25532#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25653#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25878#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25189#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24876#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24877#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25979#L1237-3 assume !(1 == ~E_9~0); 25980#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26142#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 26028#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25027#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25028#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 25292#L1572 assume !(0 == start_simulation_~tmp~3#1); 25323#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25485#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24806#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24864#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 24865#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24777#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24778#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25625#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 24956#L1553-2 [2024-10-13 17:45:06,756 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,757 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2024-10-13 17:45:06,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16246478] [2024-10-13 17:45:06,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,824 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,824 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16246478] [2024-10-13 17:45:06,824 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [16246478] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,824 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553521040] [2024-10-13 17:45:06,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,825 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:06,825 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:06,825 INFO L85 PathProgramCache]: Analyzing trace with hash -671382823, now seen corresponding path program 1 times [2024-10-13 17:45:06,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:06,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016190966] [2024-10-13 17:45:06,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:06,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:06,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:06,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:06,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:06,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016190966] [2024-10-13 17:45:06,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016190966] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:06,870 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:06,870 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:06,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491396626] [2024-10-13 17:45:06,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:06,870 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:06,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:06,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:06,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:06,871 INFO L87 Difference]: Start difference. First operand 1372 states and 2026 transitions. cyclomatic complexity: 655 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:06,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:06,960 INFO L93 Difference]: Finished difference Result 2526 states and 3716 transitions. [2024-10-13 17:45:06,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2526 states and 3716 transitions. [2024-10-13 17:45:06,969 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2024-10-13 17:45:06,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2526 states to 2526 states and 3716 transitions. [2024-10-13 17:45:06,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2526 [2024-10-13 17:45:06,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2526 [2024-10-13 17:45:06,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2526 states and 3716 transitions. [2024-10-13 17:45:06,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:06,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2024-10-13 17:45:06,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2526 states and 3716 transitions. [2024-10-13 17:45:07,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2526 to 2526. [2024-10-13 17:45:07,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2526 states, 2526 states have (on average 1.471100554235946) internal successors, (3716), 2525 states have internal predecessors, (3716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:07,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2526 states to 2526 states and 3716 transitions. [2024-10-13 17:45:07,018 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2024-10-13 17:45:07,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:07,019 INFO L425 stractBuchiCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2024-10-13 17:45:07,019 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-13 17:45:07,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2526 states and 3716 transitions. [2024-10-13 17:45:07,026 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2024-10-13 17:45:07,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:07,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:07,027 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:07,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:07,028 INFO L745 eck$LassoCheckResult]: Stem: 29063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29654#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 29335#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29336#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29622#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29797#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29508#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29509#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29387#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29388#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29751#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29709#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 29629#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29630#L1024 assume !(0 == ~M_E~0); 29894#L1024-2 assume !(0 == ~T1_E~0); 29059#L1029-1 assume !(0 == ~T2_E~0); 29060#L1034-1 assume !(0 == ~T3_E~0); 29163#L1039-1 assume !(0 == ~T4_E~0); 30008#L1044-1 assume !(0 == ~T5_E~0); 29408#L1049-1 assume !(0 == ~T6_E~0); 29409#L1054-1 assume !(0 == ~T7_E~0); 29653#L1059-1 assume !(0 == ~T8_E~0); 29109#L1064-1 assume !(0 == ~T9_E~0); 29110#L1069-1 assume !(0 == ~T10_E~0); 29863#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29924#L1079-1 assume !(0 == ~E_1~0); 29896#L1084-1 assume !(0 == ~E_2~0); 29897#L1089-1 assume !(0 == ~E_3~0); 29943#L1094-1 assume !(0 == ~E_4~0); 29499#L1099-1 assume !(0 == ~E_5~0); 29500#L1104-1 assume !(0 == ~E_6~0); 29769#L1109-1 assume !(0 == ~E_7~0); 29277#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29278#L1119-1 assume !(0 == ~E_9~0); 29345#L1124-1 assume !(0 == ~E_10~0); 28763#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28764#L502 assume 1 == ~m_pc~0; 29651#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28889#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28890#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29703#L1273 assume !(0 != activate_threads_~tmp~1#1); 29704#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30054#L521 assume !(1 == ~t1_pc~0); 29972#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28814#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28780#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 28800#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28801#L540 assume 1 == ~t2_pc~0; 29908#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29611#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29274#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 29968#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29087#L559 assume 1 == ~t3_pc~0; 29088#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29366#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28716#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28717#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 28907#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28908#L578 assume !(1 == ~t4_pc~0); 29028#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29027#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28846#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28847#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29685#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29686#L597 assume 1 == ~t5_pc~0; 30071#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28834#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28835#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29892#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 29631#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29632#L616 assume !(1 == ~t6_pc~0); 29648#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29647#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29250#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 29488#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29489#L635 assume 1 == ~t7_pc~0; 29688#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28803#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29939#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 29624#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29625#L654 assume !(1 == ~t8_pc~0); 29439#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29440#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29820#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29821#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 29861#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29057#L673 assume 1 == ~t9_pc~0; 29058#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28754#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29329#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29330#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 29781#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29782#L692 assume !(1 == ~t10_pc~0); 29724#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29723#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29491#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29492#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 29503#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29839#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 30094#L1142-2 assume !(1 == ~T1_E~0); 30494#L1147-1 assume !(1 == ~T2_E~0); 30488#L1152-1 assume !(1 == ~T3_E~0); 30093#L1157-1 assume !(1 == ~T4_E~0); 30424#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30421#L1167-1 assume !(1 == ~T6_E~0); 30419#L1172-1 assume !(1 == ~T7_E~0); 30417#L1177-1 assume !(1 == ~T8_E~0); 30397#L1182-1 assume !(1 == ~T9_E~0); 30240#L1187-1 assume !(1 == ~T10_E~0); 30239#L1192-1 assume !(1 == ~E_M~0); 29227#L1197-1 assume !(1 == ~E_1~0); 29228#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29613#L1207-1 assume !(1 == ~E_3~0); 29589#L1212-1 assume !(1 == ~E_4~0); 28819#L1217-1 assume !(1 == ~E_5~0); 28820#L1222-1 assume !(1 == ~E_6~0); 29586#L1227-1 assume !(1 == ~E_7~0); 29587#L1232-1 assume !(1 == ~E_8~0); 28693#L1237-1 assume !(1 == ~E_9~0); 28694#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30138#L1247-1 assume { :end_inline_reset_delta_events } true; 30131#L1553-2 [2024-10-13 17:45:07,028 INFO L747 eck$LassoCheckResult]: Loop: 30131#L1553-2 assume !false; 30125#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30121#L999-1 assume !false; 30120#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30119#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30108#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30107#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30105#L854 assume !(0 != eval_~tmp~0#1); 30104#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30103#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30101#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30102#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30962#L1029-3 assume !(0 == ~T2_E~0); 30961#L1034-3 assume !(0 == ~T3_E~0); 30960#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30959#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30958#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30957#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30956#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30955#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30954#L1069-3 assume !(0 == ~T10_E~0); 30953#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30952#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30951#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30950#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30949#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30948#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30947#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30031#L1109-3 assume !(0 == ~E_7~0); 29788#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29789#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30078#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30087#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30044#L502-36 assume 1 == ~m_pc~0; 29803#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28681#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28682#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29111#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29112#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29392#L521-36 assume 1 == ~t1_pc~0; 29393#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29404#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29578#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29985#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29865#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29866#L540-36 assume 1 == ~t2_pc~0; 30048#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28771#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29184#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29867#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29522#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28690#L559-36 assume !(1 == ~t3_pc~0); 28691#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 29150#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29326#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29327#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 29673#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29920#L578-36 assume 1 == ~t4_pc~0; 29641#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29599#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29534#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29535#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29428#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29429#L597-36 assume !(1 == ~t5_pc~0); 29661#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 30027#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29967#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29614#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29229#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29230#L616-36 assume 1 == ~t6_pc~0; 30049#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28759#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28760#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29305#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29482#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29817#L635-36 assume !(1 == ~t7_pc~0); 30097#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 30550#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30548#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30546#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30544#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30338#L654-36 assume 1 == ~t8_pc~0; 30334#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30332#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30330#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30328#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30326#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30324#L673-36 assume !(1 == ~t9_pc~0); 30320#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30318#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30316#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30314#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30312#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30310#L692-36 assume 1 == ~t10_pc~0; 30306#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30304#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30302#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30300#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 30298#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30296#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29633#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30292#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30290#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30032#L1157-3 assume !(1 == ~T4_E~0); 30287#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30285#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30284#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30283#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30282#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30281#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30280#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30279#L1197-3 assume !(1 == ~E_1~0); 30278#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30277#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30276#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30275#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30274#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30273#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30272#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30271#L1237-3 assume !(1 == ~E_9~0); 30270#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30269#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30268#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30257#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30256#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 30255#L1572 assume !(0 == start_simulation_~tmp~3#1); 29232#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30249#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30241#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 30157#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30150#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30143#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30139#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 30131#L1553-2 [2024-10-13 17:45:07,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:07,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2024-10-13 17:45:07,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:07,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272186235] [2024-10-13 17:45:07,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:07,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:07,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:07,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:07,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:07,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272186235] [2024-10-13 17:45:07,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272186235] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:07,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:07,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:07,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [580580030] [2024-10-13 17:45:07,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:07,079 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:07,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:07,080 INFO L85 PathProgramCache]: Analyzing trace with hash -2013593701, now seen corresponding path program 1 times [2024-10-13 17:45:07,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:07,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681705141] [2024-10-13 17:45:07,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:07,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:07,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:07,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:07,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:07,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681705141] [2024-10-13 17:45:07,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681705141] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:07,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:07,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:07,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828926556] [2024-10-13 17:45:07,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:07,123 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:07,123 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:07,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:07,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:07,124 INFO L87 Difference]: Start difference. First operand 2526 states and 3716 transitions. cyclomatic complexity: 1192 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:07,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:07,261 INFO L93 Difference]: Finished difference Result 4664 states and 6847 transitions. [2024-10-13 17:45:07,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4664 states and 6847 transitions. [2024-10-13 17:45:07,327 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4471 [2024-10-13 17:45:07,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4664 states to 4664 states and 6847 transitions. [2024-10-13 17:45:07,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4664 [2024-10-13 17:45:07,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4664 [2024-10-13 17:45:07,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4664 states and 6847 transitions. [2024-10-13 17:45:07,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:07,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4664 states and 6847 transitions. [2024-10-13 17:45:07,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4664 states and 6847 transitions. [2024-10-13 17:45:07,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4664 to 4662. [2024-10-13 17:45:07,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4662 states, 4662 states have (on average 1.4682539682539681) internal successors, (6845), 4661 states have internal predecessors, (6845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:07,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4662 states to 4662 states and 6845 transitions. [2024-10-13 17:45:07,408 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4662 states and 6845 transitions. [2024-10-13 17:45:07,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:07,409 INFO L425 stractBuchiCegarLoop]: Abstraction has 4662 states and 6845 transitions. [2024-10-13 17:45:07,409 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-13 17:45:07,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4662 states and 6845 transitions. [2024-10-13 17:45:07,423 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4471 [2024-10-13 17:45:07,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:07,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:07,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:07,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:07,425 INFO L745 eck$LassoCheckResult]: Stem: 36263#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36264#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37182#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37183#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36850#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 36535#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36536#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36819#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36992#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36705#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36706#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36589#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36590#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36945#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36905#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36827#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36828#L1024 assume !(0 == ~M_E~0); 37088#L1024-2 assume !(0 == ~T1_E~0); 36259#L1029-1 assume !(0 == ~T2_E~0); 36260#L1034-1 assume !(0 == ~T3_E~0); 36362#L1039-1 assume !(0 == ~T4_E~0); 37206#L1044-1 assume !(0 == ~T5_E~0); 36609#L1049-1 assume !(0 == ~T6_E~0); 36610#L1054-1 assume !(0 == ~T7_E~0); 36849#L1059-1 assume !(0 == ~T8_E~0); 36309#L1064-1 assume !(0 == ~T9_E~0); 36310#L1069-1 assume !(0 == ~T10_E~0); 37057#L1074-1 assume !(0 == ~E_M~0); 37118#L1079-1 assume !(0 == ~E_1~0); 37090#L1084-1 assume !(0 == ~E_2~0); 37091#L1089-1 assume !(0 == ~E_3~0); 37136#L1094-1 assume !(0 == ~E_4~0); 36695#L1099-1 assume !(0 == ~E_5~0); 36696#L1104-1 assume !(0 == ~E_6~0); 36963#L1109-1 assume !(0 == ~E_7~0); 36476#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36477#L1119-1 assume !(0 == ~E_9~0); 36550#L1124-1 assume !(0 == ~E_10~0); 35963#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35964#L502 assume 1 == ~m_pc~0; 36847#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36089#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36090#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36901#L1273 assume !(0 != activate_threads_~tmp~1#1); 36902#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37238#L521 assume !(1 == ~t1_pc~0); 37167#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36014#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35980#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 36000#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36001#L540 assume 1 == ~t2_pc~0; 37102#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36807#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36474#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36475#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 37163#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36287#L559 assume 1 == ~t3_pc~0; 36288#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36566#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35916#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35917#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 36107#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36108#L578 assume !(1 == ~t4_pc~0); 36231#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36230#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36047#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36048#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36881#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36882#L597 assume 1 == ~t5_pc~0; 37255#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36034#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36035#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37086#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 36829#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36830#L616 assume !(1 == ~t6_pc~0); 36846#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36845#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36448#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36449#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 36685#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36686#L635 assume 1 == ~t7_pc~0; 36885#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36003#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36380#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37132#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 36820#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36821#L654 assume !(1 == ~t8_pc~0); 36636#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36637#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37019#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37020#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 37055#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36257#L673 assume 1 == ~t9_pc~0; 36258#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35956#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36530#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36531#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 36976#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36977#L692 assume !(1 == ~t10_pc~0); 36922#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36921#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36687#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36688#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 36699#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37034#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 37275#L1142-2 assume !(1 == ~T1_E~0); 37560#L1147-1 assume !(1 == ~T2_E~0); 37273#L1152-1 assume !(1 == ~T3_E~0); 37274#L1157-1 assume !(1 == ~T4_E~0); 37490#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36723#L1167-1 assume !(1 == ~T6_E~0); 36724#L1172-1 assume !(1 == ~T7_E~0); 37169#L1177-1 assume !(1 == ~T8_E~0); 37170#L1182-1 assume !(1 == ~T9_E~0); 36968#L1187-1 assume !(1 == ~T10_E~0); 36969#L1192-1 assume !(1 == ~E_M~0); 37369#L1197-1 assume !(1 == ~E_1~0); 37367#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37365#L1207-1 assume !(1 == ~E_3~0); 37364#L1212-1 assume !(1 == ~E_4~0); 37352#L1217-1 assume !(1 == ~E_5~0); 37350#L1222-1 assume !(1 == ~E_6~0); 37348#L1227-1 assume !(1 == ~E_7~0); 37336#L1232-1 assume !(1 == ~E_8~0); 37327#L1237-1 assume !(1 == ~E_9~0); 37319#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37312#L1247-1 assume { :end_inline_reset_delta_events } true; 37308#L1553-2 [2024-10-13 17:45:07,426 INFO L747 eck$LassoCheckResult]: Loop: 37308#L1553-2 assume !false; 37302#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37298#L999-1 assume !false; 37297#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37296#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37285#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37284#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37282#L854 assume !(0 != eval_~tmp~0#1); 37281#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37280#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37278#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37279#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38470#L1029-3 assume !(0 == ~T2_E~0); 38467#L1034-3 assume !(0 == ~T3_E~0); 38464#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38461#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38458#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38455#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38452#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38449#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38446#L1069-3 assume !(0 == ~T10_E~0); 38443#L1074-3 assume !(0 == ~E_M~0); 38439#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38434#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38429#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38423#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38418#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38413#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38408#L1109-3 assume !(0 == ~E_7~0); 38401#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38396#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38390#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38385#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38381#L502-36 assume !(1 == ~m_pc~0); 38353#L502-38 is_master_triggered_~__retres1~0#1 := 0; 38351#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38348#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38346#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38344#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38342#L521-36 assume 1 == ~t1_pc~0; 38340#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38337#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38335#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38333#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38331#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38329#L540-36 assume !(1 == ~t2_pc~0); 38326#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 38316#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38309#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38300#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38292#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38285#L559-36 assume 1 == ~t3_pc~0; 38278#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38269#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38261#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38252#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 38244#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38237#L578-36 assume 1 == ~t4_pc~0; 38229#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38220#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38212#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38203#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38195#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38189#L597-36 assume !(1 == ~t5_pc~0); 38182#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 38174#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38167#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38160#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38152#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38145#L616-36 assume 1 == ~t6_pc~0; 38138#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38131#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38124#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38117#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38110#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38105#L635-36 assume !(1 == ~t7_pc~0); 38065#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 38057#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38049#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38041#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38033#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38025#L654-36 assume 1 == ~t8_pc~0; 38016#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38008#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38000#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37992#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37984#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37976#L673-36 assume 1 == ~t9_pc~0; 37968#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37959#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37951#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37941#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37935#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37930#L692-36 assume 1 == ~t10_pc~0; 37820#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37817#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37815#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37813#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 37811#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37809#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36825#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37806#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37786#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37226#L1157-3 assume !(1 == ~T4_E~0); 37769#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37761#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37754#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37747#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37738#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37730#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37722#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37713#L1197-3 assume !(1 == ~E_1~0); 37707#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37701#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37693#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37686#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37679#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37672#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37666#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37661#L1237-3 assume !(1 == ~E_9~0); 37654#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37648#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37444#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37433#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37432#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 37431#L1572 assume !(0 == start_simulation_~tmp~3#1); 36431#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37359#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37351#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37349#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 37337#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37328#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37320#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37313#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 37308#L1553-2 [2024-10-13 17:45:07,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:07,426 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2024-10-13 17:45:07,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:07,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168187413] [2024-10-13 17:45:07,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:07,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:07,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:07,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:07,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:07,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168187413] [2024-10-13 17:45:07,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168187413] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:07,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:07,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:07,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879190662] [2024-10-13 17:45:07,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:07,474 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:07,475 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:07,475 INFO L85 PathProgramCache]: Analyzing trace with hash 590468125, now seen corresponding path program 1 times [2024-10-13 17:45:07,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:07,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304650302] [2024-10-13 17:45:07,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:07,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:07,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:07,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:07,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:07,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304650302] [2024-10-13 17:45:07,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304650302] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:07,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:07,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:07,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554747598] [2024-10-13 17:45:07,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:07,509 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:07,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:07,509 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:07,509 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:07,509 INFO L87 Difference]: Start difference. First operand 4662 states and 6845 transitions. cyclomatic complexity: 2187 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:07,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:07,637 INFO L93 Difference]: Finished difference Result 8740 states and 12800 transitions. [2024-10-13 17:45:07,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8740 states and 12800 transitions. [2024-10-13 17:45:07,672 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8525 [2024-10-13 17:45:07,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8740 states to 8740 states and 12800 transitions. [2024-10-13 17:45:07,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8740 [2024-10-13 17:45:07,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8740 [2024-10-13 17:45:07,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8740 states and 12800 transitions. [2024-10-13 17:45:07,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:07,712 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8740 states and 12800 transitions. [2024-10-13 17:45:07,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8740 states and 12800 transitions. [2024-10-13 17:45:07,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8740 to 8736. [2024-10-13 17:45:07,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8736 states, 8736 states have (on average 1.4647435897435896) internal successors, (12796), 8735 states have internal predecessors, (12796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:07,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8736 states to 8736 states and 12796 transitions. [2024-10-13 17:45:07,836 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8736 states and 12796 transitions. [2024-10-13 17:45:07,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:07,836 INFO L425 stractBuchiCegarLoop]: Abstraction has 8736 states and 12796 transitions. [2024-10-13 17:45:07,836 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-13 17:45:07,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8736 states and 12796 transitions. [2024-10-13 17:45:07,861 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8525 [2024-10-13 17:45:07,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:07,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:07,862 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:07,862 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:07,863 INFO L745 eck$LassoCheckResult]: Stem: 49675#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50613#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50614#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50269#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 49948#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49949#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50238#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50418#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50123#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50124#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50000#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50001#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50370#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50327#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50245#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50246#L1024 assume !(0 == ~M_E~0); 50519#L1024-2 assume !(0 == ~T1_E~0); 49671#L1029-1 assume !(0 == ~T2_E~0); 49672#L1034-1 assume !(0 == ~T3_E~0); 49774#L1039-1 assume !(0 == ~T4_E~0); 50637#L1044-1 assume !(0 == ~T5_E~0); 50021#L1049-1 assume !(0 == ~T6_E~0); 50022#L1054-1 assume !(0 == ~T7_E~0); 50268#L1059-1 assume !(0 == ~T8_E~0); 49721#L1064-1 assume !(0 == ~T9_E~0); 49722#L1069-1 assume !(0 == ~T10_E~0); 50488#L1074-1 assume !(0 == ~E_M~0); 50550#L1079-1 assume !(0 == ~E_1~0); 50521#L1084-1 assume !(0 == ~E_2~0); 50522#L1089-1 assume !(0 == ~E_3~0); 50570#L1094-1 assume !(0 == ~E_4~0); 50114#L1099-1 assume !(0 == ~E_5~0); 50115#L1104-1 assume !(0 == ~E_6~0); 50388#L1109-1 assume !(0 == ~E_7~0); 49889#L1114-1 assume !(0 == ~E_8~0); 49890#L1119-1 assume !(0 == ~E_9~0); 49958#L1124-1 assume !(0 == ~E_10~0); 49375#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49376#L502 assume 1 == ~m_pc~0; 50266#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49501#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49502#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50321#L1273 assume !(0 != activate_threads_~tmp~1#1); 50322#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50676#L521 assume !(1 == ~t1_pc~0); 50599#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49426#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49391#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49392#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 49412#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49413#L540 assume 1 == ~t2_pc~0; 50534#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50226#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49885#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49886#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 50595#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49699#L559 assume 1 == ~t3_pc~0; 49700#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49979#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49328#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49329#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 49519#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49520#L578 assume !(1 == ~t4_pc~0); 49641#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49640#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49459#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49460#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50303#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50304#L597 assume 1 == ~t5_pc~0; 50694#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49446#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49447#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50517#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 50247#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50248#L616 assume !(1 == ~t6_pc~0); 50263#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50262#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49861#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49862#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 50102#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50103#L635 assume 1 == ~t7_pc~0; 50306#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49415#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49790#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50566#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 50240#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50241#L654 assume !(1 == ~t8_pc~0); 50051#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50052#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50448#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 50486#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49669#L673 assume 1 == ~t9_pc~0; 49670#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49366#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49944#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49945#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 50402#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50403#L692 assume !(1 == ~t10_pc~0); 50342#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50341#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50105#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50106#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 50118#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50465#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 50720#L1142-2 assume !(1 == ~T1_E~0); 50452#L1147-1 assume !(1 == ~T2_E~0); 50453#L1152-1 assume !(1 == ~T3_E~0); 51084#L1157-1 assume !(1 == ~T4_E~0); 51081#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51077#L1167-1 assume !(1 == ~T6_E~0); 51074#L1172-1 assume !(1 == ~T7_E~0); 51071#L1177-1 assume !(1 == ~T8_E~0); 51068#L1182-1 assume !(1 == ~T9_E~0); 51064#L1187-1 assume !(1 == ~T10_E~0); 51061#L1192-1 assume !(1 == ~E_M~0); 51057#L1197-1 assume !(1 == ~E_1~0); 50866#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50864#L1207-1 assume !(1 == ~E_3~0); 50839#L1212-1 assume !(1 == ~E_4~0); 50827#L1217-1 assume !(1 == ~E_5~0); 50825#L1222-1 assume !(1 == ~E_6~0); 50804#L1227-1 assume !(1 == ~E_7~0); 50802#L1232-1 assume !(1 == ~E_8~0); 50786#L1237-1 assume !(1 == ~E_9~0); 50770#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50761#L1247-1 assume { :end_inline_reset_delta_events } true; 50754#L1553-2 [2024-10-13 17:45:07,863 INFO L747 eck$LassoCheckResult]: Loop: 50754#L1553-2 assume !false; 50748#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50744#L999-1 assume !false; 50743#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50742#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50731#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50730#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50728#L854 assume !(0 != eval_~tmp~0#1); 50727#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50726#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50724#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50725#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52358#L1029-3 assume !(0 == ~T2_E~0); 52356#L1034-3 assume !(0 == ~T3_E~0); 52354#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52352#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52350#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52348#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52346#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52344#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52342#L1069-3 assume !(0 == ~T10_E~0); 52340#L1074-3 assume !(0 == ~E_M~0); 52338#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52336#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52334#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52332#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52329#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52327#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52325#L1109-3 assume !(0 == ~E_7~0); 52323#L1114-3 assume !(0 == ~E_8~0); 52321#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52319#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52316#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52314#L502-36 assume !(1 == ~m_pc~0); 52284#L502-38 is_master_triggered_~__retres1~0#1 := 0; 52282#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52279#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52277#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52275#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52273#L521-36 assume 1 == ~t1_pc~0; 52270#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52268#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52265#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52263#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52261#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52259#L540-36 assume !(1 == ~t2_pc~0); 52256#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 52254#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52251#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52249#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52247#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52245#L559-36 assume 1 == ~t3_pc~0; 52242#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52240#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52237#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52235#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 52233#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52231#L578-36 assume 1 == ~t4_pc~0; 52228#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52226#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52223#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51841#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51839#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50276#L597-36 assume !(1 == ~t5_pc~0); 50277#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 51694#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51691#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51689#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51687#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51685#L616-36 assume 1 == ~t6_pc~0; 51659#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51644#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51642#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51640#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51637#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51635#L635-36 assume !(1 == ~t7_pc~0); 51632#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 51625#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51598#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51596#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51593#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51592#L654-36 assume 1 == ~t8_pc~0; 51578#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51566#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51564#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51561#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51559#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51557#L673-36 assume !(1 == ~t9_pc~0); 51554#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 50125#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49982#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49983#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51504#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51502#L692-36 assume 1 == ~t10_pc~0; 51479#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51477#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51468#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51460#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 51452#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51444#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50249#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51429#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51420#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50662#L1157-3 assume !(1 == ~T4_E~0); 51405#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51400#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51395#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51390#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51384#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51379#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51374#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 51367#L1197-3 assume !(1 == ~E_1~0); 51364#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51361#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51357#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51354#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51351#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51348#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51345#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51341#L1237-3 assume !(1 == ~E_9~0); 51338#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51336#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51334#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51322#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51177#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 50863#L1572 assume !(0 == start_simulation_~tmp~3#1); 49843#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50834#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50826#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50805#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 50788#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50774#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50771#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50762#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 50754#L1553-2 [2024-10-13 17:45:07,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:07,863 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2024-10-13 17:45:07,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:07,864 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040419979] [2024-10-13 17:45:07,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:07,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:07,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:07,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:07,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:07,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040419979] [2024-10-13 17:45:07,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040419979] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:07,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:07,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:07,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068090424] [2024-10-13 17:45:07,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:07,905 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:07,905 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:07,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1184532576, now seen corresponding path program 1 times [2024-10-13 17:45:07,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:07,905 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465332250] [2024-10-13 17:45:07,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:07,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:07,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:08,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:08,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:08,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465332250] [2024-10-13 17:45:08,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465332250] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:08,021 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:08,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:08,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447832745] [2024-10-13 17:45:08,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:08,021 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:08,021 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:08,022 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:08,022 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:08,022 INFO L87 Difference]: Start difference. First operand 8736 states and 12796 transitions. cyclomatic complexity: 4068 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:08,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:08,177 INFO L93 Difference]: Finished difference Result 17155 states and 24947 transitions. [2024-10-13 17:45:08,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17155 states and 24947 transitions. [2024-10-13 17:45:08,247 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16929 [2024-10-13 17:45:08,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17155 states to 17155 states and 24947 transitions. [2024-10-13 17:45:08,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17155 [2024-10-13 17:45:08,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17155 [2024-10-13 17:45:08,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17155 states and 24947 transitions. [2024-10-13 17:45:08,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:08,321 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17155 states and 24947 transitions. [2024-10-13 17:45:08,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17155 states and 24947 transitions. [2024-10-13 17:45:08,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17155 to 16547. [2024-10-13 17:45:08,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16547 states, 16547 states have (on average 1.455913458632985) internal successors, (24091), 16546 states have internal predecessors, (24091), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:08,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16547 states to 16547 states and 24091 transitions. [2024-10-13 17:45:08,574 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16547 states and 24091 transitions. [2024-10-13 17:45:08,575 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:08,575 INFO L425 stractBuchiCegarLoop]: Abstraction has 16547 states and 24091 transitions. [2024-10-13 17:45:08,575 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-13 17:45:08,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16547 states and 24091 transitions. [2024-10-13 17:45:08,621 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16321 [2024-10-13 17:45:08,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:08,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:08,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:08,622 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:08,623 INFO L745 eck$LassoCheckResult]: Stem: 75581#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76637#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76638#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76213#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 75869#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75870#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76181#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76378#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76053#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76054#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75928#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75929#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76324#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76274#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76190#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76191#L1024 assume !(0 == ~M_E~0); 76509#L1024-2 assume !(0 == ~T1_E~0); 75576#L1029-1 assume !(0 == ~T2_E~0); 75577#L1034-1 assume !(0 == ~T3_E~0); 75685#L1039-1 assume !(0 == ~T4_E~0); 76671#L1044-1 assume !(0 == ~T5_E~0); 75947#L1049-1 assume !(0 == ~T6_E~0); 75948#L1054-1 assume !(0 == ~T7_E~0); 76212#L1059-1 assume !(0 == ~T8_E~0); 75632#L1064-1 assume !(0 == ~T9_E~0); 75633#L1069-1 assume !(0 == ~T10_E~0); 76472#L1074-1 assume !(0 == ~E_M~0); 76550#L1079-1 assume !(0 == ~E_1~0); 76514#L1084-1 assume !(0 == ~E_2~0); 76515#L1089-1 assume !(0 == ~E_3~0); 76582#L1094-1 assume !(0 == ~E_4~0); 76042#L1099-1 assume !(0 == ~E_5~0); 76043#L1104-1 assume !(0 == ~E_6~0); 76345#L1109-1 assume !(0 == ~E_7~0); 75807#L1114-1 assume !(0 == ~E_8~0); 75808#L1119-1 assume !(0 == ~E_9~0); 75884#L1124-1 assume !(0 == ~E_10~0); 75273#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75274#L502 assume !(1 == ~m_pc~0); 75474#L502-2 is_master_triggered_~__retres1~0#1 := 0; 75404#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75405#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76270#L1273 assume !(0 != activate_threads_~tmp~1#1); 76271#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76738#L521 assume !(1 == ~t1_pc~0); 76621#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75326#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75289#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75290#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 75310#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75311#L540 assume 1 == ~t2_pc~0; 76529#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76164#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75805#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75806#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 76615#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75610#L559 assume 1 == ~t3_pc~0; 75611#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75900#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75226#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75227#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 75420#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75421#L578 assume !(1 == ~t4_pc~0); 75546#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75545#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75358#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75359#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76248#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76249#L597 assume 1 == ~t5_pc~0; 76768#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75344#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75345#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76507#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 76192#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76193#L616 assume !(1 == ~t6_pc~0); 76210#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76209#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75778#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75779#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 76032#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76033#L635 assume 1 == ~t7_pc~0; 76251#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75313#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75702#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76577#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 76183#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76184#L654 assume !(1 == ~t8_pc~0); 75976#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75977#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76417#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76418#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 76469#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75574#L673 assume 1 == ~t9_pc~0; 75575#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75266#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75862#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75863#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 76357#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76358#L692 assume !(1 == ~t10_pc~0); 76293#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76292#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76034#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76035#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 76046#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76437#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 76820#L1142-2 assume !(1 == ~T1_E~0); 85261#L1147-1 assume !(1 == ~T2_E~0); 76819#L1152-1 assume !(1 == ~T3_E~0); 75906#L1157-1 assume !(1 == ~T4_E~0); 75907#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76521#L1167-1 assume !(1 == ~T6_E~0); 85966#L1172-1 assume !(1 == ~T7_E~0); 85964#L1177-1 assume !(1 == ~T8_E~0); 76231#L1182-1 assume !(1 == ~T9_E~0); 76232#L1187-1 assume !(1 == ~T10_E~0); 76350#L1192-1 assume !(1 == ~E_M~0); 76407#L1197-1 assume !(1 == ~E_1~0); 76422#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 76423#L1207-1 assume !(1 == ~E_3~0); 76142#L1212-1 assume !(1 == ~E_4~0); 76143#L1217-1 assume !(1 == ~E_5~0); 76839#L1222-1 assume !(1 == ~E_6~0); 76840#L1227-1 assume !(1 == ~E_7~0); 76228#L1232-1 assume !(1 == ~E_8~0); 75203#L1237-1 assume !(1 == ~E_9~0); 75204#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 76211#L1247-1 assume { :end_inline_reset_delta_events } true; 75379#L1553-2 [2024-10-13 17:45:08,623 INFO L747 eck$LassoCheckResult]: Loop: 75379#L1553-2 assume !false; 75380#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75518#L999-1 assume !false; 75668#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 75466#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 75347#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 75841#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 75842#L854 assume !(0 != eval_~tmp~0#1); 76299#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90685#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90683#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 90684#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 91425#L1029-3 assume !(0 == ~T2_E~0); 91423#L1034-3 assume !(0 == ~T3_E~0); 91421#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 91419#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 91417#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 91416#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 91415#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 91414#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 91413#L1069-3 assume !(0 == ~T10_E~0); 91412#L1074-3 assume !(0 == ~E_M~0); 76639#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76223#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76093#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76094#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76013#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76014#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76381#L1109-3 assume !(0 == ~E_7~0); 76365#L1114-3 assume !(0 == ~E_8~0); 76366#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76775#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76787#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76727#L502-36 assume !(1 == ~m_pc~0); 75720#L502-38 is_master_triggered_~__retres1~0#1 := 0; 75191#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75192#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75634#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75635#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75925#L521-36 assume !(1 == ~t1_pc~0); 75927#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 75939#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76128#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76636#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76474#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76475#L540-36 assume !(1 == ~t2_pc~0); 75280#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 75281#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75705#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76476#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76068#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75200#L559-36 assume !(1 == ~t3_pc~0); 75201#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 75674#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75857#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75858#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 76233#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76546#L578-36 assume !(1 == ~t4_pc~0); 76151#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 76152#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76081#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76082#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75965#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75966#L597-36 assume 1 == ~t5_pc~0; 76221#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76704#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76614#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76166#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 75751#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75752#L616-36 assume !(1 == ~t6_pc~0); 76648#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 75269#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75270#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75836#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76024#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 91298#L635-36 assume 1 == ~t7_pc~0; 91296#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 91292#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 91290#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 91288#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 91286#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 91284#L654-36 assume !(1 == ~t8_pc~0); 91243#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 91240#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 91238#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91236#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 91233#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 91226#L673-36 assume 1 == ~t9_pc~0; 76519#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76052#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75902#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75903#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 91211#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91206#L692-36 assume !(1 == ~t10_pc~0); 91201#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 91198#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91197#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75625#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 75626#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76023#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76189#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76666#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76667#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76107#L1157-3 assume !(1 == ~T4_E~0); 76108#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76482#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76643#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 76003#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75894#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 75895#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75909#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 75714#L1197-3 assume !(1 == ~E_1~0); 75715#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75985#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 90910#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90908#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 90906#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 90904#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90902#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86234#L1237-3 assume !(1 == ~E_9~0); 90898#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 90896#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 90894#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 90882#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 90880#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 90878#L1572 assume !(0 == start_simulation_~tmp~3#1); 77473#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 90753#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 90745#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 76806#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75195#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75196#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 76086#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 75379#L1553-2 [2024-10-13 17:45:08,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:08,624 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2024-10-13 17:45:08,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:08,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479554417] [2024-10-13 17:45:08,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:08,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:08,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:08,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:08,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:08,662 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479554417] [2024-10-13 17:45:08,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1479554417] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:08,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:08,662 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:08,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956086767] [2024-10-13 17:45:08,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:08,662 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:08,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:08,662 INFO L85 PathProgramCache]: Analyzing trace with hash -55286749, now seen corresponding path program 1 times [2024-10-13 17:45:08,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:08,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260799689] [2024-10-13 17:45:08,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:08,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:08,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:08,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:08,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:08,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [260799689] [2024-10-13 17:45:08,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [260799689] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:08,791 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:08,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:08,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347111266] [2024-10-13 17:45:08,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:08,792 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:08,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:08,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:08,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:08,793 INFO L87 Difference]: Start difference. First operand 16547 states and 24091 transitions. cyclomatic complexity: 7560 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:08,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:08,935 INFO L93 Difference]: Finished difference Result 31457 states and 45569 transitions. [2024-10-13 17:45:08,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31457 states and 45569 transitions. [2024-10-13 17:45:09,053 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31184 [2024-10-13 17:45:09,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31457 states to 31457 states and 45569 transitions. [2024-10-13 17:45:09,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31457 [2024-10-13 17:45:09,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31457 [2024-10-13 17:45:09,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31457 states and 45569 transitions. [2024-10-13 17:45:09,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:09,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31457 states and 45569 transitions. [2024-10-13 17:45:09,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31457 states and 45569 transitions. [2024-10-13 17:45:09,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31457 to 31425. [2024-10-13 17:45:09,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31425 states, 31425 states have (on average 1.4490692124105011) internal successors, (45537), 31424 states have internal predecessors, (45537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:09,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31425 states to 31425 states and 45537 transitions. [2024-10-13 17:45:09,862 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31425 states and 45537 transitions. [2024-10-13 17:45:09,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:09,863 INFO L425 stractBuchiCegarLoop]: Abstraction has 31425 states and 45537 transitions. [2024-10-13 17:45:09,863 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-13 17:45:09,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31425 states and 45537 transitions. [2024-10-13 17:45:10,158 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31152 [2024-10-13 17:45:10,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:10,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:10,160 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:10,160 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:10,161 INFO L745 eck$LassoCheckResult]: Stem: 123588#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 123589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 124556#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 124557#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 124198#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 123871#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 123872#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124158#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124348#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124041#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 124042#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123922#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 123923#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 124299#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 124254#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 124170#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124171#L1024 assume !(0 == ~M_E~0); 124461#L1024-2 assume !(0 == ~T1_E~0); 123584#L1029-1 assume !(0 == ~T2_E~0); 123585#L1034-1 assume !(0 == ~T3_E~0); 123693#L1039-1 assume !(0 == ~T4_E~0); 124583#L1044-1 assume !(0 == ~T5_E~0); 123942#L1049-1 assume !(0 == ~T6_E~0); 123943#L1054-1 assume !(0 == ~T7_E~0); 124197#L1059-1 assume !(0 == ~T8_E~0); 123639#L1064-1 assume !(0 == ~T9_E~0); 123640#L1069-1 assume !(0 == ~T10_E~0); 124428#L1074-1 assume !(0 == ~E_M~0); 124492#L1079-1 assume !(0 == ~E_1~0); 124463#L1084-1 assume !(0 == ~E_2~0); 124464#L1089-1 assume !(0 == ~E_3~0); 124512#L1094-1 assume !(0 == ~E_4~0); 124032#L1099-1 assume !(0 == ~E_5~0); 124033#L1104-1 assume !(0 == ~E_6~0); 124318#L1109-1 assume !(0 == ~E_7~0); 123810#L1114-1 assume !(0 == ~E_8~0); 123811#L1119-1 assume !(0 == ~E_9~0); 123881#L1124-1 assume !(0 == ~E_10~0); 123284#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123285#L502 assume !(1 == ~m_pc~0); 123479#L502-2 is_master_triggered_~__retres1~0#1 := 0; 123411#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123412#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124248#L1273 assume !(0 != activate_threads_~tmp~1#1); 124249#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124634#L521 assume !(1 == ~t1_pc~0); 124544#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123335#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123301#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 123321#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123322#L540 assume !(1 == ~t2_pc~0); 124145#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124146#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123806#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123807#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 124538#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123617#L559 assume 1 == ~t3_pc~0; 123618#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 123901#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123238#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 123429#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123430#L578 assume !(1 == ~t4_pc~0); 123548#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 123547#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123368#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123369#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124228#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124229#L597 assume 1 == ~t5_pc~0; 124653#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 123356#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123357#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124459#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 124172#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124173#L616 assume !(1 == ~t6_pc~0); 124192#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 124191#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123780#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 123781#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 124021#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124022#L635 assume 1 == ~t7_pc~0; 124233#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 123324#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123709#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124508#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 124163#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 124164#L654 assume !(1 == ~t8_pc~0); 123971#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 123972#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124373#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124374#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 124426#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123582#L673 assume 1 == ~t9_pc~0; 123583#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123275#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123865#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123866#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 124330#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 124331#L692 assume !(1 == ~t10_pc~0); 124270#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 124269#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124024#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124025#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 124036#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124402#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 123489#L1142-2 assume !(1 == ~T1_E~0); 123490#L1147-1 assume !(1 == ~T2_E~0); 124380#L1152-1 assume !(1 == ~T3_E~0); 123908#L1157-1 assume !(1 == ~T4_E~0); 123909#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 124061#L1167-1 assume !(1 == ~T6_E~0); 124062#L1172-1 assume !(1 == ~T7_E~0); 124530#L1177-1 assume !(1 == ~T8_E~0); 124216#L1182-1 assume !(1 == ~T9_E~0); 124217#L1187-1 assume !(1 == ~T10_E~0); 124323#L1192-1 assume !(1 == ~E_M~0); 123759#L1197-1 assume !(1 == ~E_1~0); 123760#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 124149#L1207-1 assume !(1 == ~E_3~0); 124124#L1212-1 assume !(1 == ~E_4~0); 123340#L1217-1 assume !(1 == ~E_5~0); 123341#L1222-1 assume !(1 == ~E_6~0); 124121#L1227-1 assume !(1 == ~E_7~0); 124122#L1232-1 assume !(1 == ~E_8~0); 124213#L1237-1 assume !(1 == ~E_9~0); 151883#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 151882#L1247-1 assume { :end_inline_reset_delta_events } true; 151881#L1553-2 [2024-10-13 17:45:10,161 INFO L747 eck$LassoCheckResult]: Loop: 151881#L1553-2 assume !false; 151880#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 151878#L999-1 assume !false; 151877#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 151274#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 151262#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 151260#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 151257#L854 assume !(0 != eval_~tmp~0#1); 151258#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 152761#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 152759#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 152757#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 152755#L1029-3 assume !(0 == ~T2_E~0); 152753#L1034-3 assume !(0 == ~T3_E~0); 152751#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 152749#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 152747#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 152745#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 152743#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 152741#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 152739#L1069-3 assume !(0 == ~T10_E~0); 152737#L1074-3 assume !(0 == ~E_M~0); 152735#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 152733#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 152731#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 152729#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 152727#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 152725#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 152723#L1109-3 assume !(0 == ~E_7~0); 152721#L1114-3 assume !(0 == ~E_8~0); 152719#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 152717#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 152715#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152713#L502-36 assume !(1 == ~m_pc~0); 152711#L502-38 is_master_triggered_~__retres1~0#1 := 0; 152709#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152707#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152705#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 152703#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152700#L521-36 assume !(1 == ~t1_pc~0); 152698#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 152695#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152693#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152691#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152689#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152687#L540-36 assume !(1 == ~t2_pc~0); 152685#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 152683#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152681#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 152679#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 152677#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152674#L559-36 assume !(1 == ~t3_pc~0); 152672#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 152669#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152667#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 152665#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 152663#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152660#L578-36 assume !(1 == ~t4_pc~0); 152658#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 152655#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152653#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 152651#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 152649#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152646#L597-36 assume !(1 == ~t5_pc~0); 152643#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 152641#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152639#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 152637#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 152635#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152632#L616-36 assume !(1 == ~t6_pc~0); 152630#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 152627#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152625#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 152623#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 152621#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 152618#L635-36 assume !(1 == ~t7_pc~0); 152615#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 152613#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 152611#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 152609#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 152607#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 152604#L654-36 assume !(1 == ~t8_pc~0); 152602#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 152599#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 152597#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 152595#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 152593#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 152590#L673-36 assume !(1 == ~t9_pc~0); 152587#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 152585#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 152583#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 152581#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 152579#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 152578#L692-36 assume 1 == ~t10_pc~0; 152574#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 152572#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 152570#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 152568#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 152566#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152565#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 143198#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 152367#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152362#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145476#L1157-3 assume !(1 == ~T4_E~0); 152358#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152356#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 152354#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 152352#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 152350#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 152347#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 152345#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 152311#L1197-3 assume !(1 == ~E_1~0); 152342#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 152340#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 152338#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 152335#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 152333#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 152330#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 152328#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 145773#L1237-3 assume !(1 == ~E_9~0); 151670#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 149128#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 149098#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 149072#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 125259#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 124182#L1572 assume !(0 == start_simulation_~tmp~3#1); 124183#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 153823#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 153816#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 153815#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 153814#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 153813#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 151453#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 151454#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 151881#L1553-2 [2024-10-13 17:45:10,161 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:10,162 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2024-10-13 17:45:10,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:10,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279003848] [2024-10-13 17:45:10,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:10,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:10,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:10,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:10,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:10,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279003848] [2024-10-13 17:45:10,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1279003848] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:10,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:10,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:10,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750937987] [2024-10-13 17:45:10,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:10,207 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:10,207 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:10,208 INFO L85 PathProgramCache]: Analyzing trace with hash -155238939, now seen corresponding path program 1 times [2024-10-13 17:45:10,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:10,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241784097] [2024-10-13 17:45:10,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:10,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:10,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:10,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:10,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:10,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241784097] [2024-10-13 17:45:10,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241784097] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:10,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:10,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:10,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73340487] [2024-10-13 17:45:10,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:10,239 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:10,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:10,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:10,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:10,240 INFO L87 Difference]: Start difference. First operand 31425 states and 45537 transitions. cyclomatic complexity: 14144 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:10,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:10,709 INFO L93 Difference]: Finished difference Result 59788 states and 86234 transitions. [2024-10-13 17:45:10,709 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59788 states and 86234 transitions. [2024-10-13 17:45:11,197 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59420 [2024-10-13 17:45:11,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59788 states to 59788 states and 86234 transitions. [2024-10-13 17:45:11,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59788 [2024-10-13 17:45:11,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59788 [2024-10-13 17:45:11,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59788 states and 86234 transitions. [2024-10-13 17:45:11,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:11,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59788 states and 86234 transitions. [2024-10-13 17:45:11,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59788 states and 86234 transitions. [2024-10-13 17:45:12,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59788 to 59724. [2024-10-13 17:45:12,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59724 states, 59724 states have (on average 1.4428035630567275) internal successors, (86170), 59723 states have internal predecessors, (86170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:12,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59724 states to 59724 states and 86170 transitions. [2024-10-13 17:45:12,870 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59724 states and 86170 transitions. [2024-10-13 17:45:12,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:12,870 INFO L425 stractBuchiCegarLoop]: Abstraction has 59724 states and 86170 transitions. [2024-10-13 17:45:12,870 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-13 17:45:12,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59724 states and 86170 transitions. [2024-10-13 17:45:13,171 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59356 [2024-10-13 17:45:13,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:13,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:13,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:13,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:13,174 INFO L745 eck$LassoCheckResult]: Stem: 214807#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 214808#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 215770#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 215771#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 215410#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 215089#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 215090#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 215378#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 215567#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215259#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215260#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215141#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215142#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 215514#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 215471#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 215385#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 215386#L1024 assume !(0 == ~M_E~0); 215678#L1024-2 assume !(0 == ~T1_E~0); 214803#L1029-1 assume !(0 == ~T2_E~0); 214804#L1034-1 assume !(0 == ~T3_E~0); 214910#L1039-1 assume !(0 == ~T4_E~0); 215797#L1044-1 assume !(0 == ~T5_E~0); 215162#L1049-1 assume !(0 == ~T6_E~0); 215163#L1054-1 assume !(0 == ~T7_E~0); 215409#L1059-1 assume !(0 == ~T8_E~0); 214855#L1064-1 assume !(0 == ~T9_E~0); 214856#L1069-1 assume !(0 == ~T10_E~0); 215645#L1074-1 assume !(0 == ~E_M~0); 215707#L1079-1 assume !(0 == ~E_1~0); 215680#L1084-1 assume !(0 == ~E_2~0); 215681#L1089-1 assume !(0 == ~E_3~0); 215726#L1094-1 assume !(0 == ~E_4~0); 215250#L1099-1 assume !(0 == ~E_5~0); 215251#L1104-1 assume !(0 == ~E_6~0); 215533#L1109-1 assume !(0 == ~E_7~0); 215030#L1114-1 assume !(0 == ~E_8~0); 215031#L1119-1 assume !(0 == ~E_9~0); 215099#L1124-1 assume !(0 == ~E_10~0); 214503#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 214504#L502 assume !(1 == ~m_pc~0); 214698#L502-2 is_master_triggered_~__retres1~0#1 := 0; 214628#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 214629#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215465#L1273 assume !(0 != activate_threads_~tmp~1#1); 215466#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215839#L521 assume !(1 == ~t1_pc~0); 215758#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 214553#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 214519#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214520#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 214539#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 214540#L540 assume !(1 == ~t2_pc~0); 215364#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 215365#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215026#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215027#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 215753#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214834#L559 assume !(1 == ~t3_pc~0); 214835#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 215120#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214456#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 214457#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 214646#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214647#L578 assume !(1 == ~t4_pc~0); 214770#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 214769#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214585#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 214586#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 215444#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215445#L597 assume 1 == ~t5_pc~0; 215861#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 214573#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214574#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215676#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 215387#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215388#L616 assume !(1 == ~t6_pc~0); 215404#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 215403#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215003#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 215004#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 215239#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 215240#L635 assume 1 == ~t7_pc~0; 215450#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 214542#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 214925#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 215722#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 215380#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 215381#L654 assume !(1 == ~t8_pc~0); 215191#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 215192#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 215598#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 215599#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 215643#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 214801#L673 assume 1 == ~t9_pc~0; 214802#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 214494#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 215083#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 215084#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 215548#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 215549#L692 assume !(1 == ~t10_pc~0); 215487#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 215486#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 215242#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 215243#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 215254#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215618#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 214710#L1142-2 assume !(1 == ~T1_E~0); 214711#L1147-1 assume !(1 == ~T2_E~0); 215605#L1152-1 assume !(1 == ~T3_E~0); 215127#L1157-1 assume !(1 == ~T4_E~0); 215128#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 215278#L1167-1 assume !(1 == ~T6_E~0); 215279#L1172-1 assume !(1 == ~T7_E~0); 215744#L1177-1 assume !(1 == ~T8_E~0); 215430#L1182-1 assume !(1 == ~T9_E~0); 215431#L1187-1 assume !(1 == ~T10_E~0); 215541#L1192-1 assume !(1 == ~E_M~0); 215596#L1197-1 assume !(1 == ~E_1~0); 215608#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 215367#L1207-1 assume !(1 == ~E_3~0); 215344#L1212-1 assume !(1 == ~E_4~0); 214558#L1217-1 assume !(1 == ~E_5~0); 214559#L1222-1 assume !(1 == ~E_6~0); 215341#L1227-1 assume !(1 == ~E_7~0); 215342#L1232-1 assume !(1 == ~E_8~0); 215427#L1237-1 assume !(1 == ~E_9~0); 237427#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 237110#L1247-1 assume { :end_inline_reset_delta_events } true; 237108#L1553-2 [2024-10-13 17:45:13,175 INFO L747 eck$LassoCheckResult]: Loop: 237108#L1553-2 assume !false; 235933#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235928#L999-1 assume !false; 235926#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 235924#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 235912#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 235911#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 235909#L854 assume !(0 != eval_~tmp~0#1); 235910#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 244368#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 244365#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 244362#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 244359#L1029-3 assume !(0 == ~T2_E~0); 244356#L1034-3 assume !(0 == ~T3_E~0); 244353#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 244350#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 244347#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 244343#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 244339#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 244336#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 244333#L1069-3 assume !(0 == ~T10_E~0); 244330#L1074-3 assume !(0 == ~E_M~0); 244327#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 244324#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 244320#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 244317#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 244314#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 244311#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 244308#L1109-3 assume !(0 == ~E_7~0); 244304#L1114-3 assume !(0 == ~E_8~0); 244300#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 244297#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 244294#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244291#L502-36 assume !(1 == ~m_pc~0); 244288#L502-38 is_master_triggered_~__retres1~0#1 := 0; 244284#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 244280#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 244277#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 244273#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244269#L521-36 assume !(1 == ~t1_pc~0); 244265#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 244259#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 244254#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 244249#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 244244#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 244238#L540-36 assume !(1 == ~t2_pc~0); 244233#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 244227#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 244221#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 216577#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 216578#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216565#L559-36 assume !(1 == ~t3_pc~0); 216566#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 216552#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216553#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 216538#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 216539#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216525#L578-36 assume !(1 == ~t4_pc~0); 216527#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 216510#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216511#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 216498#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 216499#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216484#L597-36 assume 1 == ~t5_pc~0; 216486#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 216470#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216471#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 216458#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 216459#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 216445#L616-36 assume !(1 == ~t6_pc~0); 216447#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 216429#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 216430#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 216416#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 216417#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216402#L635-36 assume !(1 == ~t7_pc~0); 216403#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 216388#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216389#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 216269#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 216270#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 216262#L654-36 assume 1 == ~t8_pc~0; 216263#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 216255#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 216256#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 216248#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 216249#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 216241#L673-36 assume !(1 == ~t9_pc~0); 216243#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 216232#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 216233#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 216225#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 216226#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 244044#L692-36 assume !(1 == ~t10_pc~0); 244043#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 244041#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 244040#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 244039#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 244038#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 244037#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 216139#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 244036#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 244035#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 241206#L1157-3 assume !(1 == ~T4_E~0); 244034#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 244033#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 244032#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 244031#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 216095#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 216096#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 216091#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 216092#L1197-3 assume !(1 == ~E_1~0); 216087#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 216088#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 216083#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 216084#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 216079#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 216080#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 216076#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 216074#L1237-3 assume !(1 == ~E_9~0); 216075#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 243449#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 243001#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 242989#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 242987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 242983#L1572 assume !(0 == start_simulation_~tmp~3#1); 242980#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 242815#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 242807#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 242419#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 237118#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 237115#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 237113#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 237111#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 237108#L1553-2 [2024-10-13 17:45:13,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:13,175 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2024-10-13 17:45:13,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:13,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322968979] [2024-10-13 17:45:13,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:13,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:13,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:13,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:13,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:13,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322968979] [2024-10-13 17:45:13,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322968979] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:13,242 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:13,242 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:13,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104930049] [2024-10-13 17:45:13,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:13,243 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:13,243 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:13,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1588686052, now seen corresponding path program 1 times [2024-10-13 17:45:13,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:13,243 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344410486] [2024-10-13 17:45:13,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:13,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:13,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:13,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:13,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:13,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344410486] [2024-10-13 17:45:13,286 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344410486] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:13,286 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:13,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:13,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1138119070] [2024-10-13 17:45:13,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:13,287 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:13,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:13,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:45:13,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:45:13,288 INFO L87 Difference]: Start difference. First operand 59724 states and 86170 transitions. cyclomatic complexity: 26510 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:13,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:13,926 INFO L93 Difference]: Finished difference Result 61575 states and 88021 transitions. [2024-10-13 17:45:13,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61575 states and 88021 transitions. [2024-10-13 17:45:14,160 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61204 [2024-10-13 17:45:14,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61575 states to 61575 states and 88021 transitions. [2024-10-13 17:45:14,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61575 [2024-10-13 17:45:14,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61575 [2024-10-13 17:45:14,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61575 states and 88021 transitions. [2024-10-13 17:45:14,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:14,701 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2024-10-13 17:45:14,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61575 states and 88021 transitions. [2024-10-13 17:45:15,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61575 to 61575. [2024-10-13 17:45:15,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61575 states, 61575 states have (on average 1.4294924888347544) internal successors, (88021), 61574 states have internal predecessors, (88021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:15,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61575 states to 61575 states and 88021 transitions. [2024-10-13 17:45:15,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2024-10-13 17:45:15,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:45:15,406 INFO L425 stractBuchiCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2024-10-13 17:45:15,406 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-13 17:45:15,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61575 states and 88021 transitions. [2024-10-13 17:45:15,886 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61204 [2024-10-13 17:45:15,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:15,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:15,888 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:15,893 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:15,893 INFO L745 eck$LassoCheckResult]: Stem: 336121#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 336122#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 337175#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337176#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 336760#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 336410#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 336411#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 336727#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 336926#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 336597#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 336598#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 336465#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 336466#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 336875#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 336822#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 336735#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 336736#L1024 assume !(0 == ~M_E~0); 337053#L1024-2 assume !(0 == ~T1_E~0); 336117#L1029-1 assume !(0 == ~T2_E~0); 336118#L1034-1 assume !(0 == ~T3_E~0); 336226#L1039-1 assume !(0 == ~T4_E~0); 337210#L1044-1 assume !(0 == ~T5_E~0); 336489#L1049-1 assume !(0 == ~T6_E~0); 336490#L1054-1 assume !(0 == ~T7_E~0); 336759#L1059-1 assume !(0 == ~T8_E~0); 336170#L1064-1 assume !(0 == ~T9_E~0); 336171#L1069-1 assume !(0 == ~T10_E~0); 337014#L1074-1 assume !(0 == ~E_M~0); 337091#L1079-1 assume !(0 == ~E_1~0); 337057#L1084-1 assume !(0 == ~E_2~0); 337058#L1089-1 assume !(0 == ~E_3~0); 337121#L1094-1 assume !(0 == ~E_4~0); 336587#L1099-1 assume !(0 == ~E_5~0); 336588#L1104-1 assume !(0 == ~E_6~0); 336894#L1109-1 assume !(0 == ~E_7~0); 336344#L1114-1 assume !(0 == ~E_8~0); 336345#L1119-1 assume !(0 == ~E_9~0); 336420#L1124-1 assume !(0 == ~E_10~0); 335812#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 335813#L502 assume !(1 == ~m_pc~0); 336010#L502-2 is_master_triggered_~__retres1~0#1 := 0; 335940#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 335941#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 336816#L1273 assume !(0 != activate_threads_~tmp~1#1); 336817#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 337277#L521 assume !(1 == ~t1_pc~0); 337157#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 335864#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 335828#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 335829#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 335850#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 335851#L540 assume !(1 == ~t2_pc~0); 336712#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 336713#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 336340#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336341#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 337151#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336149#L559 assume !(1 == ~t3_pc~0); 336150#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 336442#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 335765#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 335766#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 335958#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 335959#L578 assume !(1 == ~t4_pc~0); 336082#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 337020#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 335896#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 335897#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 336794#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336795#L597 assume 1 == ~t5_pc~0; 337308#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 335884#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 335885#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 337050#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 336737#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 336738#L616 assume !(1 == ~t6_pc~0); 336754#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 336753#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 336317#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 336318#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 336575#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 336576#L635 assume 1 == ~t7_pc~0; 336799#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 335853#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 336242#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 337117#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 336729#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 336730#L654 assume !(1 == ~t8_pc~0); 336520#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 336521#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 336960#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 336961#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 337012#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 336115#L673 assume 1 == ~t9_pc~0; 336116#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 335803#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 336404#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 336405#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 336906#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 336907#L692 assume !(1 == ~t10_pc~0); 336841#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 336840#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 336578#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 336579#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 336591#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336983#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 336022#L1142-2 assume !(1 == ~T1_E~0); 336023#L1147-1 assume !(1 == ~T2_E~0); 336968#L1152-1 assume !(1 == ~T3_E~0); 337368#L1157-1 assume !(1 == ~T4_E~0); 346142#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 346141#L1167-1 assume !(1 == ~T6_E~0); 346138#L1172-1 assume !(1 == ~T7_E~0); 346137#L1177-1 assume !(1 == ~T8_E~0); 346135#L1182-1 assume !(1 == ~T9_E~0); 346133#L1187-1 assume !(1 == ~T10_E~0); 346132#L1192-1 assume !(1 == ~E_M~0); 346131#L1197-1 assume !(1 == ~E_1~0); 346129#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 346126#L1207-1 assume !(1 == ~E_3~0); 346124#L1212-1 assume !(1 == ~E_4~0); 346122#L1217-1 assume !(1 == ~E_5~0); 346120#L1222-1 assume !(1 == ~E_6~0); 346117#L1227-1 assume !(1 == ~E_7~0); 346115#L1232-1 assume !(1 == ~E_8~0); 346111#L1237-1 assume !(1 == ~E_9~0); 346109#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 345784#L1247-1 assume { :end_inline_reset_delta_events } true; 345781#L1553-2 [2024-10-13 17:45:15,894 INFO L747 eck$LassoCheckResult]: Loop: 345781#L1553-2 assume !false; 345779#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 345774#L999-1 assume !false; 345772#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 345770#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 345758#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 345755#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 345752#L854 assume !(0 != eval_~tmp~0#1); 345753#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 365950#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 365948#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 365945#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 365943#L1029-3 assume !(0 == ~T2_E~0); 365941#L1034-3 assume !(0 == ~T3_E~0); 365939#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 365937#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 365935#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 365932#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 365930#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 365928#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 365926#L1069-3 assume !(0 == ~T10_E~0); 365924#L1074-3 assume !(0 == ~E_M~0); 365922#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 365919#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 365917#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 365915#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 365913#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 365911#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 365909#L1109-3 assume !(0 == ~E_7~0); 365906#L1114-3 assume !(0 == ~E_8~0); 365904#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 365902#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 365900#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 365898#L502-36 assume !(1 == ~m_pc~0); 365896#L502-38 is_master_triggered_~__retres1~0#1 := 0; 365893#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 365891#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 365889#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 365887#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 365885#L521-36 assume !(1 == ~t1_pc~0); 365883#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 365879#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365877#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 365875#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 365873#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365871#L540-36 assume !(1 == ~t2_pc~0); 365870#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 365866#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365864#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 365862#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 365859#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365858#L559-36 assume !(1 == ~t3_pc~0); 365857#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 365856#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365855#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 365853#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 365852#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365851#L578-36 assume 1 == ~t4_pc~0; 365849#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 365850#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 365854#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 365841#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 352324#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 352322#L597-36 assume 1 == ~t5_pc~0; 352319#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 352316#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 352314#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 352312#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 352310#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 352308#L616-36 assume !(1 == ~t6_pc~0); 352305#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 352302#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 352300#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 352298#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 352296#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 352294#L635-36 assume 1 == ~t7_pc~0; 352291#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 352288#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 352286#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 352284#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 352282#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 352280#L654-36 assume !(1 == ~t8_pc~0); 352277#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 352274#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 352272#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 352270#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 352268#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 352266#L673-36 assume 1 == ~t9_pc~0; 352263#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 352260#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 352258#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 352256#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 352254#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 352252#L692-36 assume !(1 == ~t10_pc~0); 352249#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 352246#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352244#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 352242#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 352240#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352238#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 337701#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 352235#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 352232#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 352228#L1157-3 assume !(1 == ~T4_E~0); 352226#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 352224#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 352222#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 352220#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 352218#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 352216#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 352214#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 352212#L1197-3 assume !(1 == ~E_1~0); 352210#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 352208#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 352206#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 352204#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 352202#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 352200#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 352199#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 352196#L1237-3 assume !(1 == ~E_9~0); 352195#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 352194#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 352193#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 352182#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 352181#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 352006#L1572 assume !(0 == start_simulation_~tmp~3#1); 352004#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 345804#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 345795#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 345793#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 345791#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 345789#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 345787#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 345785#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 345781#L1553-2 [2024-10-13 17:45:15,894 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:15,895 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2024-10-13 17:45:15,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:15,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370682740] [2024-10-13 17:45:15,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:15,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:15,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:15,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:15,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:15,994 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370682740] [2024-10-13 17:45:15,994 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370682740] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:15,994 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:15,994 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:15,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005948732] [2024-10-13 17:45:15,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:15,995 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:15,995 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:15,995 INFO L85 PathProgramCache]: Analyzing trace with hash 1787027042, now seen corresponding path program 1 times [2024-10-13 17:45:15,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:15,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844985505] [2024-10-13 17:45:15,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:15,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:16,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:16,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:16,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:16,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844985505] [2024-10-13 17:45:16,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844985505] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:16,081 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:16,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:16,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786333684] [2024-10-13 17:45:16,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:16,082 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:16,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:16,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:16,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:16,082 INFO L87 Difference]: Start difference. First operand 61575 states and 88021 transitions. cyclomatic complexity: 26510 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:16,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:16,668 INFO L93 Difference]: Finished difference Result 117170 states and 166838 transitions. [2024-10-13 17:45:16,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117170 states and 166838 transitions. [2024-10-13 17:45:17,194 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116512 [2024-10-13 17:45:18,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117170 states to 117170 states and 166838 transitions. [2024-10-13 17:45:18,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117170 [2024-10-13 17:45:18,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117170 [2024-10-13 17:45:18,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117170 states and 166838 transitions. [2024-10-13 17:45:18,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:18,336 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117170 states and 166838 transitions. [2024-10-13 17:45:18,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117170 states and 166838 transitions. [2024-10-13 17:45:19,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117170 to 117042. [2024-10-13 17:45:19,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117042 states, 117042 states have (on average 1.424360485979392) internal successors, (166710), 117041 states have internal predecessors, (166710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:19,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117042 states to 117042 states and 166710 transitions. [2024-10-13 17:45:19,954 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117042 states and 166710 transitions. [2024-10-13 17:45:19,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:19,955 INFO L425 stractBuchiCegarLoop]: Abstraction has 117042 states and 166710 transitions. [2024-10-13 17:45:19,955 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-13 17:45:19,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117042 states and 166710 transitions. [2024-10-13 17:45:20,631 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116384 [2024-10-13 17:45:20,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:20,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:20,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:20,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:20,634 INFO L745 eck$LassoCheckResult]: Stem: 514867#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 514868#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 515830#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 515831#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 515469#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 515137#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 515138#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 515436#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 515627#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 515315#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 515316#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 515189#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 515190#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 515577#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 515526#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 515444#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 515445#L1024 assume !(0 == ~M_E~0); 515741#L1024-2 assume !(0 == ~T1_E~0); 514863#L1029-1 assume !(0 == ~T2_E~0); 514864#L1034-1 assume !(0 == ~T3_E~0); 514967#L1039-1 assume !(0 == ~T4_E~0); 515859#L1044-1 assume !(0 == ~T5_E~0); 515211#L1049-1 assume !(0 == ~T6_E~0); 515212#L1054-1 assume !(0 == ~T7_E~0); 515468#L1059-1 assume !(0 == ~T8_E~0); 514914#L1064-1 assume !(0 == ~T9_E~0); 514915#L1069-1 assume !(0 == ~T10_E~0); 515705#L1074-1 assume !(0 == ~E_M~0); 515772#L1079-1 assume !(0 == ~E_1~0); 515743#L1084-1 assume !(0 == ~E_2~0); 515744#L1089-1 assume !(0 == ~E_3~0); 515791#L1094-1 assume !(0 == ~E_4~0); 515306#L1099-1 assume !(0 == ~E_5~0); 515307#L1104-1 assume !(0 == ~E_6~0); 515595#L1109-1 assume !(0 == ~E_7~0); 515081#L1114-1 assume !(0 == ~E_8~0); 515082#L1119-1 assume !(0 == ~E_9~0); 515147#L1124-1 assume !(0 == ~E_10~0); 514563#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 514564#L502 assume !(1 == ~m_pc~0); 514758#L502-2 is_master_triggered_~__retres1~0#1 := 0; 514689#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 514690#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 515520#L1273 assume !(0 != activate_threads_~tmp~1#1); 515521#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 515915#L521 assume !(1 == ~t1_pc~0); 515819#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 514614#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 514579#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 514580#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 514600#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 514601#L540 assume !(1 == ~t2_pc~0); 515424#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 515425#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 515077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 515078#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 515815#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 514893#L559 assume !(1 == ~t3_pc~0); 514894#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 515167#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 514516#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 514517#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 514707#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 514708#L578 assume !(1 == ~t4_pc~0); 514827#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 515711#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 514646#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 514647#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 515500#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 515501#L597 assume !(1 == ~t5_pc~0); 515454#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 514634#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 514635#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 515739#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 515446#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 515447#L616 assume !(1 == ~t6_pc~0); 515463#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 515462#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 515054#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 515055#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 515294#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 515295#L635 assume 1 == ~t7_pc~0; 515505#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 514603#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 514983#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 515787#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 515439#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 515440#L654 assume !(1 == ~t8_pc~0); 515240#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 515241#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 515655#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 515656#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 515703#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 514861#L673 assume 1 == ~t9_pc~0; 514862#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 514554#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 515131#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 515132#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 515610#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 515611#L692 assume !(1 == ~t10_pc~0); 515546#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 515545#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 515297#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 515298#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 515310#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515681#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 514768#L1142-2 assume !(1 == ~T1_E~0); 514769#L1147-1 assume !(1 == ~T2_E~0); 515662#L1152-1 assume !(1 == ~T3_E~0); 515174#L1157-1 assume !(1 == ~T4_E~0); 515175#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 515749#L1167-1 assume !(1 == ~T6_E~0); 516844#L1172-1 assume !(1 == ~T7_E~0); 516842#L1177-1 assume !(1 == ~T8_E~0); 516840#L1182-1 assume !(1 == ~T9_E~0); 516838#L1187-1 assume !(1 == ~T10_E~0); 516837#L1192-1 assume !(1 == ~E_M~0); 516834#L1197-1 assume !(1 == ~E_1~0); 516832#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 516830#L1207-1 assume !(1 == ~E_3~0); 516828#L1212-1 assume !(1 == ~E_4~0); 516826#L1217-1 assume !(1 == ~E_5~0); 516824#L1222-1 assume !(1 == ~E_6~0); 516822#L1227-1 assume !(1 == ~E_7~0); 516777#L1232-1 assume !(1 == ~E_8~0); 516712#L1237-1 assume !(1 == ~E_9~0); 516700#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 516691#L1247-1 assume { :end_inline_reset_delta_events } true; 516684#L1553-2 [2024-10-13 17:45:20,634 INFO L747 eck$LassoCheckResult]: Loop: 516684#L1553-2 assume !false; 516678#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 516674#L999-1 assume !false; 516673#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 516672#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 516661#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 516660#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 516658#L854 assume !(0 != eval_~tmp~0#1); 516657#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 516656#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 516653#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 516654#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 519380#L1029-3 assume !(0 == ~T2_E~0); 519378#L1034-3 assume !(0 == ~T3_E~0); 519376#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 519374#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 519371#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 519369#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 519367#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 519366#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 519365#L1069-3 assume !(0 == ~T10_E~0); 519363#L1074-3 assume !(0 == ~E_M~0); 519361#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 518901#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 518899#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 518897#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 518895#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 518893#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 518891#L1109-3 assume !(0 == ~E_7~0); 518889#L1114-3 assume !(0 == ~E_8~0); 518887#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 518886#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 518885#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 518883#L502-36 assume !(1 == ~m_pc~0); 518881#L502-38 is_master_triggered_~__retres1~0#1 := 0; 518878#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518876#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 518874#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 518872#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 518870#L521-36 assume !(1 == ~t1_pc~0); 518868#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 518099#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 518097#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 518095#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 518093#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 518089#L540-36 assume !(1 == ~t2_pc~0); 518085#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 518081#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 518077#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 518073#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 518069#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 518066#L559-36 assume !(1 == ~t3_pc~0); 518063#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 518061#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 518060#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 518059#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 518058#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 517888#L578-36 assume 1 == ~t4_pc~0; 517886#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 517887#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 518057#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 517877#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 517875#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 517846#L597-36 assume !(1 == ~t5_pc~0); 517839#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 517832#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 517824#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 517817#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 517810#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 517801#L616-36 assume !(1 == ~t6_pc~0); 517794#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 517786#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 517778#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 517774#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 517486#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 517483#L635-36 assume 1 == ~t7_pc~0; 517481#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 517478#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 517476#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 517474#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 517472#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 517469#L654-36 assume !(1 == ~t8_pc~0); 517362#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 517359#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 517358#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 517357#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 517356#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 517352#L673-36 assume 1 == ~t9_pc~0; 517350#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 517347#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 517346#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 517343#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 517342#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 517341#L692-36 assume !(1 == ~t10_pc~0); 517340#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 517338#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 517195#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 517193#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 517190#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 517188#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 516448#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 517185#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 517183#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 517180#L1157-3 assume !(1 == ~T4_E~0); 517178#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 517176#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 517174#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 517172#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 517170#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 517168#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 517070#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 517066#L1197-3 assume !(1 == ~E_1~0); 517063#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 517004#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 517001#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 516999#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 516997#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 516988#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 516977#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 516970#L1237-3 assume !(1 == ~E_9~0); 516964#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 516959#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 516812#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 516801#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 516800#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 516797#L1572 assume !(0 == start_simulation_~tmp~3#1); 516795#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 516731#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 516724#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 516721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 516720#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 516716#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 516701#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 516692#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 516684#L1553-2 [2024-10-13 17:45:20,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:20,635 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2024-10-13 17:45:20,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:20,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588787780] [2024-10-13 17:45:20,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:20,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:20,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:20,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:20,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:20,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588787780] [2024-10-13 17:45:20,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588787780] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:20,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:20,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:20,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019337802] [2024-10-13 17:45:20,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:20,682 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:20,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:20,682 INFO L85 PathProgramCache]: Analyzing trace with hash -168294173, now seen corresponding path program 1 times [2024-10-13 17:45:20,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:20,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946887558] [2024-10-13 17:45:20,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:20,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:20,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:20,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:20,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:20,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946887558] [2024-10-13 17:45:20,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1946887558] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:20,712 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:20,712 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:20,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375622312] [2024-10-13 17:45:20,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:20,713 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:20,713 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:20,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:20,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:20,713 INFO L87 Difference]: Start difference. First operand 117042 states and 166710 transitions. cyclomatic complexity: 49796 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:21,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:21,989 INFO L93 Difference]: Finished difference Result 281557 states and 398399 transitions. [2024-10-13 17:45:21,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281557 states and 398399 transitions. [2024-10-13 17:45:23,126 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 279812 [2024-10-13 17:45:24,327 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281557 states to 281557 states and 398399 transitions. [2024-10-13 17:45:24,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281557 [2024-10-13 17:45:24,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281557 [2024-10-13 17:45:24,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281557 states and 398399 transitions. [2024-10-13 17:45:24,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:24,585 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281557 states and 398399 transitions. [2024-10-13 17:45:24,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281557 states and 398399 transitions. [2024-10-13 17:45:26,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281557 to 227265. [2024-10-13 17:45:27,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227265 states, 227265 states have (on average 1.4180582139792752) internal successors, (322275), 227264 states have internal predecessors, (322275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:27,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227265 states to 227265 states and 322275 transitions. [2024-10-13 17:45:27,601 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227265 states and 322275 transitions. [2024-10-13 17:45:27,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:27,602 INFO L425 stractBuchiCegarLoop]: Abstraction has 227265 states and 322275 transitions. [2024-10-13 17:45:27,602 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-13 17:45:27,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227265 states and 322275 transitions. [2024-10-13 17:45:28,806 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 226160 [2024-10-13 17:45:28,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:28,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:28,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:28,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:28,816 INFO L745 eck$LassoCheckResult]: Stem: 913477#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 913478#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 914511#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 914512#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 914101#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 913765#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 913766#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 914063#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 914270#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 913945#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 913946#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 913818#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 913819#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 914216#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 914162#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 914072#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 914073#L1024 assume !(0 == ~M_E~0); 914398#L1024-2 assume !(0 == ~T1_E~0); 913473#L1029-1 assume !(0 == ~T2_E~0); 913474#L1034-1 assume !(0 == ~T3_E~0); 913581#L1039-1 assume !(0 == ~T4_E~0); 914535#L1044-1 assume !(0 == ~T5_E~0); 913840#L1049-1 assume !(0 == ~T6_E~0); 913841#L1054-1 assume !(0 == ~T7_E~0); 914100#L1059-1 assume !(0 == ~T8_E~0); 913528#L1064-1 assume !(0 == ~T9_E~0); 913529#L1069-1 assume !(0 == ~T10_E~0); 914362#L1074-1 assume !(0 == ~E_M~0); 914435#L1079-1 assume !(0 == ~E_1~0); 914400#L1084-1 assume !(0 == ~E_2~0); 914401#L1089-1 assume !(0 == ~E_3~0); 914461#L1094-1 assume !(0 == ~E_4~0); 913935#L1099-1 assume !(0 == ~E_5~0); 913936#L1104-1 assume !(0 == ~E_6~0); 914239#L1109-1 assume !(0 == ~E_7~0); 913704#L1114-1 assume !(0 == ~E_8~0); 913705#L1119-1 assume !(0 == ~E_9~0); 913776#L1124-1 assume !(0 == ~E_10~0); 913172#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913173#L502 assume !(1 == ~m_pc~0); 913368#L502-2 is_master_triggered_~__retres1~0#1 := 0; 913299#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 913300#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 914156#L1273 assume !(0 != activate_threads_~tmp~1#1); 914157#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 914595#L521 assume !(1 == ~t1_pc~0); 914497#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 913223#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 913188#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 913189#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 913209#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 913210#L540 assume !(1 == ~t2_pc~0); 914051#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 914052#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 913700#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 913701#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 914491#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 913507#L559 assume !(1 == ~t3_pc~0); 913508#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 913796#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 913125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 913126#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 913317#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 913318#L578 assume !(1 == ~t4_pc~0); 913437#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 914367#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 914395#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 914577#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 914133#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 914134#L597 assume !(1 == ~t5_pc~0); 914083#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 913243#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 913244#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 914396#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 914074#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 914075#L616 assume !(1 == ~t6_pc~0); 914095#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 914094#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 913675#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 913676#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 913923#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 913924#L635 assume !(1 == ~t7_pc~0); 913211#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 913212#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 913598#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 914456#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 914065#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 914066#L654 assume !(1 == ~t8_pc~0); 913870#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 913871#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 914303#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 914304#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 914360#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 913471#L673 assume 1 == ~t9_pc~0; 913472#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 913163#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 913759#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 913760#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 914253#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 914254#L692 assume !(1 == ~t10_pc~0); 914183#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 914182#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 913926#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 913927#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 913940#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 914334#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 913378#L1142-2 assume !(1 == ~T1_E~0); 913379#L1147-1 assume !(1 == ~T2_E~0); 914684#L1152-1 assume !(1 == ~T3_E~0); 914685#L1157-1 assume !(1 == ~T4_E~0); 914409#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 914410#L1167-1 assume !(1 == ~T6_E~0); 914479#L1172-1 assume !(1 == ~T7_E~0); 914480#L1177-1 assume !(1 == ~T8_E~0); 914119#L1182-1 assume !(1 == ~T9_E~0); 914120#L1187-1 assume !(1 == ~T10_E~0); 914301#L1192-1 assume !(1 == ~E_M~0); 914302#L1197-1 assume !(1 == ~E_1~0); 914315#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 914316#L1207-1 assume !(1 == ~E_3~0); 949524#L1212-1 assume !(1 == ~E_4~0); 949523#L1217-1 assume !(1 == ~E_5~0); 949522#L1222-1 assume !(1 == ~E_6~0); 914026#L1227-1 assume !(1 == ~E_7~0); 914027#L1232-1 assume !(1 == ~E_8~0); 913103#L1237-1 assume !(1 == ~E_9~0); 913104#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 914098#L1247-1 assume { :end_inline_reset_delta_events } true; 914099#L1553-2 [2024-10-13 17:45:28,817 INFO L747 eck$LassoCheckResult]: Loop: 914099#L1553-2 assume !false; 957399#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 957392#L999-1 assume !false; 957389#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 957359#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 957343#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 957336#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 957330#L854 assume !(0 != eval_~tmp~0#1); 957331#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 964871#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 964866#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 964861#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 964856#L1029-3 assume !(0 == ~T2_E~0); 964851#L1034-3 assume !(0 == ~T3_E~0); 964845#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 964840#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 964835#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 964830#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 964825#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 964820#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 964816#L1069-3 assume !(0 == ~T10_E~0); 964810#L1074-3 assume !(0 == ~E_M~0); 964804#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 964798#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 964792#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 964787#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 964781#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 964775#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 964770#L1109-3 assume !(0 == ~E_7~0); 964765#L1114-3 assume !(0 == ~E_8~0); 964760#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 964754#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 964748#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 964741#L502-36 assume !(1 == ~m_pc~0); 964736#L502-38 is_master_triggered_~__retres1~0#1 := 0; 964731#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 964726#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 964721#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 964715#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 964711#L521-36 assume !(1 == ~t1_pc~0); 964706#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 964700#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 964695#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 958933#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 958930#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 958928#L540-36 assume !(1 == ~t2_pc~0); 958926#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 958924#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 958922#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 958920#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 958917#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 958915#L559-36 assume !(1 == ~t3_pc~0); 958913#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 958911#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 958909#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 958133#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 958132#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 958131#L578-36 assume !(1 == ~t4_pc~0); 958130#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 958128#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 958126#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 958124#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 958122#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 958121#L597-36 assume !(1 == ~t5_pc~0); 958120#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 958118#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 958116#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 958114#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 958112#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 958110#L616-36 assume !(1 == ~t6_pc~0); 958108#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 958105#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 958102#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 958100#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 958098#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 958096#L635-36 assume !(1 == ~t7_pc~0); 927863#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 958093#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 958091#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 958089#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 958087#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 958085#L654-36 assume 1 == ~t8_pc~0; 958082#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 958080#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 958078#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 958075#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 958072#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 958069#L673-36 assume 1 == ~t9_pc~0; 958066#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 958062#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 958058#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 958054#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 958049#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 958045#L692-36 assume !(1 == ~t10_pc~0); 958042#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 958038#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 958035#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 958032#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 958029#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 958026#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 944663#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 958020#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 958014#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 956402#L1157-3 assume !(1 == ~T4_E~0); 958005#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 958000#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 957994#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 957988#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 957982#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 957975#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 957968#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 956693#L1197-3 assume !(1 == ~E_1~0); 957955#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 957947#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 957940#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 957934#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 957928#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 957922#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 957917#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 948907#L1237-3 assume !(1 == ~E_9~0); 957906#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 957900#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 957656#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 957644#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 957642#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 957636#L1572 assume !(0 == start_simulation_~tmp~3#1); 957634#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 957452#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 957444#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 957442#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 957440#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 957436#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 957425#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 957415#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 914099#L1553-2 [2024-10-13 17:45:28,820 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:28,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2024-10-13 17:45:28,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:28,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816072922] [2024-10-13 17:45:28,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:28,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:28,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:28,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:28,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:28,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816072922] [2024-10-13 17:45:28,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816072922] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:28,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:28,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:28,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107824208] [2024-10-13 17:45:28,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:28,887 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:28,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:28,887 INFO L85 PathProgramCache]: Analyzing trace with hash -384235546, now seen corresponding path program 1 times [2024-10-13 17:45:28,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:28,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542986361] [2024-10-13 17:45:28,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:28,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:28,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:28,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:28,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:28,922 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542986361] [2024-10-13 17:45:28,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542986361] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:28,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:28,923 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:28,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765377728] [2024-10-13 17:45:28,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:28,923 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:28,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:28,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:28,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:28,924 INFO L87 Difference]: Start difference. First operand 227265 states and 322275 transitions. cyclomatic complexity: 95138 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:31,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:31,109 INFO L93 Difference]: Finished difference Result 431696 states and 610128 transitions. [2024-10-13 17:45:31,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 431696 states and 610128 transitions. [2024-10-13 17:45:33,173 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 429184 [2024-10-13 17:45:34,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 431696 states to 431696 states and 610128 transitions. [2024-10-13 17:45:34,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 431696 [2024-10-13 17:45:34,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 431696 [2024-10-13 17:45:34,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 431696 states and 610128 transitions. [2024-10-13 17:45:35,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:35,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 431696 states and 610128 transitions. [2024-10-13 17:45:35,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431696 states and 610128 transitions. [2024-10-13 17:45:38,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431696 to 431184. [2024-10-13 17:45:39,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 431184 states, 431184 states have (on average 1.4138186945712272) internal successors, (609616), 431183 states have internal predecessors, (609616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:41,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431184 states to 431184 states and 609616 transitions. [2024-10-13 17:45:41,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 431184 states and 609616 transitions. [2024-10-13 17:45:41,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:41,125 INFO L425 stractBuchiCegarLoop]: Abstraction has 431184 states and 609616 transitions. [2024-10-13 17:45:41,125 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-13 17:45:41,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 431184 states and 609616 transitions. [2024-10-13 17:45:42,883 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 428672 [2024-10-13 17:45:42,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:42,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:42,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:42,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:42,886 INFO L745 eck$LassoCheckResult]: Stem: 1572440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1572441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1573496#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1573497#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1573081#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 1572729#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1572730#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1573043#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1573243#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1572918#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1572919#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1572786#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1572787#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1573190#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1573141#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1573051#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1573052#L1024 assume !(0 == ~M_E~0); 1573379#L1024-2 assume !(0 == ~T1_E~0); 1572436#L1029-1 assume !(0 == ~T2_E~0); 1572437#L1034-1 assume !(0 == ~T3_E~0); 1572540#L1039-1 assume !(0 == ~T4_E~0); 1573532#L1044-1 assume !(0 == ~T5_E~0); 1572810#L1049-1 assume !(0 == ~T6_E~0); 1572811#L1054-1 assume !(0 == ~T7_E~0); 1573080#L1059-1 assume !(0 == ~T8_E~0); 1572488#L1064-1 assume !(0 == ~T9_E~0); 1572489#L1069-1 assume !(0 == ~T10_E~0); 1573341#L1074-1 assume !(0 == ~E_M~0); 1573416#L1079-1 assume !(0 == ~E_1~0); 1573383#L1084-1 assume !(0 == ~E_2~0); 1573384#L1089-1 assume !(0 == ~E_3~0); 1573447#L1094-1 assume !(0 == ~E_4~0); 1572908#L1099-1 assume !(0 == ~E_5~0); 1572909#L1104-1 assume !(0 == ~E_6~0); 1573209#L1109-1 assume !(0 == ~E_7~0); 1572663#L1114-1 assume !(0 == ~E_8~0); 1572664#L1119-1 assume !(0 == ~E_9~0); 1572741#L1124-1 assume !(0 == ~E_10~0); 1572139#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1572140#L502 assume !(1 == ~m_pc~0); 1572335#L502-2 is_master_triggered_~__retres1~0#1 := 0; 1572265#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1572266#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1573135#L1273 assume !(0 != activate_threads_~tmp~1#1); 1573136#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1573595#L521 assume !(1 == ~t1_pc~0); 1573481#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1572191#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1572155#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1572156#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 1572177#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1572178#L540 assume !(1 == ~t2_pc~0); 1573028#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1573029#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1572659#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1572660#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 1573477#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1572467#L559 assume !(1 == ~t3_pc~0); 1572468#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1572763#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1572092#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1572093#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 1572283#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1572284#L578 assume !(1 == ~t4_pc~0); 1572403#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1573347#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1573376#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1573580#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 1573114#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1573115#L597 assume !(1 == ~t5_pc~0); 1573065#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1572211#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1572212#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1573377#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 1573053#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1573054#L616 assume !(1 == ~t6_pc~0); 1573075#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1573074#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1572634#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1572635#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 1572896#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1572897#L635 assume !(1 == ~t7_pc~0); 1572179#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1572180#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1572557#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1573442#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 1573045#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1573046#L654 assume !(1 == ~t8_pc~0); 1572840#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1572841#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1573278#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1573279#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 1573338#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1572435#L673 assume !(1 == ~t9_pc~0); 1572129#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1572130#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1572723#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1572724#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 1573223#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1573224#L692 assume !(1 == ~t10_pc~0); 1573161#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1573160#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1572900#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1572901#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 1572912#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1573307#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 1572345#L1142-2 assume !(1 == ~T1_E~0); 1572346#L1147-1 assume !(1 == ~T2_E~0); 1573674#L1152-1 assume !(1 == ~T3_E~0); 1572770#L1157-1 assume !(1 == ~T4_E~0); 1572771#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1572938#L1167-1 assume !(1 == ~T6_E~0); 1572939#L1172-1 assume !(1 == ~T7_E~0); 1573465#L1177-1 assume !(1 == ~T8_E~0); 1573099#L1182-1 assume !(1 == ~T9_E~0); 1573100#L1187-1 assume !(1 == ~T10_E~0); 1573216#L1192-1 assume !(1 == ~E_M~0); 1572608#L1197-1 assume !(1 == ~E_1~0); 1572609#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1573033#L1207-1 assume !(1 == ~E_3~0); 1573004#L1212-1 assume !(1 == ~E_4~0); 1572196#L1217-1 assume !(1 == ~E_5~0); 1572197#L1222-1 assume !(1 == ~E_6~0); 1573001#L1227-1 assume !(1 == ~E_7~0); 1573002#L1232-1 assume !(1 == ~E_8~0); 1572071#L1237-1 assume !(1 == ~E_9~0); 1572072#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1573078#L1247-1 assume { :end_inline_reset_delta_events } true; 1573079#L1553-2 [2024-10-13 17:45:42,886 INFO L747 eck$LassoCheckResult]: Loop: 1573079#L1553-2 assume !false; 1742384#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1742379#L999-1 assume !false; 1742377#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1742373#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1742362#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1742361#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1742359#L854 assume !(0 != eval_~tmp~0#1); 1742360#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1743212#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1743210#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1743208#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1743206#L1029-3 assume !(0 == ~T2_E~0); 1743203#L1034-3 assume !(0 == ~T3_E~0); 1743200#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1743197#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1743194#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1743190#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1743187#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1743184#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1743180#L1069-3 assume !(0 == ~T10_E~0); 1743177#L1074-3 assume !(0 == ~E_M~0); 1743174#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1743165#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1743164#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1743163#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1743162#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1743160#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1743159#L1109-3 assume !(0 == ~E_7~0); 1743077#L1114-3 assume !(0 == ~E_8~0); 1743073#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1743071#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1743069#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1743067#L502-36 assume !(1 == ~m_pc~0); 1743061#L502-38 is_master_triggered_~__retres1~0#1 := 0; 1743056#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1743052#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1743048#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1743045#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1743042#L521-36 assume !(1 == ~t1_pc~0); 1743038#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1743033#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1743030#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1743027#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1743024#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1743021#L540-36 assume !(1 == ~t2_pc~0); 1743017#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1743014#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1743009#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1743003#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1742998#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1742993#L559-36 assume !(1 == ~t3_pc~0); 1742990#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1742987#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1742983#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1742977#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 1742973#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1742969#L578-36 assume 1 == ~t4_pc~0; 1742963#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1742958#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1742953#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1742946#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1742941#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1742937#L597-36 assume !(1 == ~t5_pc~0); 1742933#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1742929#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1742926#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1742923#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1742920#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1742887#L616-36 assume 1 == ~t6_pc~0; 1742878#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1742872#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1742866#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1742861#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1742856#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1742848#L635-36 assume !(1 == ~t7_pc~0); 1732771#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1742840#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1742835#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1742829#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1742823#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1742817#L654-36 assume 1 == ~t8_pc~0; 1742812#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1742809#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1742806#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1742802#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1742799#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1742796#L673-36 assume !(1 == ~t9_pc~0); 1742790#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1742784#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1742778#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1742772#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1742766#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1742761#L692-36 assume 1 == ~t10_pc~0; 1742755#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1742748#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1742743#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1742738#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 1742733#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1742728#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1657203#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1742718#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1742713#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1713619#L1157-3 assume !(1 == ~T4_E~0); 1742704#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1742699#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1742695#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1742690#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1742685#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1742680#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1742674#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1725220#L1197-3 assume !(1 == ~E_1~0); 1742662#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1742654#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1742647#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1742640#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1742633#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1742628#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1742623#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1700258#L1237-3 assume !(1 == ~E_9~0); 1742616#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1742611#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1742554#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1742539#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1742535#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1742529#L1572 assume !(0 == start_simulation_~tmp~3#1); 1742527#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1742432#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1742422#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1742416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1742412#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1742409#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1742404#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1742398#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1573079#L1553-2 [2024-10-13 17:45:42,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:42,887 INFO L85 PathProgramCache]: Analyzing trace with hash -1513086067, now seen corresponding path program 1 times [2024-10-13 17:45:42,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:42,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104337742] [2024-10-13 17:45:42,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:42,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:42,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:42,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:42,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:42,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104337742] [2024-10-13 17:45:42,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104337742] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:42,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:42,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:42,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025405522] [2024-10-13 17:45:42,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:42,929 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:42,929 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:42,929 INFO L85 PathProgramCache]: Analyzing trace with hash 1583210530, now seen corresponding path program 1 times [2024-10-13 17:45:42,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:42,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066964530] [2024-10-13 17:45:42,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:42,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:42,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:42,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:42,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:42,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066964530] [2024-10-13 17:45:42,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066964530] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:42,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:42,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:42,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [118606914] [2024-10-13 17:45:42,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:42,957 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:42,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:42,957 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:42,957 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:42,958 INFO L87 Difference]: Start difference. First operand 431184 states and 609616 transitions. cyclomatic complexity: 178688 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:45,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:45,048 INFO L93 Difference]: Finished difference Result 489437 states and 691881 transitions. [2024-10-13 17:45:45,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 489437 states and 691881 transitions.