./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a046e57d Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-mul-div-a046e57-m [2024-10-13 17:45:54,032 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-13 17:45:54,085 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-13 17:45:54,090 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-13 17:45:54,091 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-13 17:45:54,110 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-13 17:45:54,110 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-13 17:45:54,110 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-13 17:45:54,111 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-13 17:45:54,111 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-13 17:45:54,111 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-13 17:45:54,112 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-13 17:45:54,112 INFO L153 SettingsManager]: * Use SBE=true [2024-10-13 17:45:54,112 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-13 17:45:54,112 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-13 17:45:54,113 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-13 17:45:54,113 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-13 17:45:54,118 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-13 17:45:54,118 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-13 17:45:54,118 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-13 17:45:54,118 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-13 17:45:54,119 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-13 17:45:54,119 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-13 17:45:54,119 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-13 17:45:54,119 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-13 17:45:54,120 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-13 17:45:54,120 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-13 17:45:54,120 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-13 17:45:54,120 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-13 17:45:54,120 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-13 17:45:54,120 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-13 17:45:54,121 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-13 17:45:54,121 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-13 17:45:54,121 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-13 17:45:54,121 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-13 17:45:54,121 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-13 17:45:54,122 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-13 17:45:54,122 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-13 17:45:54,122 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-13 17:45:54,122 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2024-10-13 17:45:54,333 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-13 17:45:54,354 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-13 17:45:54,356 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-13 17:45:54,357 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-13 17:45:54,357 INFO L274 PluginConnector]: CDTParser initialized [2024-10-13 17:45:54,358 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c [2024-10-13 17:45:55,524 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-13 17:45:55,678 INFO L384 CDTParser]: Found 1 translation units. [2024-10-13 17:45:55,678 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c [2024-10-13 17:45:55,688 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4cca17b15/aea50ae11cd54ba0bd79284f1753f95d/FLAG83ad21491 [2024-10-13 17:45:55,700 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4cca17b15/aea50ae11cd54ba0bd79284f1753f95d [2024-10-13 17:45:55,703 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-13 17:45:55,704 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-13 17:45:55,706 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-13 17:45:55,707 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-13 17:45:55,710 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-13 17:45:55,711 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:45:55" (1/1) ... [2024-10-13 17:45:55,712 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3a9d854c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:55, skipping insertion in model container [2024-10-13 17:45:55,712 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:45:55" (1/1) ... [2024-10-13 17:45:55,748 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-13 17:45:55,936 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:45:55,948 INFO L200 MainTranslator]: Completed pre-run [2024-10-13 17:45:55,981 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:45:56,000 INFO L204 MainTranslator]: Completed translation [2024-10-13 17:45:56,001 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56 WrapperNode [2024-10-13 17:45:56,001 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-13 17:45:56,002 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-13 17:45:56,002 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-13 17:45:56,002 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-13 17:45:56,007 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,036 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,099 INFO L138 Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 87, statements flattened = 1241 [2024-10-13 17:45:56,099 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-13 17:45:56,100 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-13 17:45:56,100 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-13 17:45:56,100 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-13 17:45:56,108 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,109 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,116 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,130 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-13 17:45:56,130 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,130 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,140 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,152 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,154 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,158 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,165 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-13 17:45:56,166 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-13 17:45:56,166 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-13 17:45:56,166 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-13 17:45:56,167 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (1/1) ... [2024-10-13 17:45:56,185 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:45:56,195 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:45:56,209 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:45:56,211 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-13 17:45:56,246 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-13 17:45:56,247 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-13 17:45:56,247 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-13 17:45:56,247 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-13 17:45:56,325 INFO L238 CfgBuilder]: Building ICFG [2024-10-13 17:45:56,327 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-13 17:45:57,066 INFO L? ?]: Removed 228 outVars from TransFormulas that were not future-live. [2024-10-13 17:45:57,066 INFO L287 CfgBuilder]: Performing block encoding [2024-10-13 17:45:57,092 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-13 17:45:57,095 INFO L314 CfgBuilder]: Removed 9 assume(true) statements. [2024-10-13 17:45:57,095 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:45:57 BoogieIcfgContainer [2024-10-13 17:45:57,096 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-13 17:45:57,096 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-13 17:45:57,096 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-13 17:45:57,099 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-13 17:45:57,100 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:57,101 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 05:45:55" (1/3) ... [2024-10-13 17:45:57,102 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3b5bcaa5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:45:57, skipping insertion in model container [2024-10-13 17:45:57,102 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:57,102 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:56" (2/3) ... [2024-10-13 17:45:57,103 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3b5bcaa5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:45:57, skipping insertion in model container [2024-10-13 17:45:57,103 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:57,104 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:45:57" (3/3) ... [2024-10-13 17:45:57,105 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2024-10-13 17:45:57,159 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-13 17:45:57,159 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-13 17:45:57,159 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-13 17:45:57,159 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-13 17:45:57,159 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-13 17:45:57,159 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-13 17:45:57,159 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-13 17:45:57,160 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-13 17:45:57,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:57,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 431 [2024-10-13 17:45:57,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:57,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:57,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:57,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:57,199 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-13 17:45:57,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:57,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 431 [2024-10-13 17:45:57,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:57,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:57,210 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:57,210 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:57,216 INFO L745 eck$LassoCheckResult]: Stem: 151#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 412#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 243#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 409#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 257#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 348#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 114#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 402#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 389#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 467#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 330#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 125#L586-2true assume !(0 == ~T1_E~0); 232#L591-1true assume !(0 == ~T2_E~0); 207#L596-1true assume !(0 == ~T3_E~0); 273#L601-1true assume !(0 == ~T4_E~0); 249#L606-1true assume !(0 == ~T5_E~0); 471#L611-1true assume !(0 == ~E_1~0); 347#L616-1true assume !(0 == ~E_2~0); 353#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 49#L626-1true assume !(0 == ~E_4~0); 304#L631-1true assume !(0 == ~E_5~0); 147#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47#L279true assume 1 == ~m_pc~0; 215#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 371#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 272#L720true assume !(0 != activate_threads_~tmp~1#1); 493#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152#L298true assume !(1 == ~t1_pc~0); 21#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 457#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54#L728true assume !(0 != activate_threads_~tmp___0~0#1); 264#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128#L317true assume 1 == ~t2_pc~0; 240#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 475#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 157#L736true assume !(0 != activate_threads_~tmp___1~0#1); 424#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L336true assume 1 == ~t3_pc~0; 188#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 494#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281#L744true assume !(0 != activate_threads_~tmp___2~0#1); 337#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 403#L355true assume !(1 == ~t4_pc~0); 335#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 106#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 318#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375#L374true assume 1 == ~t5_pc~0; 387#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 390#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 430#L760true assume !(0 != activate_threads_~tmp___4~0#1); 234#L760-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 438#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 499#L649-2true assume !(1 == ~T1_E~0); 39#L654-1true assume !(1 == ~T2_E~0); 269#L659-1true assume !(1 == ~T3_E~0); 156#L664-1true assume !(1 == ~T4_E~0); 35#L669-1true assume !(1 == ~T5_E~0); 320#L674-1true assume !(1 == ~E_1~0); 333#L679-1true assume !(1 == ~E_2~0); 96#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 202#L689-1true assume !(1 == ~E_4~0); 490#L694-1true assume !(1 == ~E_5~0); 201#L699-1true assume { :end_inline_reset_delta_events } true; 480#L900-2true [2024-10-13 17:45:57,218 INFO L747 eck$LassoCheckResult]: Loop: 480#L900-2true assume !false; 508#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 212#L561-1true assume false; 75#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 363#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 425#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 319#L586-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 218#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 109#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 229#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 377#L606-3true assume !(0 == ~T5_E~0); 261#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 265#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 43#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L626-3true assume 0 == ~E_4~0;~E_4~0 := 1; 509#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 23#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 435#L279-18true assume !(1 == ~m_pc~0); 164#L279-20true is_master_triggered_~__retres1~0#1 := 0; 222#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 395#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 349#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233#L298-18true assume !(1 == ~t1_pc~0); 8#L298-20true is_transmit1_triggered_~__retres1~1#1 := 0; 113#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 422#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 450#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 208#L317-18true assume !(1 == ~t2_pc~0); 228#L317-20true is_transmit2_triggered_~__retres1~2#1 := 0; 242#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 356#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 352#L336-18true assume 1 == ~t3_pc~0; 323#L337-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 398#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 177#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 291#L355-18true assume 1 == ~t4_pc~0; 414#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 421#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336#L374-18true assume !(1 == ~t5_pc~0); 294#L374-20true is_transmit5_triggered_~__retres1~5#1 := 0; 173#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133#is_transmit5_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 452#L760-18true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 275#L760-20true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 462#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 187#L649-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 170#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 83#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 456#L664-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 24#L669-3true assume !(1 == ~T5_E~0); 484#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 19#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 183#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 2#L689-3true assume 1 == ~E_4~0;~E_4~0 := 2; 137#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 17#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 419#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 483#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 217#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 200#L919true assume !(0 == start_simulation_~tmp~3#1); 492#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 301#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 380#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 193#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 355#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 372#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 332#L932true assume !(0 != start_simulation_~tmp___0~1#1); 480#L900-2true [2024-10-13 17:45:57,224 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:57,224 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2024-10-13 17:45:57,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:57,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477207452] [2024-10-13 17:45:57,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:57,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:57,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:57,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:57,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:57,451 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477207452] [2024-10-13 17:45:57,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477207452] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:57,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:57,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:57,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794596096] [2024-10-13 17:45:57,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:57,457 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:57,457 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:57,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1472852014, now seen corresponding path program 1 times [2024-10-13 17:45:57,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:57,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961236558] [2024-10-13 17:45:57,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:57,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:57,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:57,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:57,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:57,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961236558] [2024-10-13 17:45:57,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961236558] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:57,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:57,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:57,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812229804] [2024-10-13 17:45:57,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:57,500 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:57,501 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:57,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:57,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:57,527 INFO L87 Difference]: Start difference. First operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:57,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:57,573 INFO L93 Difference]: Finished difference Result 510 states and 758 transitions. [2024-10-13 17:45:57,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 510 states and 758 transitions. [2024-10-13 17:45:57,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:57,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 510 states to 504 states and 752 transitions. [2024-10-13 17:45:57,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-10-13 17:45:57,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-10-13 17:45:57,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 752 transitions. [2024-10-13 17:45:57,591 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:57,591 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 752 transitions. [2024-10-13 17:45:57,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 752 transitions. [2024-10-13 17:45:57,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-10-13 17:45:57,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.492063492063492) internal successors, (752), 503 states have internal predecessors, (752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:57,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 752 transitions. [2024-10-13 17:45:57,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 752 transitions. [2024-10-13 17:45:57,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:57,640 INFO L425 stractBuchiCegarLoop]: Abstraction has 504 states and 752 transitions. [2024-10-13 17:45:57,640 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-13 17:45:57,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 752 transitions. [2024-10-13 17:45:57,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:57,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:57,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:57,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:57,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:57,646 INFO L745 eck$LassoCheckResult]: Stem: 1302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1408#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1409#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1426#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1427#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1237#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1238#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1515#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1516#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1482#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1206#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1207#L586-2 assume !(0 == ~T1_E~0); 1258#L591-1 assume !(0 == ~T2_E~0); 1372#L596-1 assume !(0 == ~T3_E~0); 1373#L601-1 assume !(0 == ~T4_E~0); 1414#L606-1 assume !(0 == ~T5_E~0); 1415#L611-1 assume !(0 == ~E_1~0); 1490#L616-1 assume !(0 == ~E_2~0); 1491#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1133#L626-1 assume !(0 == ~E_4~0); 1134#L631-1 assume !(0 == ~E_5~0); 1297#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1128#L279 assume 1 == ~m_pc~0; 1129#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1378#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1272#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1273#L720 assume !(0 != activate_threads_~tmp~1#1); 1437#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1304#L298 assume !(1 == ~t1_pc~0); 1075#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1076#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1101#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1102#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1142#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1264#L317 assume 1 == ~t2_pc~0; 1265#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1406#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1413#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1313#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1314#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1479#L336 assume 1 == ~t3_pc~0; 1351#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1352#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1049#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1445#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1486#L355 assume !(1 == ~t4_pc~0); 1369#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1224#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1172#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1173#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1152#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1153#L374 assume 1 == ~t5_pc~0; 1508#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1288#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1279#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1397#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1398#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1527#L649-2 assume !(1 == ~T1_E~0); 1114#L654-1 assume !(1 == ~T2_E~0); 1115#L659-1 assume !(1 == ~T3_E~0); 1312#L664-1 assume !(1 == ~T4_E~0); 1106#L669-1 assume !(1 == ~T5_E~0); 1107#L674-1 assume !(1 == ~E_1~0); 1471#L679-1 assume !(1 == ~E_2~0); 1211#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1212#L689-1 assume !(1 == ~E_4~0); 1365#L694-1 assume !(1 == ~E_5~0); 1363#L699-1 assume { :end_inline_reset_delta_events } true; 1364#L900-2 [2024-10-13 17:45:57,648 INFO L747 eck$LassoCheckResult]: Loop: 1364#L900-2 assume !false; 1533#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1283#L561-1 assume !false; 1339#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1331#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1077#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1078#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1200#L486 assume !(0 != eval_~tmp~0#1); 1179#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1180#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1502#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1470#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1380#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1228#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1229#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1393#L606-3 assume !(0 == ~T5_E~0); 1429#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1430#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1122#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1073#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1074#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1079#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1080#L279-18 assume 1 == ~m_pc~0; 1187#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1188#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1317#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1318#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1492#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1396#L298-18 assume !(1 == ~t1_pc~0); 1046#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1047#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1236#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1254#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1255#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1374#L317-18 assume 1 == ~t2_pc~0; 1289#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1290#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1404#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1239#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1240#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1495#L336-18 assume 1 == ~t3_pc~0; 1475#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1476#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1340#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1181#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1182#L355-18 assume !(1 == ~t4_pc~0); 1443#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1444#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1345#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1346#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1274#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1275#L374-18 assume !(1 == ~t5_pc~0); 1457#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 1336#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1276#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1277#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1438#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1439#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1350#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1330#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1191#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1192#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1083#L669-3 assume !(1 == ~T5_E~0); 1084#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1071#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1072#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1031#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1032#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1066#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1067#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1069#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1379#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1362#L919 assume !(0 == start_simulation_~tmp~3#1); 1082#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1461#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1060#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1099#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1358#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1496#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1484#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1364#L900-2 [2024-10-13 17:45:57,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:57,649 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2024-10-13 17:45:57,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:57,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994384370] [2024-10-13 17:45:57,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:57,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:57,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:57,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:57,710 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:57,710 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994384370] [2024-10-13 17:45:57,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994384370] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:57,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:57,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:57,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830171042] [2024-10-13 17:45:57,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:57,712 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:57,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:57,712 INFO L85 PathProgramCache]: Analyzing trace with hash 1177747720, now seen corresponding path program 1 times [2024-10-13 17:45:57,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:57,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171691348] [2024-10-13 17:45:57,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:57,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:57,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:57,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:57,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:57,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171691348] [2024-10-13 17:45:57,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171691348] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:57,827 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:57,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:57,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404730061] [2024-10-13 17:45:57,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:57,828 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:57,828 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:57,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:57,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:57,829 INFO L87 Difference]: Start difference. First operand 504 states and 752 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:57,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:57,846 INFO L93 Difference]: Finished difference Result 504 states and 751 transitions. [2024-10-13 17:45:57,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 751 transitions. [2024-10-13 17:45:57,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:57,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 751 transitions. [2024-10-13 17:45:57,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-10-13 17:45:57,852 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-10-13 17:45:57,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 751 transitions. [2024-10-13 17:45:57,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:57,853 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 751 transitions. [2024-10-13 17:45:57,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 751 transitions. [2024-10-13 17:45:57,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-10-13 17:45:57,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4900793650793651) internal successors, (751), 503 states have internal predecessors, (751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:57,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 751 transitions. [2024-10-13 17:45:57,866 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 751 transitions. [2024-10-13 17:45:57,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:57,867 INFO L425 stractBuchiCegarLoop]: Abstraction has 504 states and 751 transitions. [2024-10-13 17:45:57,867 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-13 17:45:57,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 751 transitions. [2024-10-13 17:45:57,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:57,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:57,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:57,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:57,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:57,872 INFO L745 eck$LassoCheckResult]: Stem: 2319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2425#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2426#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2443#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 2444#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2254#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2255#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2532#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2533#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2499#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2223#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 2224#L586-2 assume !(0 == ~T1_E~0); 2275#L591-1 assume !(0 == ~T2_E~0); 2389#L596-1 assume !(0 == ~T3_E~0); 2390#L601-1 assume !(0 == ~T4_E~0); 2431#L606-1 assume !(0 == ~T5_E~0); 2432#L611-1 assume !(0 == ~E_1~0); 2507#L616-1 assume !(0 == ~E_2~0); 2508#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2150#L626-1 assume !(0 == ~E_4~0); 2151#L631-1 assume !(0 == ~E_5~0); 2314#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2145#L279 assume 1 == ~m_pc~0; 2146#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2395#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2289#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2290#L720 assume !(0 != activate_threads_~tmp~1#1); 2454#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2321#L298 assume !(1 == ~t1_pc~0); 2092#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2093#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2118#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2119#L728 assume !(0 != activate_threads_~tmp___0~0#1); 2159#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2281#L317 assume 1 == ~t2_pc~0; 2282#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2423#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2430#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2330#L736 assume !(0 != activate_threads_~tmp___1~0#1); 2331#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2496#L336 assume 1 == ~t3_pc~0; 2368#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2369#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2065#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2066#L744 assume !(0 != activate_threads_~tmp___2~0#1); 2462#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2503#L355 assume !(1 == ~t4_pc~0); 2386#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2241#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2189#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2190#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2169#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2170#L374 assume 1 == ~t5_pc~0; 2525#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2305#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2295#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2296#L760 assume !(0 != activate_threads_~tmp___4~0#1); 2414#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2415#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 2544#L649-2 assume !(1 == ~T1_E~0); 2131#L654-1 assume !(1 == ~T2_E~0); 2132#L659-1 assume !(1 == ~T3_E~0); 2329#L664-1 assume !(1 == ~T4_E~0); 2123#L669-1 assume !(1 == ~T5_E~0); 2124#L674-1 assume !(1 == ~E_1~0); 2488#L679-1 assume !(1 == ~E_2~0); 2228#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2229#L689-1 assume !(1 == ~E_4~0); 2382#L694-1 assume !(1 == ~E_5~0); 2380#L699-1 assume { :end_inline_reset_delta_events } true; 2381#L900-2 [2024-10-13 17:45:57,876 INFO L747 eck$LassoCheckResult]: Loop: 2381#L900-2 assume !false; 2550#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2300#L561-1 assume !false; 2356#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2348#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2094#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2095#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2217#L486 assume !(0 != eval_~tmp~0#1); 2196#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2197#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2519#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2487#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2397#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2245#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2246#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2410#L606-3 assume !(0 == ~T5_E~0); 2446#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2447#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2139#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2090#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2091#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2096#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2097#L279-18 assume 1 == ~m_pc~0; 2204#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2205#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2334#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2335#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2509#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2413#L298-18 assume 1 == ~t1_pc~0; 2070#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2064#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2253#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2271#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2272#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2391#L317-18 assume 1 == ~t2_pc~0; 2306#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2307#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2421#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2256#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2257#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2512#L336-18 assume 1 == ~t3_pc~0; 2492#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2493#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2448#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2357#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2198#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2199#L355-18 assume 1 == ~t4_pc~0; 2472#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2461#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2362#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2363#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2291#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2292#L374-18 assume 1 == ~t5_pc~0; 2502#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2353#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2293#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2294#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2455#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2456#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2367#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2347#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2208#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2209#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2098#L669-3 assume !(1 == ~T5_E~0); 2099#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2088#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2089#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2048#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2049#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2083#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2084#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2086#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2396#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2379#L919 assume !(0 == start_simulation_~tmp~3#1); 2101#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2478#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2077#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2115#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2116#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2375#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2513#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2501#L932 assume !(0 != start_simulation_~tmp___0~1#1); 2381#L900-2 [2024-10-13 17:45:57,877 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:57,877 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2024-10-13 17:45:57,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:57,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214532021] [2024-10-13 17:45:57,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:57,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:57,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:57,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:57,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:57,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214532021] [2024-10-13 17:45:57,924 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [214532021] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:57,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:57,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:57,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523994499] [2024-10-13 17:45:57,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:57,924 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:57,925 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:57,925 INFO L85 PathProgramCache]: Analyzing trace with hash -1398059989, now seen corresponding path program 1 times [2024-10-13 17:45:57,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:57,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590253286] [2024-10-13 17:45:57,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:57,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:57,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590253286] [2024-10-13 17:45:58,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1590253286] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:58,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297667006] [2024-10-13 17:45:58,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,023 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:58,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:58,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:58,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:58,025 INFO L87 Difference]: Start difference. First operand 504 states and 751 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:58,035 INFO L93 Difference]: Finished difference Result 504 states and 750 transitions. [2024-10-13 17:45:58,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 750 transitions. [2024-10-13 17:45:58,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:58,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 750 transitions. [2024-10-13 17:45:58,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-10-13 17:45:58,041 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-10-13 17:45:58,041 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 750 transitions. [2024-10-13 17:45:58,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:58,042 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 750 transitions. [2024-10-13 17:45:58,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 750 transitions. [2024-10-13 17:45:58,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-10-13 17:45:58,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4880952380952381) internal successors, (750), 503 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 750 transitions. [2024-10-13 17:45:58,052 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 750 transitions. [2024-10-13 17:45:58,053 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:58,053 INFO L425 stractBuchiCegarLoop]: Abstraction has 504 states and 750 transitions. [2024-10-13 17:45:58,053 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-13 17:45:58,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 750 transitions. [2024-10-13 17:45:58,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:58,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:58,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:58,056 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,057 INFO L745 eck$LassoCheckResult]: Stem: 3336#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3337#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3442#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3443#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3460#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3461#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3271#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3272#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3549#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3550#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3516#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3240#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3241#L586-2 assume !(0 == ~T1_E~0); 3292#L591-1 assume !(0 == ~T2_E~0); 3406#L596-1 assume !(0 == ~T3_E~0); 3407#L601-1 assume !(0 == ~T4_E~0); 3448#L606-1 assume !(0 == ~T5_E~0); 3449#L611-1 assume !(0 == ~E_1~0); 3524#L616-1 assume !(0 == ~E_2~0); 3525#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3167#L626-1 assume !(0 == ~E_4~0); 3168#L631-1 assume !(0 == ~E_5~0); 3331#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3162#L279 assume 1 == ~m_pc~0; 3163#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3412#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3306#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3307#L720 assume !(0 != activate_threads_~tmp~1#1); 3471#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3338#L298 assume !(1 == ~t1_pc~0); 3109#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3110#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3136#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3176#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3298#L317 assume 1 == ~t2_pc~0; 3299#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3440#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3447#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3347#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3348#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3513#L336 assume 1 == ~t3_pc~0; 3385#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3386#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3082#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3083#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3479#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3520#L355 assume !(1 == ~t4_pc~0); 3403#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3258#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3206#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3207#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3186#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3187#L374 assume 1 == ~t5_pc~0; 3542#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3322#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3312#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3313#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3431#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3432#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3561#L649-2 assume !(1 == ~T1_E~0); 3148#L654-1 assume !(1 == ~T2_E~0); 3149#L659-1 assume !(1 == ~T3_E~0); 3346#L664-1 assume !(1 == ~T4_E~0); 3140#L669-1 assume !(1 == ~T5_E~0); 3141#L674-1 assume !(1 == ~E_1~0); 3505#L679-1 assume !(1 == ~E_2~0); 3245#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3246#L689-1 assume !(1 == ~E_4~0); 3399#L694-1 assume !(1 == ~E_5~0); 3397#L699-1 assume { :end_inline_reset_delta_events } true; 3398#L900-2 [2024-10-13 17:45:58,059 INFO L747 eck$LassoCheckResult]: Loop: 3398#L900-2 assume !false; 3567#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3317#L561-1 assume !false; 3373#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3365#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3111#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3112#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3234#L486 assume !(0 != eval_~tmp~0#1); 3213#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3214#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3536#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3504#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3414#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3262#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3263#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3427#L606-3 assume !(0 == ~T5_E~0); 3463#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3464#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3156#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3107#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3108#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3113#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3114#L279-18 assume 1 == ~m_pc~0; 3221#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3222#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3351#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3352#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3526#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3430#L298-18 assume !(1 == ~t1_pc~0); 3080#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3081#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3270#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3288#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3289#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3408#L317-18 assume 1 == ~t2_pc~0; 3323#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3324#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3438#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3273#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3274#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3529#L336-18 assume 1 == ~t3_pc~0; 3509#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3510#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3465#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3374#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3215#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3216#L355-18 assume 1 == ~t4_pc~0; 3489#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3478#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3379#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3380#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3308#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3309#L374-18 assume !(1 == ~t5_pc~0); 3491#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 3370#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3310#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3311#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3472#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3473#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3384#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3364#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3225#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3226#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3115#L669-3 assume !(1 == ~T5_E~0); 3116#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3105#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3106#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3065#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3066#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3100#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3101#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3103#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3413#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3396#L919 assume !(0 == start_simulation_~tmp~3#1); 3118#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3495#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3094#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3133#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3392#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3530#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3518#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3398#L900-2 [2024-10-13 17:45:58,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,060 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2024-10-13 17:45:58,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902020213] [2024-10-13 17:45:58,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902020213] [2024-10-13 17:45:58,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902020213] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:58,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954231842] [2024-10-13 17:45:58,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,104 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:58,104 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1352402967, now seen corresponding path program 1 times [2024-10-13 17:45:58,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573639564] [2024-10-13 17:45:58,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573639564] [2024-10-13 17:45:58,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573639564] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,163 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:58,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703429555] [2024-10-13 17:45:58,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,164 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:58,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:58,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:58,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:58,164 INFO L87 Difference]: Start difference. First operand 504 states and 750 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:58,174 INFO L93 Difference]: Finished difference Result 504 states and 749 transitions. [2024-10-13 17:45:58,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 749 transitions. [2024-10-13 17:45:58,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:58,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 749 transitions. [2024-10-13 17:45:58,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-10-13 17:45:58,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-10-13 17:45:58,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 749 transitions. [2024-10-13 17:45:58,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:58,182 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 749 transitions. [2024-10-13 17:45:58,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 749 transitions. [2024-10-13 17:45:58,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-10-13 17:45:58,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4861111111111112) internal successors, (749), 503 states have internal predecessors, (749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 749 transitions. [2024-10-13 17:45:58,191 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 749 transitions. [2024-10-13 17:45:58,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:58,192 INFO L425 stractBuchiCegarLoop]: Abstraction has 504 states and 749 transitions. [2024-10-13 17:45:58,193 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-13 17:45:58,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 749 transitions. [2024-10-13 17:45:58,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:58,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:58,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:58,198 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,200 INFO L745 eck$LassoCheckResult]: Stem: 4353#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4477#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 4478#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4288#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4289#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4566#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4567#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4533#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4257#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 4258#L586-2 assume !(0 == ~T1_E~0); 4309#L591-1 assume !(0 == ~T2_E~0); 4423#L596-1 assume !(0 == ~T3_E~0); 4424#L601-1 assume !(0 == ~T4_E~0); 4465#L606-1 assume !(0 == ~T5_E~0); 4466#L611-1 assume !(0 == ~E_1~0); 4541#L616-1 assume !(0 == ~E_2~0); 4542#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4184#L626-1 assume !(0 == ~E_4~0); 4185#L631-1 assume !(0 == ~E_5~0); 4348#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4179#L279 assume 1 == ~m_pc~0; 4180#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4429#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4323#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4324#L720 assume !(0 != activate_threads_~tmp~1#1); 4488#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4355#L298 assume !(1 == ~t1_pc~0); 4126#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4127#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4152#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4153#L728 assume !(0 != activate_threads_~tmp___0~0#1); 4193#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4315#L317 assume 1 == ~t2_pc~0; 4316#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4457#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4464#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4364#L736 assume !(0 != activate_threads_~tmp___1~0#1); 4365#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4530#L336 assume 1 == ~t3_pc~0; 4402#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4403#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4099#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4100#L744 assume !(0 != activate_threads_~tmp___2~0#1); 4496#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4537#L355 assume !(1 == ~t4_pc~0); 4420#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4275#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4223#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4224#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4203#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4204#L374 assume 1 == ~t5_pc~0; 4559#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4339#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4329#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4330#L760 assume !(0 != activate_threads_~tmp___4~0#1); 4448#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4449#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 4578#L649-2 assume !(1 == ~T1_E~0); 4165#L654-1 assume !(1 == ~T2_E~0); 4166#L659-1 assume !(1 == ~T3_E~0); 4363#L664-1 assume !(1 == ~T4_E~0); 4157#L669-1 assume !(1 == ~T5_E~0); 4158#L674-1 assume !(1 == ~E_1~0); 4522#L679-1 assume !(1 == ~E_2~0); 4262#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4263#L689-1 assume !(1 == ~E_4~0); 4416#L694-1 assume !(1 == ~E_5~0); 4414#L699-1 assume { :end_inline_reset_delta_events } true; 4415#L900-2 [2024-10-13 17:45:58,200 INFO L747 eck$LassoCheckResult]: Loop: 4415#L900-2 assume !false; 4584#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4334#L561-1 assume !false; 4390#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4382#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4128#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4129#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4251#L486 assume !(0 != eval_~tmp~0#1); 4230#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4553#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4521#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4431#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4279#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4280#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4444#L606-3 assume !(0 == ~T5_E~0); 4480#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4481#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4173#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4124#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4125#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4130#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4131#L279-18 assume !(1 == ~m_pc~0); 4240#L279-20 is_master_triggered_~__retres1~0#1 := 0; 4239#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4368#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4369#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4543#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4447#L298-18 assume !(1 == ~t1_pc~0); 4097#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4098#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4287#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4305#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4306#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4425#L317-18 assume 1 == ~t2_pc~0; 4340#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4341#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4455#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4290#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4291#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4546#L336-18 assume !(1 == ~t3_pc~0); 4528#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4527#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4482#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4391#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4232#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4233#L355-18 assume 1 == ~t4_pc~0; 4506#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4495#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4396#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4397#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4325#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4326#L374-18 assume 1 == ~t5_pc~0; 4536#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4387#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4327#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4328#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4489#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4490#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4401#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4381#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4242#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4243#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4132#L669-3 assume !(1 == ~T5_E~0); 4133#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4122#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4123#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4082#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4083#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4117#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4118#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4120#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4430#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4413#L919 assume !(0 == start_simulation_~tmp~3#1); 4135#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4512#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4111#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4149#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4150#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4409#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4547#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4535#L932 assume !(0 != start_simulation_~tmp___0~1#1); 4415#L900-2 [2024-10-13 17:45:58,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,201 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2024-10-13 17:45:58,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664043828] [2024-10-13 17:45:58,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,231 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664043828] [2024-10-13 17:45:58,231 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664043828] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,231 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,231 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:58,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332627711] [2024-10-13 17:45:58,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,232 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:58,232 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1062290040, now seen corresponding path program 1 times [2024-10-13 17:45:58,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319229500] [2024-10-13 17:45:58,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,287 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319229500] [2024-10-13 17:45:58,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319229500] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,287 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,288 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:58,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241899698] [2024-10-13 17:45:58,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,288 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:58,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:58,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:58,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:58,289 INFO L87 Difference]: Start difference. First operand 504 states and 749 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:58,299 INFO L93 Difference]: Finished difference Result 504 states and 748 transitions. [2024-10-13 17:45:58,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 748 transitions. [2024-10-13 17:45:58,302 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:58,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 748 transitions. [2024-10-13 17:45:58,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-10-13 17:45:58,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-10-13 17:45:58,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 748 transitions. [2024-10-13 17:45:58,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:58,305 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 748 transitions. [2024-10-13 17:45:58,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 748 transitions. [2024-10-13 17:45:58,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-10-13 17:45:58,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4841269841269842) internal successors, (748), 503 states have internal predecessors, (748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 748 transitions. [2024-10-13 17:45:58,311 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 748 transitions. [2024-10-13 17:45:58,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:58,313 INFO L425 stractBuchiCegarLoop]: Abstraction has 504 states and 748 transitions. [2024-10-13 17:45:58,314 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-13 17:45:58,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 748 transitions. [2024-10-13 17:45:58,316 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-10-13 17:45:58,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:58,316 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:58,317 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,318 INFO L745 eck$LassoCheckResult]: Stem: 5370#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5371#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5476#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5477#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5494#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5495#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5305#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5306#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5583#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5584#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5550#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5274#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5275#L586-2 assume !(0 == ~T1_E~0); 5326#L591-1 assume !(0 == ~T2_E~0); 5440#L596-1 assume !(0 == ~T3_E~0); 5441#L601-1 assume !(0 == ~T4_E~0); 5482#L606-1 assume !(0 == ~T5_E~0); 5483#L611-1 assume !(0 == ~E_1~0); 5558#L616-1 assume !(0 == ~E_2~0); 5559#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5201#L626-1 assume !(0 == ~E_4~0); 5202#L631-1 assume !(0 == ~E_5~0); 5365#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5196#L279 assume 1 == ~m_pc~0; 5197#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5446#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5340#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5341#L720 assume !(0 != activate_threads_~tmp~1#1); 5505#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5372#L298 assume !(1 == ~t1_pc~0); 5143#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5144#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5169#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5170#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5210#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5332#L317 assume 1 == ~t2_pc~0; 5333#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5474#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5381#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5382#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5547#L336 assume 1 == ~t3_pc~0; 5419#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5420#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5117#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5513#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5554#L355 assume !(1 == ~t4_pc~0); 5437#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5292#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5240#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5241#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5220#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5221#L374 assume 1 == ~t5_pc~0; 5576#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5356#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5347#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5465#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5466#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5595#L649-2 assume !(1 == ~T1_E~0); 5182#L654-1 assume !(1 == ~T2_E~0); 5183#L659-1 assume !(1 == ~T3_E~0); 5380#L664-1 assume !(1 == ~T4_E~0); 5174#L669-1 assume !(1 == ~T5_E~0); 5175#L674-1 assume !(1 == ~E_1~0); 5539#L679-1 assume !(1 == ~E_2~0); 5279#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5280#L689-1 assume !(1 == ~E_4~0); 5433#L694-1 assume !(1 == ~E_5~0); 5431#L699-1 assume { :end_inline_reset_delta_events } true; 5432#L900-2 [2024-10-13 17:45:58,318 INFO L747 eck$LassoCheckResult]: Loop: 5432#L900-2 assume !false; 5601#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5351#L561-1 assume !false; 5407#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5399#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5145#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5146#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5268#L486 assume !(0 != eval_~tmp~0#1); 5247#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5248#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5570#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5538#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5448#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5296#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5297#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5461#L606-3 assume !(0 == ~T5_E~0); 5497#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5498#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5190#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5141#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5142#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5147#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5148#L279-18 assume 1 == ~m_pc~0; 5255#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5256#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5385#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5386#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5560#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5464#L298-18 assume 1 == ~t1_pc~0; 5121#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5115#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5304#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5322#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5323#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5442#L317-18 assume 1 == ~t2_pc~0; 5357#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5358#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5472#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5307#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5308#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5563#L336-18 assume 1 == ~t3_pc~0; 5543#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5544#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5499#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5408#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5249#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5250#L355-18 assume 1 == ~t4_pc~0; 5523#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5512#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5413#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5414#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5342#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5343#L374-18 assume 1 == ~t5_pc~0; 5553#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5404#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5344#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5345#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5506#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5507#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5418#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5398#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5259#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5260#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5149#L669-3 assume !(1 == ~T5_E~0); 5150#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5139#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5140#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5099#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5100#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5134#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5135#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5137#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5447#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5430#L919 assume !(0 == start_simulation_~tmp~3#1); 5152#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5529#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5128#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5166#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5167#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5426#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5564#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5552#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5432#L900-2 [2024-10-13 17:45:58,319 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,319 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2024-10-13 17:45:58,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,319 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030421813] [2024-10-13 17:45:58,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2030421813] [2024-10-13 17:45:58,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2030421813] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:58,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000294042] [2024-10-13 17:45:58,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,355 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:58,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,355 INFO L85 PathProgramCache]: Analyzing trace with hash -1398059989, now seen corresponding path program 2 times [2024-10-13 17:45:58,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144147964] [2024-10-13 17:45:58,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144147964] [2024-10-13 17:45:58,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144147964] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:58,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486372399] [2024-10-13 17:45:58,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,398 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:58,399 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:58,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:58,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:58,399 INFO L87 Difference]: Start difference. First operand 504 states and 748 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:58,457 INFO L93 Difference]: Finished difference Result 887 states and 1304 transitions. [2024-10-13 17:45:58,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 887 states and 1304 transitions. [2024-10-13 17:45:58,460 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 810 [2024-10-13 17:45:58,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 887 states to 887 states and 1304 transitions. [2024-10-13 17:45:58,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 887 [2024-10-13 17:45:58,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 887 [2024-10-13 17:45:58,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 887 states and 1304 transitions. [2024-10-13 17:45:58,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:58,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 887 states and 1304 transitions. [2024-10-13 17:45:58,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 887 states and 1304 transitions. [2024-10-13 17:45:58,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 887 to 887. [2024-10-13 17:45:58,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 887 states, 887 states have (on average 1.4701240135287486) internal successors, (1304), 886 states have internal predecessors, (1304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 887 states to 887 states and 1304 transitions. [2024-10-13 17:45:58,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 887 states and 1304 transitions. [2024-10-13 17:45:58,479 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:58,479 INFO L425 stractBuchiCegarLoop]: Abstraction has 887 states and 1304 transitions. [2024-10-13 17:45:58,480 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-13 17:45:58,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 887 states and 1304 transitions. [2024-10-13 17:45:58,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 810 [2024-10-13 17:45:58,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:58,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:58,484 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,487 INFO L745 eck$LassoCheckResult]: Stem: 6769#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6770#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6878#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6896#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 6897#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6704#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6705#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6987#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6988#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6954#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6676#L586 assume !(0 == ~M_E~0); 6677#L586-2 assume !(0 == ~T1_E~0); 6725#L591-1 assume !(0 == ~T2_E~0); 6842#L596-1 assume !(0 == ~T3_E~0); 6843#L601-1 assume !(0 == ~T4_E~0); 6884#L606-1 assume !(0 == ~T5_E~0); 6885#L611-1 assume !(0 == ~E_1~0); 6961#L616-1 assume !(0 == ~E_2~0); 6962#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6601#L626-1 assume !(0 == ~E_4~0); 6602#L631-1 assume !(0 == ~E_5~0); 6764#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6596#L279 assume !(1 == ~m_pc~0); 6598#L279-2 is_master_triggered_~__retres1~0#1 := 0; 6908#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6739#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6740#L720 assume !(0 != activate_threads_~tmp~1#1); 6907#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6771#L298 assume !(1 == ~t1_pc~0); 6545#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6546#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6573#L728 assume !(0 != activate_threads_~tmp___0~0#1); 6610#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6731#L317 assume 1 == ~t2_pc~0; 6732#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6877#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6883#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6781#L736 assume !(0 != activate_threads_~tmp___1~0#1); 6782#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6951#L336 assume 1 == ~t3_pc~0; 6820#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6821#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6516#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6517#L744 assume !(0 != activate_threads_~tmp___2~0#1); 6916#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6958#L355 assume !(1 == ~t4_pc~0); 6841#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6693#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6640#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6641#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6623#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6624#L374 assume 1 == ~t5_pc~0; 6980#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6758#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6745#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6746#L760 assume !(0 != activate_threads_~tmp___4~0#1); 6866#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6867#L649 assume !(1 == ~M_E~0); 7000#L649-2 assume !(1 == ~T1_E~0); 6582#L654-1 assume !(1 == ~T2_E~0); 6583#L659-1 assume !(1 == ~T3_E~0); 6779#L664-1 assume !(1 == ~T4_E~0); 6574#L669-1 assume !(1 == ~T5_E~0); 6575#L674-1 assume !(1 == ~E_1~0); 6942#L679-1 assume !(1 == ~E_2~0); 6678#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6679#L689-1 assume !(1 == ~E_4~0); 6836#L694-1 assume !(1 == ~E_5~0); 6833#L699-1 assume { :end_inline_reset_delta_events } true; 6834#L900-2 [2024-10-13 17:45:58,488 INFO L747 eck$LassoCheckResult]: Loop: 6834#L900-2 assume !false; 7007#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6750#L561-1 assume !false; 6808#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6799#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6543#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6544#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6667#L486 assume !(0 != eval_~tmp~0#1); 6647#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6648#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6974#L586-3 assume !(0 == ~M_E~0); 6941#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6849#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6695#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6696#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6862#L606-3 assume !(0 == ~T5_E~0); 6899#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6900#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6590#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6541#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6542#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6547#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6548#L279-18 assume !(1 == ~m_pc~0); 6656#L279-20 is_master_triggered_~__retres1~0#1 := 0; 6791#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6784#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6785#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6963#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6865#L298-18 assume !(1 == ~t1_pc~0); 6514#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6515#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6703#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6721#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6722#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6844#L317-18 assume 1 == ~t2_pc~0; 6754#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6755#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6873#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6706#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6707#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6966#L336-18 assume 1 == ~t3_pc~0; 6946#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6947#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6901#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6807#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6649#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6650#L355-18 assume !(1 == ~t4_pc~0); 6914#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 6915#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6812#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6813#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6741#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6742#L374-18 assume !(1 == ~t5_pc~0); 6928#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 6804#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6743#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6744#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6909#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6910#L649-3 assume !(1 == ~M_E~0); 6818#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6798#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6658#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6659#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6549#L669-3 assume !(1 == ~T5_E~0); 6550#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6539#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6540#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6499#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6500#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6534#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6535#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6537#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6848#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6832#L919 assume !(0 == start_simulation_~tmp~3#1); 6552#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6932#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6528#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6566#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 6567#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6826#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6967#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6955#L932 assume !(0 != start_simulation_~tmp___0~1#1); 6834#L900-2 [2024-10-13 17:45:58,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,488 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2024-10-13 17:45:58,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929794010] [2024-10-13 17:45:58,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929794010] [2024-10-13 17:45:58,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929794010] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:58,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071280940] [2024-10-13 17:45:58,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,533 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:58,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,533 INFO L85 PathProgramCache]: Analyzing trace with hash -785849181, now seen corresponding path program 1 times [2024-10-13 17:45:58,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319043129] [2024-10-13 17:45:58,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319043129] [2024-10-13 17:45:58,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1319043129] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,588 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:58,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80160736] [2024-10-13 17:45:58,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,589 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:58,589 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:58,589 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:45:58,589 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:45:58,589 INFO L87 Difference]: Start difference. First operand 887 states and 1304 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:58,689 INFO L93 Difference]: Finished difference Result 1620 states and 2381 transitions. [2024-10-13 17:45:58,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1620 states and 2381 transitions. [2024-10-13 17:45:58,695 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1532 [2024-10-13 17:45:58,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1620 states to 1620 states and 2381 transitions. [2024-10-13 17:45:58,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1620 [2024-10-13 17:45:58,701 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1620 [2024-10-13 17:45:58,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1620 states and 2381 transitions. [2024-10-13 17:45:58,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:58,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1620 states and 2381 transitions. [2024-10-13 17:45:58,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states and 2381 transitions. [2024-10-13 17:45:58,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 1618. [2024-10-13 17:45:58,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1618 states, 1618 states have (on average 1.4703337453646477) internal successors, (2379), 1617 states have internal predecessors, (2379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2379 transitions. [2024-10-13 17:45:58,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1618 states and 2379 transitions. [2024-10-13 17:45:58,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:45:58,722 INFO L425 stractBuchiCegarLoop]: Abstraction has 1618 states and 2379 transitions. [2024-10-13 17:45:58,723 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-13 17:45:58,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1618 states and 2379 transitions. [2024-10-13 17:45:58,727 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1532 [2024-10-13 17:45:58,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:58,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:58,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,728 INFO L745 eck$LassoCheckResult]: Stem: 9293#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9404#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9405#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9422#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 9423#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9227#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9228#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9529#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9530#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9491#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9197#L586 assume !(0 == ~M_E~0); 9198#L586-2 assume !(0 == ~T1_E~0); 9248#L591-1 assume !(0 == ~T2_E~0); 9367#L596-1 assume !(0 == ~T3_E~0); 9368#L601-1 assume !(0 == ~T4_E~0); 9409#L606-1 assume !(0 == ~T5_E~0); 9410#L611-1 assume !(0 == ~E_1~0); 9499#L616-1 assume !(0 == ~E_2~0); 9500#L621-1 assume !(0 == ~E_3~0); 9121#L626-1 assume !(0 == ~E_4~0); 9122#L631-1 assume !(0 == ~E_5~0); 9288#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9118#L279 assume !(1 == ~m_pc~0); 9120#L279-2 is_master_triggered_~__retres1~0#1 := 0; 9439#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9262#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9263#L720 assume !(0 != activate_threads_~tmp~1#1); 9438#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9295#L298 assume !(1 == ~t1_pc~0); 9064#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9065#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9090#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9091#L728 assume !(0 != activate_threads_~tmp___0~0#1); 9130#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9254#L317 assume 1 == ~t2_pc~0; 9255#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9402#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9408#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9305#L736 assume !(0 != activate_threads_~tmp___1~0#1); 9306#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9484#L336 assume 1 == ~t3_pc~0; 9346#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9347#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9035#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9036#L744 assume !(0 != activate_threads_~tmp___2~0#1); 9447#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9495#L355 assume !(1 == ~t4_pc~0); 9366#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9216#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9160#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9161#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9143#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9144#L374 assume 1 == ~t5_pc~0; 9520#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9282#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9268#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9269#L760 assume !(0 != activate_threads_~tmp___4~0#1); 9391#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9392#L649 assume !(1 == ~M_E~0); 9551#L649-2 assume !(1 == ~T1_E~0); 9100#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9101#L659-1 assume !(1 == ~T3_E~0); 9646#L664-1 assume !(1 == ~T4_E~0); 9645#L669-1 assume !(1 == ~T5_E~0); 9644#L674-1 assume !(1 == ~E_1~0); 9643#L679-1 assume !(1 == ~E_2~0); 9642#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9201#L689-1 assume !(1 == ~E_4~0); 9361#L694-1 assume !(1 == ~E_5~0); 9629#L699-1 assume { :end_inline_reset_delta_events } true; 9621#L900-2 [2024-10-13 17:45:58,729 INFO L747 eck$LassoCheckResult]: Loop: 9621#L900-2 assume !false; 9615#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9611#L561-1 assume !false; 9610#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9608#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9603#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9602#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9600#L486 assume !(0 != eval_~tmp~0#1); 9599#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9598#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9597#L586-3 assume !(0 == ~M_E~0); 9596#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9593#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9594#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10599#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10598#L606-3 assume !(0 == ~T5_E~0); 10597#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10596#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10595#L621-3 assume !(0 == ~E_3~0); 10594#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10593#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10592#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10591#L279-18 assume !(1 == ~m_pc~0); 10589#L279-20 is_master_triggered_~__retres1~0#1 := 0; 10588#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10587#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10586#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10585#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10584#L298-18 assume !(1 == ~t1_pc~0); 10582#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 10581#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10580#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10579#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10578#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10577#L317-18 assume !(1 == ~t2_pc~0); 10576#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 10574#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10573#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10572#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10571#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10570#L336-18 assume !(1 == ~t3_pc~0); 10568#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 10567#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10566#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10565#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10564#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10563#L355-18 assume 1 == ~t4_pc~0; 10561#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10560#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10354#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9828#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9829#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9492#L374-18 assume 1 == ~t5_pc~0; 9493#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9329#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9266#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9267#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9440#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9441#L649-3 assume !(1 == ~M_E~0); 9343#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9323#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9178#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9179#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9070#L669-3 assume !(1 == ~T5_E~0); 9071#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9058#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9059#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9018#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9019#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9053#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9054#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9056#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9373#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9356#L919 assume !(0 == start_simulation_~tmp~3#1); 9069#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9571#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9677#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9668#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9656#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9640#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9628#L932 assume !(0 != start_simulation_~tmp___0~1#1); 9621#L900-2 [2024-10-13 17:45:58,729 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,729 INFO L85 PathProgramCache]: Analyzing trace with hash 1446688901, now seen corresponding path program 1 times [2024-10-13 17:45:58,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122025338] [2024-10-13 17:45:58,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,764 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2122025338] [2024-10-13 17:45:58,766 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2122025338] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,766 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,766 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:58,766 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549982002] [2024-10-13 17:45:58,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,766 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:58,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,767 INFO L85 PathProgramCache]: Analyzing trace with hash 259039073, now seen corresponding path program 1 times [2024-10-13 17:45:58,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11556984] [2024-10-13 17:45:58,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11556984] [2024-10-13 17:45:58,810 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11556984] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,810 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,810 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:58,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993274385] [2024-10-13 17:45:58,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,811 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:58,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:58,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:58,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:58,811 INFO L87 Difference]: Start difference. First operand 1618 states and 2379 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:58,857 INFO L93 Difference]: Finished difference Result 3035 states and 4428 transitions. [2024-10-13 17:45:58,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3035 states and 4428 transitions. [2024-10-13 17:45:58,869 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2942 [2024-10-13 17:45:58,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3035 states to 3035 states and 4428 transitions. [2024-10-13 17:45:58,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3035 [2024-10-13 17:45:58,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3035 [2024-10-13 17:45:58,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3035 states and 4428 transitions. [2024-10-13 17:45:58,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:58,884 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3035 states and 4428 transitions. [2024-10-13 17:45:58,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3035 states and 4428 transitions. [2024-10-13 17:45:58,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3035 to 3027. [2024-10-13 17:45:58,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3027 states, 3027 states have (on average 1.4601916088536504) internal successors, (4420), 3026 states have internal predecessors, (4420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:58,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3027 states to 3027 states and 4420 transitions. [2024-10-13 17:45:58,923 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3027 states and 4420 transitions. [2024-10-13 17:45:58,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:58,925 INFO L425 stractBuchiCegarLoop]: Abstraction has 3027 states and 4420 transitions. [2024-10-13 17:45:58,925 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-13 17:45:58,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3027 states and 4420 transitions. [2024-10-13 17:45:58,934 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2934 [2024-10-13 17:45:58,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:58,934 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:58,935 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,935 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:58,935 INFO L745 eck$LassoCheckResult]: Stem: 13959#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 13960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 14077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14099#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 14100#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13893#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13894#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14225#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14226#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14177#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13863#L586 assume !(0 == ~M_E~0); 13864#L586-2 assume !(0 == ~T1_E~0); 13915#L591-1 assume !(0 == ~T2_E~0); 14038#L596-1 assume !(0 == ~T3_E~0); 14039#L601-1 assume !(0 == ~T4_E~0); 14087#L606-1 assume !(0 == ~T5_E~0); 14088#L611-1 assume !(0 == ~E_1~0); 14188#L616-1 assume !(0 == ~E_2~0); 14189#L621-1 assume !(0 == ~E_3~0); 13782#L626-1 assume !(0 == ~E_4~0); 13783#L631-1 assume !(0 == ~E_5~0); 13954#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13779#L279 assume !(1 == ~m_pc~0); 13781#L279-2 is_master_triggered_~__retres1~0#1 := 0; 14116#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13928#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13929#L720 assume !(0 != activate_threads_~tmp~1#1); 14115#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13961#L298 assume !(1 == ~t1_pc~0); 13726#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13727#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13752#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13753#L728 assume !(0 != activate_threads_~tmp___0~0#1); 13792#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13921#L317 assume !(1 == ~t2_pc~0); 13922#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14135#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14083#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13973#L736 assume !(0 != activate_threads_~tmp___1~0#1); 13974#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14171#L336 assume 1 == ~t3_pc~0; 14014#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14015#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13697#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13698#L744 assume !(0 != activate_threads_~tmp___2~0#1); 14124#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14183#L355 assume !(1 == ~t4_pc~0); 14037#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13881#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13824#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13825#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13806#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13807#L374 assume 1 == ~t5_pc~0; 14216#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13947#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13935#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13936#L760 assume !(0 != activate_threads_~tmp___4~0#1); 14067#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14068#L649 assume !(1 == ~M_E~0); 14245#L649-2 assume !(1 == ~T1_E~0); 13762#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13763#L659-1 assume !(1 == ~T3_E~0); 13969#L664-1 assume !(1 == ~T4_E~0); 13970#L669-1 assume !(1 == ~T5_E~0); 14158#L674-1 assume !(1 == ~E_1~0); 14159#L679-1 assume !(1 == ~E_2~0); 13865#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 13866#L689-1 assume !(1 == ~E_4~0); 15787#L694-1 assume !(1 == ~E_5~0); 14028#L699-1 assume { :end_inline_reset_delta_events } true; 14029#L900-2 [2024-10-13 17:45:58,935 INFO L747 eck$LassoCheckResult]: Loop: 14029#L900-2 assume !false; 16400#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16396#L561-1 assume !false; 14001#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14002#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16390#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16389#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16388#L486 assume !(0 != eval_~tmp~0#1); 16387#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14204#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14205#L586-3 assume !(0 == ~M_E~0); 14157#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14047#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13884#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13885#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14063#L606-3 assume !(0 == ~T5_E~0); 14102#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14103#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13771#L621-3 assume !(0 == ~E_3~0); 13722#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13723#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13728#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13729#L279-18 assume !(1 == ~m_pc~0); 13840#L279-20 is_master_triggered_~__retres1~0#1 := 0; 13983#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13976#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13977#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14190#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14066#L298-18 assume 1 == ~t1_pc~0; 13702#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13696#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13892#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13911#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13912#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14040#L317-18 assume !(1 == ~t2_pc~0); 14041#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 14062#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14074#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13895#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13896#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14193#L336-18 assume 1 == ~t3_pc~0; 14163#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14164#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14105#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14106#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16593#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14137#L355-18 assume 1 == ~t4_pc~0; 14138#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14123#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14007#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14008#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13930#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13931#L374-18 assume 1 == ~t5_pc~0; 14181#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13998#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13932#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13933#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14117#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14118#L649-3 assume !(1 == ~M_E~0); 14251#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16568#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15939#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16567#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16566#L669-3 assume !(1 == ~T5_E~0); 16565#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16564#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16563#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15923#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16562#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16561#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16545#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16541#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16539#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 16522#L919 assume !(0 == start_simulation_~tmp~3#1); 16506#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14143#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13709#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13747#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 13748#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14018#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14194#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 14213#L932 assume !(0 != start_simulation_~tmp___0~1#1); 14029#L900-2 [2024-10-13 17:45:58,936 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,936 INFO L85 PathProgramCache]: Analyzing trace with hash -318127708, now seen corresponding path program 1 times [2024-10-13 17:45:58,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144640495] [2024-10-13 17:45:58,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:58,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:58,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:58,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144640495] [2024-10-13 17:45:58,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2144640495] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:58,984 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:58,984 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:58,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377020620] [2024-10-13 17:45:58,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:58,985 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:58,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:58,985 INFO L85 PathProgramCache]: Analyzing trace with hash -1983215069, now seen corresponding path program 1 times [2024-10-13 17:45:58,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:58,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800058104] [2024-10-13 17:45:58,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:58,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:58,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:59,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:59,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:59,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800058104] [2024-10-13 17:45:59,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800058104] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:59,035 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:59,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:59,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1311473993] [2024-10-13 17:45:59,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:59,036 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:59,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:59,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:59,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:59,036 INFO L87 Difference]: Start difference. First operand 3027 states and 4420 transitions. cyclomatic complexity: 1397 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:59,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:59,106 INFO L93 Difference]: Finished difference Result 5566 states and 8084 transitions. [2024-10-13 17:45:59,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5566 states and 8084 transitions. [2024-10-13 17:45:59,125 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5458 [2024-10-13 17:45:59,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5566 states to 5566 states and 8084 transitions. [2024-10-13 17:45:59,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5566 [2024-10-13 17:45:59,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5566 [2024-10-13 17:45:59,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5566 states and 8084 transitions. [2024-10-13 17:45:59,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:59,151 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5566 states and 8084 transitions. [2024-10-13 17:45:59,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5566 states and 8084 transitions. [2024-10-13 17:45:59,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5566 to 5550. [2024-10-13 17:45:59,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5550 states, 5550 states have (on average 1.4536936936936937) internal successors, (8068), 5549 states have internal predecessors, (8068), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:59,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5550 states to 5550 states and 8068 transitions. [2024-10-13 17:45:59,220 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5550 states and 8068 transitions. [2024-10-13 17:45:59,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:45:59,221 INFO L425 stractBuchiCegarLoop]: Abstraction has 5550 states and 8068 transitions. [2024-10-13 17:45:59,221 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-13 17:45:59,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5550 states and 8068 transitions. [2024-10-13 17:45:59,235 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5442 [2024-10-13 17:45:59,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:59,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:59,236 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:59,236 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:59,236 INFO L745 eck$LassoCheckResult]: Stem: 22559#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 22560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 22671#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22672#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22689#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 22690#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22494#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22495#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22808#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22809#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22769#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22461#L586 assume !(0 == ~M_E~0); 22462#L586-2 assume !(0 == ~T1_E~0); 22516#L591-1 assume !(0 == ~T2_E~0); 22631#L596-1 assume !(0 == ~T3_E~0); 22632#L601-1 assume !(0 == ~T4_E~0); 22677#L606-1 assume !(0 == ~T5_E~0); 22678#L611-1 assume !(0 == ~E_1~0); 22778#L616-1 assume !(0 == ~E_2~0); 22779#L621-1 assume !(0 == ~E_3~0); 22386#L626-1 assume !(0 == ~E_4~0); 22387#L631-1 assume !(0 == ~E_5~0); 22554#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22381#L279 assume !(1 == ~m_pc~0); 22383#L279-2 is_master_triggered_~__retres1~0#1 := 0; 22706#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22529#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22530#L720 assume !(0 != activate_threads_~tmp~1#1); 22705#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22561#L298 assume !(1 == ~t1_pc~0); 22326#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22327#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22352#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22353#L728 assume !(0 != activate_threads_~tmp___0~0#1); 22395#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22522#L317 assume !(1 == ~t2_pc~0); 22523#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22729#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22570#L736 assume !(0 != activate_threads_~tmp___1~0#1); 22571#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22765#L336 assume !(1 == ~t3_pc~0); 22766#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22841#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22299#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22300#L744 assume !(0 != activate_threads_~tmp___2~0#1); 22715#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22774#L355 assume !(1 == ~t4_pc~0); 22628#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22481#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22426#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22427#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22405#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22406#L374 assume 1 == ~t5_pc~0; 22801#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22544#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22535#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22536#L760 assume !(0 != activate_threads_~tmp___4~0#1); 22659#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22660#L649 assume !(1 == ~M_E~0); 22834#L649-2 assume !(1 == ~T1_E~0); 22365#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22366#L659-1 assume !(1 == ~T3_E~0); 25084#L664-1 assume !(1 == ~T4_E~0); 25083#L669-1 assume !(1 == ~T5_E~0); 25082#L674-1 assume !(1 == ~E_1~0); 25081#L679-1 assume !(1 == ~E_2~0); 25080#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 22468#L689-1 assume !(1 == ~E_4~0); 25079#L694-1 assume !(1 == ~E_5~0); 25078#L699-1 assume { :end_inline_reset_delta_events } true; 25076#L900-2 [2024-10-13 17:45:59,236 INFO L747 eck$LassoCheckResult]: Loop: 25076#L900-2 assume !false; 25075#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25071#L561-1 assume !false; 25070#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25068#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25063#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25062#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25060#L486 assume !(0 != eval_~tmp~0#1); 25061#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25515#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25513#L586-3 assume !(0 == ~M_E~0); 25511#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25509#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25507#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25504#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25501#L606-3 assume !(0 == ~T5_E~0); 25498#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25495#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25492#L621-3 assume !(0 == ~E_3~0); 25489#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25486#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25483#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25480#L279-18 assume !(1 == ~m_pc~0); 25475#L279-20 is_master_triggered_~__retres1~0#1 := 0; 25472#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25469#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25466#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25462#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25459#L298-18 assume 1 == ~t1_pc~0; 25456#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25451#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25448#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25445#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25442#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25438#L317-18 assume !(1 == ~t2_pc~0); 25435#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 25431#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25428#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25425#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25422#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25419#L336-18 assume !(1 == ~t3_pc~0); 25416#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 25413#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25410#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25407#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25405#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25403#L355-18 assume 1 == ~t4_pc~0; 25400#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25398#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25394#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25389#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25385#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25380#L374-18 assume 1 == ~t5_pc~0; 25376#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25371#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25367#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25362#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25359#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25355#L649-3 assume !(1 == ~M_E~0); 24846#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25347#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25329#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25339#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25335#L669-3 assume !(1 == ~T5_E~0); 25332#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25327#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25322#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25311#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25317#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25314#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25302#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25292#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25286#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 24196#L919 assume !(0 == start_simulation_~tmp~3#1); 23376#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 23377#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25089#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25088#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 25087#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25086#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25085#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 25077#L932 assume !(0 != start_simulation_~tmp___0~1#1); 25076#L900-2 [2024-10-13 17:45:59,237 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:59,237 INFO L85 PathProgramCache]: Analyzing trace with hash -375271933, now seen corresponding path program 1 times [2024-10-13 17:45:59,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:59,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015182265] [2024-10-13 17:45:59,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:59,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:59,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:59,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:59,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:59,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015182265] [2024-10-13 17:45:59,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015182265] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:59,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:59,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:59,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458888916] [2024-10-13 17:45:59,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:59,272 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:59,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:59,273 INFO L85 PathProgramCache]: Analyzing trace with hash 156237826, now seen corresponding path program 1 times [2024-10-13 17:45:59,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:59,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557762119] [2024-10-13 17:45:59,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:59,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:59,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:59,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:59,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:59,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557762119] [2024-10-13 17:45:59,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557762119] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:59,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:59,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:59,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [195717758] [2024-10-13 17:45:59,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:59,311 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:59,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:59,312 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:45:59,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:45:59,312 INFO L87 Difference]: Start difference. First operand 5550 states and 8068 transitions. cyclomatic complexity: 2526 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:59,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:59,441 INFO L93 Difference]: Finished difference Result 5805 states and 8323 transitions. [2024-10-13 17:45:59,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5805 states and 8323 transitions. [2024-10-13 17:45:59,461 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5694 [2024-10-13 17:45:59,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5805 states to 5805 states and 8323 transitions. [2024-10-13 17:45:59,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5805 [2024-10-13 17:45:59,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5805 [2024-10-13 17:45:59,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5805 states and 8323 transitions. [2024-10-13 17:45:59,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:59,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5805 states and 8323 transitions. [2024-10-13 17:45:59,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5805 states and 8323 transitions. [2024-10-13 17:45:59,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5805 to 5805. [2024-10-13 17:45:59,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5805 states, 5805 states have (on average 1.4337639965546942) internal successors, (8323), 5804 states have internal predecessors, (8323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:59,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5805 states to 5805 states and 8323 transitions. [2024-10-13 17:45:59,599 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5805 states and 8323 transitions. [2024-10-13 17:45:59,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:45:59,600 INFO L425 stractBuchiCegarLoop]: Abstraction has 5805 states and 8323 transitions. [2024-10-13 17:45:59,600 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-13 17:45:59,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5805 states and 8323 transitions. [2024-10-13 17:45:59,614 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5694 [2024-10-13 17:45:59,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:59,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:59,615 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:59,615 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:59,615 INFO L745 eck$LassoCheckResult]: Stem: 33927#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 33928#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 34044#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34045#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34064#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 34065#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33860#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33861#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34181#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34182#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34137#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33832#L586 assume !(0 == ~M_E~0); 33833#L586-2 assume !(0 == ~T1_E~0); 33882#L591-1 assume !(0 == ~T2_E~0); 34005#L596-1 assume !(0 == ~T3_E~0); 34006#L601-1 assume !(0 == ~T4_E~0); 34052#L606-1 assume !(0 == ~T5_E~0); 34053#L611-1 assume !(0 == ~E_1~0); 34150#L616-1 assume !(0 == ~E_2~0); 34151#L621-1 assume !(0 == ~E_3~0); 33750#L626-1 assume !(0 == ~E_4~0); 33751#L631-1 assume !(0 == ~E_5~0); 33920#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33745#L279 assume !(1 == ~m_pc~0); 33747#L279-2 is_master_triggered_~__retres1~0#1 := 0; 34080#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33895#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33896#L720 assume !(0 != activate_threads_~tmp~1#1); 34079#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33929#L298 assume !(1 == ~t1_pc~0); 33692#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33693#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33718#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33719#L728 assume !(0 != activate_threads_~tmp___0~0#1); 33760#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33888#L317 assume !(1 == ~t2_pc~0); 33889#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34099#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34049#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33939#L736 assume !(0 != activate_threads_~tmp___1~0#1); 33940#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34134#L336 assume !(1 == ~t3_pc~0); 34135#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34211#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33665#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33666#L744 assume !(0 != activate_threads_~tmp___2~0#1); 34089#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34142#L355 assume !(1 == ~t4_pc~0); 34004#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33847#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33793#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33794#L752 assume !(0 != activate_threads_~tmp___3~0#1); 33774#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33775#L374 assume 1 == ~t5_pc~0; 34174#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33914#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33901#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33902#L760 assume !(0 != activate_threads_~tmp___4~0#1); 34033#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34034#L649 assume !(1 == ~M_E~0); 34204#L649-2 assume !(1 == ~T1_E~0); 33730#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33731#L659-1 assume !(1 == ~T3_E~0); 33937#L664-1 assume !(1 == ~T4_E~0); 33722#L669-1 assume !(1 == ~T5_E~0); 33723#L674-1 assume !(1 == ~E_1~0); 34123#L679-1 assume !(1 == ~E_2~0); 33834#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 33835#L689-1 assume !(1 == ~E_4~0); 33998#L694-1 assume !(1 == ~E_5~0); 34230#L699-1 assume { :end_inline_reset_delta_events } true; 35727#L900-2 [2024-10-13 17:45:59,615 INFO L747 eck$LassoCheckResult]: Loop: 35727#L900-2 assume !false; 34827#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34824#L561-1 assume !false; 34817#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 34818#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 34802#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 34803#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34796#L486 assume !(0 != eval_~tmp~0#1); 33800#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33801#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34168#L586-3 assume !(0 == ~M_E~0); 34122#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34015#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33851#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33852#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34031#L606-3 assume !(0 == ~T5_E~0); 34068#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34069#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33739#L621-3 assume !(0 == ~E_3~0); 33690#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33691#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33696#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33697#L279-18 assume !(1 == ~m_pc~0); 33810#L279-20 is_master_triggered_~__retres1~0#1 := 0; 33948#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33942#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33943#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34152#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34032#L298-18 assume 1 == ~t1_pc~0; 33670#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33664#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33857#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33878#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33879#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34009#L317-18 assume !(1 == ~t2_pc~0); 34010#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 34026#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34040#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33862#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33863#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34155#L336-18 assume !(1 == ~t3_pc~0); 34156#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 34185#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34071#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33965#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33803#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33804#L355-18 assume 1 == ~t4_pc~0; 34101#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34193#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39407#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39406#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33897#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33898#L374-18 assume !(1 == ~t5_pc~0); 34103#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 33959#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33899#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33900#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34081#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34082#L649-3 assume !(1 == ~M_E~0); 33978#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33979#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35547#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39129#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39128#L669-3 assume !(1 == ~T5_E~0); 39127#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39126#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39125#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35539#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39124#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39123#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 39119#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 39116#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 35910#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 34859#L919 assume !(0 == start_simulation_~tmp~3#1); 34861#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 35863#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 35857#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 35856#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 35855#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35853#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34834#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 34835#L932 assume !(0 != start_simulation_~tmp___0~1#1); 35727#L900-2 [2024-10-13 17:45:59,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:59,616 INFO L85 PathProgramCache]: Analyzing trace with hash -1192920383, now seen corresponding path program 1 times [2024-10-13 17:45:59,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:59,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201233402] [2024-10-13 17:45:59,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:59,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:59,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:59,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:59,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:59,648 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201233402] [2024-10-13 17:45:59,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [201233402] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:59,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:59,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:59,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [372803264] [2024-10-13 17:45:59,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:59,649 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:59,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:59,650 INFO L85 PathProgramCache]: Analyzing trace with hash 99093601, now seen corresponding path program 1 times [2024-10-13 17:45:59,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:59,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896413060] [2024-10-13 17:45:59,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:59,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:59,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:59,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:59,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:59,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896413060] [2024-10-13 17:45:59,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896413060] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:59,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:59,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:45:59,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725268039] [2024-10-13 17:45:59,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:59,696 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:59,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:59,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:59,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:59,697 INFO L87 Difference]: Start difference. First operand 5805 states and 8323 transitions. cyclomatic complexity: 2526 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:59,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:45:59,779 INFO L93 Difference]: Finished difference Result 11422 states and 16248 transitions. [2024-10-13 17:45:59,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11422 states and 16248 transitions. [2024-10-13 17:45:59,831 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11256 [2024-10-13 17:45:59,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11422 states to 11422 states and 16248 transitions. [2024-10-13 17:45:59,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11422 [2024-10-13 17:45:59,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11422 [2024-10-13 17:45:59,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11422 states and 16248 transitions. [2024-10-13 17:45:59,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:45:59,890 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11422 states and 16248 transitions. [2024-10-13 17:45:59,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11422 states and 16248 transitions. [2024-10-13 17:46:00,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11422 to 11358. [2024-10-13 17:46:00,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11358 states, 11358 states have (on average 1.4234900510653283) internal successors, (16168), 11357 states have internal predecessors, (16168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11358 states to 11358 states and 16168 transitions. [2024-10-13 17:46:00,109 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11358 states and 16168 transitions. [2024-10-13 17:46:00,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,110 INFO L425 stractBuchiCegarLoop]: Abstraction has 11358 states and 16168 transitions. [2024-10-13 17:46:00,110 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-13 17:46:00,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11358 states and 16168 transitions. [2024-10-13 17:46:00,148 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11224 [2024-10-13 17:46:00,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,150 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,150 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,150 INFO L745 eck$LassoCheckResult]: Stem: 51167#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 51168#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 51299#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51300#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51319#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 51320#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51097#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51098#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51450#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51451#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51401#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51066#L586 assume !(0 == ~M_E~0); 51067#L586-2 assume !(0 == ~T1_E~0); 51120#L591-1 assume !(0 == ~T2_E~0); 51253#L596-1 assume !(0 == ~T3_E~0); 51254#L601-1 assume !(0 == ~T4_E~0); 51307#L606-1 assume !(0 == ~T5_E~0); 51308#L611-1 assume !(0 == ~E_1~0); 51417#L616-1 assume !(0 == ~E_2~0); 51418#L621-1 assume !(0 == ~E_3~0); 50987#L626-1 assume !(0 == ~E_4~0); 50988#L631-1 assume !(0 == ~E_5~0); 51160#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50982#L279 assume !(1 == ~m_pc~0); 50984#L279-2 is_master_triggered_~__retres1~0#1 := 0; 51341#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51134#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51135#L720 assume !(0 != activate_threads_~tmp~1#1); 51340#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51169#L298 assume !(1 == ~t1_pc~0); 50927#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50928#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50953#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50954#L728 assume !(0 != activate_threads_~tmp___0~0#1); 50996#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51127#L317 assume !(1 == ~t2_pc~0); 51128#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51360#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51306#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51179#L736 assume !(0 != activate_threads_~tmp___1~0#1); 51180#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51398#L336 assume !(1 == ~t3_pc~0); 51399#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51491#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50900#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50901#L744 assume !(0 != activate_threads_~tmp___2~0#1); 51349#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51409#L355 assume !(1 == ~t4_pc~0); 51252#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51083#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51026#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 51027#L752 assume !(0 != activate_threads_~tmp___3~0#1); 51008#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51009#L374 assume !(1 == ~t5_pc~0); 51153#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 51154#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51140#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51141#L760 assume !(0 != activate_threads_~tmp___4~0#1); 51287#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51288#L649 assume !(1 == ~M_E~0); 51482#L649-2 assume !(1 == ~T1_E~0); 50966#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50967#L659-1 assume !(1 == ~T3_E~0); 54203#L664-1 assume !(1 == ~T4_E~0); 54202#L669-1 assume !(1 == ~T5_E~0); 54201#L674-1 assume !(1 == ~E_1~0); 54200#L679-1 assume !(1 == ~E_2~0); 54199#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 51070#L689-1 assume !(1 == ~E_4~0); 51511#L694-1 assume !(1 == ~E_5~0); 51242#L699-1 assume { :end_inline_reset_delta_events } true; 51243#L900-2 [2024-10-13 17:46:00,151 INFO L747 eck$LassoCheckResult]: Loop: 51243#L900-2 assume !false; 54260#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54249#L561-1 assume !false; 54243#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54158#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54149#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53819#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53817#L486 assume !(0 != eval_~tmp~0#1); 53818#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54706#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54702#L586-3 assume !(0 == ~M_E~0); 54698#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54694#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54690#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54687#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54683#L606-3 assume !(0 == ~T5_E~0); 54680#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54677#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54673#L621-3 assume !(0 == ~E_3~0); 54668#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54664#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54659#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54654#L279-18 assume !(1 == ~m_pc~0); 54649#L279-20 is_master_triggered_~__retres1~0#1 := 0; 54645#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54640#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 54636#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54632#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54627#L298-18 assume !(1 == ~t1_pc~0); 54622#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 54618#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54614#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54610#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54607#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54602#L317-18 assume !(1 == ~t2_pc~0); 54599#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 54597#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54594#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54591#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54587#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54584#L336-18 assume !(1 == ~t3_pc~0); 54581#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 54578#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54574#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54571#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54146#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53699#L355-18 assume 1 == ~t4_pc~0; 53697#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53698#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53720#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53687#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53685#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53683#L374-18 assume !(1 == ~t5_pc~0); 53681#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 53679#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53677#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53675#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53671#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53669#L649-3 assume !(1 == ~M_E~0); 53666#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53665#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53661#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53660#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53658#L669-3 assume !(1 == ~T5_E~0); 53656#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53654#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53652#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53648#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53647#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53645#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 53636#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 53632#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53630#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 53627#L919 assume !(0 == start_simulation_~tmp~3#1); 53628#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54311#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54304#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54302#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 54300#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54298#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54296#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 54294#L932 assume !(0 != start_simulation_~tmp___0~1#1); 51243#L900-2 [2024-10-13 17:46:00,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,151 INFO L85 PathProgramCache]: Analyzing trace with hash -52568672, now seen corresponding path program 1 times [2024-10-13 17:46:00,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202475162] [2024-10-13 17:46:00,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1202475162] [2024-10-13 17:46:00,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1202475162] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,187 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,187 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:00,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193924274] [2024-10-13 17:46:00,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,188 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,188 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,188 INFO L85 PathProgramCache]: Analyzing trace with hash 201894848, now seen corresponding path program 1 times [2024-10-13 17:46:00,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423563707] [2024-10-13 17:46:00,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423563707] [2024-10-13 17:46:00,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423563707] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,236 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:00,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077899185] [2024-10-13 17:46:00,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,237 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:00,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:00,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:00,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:00,238 INFO L87 Difference]: Start difference. First operand 11358 states and 16168 transitions. cyclomatic complexity: 4826 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,281 INFO L93 Difference]: Finished difference Result 11352 states and 16075 transitions. [2024-10-13 17:46:00,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11352 states and 16075 transitions. [2024-10-13 17:46:00,329 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11224 [2024-10-13 17:46:00,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11352 states to 11352 states and 16075 transitions. [2024-10-13 17:46:00,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11352 [2024-10-13 17:46:00,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11352 [2024-10-13 17:46:00,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11352 states and 16075 transitions. [2024-10-13 17:46:00,379 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,379 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11352 states and 16075 transitions. [2024-10-13 17:46:00,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11352 states and 16075 transitions. [2024-10-13 17:46:00,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11352 to 5897. [2024-10-13 17:46:00,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5897 states, 5897 states have (on average 1.4132609801594032) internal successors, (8334), 5896 states have internal predecessors, (8334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5897 states to 5897 states and 8334 transitions. [2024-10-13 17:46:00,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5897 states and 8334 transitions. [2024-10-13 17:46:00,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,591 INFO L425 stractBuchiCegarLoop]: Abstraction has 5897 states and 8334 transitions. [2024-10-13 17:46:00,591 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-13 17:46:00,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5897 states and 8334 transitions. [2024-10-13 17:46:00,601 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5796 [2024-10-13 17:46:00,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,603 INFO L745 eck$LassoCheckResult]: Stem: 73878#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 73879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 73999#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74000#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74019#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 74020#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73812#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73813#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74139#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74140#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74100#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73783#L586 assume !(0 == ~M_E~0); 73784#L586-2 assume !(0 == ~T1_E~0); 73833#L591-1 assume !(0 == ~T2_E~0); 73958#L596-1 assume !(0 == ~T3_E~0); 73959#L601-1 assume !(0 == ~T4_E~0); 74006#L606-1 assume !(0 == ~T5_E~0); 74007#L611-1 assume !(0 == ~E_1~0); 74110#L616-1 assume !(0 == ~E_2~0); 74111#L621-1 assume !(0 == ~E_3~0); 73704#L626-1 assume !(0 == ~E_4~0); 73705#L631-1 assume !(0 == ~E_5~0); 73871#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73701#L279 assume !(1 == ~m_pc~0); 73703#L279-2 is_master_triggered_~__retres1~0#1 := 0; 74035#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73846#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 73847#L720 assume !(0 != activate_threads_~tmp~1#1); 74034#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73880#L298 assume !(1 == ~t1_pc~0); 73649#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73650#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73675#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 73676#L728 assume !(0 != activate_threads_~tmp___0~0#1); 73713#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73839#L317 assume !(1 == ~t2_pc~0); 73840#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 74057#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74005#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 73891#L736 assume !(0 != activate_threads_~tmp___1~0#1); 73892#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74094#L336 assume !(1 == ~t3_pc~0); 74095#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 74179#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73620#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 73621#L744 assume !(0 != activate_threads_~tmp___2~0#1); 74045#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74106#L355 assume !(1 == ~t4_pc~0); 73957#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74103#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73743#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73744#L752 assume !(0 != activate_threads_~tmp___3~0#1); 73725#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73726#L374 assume !(1 == ~t5_pc~0); 73864#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 73865#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73852#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73853#L760 assume !(0 != activate_threads_~tmp___4~0#1); 73984#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73985#L649 assume !(1 == ~M_E~0); 74168#L649-2 assume !(1 == ~T1_E~0); 73685#L654-1 assume !(1 == ~T2_E~0); 73686#L659-1 assume !(1 == ~T3_E~0); 73888#L664-1 assume !(1 == ~T4_E~0); 73677#L669-1 assume !(1 == ~T5_E~0); 73678#L674-1 assume !(1 == ~E_1~0); 74082#L679-1 assume !(1 == ~E_2~0); 73785#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 73786#L689-1 assume !(1 == ~E_4~0); 73952#L694-1 assume !(1 == ~E_5~0); 73949#L699-1 assume { :end_inline_reset_delta_events } true; 73950#L900-2 [2024-10-13 17:46:00,606 INFO L747 eck$LassoCheckResult]: Loop: 73950#L900-2 assume !false; 76965#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76960#L561-1 assume !false; 76958#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 76774#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 76767#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 76765#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 76762#L486 assume !(0 != eval_~tmp~0#1); 76763#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77138#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77136#L586-3 assume !(0 == ~M_E~0); 77134#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77131#L591-3 assume !(0 == ~T2_E~0); 77130#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77128#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77125#L606-3 assume !(0 == ~T5_E~0); 77123#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77121#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77119#L621-3 assume !(0 == ~E_3~0); 77117#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 77115#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77114#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77113#L279-18 assume !(1 == ~m_pc~0); 77109#L279-20 is_master_triggered_~__retres1~0#1 := 0; 77107#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77105#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 77103#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77101#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77099#L298-18 assume 1 == ~t1_pc~0; 77097#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77094#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77092#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77090#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77088#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77086#L317-18 assume !(1 == ~t2_pc~0); 77084#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 77082#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77080#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77078#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77076#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77072#L336-18 assume !(1 == ~t3_pc~0); 77070#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 77068#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77066#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77063#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77061#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77059#L355-18 assume 1 == ~t4_pc~0; 77057#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77058#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77183#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77048#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77046#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77043#L374-18 assume !(1 == ~t5_pc~0); 77041#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 77039#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77037#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77035#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77033#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77031#L649-3 assume !(1 == ~M_E~0); 77027#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77025#L654-3 assume !(1 == ~T2_E~0); 77023#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77021#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77020#L669-3 assume !(1 == ~T5_E~0); 77019#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77018#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77016#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77014#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77012#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77010#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 77001#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 76997#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 76995#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 76992#L919 assume !(0 == start_simulation_~tmp~3#1); 76989#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 76987#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 76979#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 76977#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 76975#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76973#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76971#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 76969#L932 assume !(0 != start_simulation_~tmp___0~1#1); 73950#L900-2 [2024-10-13 17:46:00,607 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,607 INFO L85 PathProgramCache]: Analyzing trace with hash -445595682, now seen corresponding path program 1 times [2024-10-13 17:46:00,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3115059] [2024-10-13 17:46:00,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,652 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,652 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3115059] [2024-10-13 17:46:00,652 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3115059] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,652 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719708677] [2024-10-13 17:46:00,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,653 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,653 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,653 INFO L85 PathProgramCache]: Analyzing trace with hash -2068561187, now seen corresponding path program 1 times [2024-10-13 17:46:00,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784122274] [2024-10-13 17:46:00,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784122274] [2024-10-13 17:46:00,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1784122274] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:00,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [811862391] [2024-10-13 17:46:00,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,692 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:00,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:00,693 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:46:00,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:46:00,693 INFO L87 Difference]: Start difference. First operand 5897 states and 8334 transitions. cyclomatic complexity: 2445 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,781 INFO L93 Difference]: Finished difference Result 8753 states and 12285 transitions. [2024-10-13 17:46:00,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8753 states and 12285 transitions. [2024-10-13 17:46:00,808 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8640 [2024-10-13 17:46:00,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8753 states to 8753 states and 12285 transitions. [2024-10-13 17:46:00,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8753 [2024-10-13 17:46:00,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8753 [2024-10-13 17:46:00,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8753 states and 12285 transitions. [2024-10-13 17:46:00,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8753 states and 12285 transitions. [2024-10-13 17:46:00,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8753 states and 12285 transitions. [2024-10-13 17:46:00,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8753 to 5897. [2024-10-13 17:46:00,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5897 states, 5897 states have (on average 1.400203493301679) internal successors, (8257), 5896 states have internal predecessors, (8257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5897 states to 5897 states and 8257 transitions. [2024-10-13 17:46:00,959 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5897 states and 8257 transitions. [2024-10-13 17:46:00,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:46:00,960 INFO L425 stractBuchiCegarLoop]: Abstraction has 5897 states and 8257 transitions. [2024-10-13 17:46:00,960 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-13 17:46:00,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5897 states and 8257 transitions. [2024-10-13 17:46:00,969 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5796 [2024-10-13 17:46:00,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,971 INFO L745 eck$LassoCheckResult]: Stem: 88544#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 88545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 88661#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88662#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88678#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 88679#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88478#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88479#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88791#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88792#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88750#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88448#L586 assume !(0 == ~M_E~0); 88449#L586-2 assume !(0 == ~T1_E~0); 88500#L591-1 assume !(0 == ~T2_E~0); 88621#L596-1 assume !(0 == ~T3_E~0); 88622#L601-1 assume !(0 == ~T4_E~0); 88666#L606-1 assume !(0 == ~T5_E~0); 88667#L611-1 assume !(0 == ~E_1~0); 88759#L616-1 assume !(0 == ~E_2~0); 88760#L621-1 assume !(0 == ~E_3~0); 88368#L626-1 assume !(0 == ~E_4~0); 88369#L631-1 assume !(0 == ~E_5~0); 88537#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88365#L279 assume !(1 == ~m_pc~0); 88367#L279-2 is_master_triggered_~__retres1~0#1 := 0; 88690#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88511#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 88512#L720 assume !(0 != activate_threads_~tmp~1#1); 88689#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88546#L298 assume !(1 == ~t1_pc~0); 88311#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88312#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88338#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88339#L728 assume !(0 != activate_threads_~tmp___0~0#1); 88378#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88505#L317 assume !(1 == ~t2_pc~0); 88506#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88709#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88665#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88557#L736 assume !(0 != activate_threads_~tmp___1~0#1); 88558#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88743#L336 assume !(1 == ~t3_pc~0); 88744#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88831#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88282#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88283#L744 assume !(0 != activate_threads_~tmp___2~0#1); 88698#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88754#L355 assume !(1 == ~t4_pc~0); 88620#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88751#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88408#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88409#L752 assume !(0 != activate_threads_~tmp___3~0#1); 88391#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88392#L374 assume !(1 == ~t5_pc~0); 88530#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 88531#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88517#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88518#L760 assume !(0 != activate_threads_~tmp___4~0#1); 88649#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88650#L649 assume !(1 == ~M_E~0); 88819#L649-2 assume !(1 == ~T1_E~0); 88348#L654-1 assume !(1 == ~T2_E~0); 88349#L659-1 assume !(1 == ~T3_E~0); 88554#L664-1 assume !(1 == ~T4_E~0); 88340#L669-1 assume !(1 == ~T5_E~0); 88341#L674-1 assume !(1 == ~E_1~0); 88733#L679-1 assume !(1 == ~E_2~0); 88450#L684-1 assume !(1 == ~E_3~0); 88451#L689-1 assume !(1 == ~E_4~0); 88615#L694-1 assume !(1 == ~E_5~0); 88612#L699-1 assume { :end_inline_reset_delta_events } true; 88613#L900-2 [2024-10-13 17:46:00,971 INFO L747 eck$LassoCheckResult]: Loop: 88613#L900-2 assume !false; 90279#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90273#L561-1 assume !false; 90269#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 90241#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 90227#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 90220#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 90212#L486 assume !(0 != eval_~tmp~0#1); 90213#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90286#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90281#L586-3 assume !(0 == ~M_E~0); 90275#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 90243#L591-3 assume !(0 == ~T2_E~0); 90228#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90221#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90214#L606-3 assume !(0 == ~T5_E~0); 90205#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 90197#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 90193#L621-3 assume !(0 == ~E_3~0); 90189#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 90184#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 90179#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90027#L279-18 assume !(1 == ~m_pc~0); 90004#L279-20 is_master_triggered_~__retres1~0#1 := 0; 89996#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89988#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 89981#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 89975#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89970#L298-18 assume 1 == ~t1_pc~0; 89968#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 89965#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89958#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 89956#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89954#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89951#L317-18 assume !(1 == ~t2_pc~0); 89949#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 89947#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89945#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 89943#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 89941#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89939#L336-18 assume !(1 == ~t3_pc~0); 89937#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 89935#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89933#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 89931#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89929#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89927#L355-18 assume !(1 == ~t4_pc~0); 89925#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 89922#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89918#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 89915#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 89912#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89909#L374-18 assume !(1 == ~t5_pc~0); 89906#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 89903#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89900#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 89896#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 89893#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89890#L649-3 assume !(1 == ~M_E~0); 89740#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89885#L654-3 assume !(1 == ~T2_E~0); 89882#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89879#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89876#L669-3 assume !(1 == ~T5_E~0); 89873#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 89870#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 89866#L684-3 assume !(1 == ~E_3~0); 89862#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89859#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89856#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 89850#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 89845#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 89841#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 89837#L919 assume !(0 == start_simulation_~tmp~3#1); 89838#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 90318#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 90309#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 90305#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 90301#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 90295#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 90292#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 90289#L932 assume !(0 != start_simulation_~tmp___0~1#1); 88613#L900-2 [2024-10-13 17:46:00,971 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,971 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2024-10-13 17:46:00,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101058905] [2024-10-13 17:46:00,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:00,978 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:00,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:01,013 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:01,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,013 INFO L85 PathProgramCache]: Analyzing trace with hash -284719240, now seen corresponding path program 1 times [2024-10-13 17:46:01,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812301326] [2024-10-13 17:46:01,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812301326] [2024-10-13 17:46:01,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [812301326] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,051 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:01,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699715301] [2024-10-13 17:46:01,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,052 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,052 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,052 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:01,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:01,052 INFO L87 Difference]: Start difference. First operand 5897 states and 8257 transitions. cyclomatic complexity: 2368 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,117 INFO L93 Difference]: Finished difference Result 6009 states and 8369 transitions. [2024-10-13 17:46:01,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6009 states and 8369 transitions. [2024-10-13 17:46:01,132 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5908 [2024-10-13 17:46:01,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6009 states to 6009 states and 8369 transitions. [2024-10-13 17:46:01,210 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6009 [2024-10-13 17:46:01,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6009 [2024-10-13 17:46:01,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6009 states and 8369 transitions. [2024-10-13 17:46:01,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,217 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6009 states and 8369 transitions. [2024-10-13 17:46:01,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6009 states and 8369 transitions. [2024-10-13 17:46:01,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6009 to 5945. [2024-10-13 17:46:01,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5945 states, 5945 states have (on average 1.3969722455845248) internal successors, (8305), 5944 states have internal predecessors, (8305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5945 states to 5945 states and 8305 transitions. [2024-10-13 17:46:01,269 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5945 states and 8305 transitions. [2024-10-13 17:46:01,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:01,270 INFO L425 stractBuchiCegarLoop]: Abstraction has 5945 states and 8305 transitions. [2024-10-13 17:46:01,270 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-13 17:46:01,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5945 states and 8305 transitions. [2024-10-13 17:46:01,279 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5844 [2024-10-13 17:46:01,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,281 INFO L745 eck$LassoCheckResult]: Stem: 100453#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 100454#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 100571#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 100572#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100590#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 100591#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100388#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100389#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100701#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100702#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100661#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100359#L586 assume !(0 == ~M_E~0); 100360#L586-2 assume !(0 == ~T1_E~0); 100409#L591-1 assume !(0 == ~T2_E~0); 100531#L596-1 assume !(0 == ~T3_E~0); 100532#L601-1 assume !(0 == ~T4_E~0); 100578#L606-1 assume !(0 == ~T5_E~0); 100579#L611-1 assume !(0 == ~E_1~0); 100673#L616-1 assume !(0 == ~E_2~0); 100674#L621-1 assume !(0 == ~E_3~0); 100280#L626-1 assume !(0 == ~E_4~0); 100281#L631-1 assume !(0 == ~E_5~0); 100446#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100275#L279 assume !(1 == ~m_pc~0); 100277#L279-2 is_master_triggered_~__retres1~0#1 := 0; 100608#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100421#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 100422#L720 assume !(0 != activate_threads_~tmp~1#1); 100607#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100455#L298 assume !(1 == ~t1_pc~0); 100225#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100226#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100251#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 100252#L728 assume !(0 != activate_threads_~tmp___0~0#1); 100290#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100415#L317 assume !(1 == ~t2_pc~0); 100416#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100626#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100577#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100466#L736 assume !(0 != activate_threads_~tmp___1~0#1); 100467#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100657#L336 assume !(1 == ~t3_pc~0); 100658#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100734#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100196#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100197#L744 assume !(0 != activate_threads_~tmp___2~0#1); 100616#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100669#L355 assume !(1 == ~t4_pc~0); 100530#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100666#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100320#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100321#L752 assume !(0 != activate_threads_~tmp___3~0#1); 100303#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100304#L374 assume !(1 == ~t5_pc~0); 100439#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100440#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100427#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100428#L760 assume !(0 != activate_threads_~tmp___4~0#1); 100558#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100559#L649 assume !(1 == ~M_E~0); 100724#L649-2 assume !(1 == ~T1_E~0); 100261#L654-1 assume !(1 == ~T2_E~0); 100262#L659-1 assume !(1 == ~T3_E~0); 100463#L664-1 assume !(1 == ~T4_E~0); 100253#L669-1 assume !(1 == ~T5_E~0); 100254#L674-1 assume !(1 == ~E_1~0); 100648#L679-1 assume !(1 == ~E_2~0); 100361#L684-1 assume !(1 == ~E_3~0); 100362#L689-1 assume !(1 == ~E_4~0); 100525#L694-1 assume !(1 == ~E_5~0); 100522#L699-1 assume { :end_inline_reset_delta_events } true; 100523#L900-2 [2024-10-13 17:46:01,281 INFO L747 eck$LassoCheckResult]: Loop: 100523#L900-2 assume !false; 105031#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 104905#L561-1 assume !false; 105030#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105028#L439 assume !(0 == ~m_st~0); 105029#L443 assume !(0 == ~t1_st~0); 105025#L447 assume !(0 == ~t2_st~0); 105026#L451 assume !(0 == ~t3_st~0); 105027#L455 assume !(0 == ~t4_st~0); 105023#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 105024#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 104567#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 104568#L486 assume !(0 != eval_~tmp~0#1); 105331#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105330#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 105329#L586-3 assume !(0 == ~M_E~0); 105328#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 105327#L591-3 assume !(0 == ~T2_E~0); 105326#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 105325#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 105324#L606-3 assume !(0 == ~T5_E~0); 105323#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 105322#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 105321#L621-3 assume !(0 == ~E_3~0); 105320#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 105319#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 105318#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105317#L279-18 assume !(1 == ~m_pc~0); 105315#L279-20 is_master_triggered_~__retres1~0#1 := 0; 105314#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105313#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 105312#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 105311#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105310#L298-18 assume 1 == ~t1_pc~0; 105309#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 105307#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105306#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 105305#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 105304#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105303#L317-18 assume !(1 == ~t2_pc~0); 105302#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 105301#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105300#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105299#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 105298#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105297#L336-18 assume !(1 == ~t3_pc~0); 105296#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 105295#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105294#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105293#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 105292#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105291#L355-18 assume 1 == ~t4_pc~0; 105289#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 105287#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105285#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105283#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 105282#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105281#L374-18 assume !(1 == ~t5_pc~0); 105280#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 105279#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105278#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105277#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 105276#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105275#L649-3 assume !(1 == ~M_E~0); 105131#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 105274#L654-3 assume !(1 == ~T2_E~0); 105273#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105272#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 105271#L669-3 assume !(1 == ~T5_E~0); 105270#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 105269#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 105268#L684-3 assume !(1 == ~E_3~0); 105267#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 105266#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 105265#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105261#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 105254#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 105068#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 105060#L919 assume !(0 == start_simulation_~tmp~3#1); 105057#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105055#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 105048#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 105046#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 105044#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 105042#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105040#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 105039#L932 assume !(0 != start_simulation_~tmp___0~1#1); 100523#L900-2 [2024-10-13 17:46:01,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,282 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2024-10-13 17:46:01,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995146899] [2024-10-13 17:46:01,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:01,288 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:01,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:01,300 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:01,300 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,301 INFO L85 PathProgramCache]: Analyzing trace with hash -1684605094, now seen corresponding path program 1 times [2024-10-13 17:46:01,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179423527] [2024-10-13 17:46:01,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179423527] [2024-10-13 17:46:01,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1179423527] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,348 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:01,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777254898] [2024-10-13 17:46:01,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,349 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:01,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:01,349 INFO L87 Difference]: Start difference. First operand 5945 states and 8305 transitions. cyclomatic complexity: 2368 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,549 INFO L93 Difference]: Finished difference Result 6089 states and 8408 transitions. [2024-10-13 17:46:01,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6089 states and 8408 transitions. [2024-10-13 17:46:01,582 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5988 [2024-10-13 17:46:01,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6089 states to 6089 states and 8408 transitions. [2024-10-13 17:46:01,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6089 [2024-10-13 17:46:01,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6089 [2024-10-13 17:46:01,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6089 states and 8408 transitions. [2024-10-13 17:46:01,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6089 states and 8408 transitions. [2024-10-13 17:46:01,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6089 states and 8408 transitions. [2024-10-13 17:46:01,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6089 to 6089. [2024-10-13 17:46:01,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6089 states, 6089 states have (on average 1.3808507144030218) internal successors, (8408), 6088 states have internal predecessors, (8408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6089 states to 6089 states and 8408 transitions. [2024-10-13 17:46:01,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6089 states and 8408 transitions. [2024-10-13 17:46:01,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:01,709 INFO L425 stractBuchiCegarLoop]: Abstraction has 6089 states and 8408 transitions. [2024-10-13 17:46:01,709 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-13 17:46:01,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6089 states and 8408 transitions. [2024-10-13 17:46:01,724 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5988 [2024-10-13 17:46:01,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,725 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,726 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,726 INFO L745 eck$LassoCheckResult]: Stem: 112502#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 112503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 112620#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112621#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112642#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 112643#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112434#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112435#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112760#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112761#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112721#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112404#L586 assume !(0 == ~M_E~0); 112405#L586-2 assume !(0 == ~T1_E~0); 112455#L591-1 assume !(0 == ~T2_E~0); 112581#L596-1 assume !(0 == ~T3_E~0); 112582#L601-1 assume !(0 == ~T4_E~0); 112629#L606-1 assume !(0 == ~T5_E~0); 112630#L611-1 assume !(0 == ~E_1~0); 112729#L616-1 assume !(0 == ~E_2~0); 112730#L621-1 assume !(0 == ~E_3~0); 112321#L626-1 assume !(0 == ~E_4~0); 112322#L631-1 assume !(0 == ~E_5~0); 112495#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112318#L279 assume !(1 == ~m_pc~0); 112320#L279-2 is_master_triggered_~__retres1~0#1 := 0; 112660#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112467#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 112468#L720 assume !(0 != activate_threads_~tmp~1#1); 112659#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112504#L298 assume !(1 == ~t1_pc~0); 112266#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 112267#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112292#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 112293#L728 assume !(0 != activate_threads_~tmp___0~0#1); 112331#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112461#L317 assume !(1 == ~t2_pc~0); 112462#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112680#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112626#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 112515#L736 assume !(0 != activate_threads_~tmp___1~0#1); 112516#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112716#L336 assume !(1 == ~t3_pc~0); 112717#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112797#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112238#L744 assume !(0 != activate_threads_~tmp___2~0#1); 112669#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112725#L355 assume !(1 == ~t4_pc~0); 112580#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 112722#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112361#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112362#L752 assume !(0 != activate_threads_~tmp___3~0#1); 112344#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112345#L374 assume !(1 == ~t5_pc~0); 112486#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 112487#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112474#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 112475#L760 assume !(0 != activate_threads_~tmp___4~0#1); 112608#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112609#L649 assume !(1 == ~M_E~0); 112789#L649-2 assume !(1 == ~T1_E~0); 112302#L654-1 assume !(1 == ~T2_E~0); 112303#L659-1 assume !(1 == ~T3_E~0); 112512#L664-1 assume !(1 == ~T4_E~0); 112294#L669-1 assume !(1 == ~T5_E~0); 112295#L674-1 assume !(1 == ~E_1~0); 112706#L679-1 assume !(1 == ~E_2~0); 112406#L684-1 assume !(1 == ~E_3~0); 112407#L689-1 assume !(1 == ~E_4~0); 112575#L694-1 assume !(1 == ~E_5~0); 112572#L699-1 assume { :end_inline_reset_delta_events } true; 112573#L900-2 [2024-10-13 17:46:01,727 INFO L747 eck$LassoCheckResult]: Loop: 112573#L900-2 assume !false; 112807#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112479#L561-1 assume !false; 112543#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 112535#L439 assume !(0 == ~m_st~0); 112536#L443 assume !(0 == ~t1_st~0); 112693#L447 assume !(0 == ~t2_st~0); 112458#L451 assume !(0 == ~t3_st~0); 112460#L455 assume !(0 == ~t4_st~0); 112640#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 112641#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118197#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 118196#L486 assume !(0 != eval_~tmp~0#1); 118195#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 118194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 118193#L586-3 assume !(0 == ~M_E~0); 118192#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 118191#L591-3 assume !(0 == ~T2_E~0); 118190#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 118189#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 118188#L606-3 assume !(0 == ~T5_E~0); 118187#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 118186#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 118185#L621-3 assume !(0 == ~E_3~0); 118184#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 118183#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 118182#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118181#L279-18 assume !(1 == ~m_pc~0); 118179#L279-20 is_master_triggered_~__retres1~0#1 := 0; 118178#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118177#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 118176#L720-18 assume !(0 != activate_threads_~tmp~1#1); 118174#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118173#L298-18 assume !(1 == ~t1_pc~0); 118171#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 118170#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118168#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118167#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 118166#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118165#L317-18 assume !(1 == ~t2_pc~0); 118164#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 118162#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118160#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 118158#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118156#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118154#L336-18 assume !(1 == ~t3_pc~0); 118152#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 118150#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118148#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118146#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 118144#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118140#L355-18 assume !(1 == ~t4_pc~0); 118136#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 118134#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118132#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118129#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 118126#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118124#L374-18 assume !(1 == ~t5_pc~0); 118122#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 118120#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118118#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118116#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 118114#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118113#L649-3 assume !(1 == ~M_E~0); 118111#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118110#L654-3 assume !(1 == ~T2_E~0); 118109#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 118108#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 118107#L669-3 assume !(1 == ~T5_E~0); 118106#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 118105#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 118104#L684-3 assume !(1 == ~E_3~0); 118102#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 118100#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 118098#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118089#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 118085#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118084#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 118083#L919 assume !(0 == start_simulation_~tmp~3#1); 118081#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118079#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 118073#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 118071#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 118070#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112749#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 112720#L932 assume !(0 != start_simulation_~tmp___0~1#1); 112573#L900-2 [2024-10-13 17:46:01,727 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,727 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2024-10-13 17:46:01,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075840451] [2024-10-13 17:46:01,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:01,736 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:01,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:01,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:01,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,752 INFO L85 PathProgramCache]: Analyzing trace with hash 1263781204, now seen corresponding path program 1 times [2024-10-13 17:46:01,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870461144] [2024-10-13 17:46:01,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,787 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870461144] [2024-10-13 17:46:01,787 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870461144] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,787 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,787 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949033516] [2024-10-13 17:46:01,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,788 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,788 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,789 INFO L87 Difference]: Start difference. First operand 6089 states and 8408 transitions. cyclomatic complexity: 2327 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,847 INFO L93 Difference]: Finished difference Result 10621 states and 14480 transitions. [2024-10-13 17:46:01,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10621 states and 14480 transitions. [2024-10-13 17:46:01,895 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10496 [2024-10-13 17:46:01,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10621 states to 10621 states and 14480 transitions. [2024-10-13 17:46:01,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10621 [2024-10-13 17:46:01,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10621 [2024-10-13 17:46:01,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10621 states and 14480 transitions. [2024-10-13 17:46:01,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,942 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10621 states and 14480 transitions. [2024-10-13 17:46:01,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10621 states and 14480 transitions. [2024-10-13 17:46:02,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10621 to 10297. [2024-10-13 17:46:02,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10297 states, 10297 states have (on average 1.365834709138584) internal successors, (14064), 10296 states have internal predecessors, (14064), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10297 states to 10297 states and 14064 transitions. [2024-10-13 17:46:02,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10297 states and 14064 transitions. [2024-10-13 17:46:02,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:02,182 INFO L425 stractBuchiCegarLoop]: Abstraction has 10297 states and 14064 transitions. [2024-10-13 17:46:02,182 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-13 17:46:02,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10297 states and 14064 transitions. [2024-10-13 17:46:02,233 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10172 [2024-10-13 17:46:02,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:02,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:02,234 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,234 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,234 INFO L745 eck$LassoCheckResult]: Stem: 129217#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 129218#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 129346#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 129347#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 129368#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 129369#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 129150#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 129151#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 129479#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 129480#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 129434#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 129117#L586 assume !(0 == ~M_E~0); 129118#L586-2 assume !(0 == ~T1_E~0); 129170#L591-1 assume !(0 == ~T2_E~0); 129302#L596-1 assume !(0 == ~T3_E~0); 129303#L601-1 assume !(0 == ~T4_E~0); 129355#L606-1 assume !(0 == ~T5_E~0); 129356#L611-1 assume !(0 == ~E_1~0); 129448#L616-1 assume !(0 == ~E_2~0); 129449#L621-1 assume !(0 == ~E_3~0); 129041#L626-1 assume !(0 == ~E_4~0); 129042#L631-1 assume !(0 == ~E_5~0); 129210#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129036#L279 assume !(1 == ~m_pc~0); 129038#L279-2 is_master_triggered_~__retres1~0#1 := 0; 129383#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129182#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 129183#L720 assume !(0 != activate_threads_~tmp~1#1); 129382#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129219#L298 assume !(1 == ~t1_pc~0); 128981#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 128982#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129007#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 129008#L728 assume !(0 != activate_threads_~tmp___0~0#1); 129051#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129176#L317 assume !(1 == ~t2_pc~0); 129177#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 129402#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129351#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 129228#L736 assume !(0 != activate_threads_~tmp___1~0#1); 129229#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129430#L336 assume !(1 == ~t3_pc~0); 129431#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 129516#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 128955#L744 assume !(0 != activate_threads_~tmp___2~0#1); 129391#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129441#L355 assume !(1 == ~t4_pc~0); 129299#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 129439#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 129081#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 129082#L752 assume !(0 != activate_threads_~tmp___3~0#1); 129062#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 129063#L374 assume !(1 == ~t5_pc~0); 129200#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 129201#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129190#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 129191#L760 assume !(0 != activate_threads_~tmp___4~0#1); 129331#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129332#L649 assume !(1 == ~M_E~0); 129508#L649-2 assume !(1 == ~T1_E~0); 129020#L654-1 assume !(1 == ~T2_E~0); 129021#L659-1 assume !(1 == ~T3_E~0); 129227#L664-1 assume !(1 == ~T4_E~0); 129012#L669-1 assume !(1 == ~T5_E~0); 129013#L674-1 assume !(1 == ~E_1~0); 129423#L679-1 assume !(1 == ~E_2~0); 129121#L684-1 assume !(1 == ~E_3~0); 129122#L689-1 assume !(1 == ~E_4~0); 129295#L694-1 assume !(1 == ~E_5~0); 129293#L699-1 assume { :end_inline_reset_delta_events } true; 129294#L900-2 [2024-10-13 17:46:02,235 INFO L747 eck$LassoCheckResult]: Loop: 129294#L900-2 assume !false; 134414#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134411#L561-1 assume !false; 134374#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 134375#L439 assume !(0 == ~m_st~0); 133248#L443 assume !(0 == ~t1_st~0); 133246#L447 assume !(0 == ~t2_st~0); 133244#L451 assume !(0 == ~t3_st~0); 133242#L455 assume !(0 == ~t4_st~0); 133239#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 133235#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 133233#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 133230#L486 assume !(0 != eval_~tmp~0#1); 133227#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 133226#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 133225#L586-3 assume !(0 == ~M_E~0); 133224#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 133223#L591-3 assume !(0 == ~T2_E~0); 133222#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 133221#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 133219#L606-3 assume !(0 == ~T5_E~0); 133218#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 133217#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 133216#L621-3 assume !(0 == ~E_3~0); 133215#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 133214#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 133213#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133212#L279-18 assume !(1 == ~m_pc~0); 133210#L279-20 is_master_triggered_~__retres1~0#1 := 0; 133208#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133207#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 133206#L720-18 assume !(0 != activate_threads_~tmp~1#1); 133205#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133204#L298-18 assume 1 == ~t1_pc~0; 133202#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 133199#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133197#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 133195#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 133193#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133191#L317-18 assume !(1 == ~t2_pc~0); 133189#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 133186#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133184#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 133182#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 133179#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133177#L336-18 assume !(1 == ~t3_pc~0); 133175#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 133173#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133171#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 133169#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 133167#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133165#L355-18 assume 1 == ~t4_pc~0; 133163#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 133164#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 133209#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 133154#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 133152#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133150#L374-18 assume !(1 == ~t5_pc~0); 133148#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 133145#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133143#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 133141#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 133139#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133137#L649-3 assume !(1 == ~M_E~0); 132600#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 133134#L654-3 assume !(1 == ~T2_E~0); 133131#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133129#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133127#L669-3 assume !(1 == ~T5_E~0); 133125#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 133123#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 133121#L684-3 assume !(1 == ~E_3~0); 133119#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 133117#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133115#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 133113#L439-1 assume !(0 == ~m_st~0); 133054#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 133104#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 133102#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 133099#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 132559#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133094#L279-21 assume 1 == ~m_pc~0; 133091#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 133089#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133087#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 133030#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 133027#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133025#L298-21 assume 1 == ~t1_pc~0; 133022#L299-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 133021#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133020#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 133018#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 133017#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133016#L317-21 assume !(1 == ~t2_pc~0); 133015#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 133013#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133012#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 133011#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 133010#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133008#L336-21 assume !(1 == ~t3_pc~0); 133006#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 133004#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133002#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 133000#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132998#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132996#L355-21 assume 1 == ~t4_pc~0; 132994#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 132995#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 133014#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 132984#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132982#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132980#L374-21 assume !(1 == ~t5_pc~0); 132977#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 132976#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132972#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 132970#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 132968#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 132965#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 132966#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134820#L798-1 assume !(1 == ~T2_E~0); 134817#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 134815#L808-1 assume !(1 == ~T4_E~0); 134813#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134811#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 134809#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 134807#L828-1 assume !(1 == ~E_3~0); 134741#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 134740#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 134739#L843-1 assume { :end_inline_reset_time_events } true; 133049#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 134682#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 134608#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 134455#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 134450#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134444#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134445#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 134440#L932 assume !(0 != start_simulation_~tmp___0~1#1); 129294#L900-2 [2024-10-13 17:46:02,236 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,236 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 4 times [2024-10-13 17:46:02,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,236 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371824586] [2024-10-13 17:46:02,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:02,243 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:02,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:02,253 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:02,253 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,254 INFO L85 PathProgramCache]: Analyzing trace with hash 179168571, now seen corresponding path program 1 times [2024-10-13 17:46:02,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627998706] [2024-10-13 17:46:02,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627998706] [2024-10-13 17:46:02,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627998706] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203268170] [2024-10-13 17:46:02,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,291 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:02,292 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:02,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:02,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:02,292 INFO L87 Difference]: Start difference. First operand 10297 states and 14064 transitions. cyclomatic complexity: 3775 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,358 INFO L93 Difference]: Finished difference Result 18768 states and 25478 transitions. [2024-10-13 17:46:02,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18768 states and 25478 transitions. [2024-10-13 17:46:02,428 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18596 [2024-10-13 17:46:02,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18768 states to 18768 states and 25478 transitions. [2024-10-13 17:46:02,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18768 [2024-10-13 17:46:02,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18768 [2024-10-13 17:46:02,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18768 states and 25478 transitions. [2024-10-13 17:46:02,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:02,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18768 states and 25478 transitions. [2024-10-13 17:46:02,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18768 states and 25478 transitions. [2024-10-13 17:46:02,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18768 to 18736. [2024-10-13 17:46:02,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18736 states, 18736 states have (on average 1.358134073441503) internal successors, (25446), 18735 states have internal predecessors, (25446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18736 states to 18736 states and 25446 transitions. [2024-10-13 17:46:02,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18736 states and 25446 transitions. [2024-10-13 17:46:02,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:02,696 INFO L425 stractBuchiCegarLoop]: Abstraction has 18736 states and 25446 transitions. [2024-10-13 17:46:02,696 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-13 17:46:02,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18736 states and 25446 transitions. [2024-10-13 17:46:02,798 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18564 [2024-10-13 17:46:02,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:02,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:02,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,801 INFO L745 eck$LassoCheckResult]: Stem: 158278#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 158279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 158403#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 158404#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 158422#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 158423#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 158213#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158214#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158539#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158540#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 158496#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158181#L586 assume !(0 == ~M_E~0); 158182#L586-2 assume !(0 == ~T1_E~0); 158234#L591-1 assume !(0 == ~T2_E~0); 158359#L596-1 assume !(0 == ~T3_E~0); 158360#L601-1 assume !(0 == ~T4_E~0); 158409#L606-1 assume !(0 == ~T5_E~0); 158410#L611-1 assume !(0 == ~E_1~0); 158506#L616-1 assume !(0 == ~E_2~0); 158507#L621-1 assume !(0 == ~E_3~0); 158105#L626-1 assume !(0 == ~E_4~0); 158106#L631-1 assume !(0 == ~E_5~0); 158271#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158101#L279 assume !(1 == ~m_pc~0); 158102#L279-2 is_master_triggered_~__retres1~0#1 := 0; 158439#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158245#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 158246#L720 assume !(0 != activate_threads_~tmp~1#1); 158438#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158280#L298 assume !(1 == ~t1_pc~0); 158050#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 158051#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 158076#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 158077#L728 assume !(0 != activate_threads_~tmp___0~0#1); 158115#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158239#L317 assume !(1 == ~t2_pc~0); 158240#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 158459#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 158408#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 158289#L736 assume !(0 != activate_threads_~tmp___1~0#1); 158290#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158491#L336 assume !(1 == ~t3_pc~0); 158492#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 158580#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 158024#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 158025#L744 assume !(0 != activate_threads_~tmp___2~0#1); 158447#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 158502#L355 assume !(1 == ~t4_pc~0); 158356#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 158501#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158145#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 158146#L752 assume !(0 != activate_threads_~tmp___3~0#1); 158126#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158127#L374 assume !(1 == ~t5_pc~0); 158260#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 158261#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158251#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 158252#L760 assume !(0 != activate_threads_~tmp___4~0#1); 158392#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158393#L649 assume !(1 == ~M_E~0); 158567#L649-2 assume !(1 == ~T1_E~0); 158086#L654-1 assume !(1 == ~T2_E~0); 158087#L659-1 assume !(1 == ~T3_E~0); 158288#L664-1 assume !(1 == ~T4_E~0); 158078#L669-1 assume !(1 == ~T5_E~0); 158079#L674-1 assume !(1 == ~E_1~0); 158483#L679-1 assume !(1 == ~E_2~0); 158185#L684-1 assume !(1 == ~E_3~0); 158186#L689-1 assume !(1 == ~E_4~0); 158352#L694-1 assume !(1 == ~E_5~0); 158350#L699-1 assume { :end_inline_reset_delta_events } true; 158351#L900-2 [2024-10-13 17:46:02,801 INFO L747 eck$LassoCheckResult]: Loop: 158351#L900-2 assume !false; 164435#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164428#L561-1 assume !false; 164422#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 164417#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 164412#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 164407#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 164402#L486 assume 0 != eval_~tmp~0#1; 164396#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 164388#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 164381#L65 assume 0 == ~m_pc~0; 163088#L92 assume !false; 164373#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164369#L279-3 assume !(1 == ~m_pc~0); 164365#L279-5 is_master_triggered_~__retres1~0#1 := 0; 164360#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 164354#is_master_triggered_returnLabel#2 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 164349#L720-3 assume !(0 != activate_threads_~tmp~1#1); 163689#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163686#L298-3 assume 1 == ~t1_pc~0; 163683#L299-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 163681#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163679#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 163532#L728-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 163530#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163531#L317-3 assume !(1 == ~t2_pc~0); 163653#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 163651#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163649#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 163648#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 163647#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163644#L336-3 assume !(1 == ~t3_pc~0); 163643#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 163642#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163641#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 163640#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 163639#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163638#L355-3 assume !(1 == ~t4_pc~0); 163636#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 163634#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163632#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163631#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 163629#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163565#L374-3 assume !(1 == ~t5_pc~0); 163525#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 163095#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163094#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 163093#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 163092#L760-5 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 163086#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 163085#$Ultimate##223 assume !false; 162138#L85 ~m_pc~0 := 1;~m_st~0 := 2; 162131#master_returnLabel#1 assume { :end_inline_master } true; 162126#L494-2 havoc eval_~tmp_ndt_1~0#1; 162043#L491-1 assume !(0 == ~t1_st~0); 162034#L505-1 assume !(0 == ~t2_st~0); 162035#L519-1 assume !(0 == ~t3_st~0); 162389#L533-1 assume !(0 == ~t4_st~0); 162384#L547-1 assume !(0 == ~t5_st~0); 162288#L561-1 assume !false; 162289#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 160459#L439 assume !(0 == ~m_st~0); 160457#L443 assume !(0 == ~t1_st~0); 160455#L447 assume !(0 == ~t2_st~0); 160453#L451 assume !(0 == ~t3_st~0); 160450#L455 assume !(0 == ~t4_st~0); 160447#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 160445#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 160443#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 160440#L486 assume !(0 != eval_~tmp~0#1); 160438#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 160436#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 160434#L586-3 assume !(0 == ~M_E~0); 160432#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 160430#L591-3 assume !(0 == ~T2_E~0); 160428#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 160426#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 160424#L606-3 assume !(0 == ~T5_E~0); 160423#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 160422#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 160420#L621-3 assume !(0 == ~E_3~0); 160418#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 160416#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 160415#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160412#L279-18 assume 1 == ~m_pc~0; 160411#L280-6 assume !(1 == ~M_E~0); 160401#L279-20 is_master_triggered_~__retres1~0#1 := 0; 160396#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160391#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 160383#L720-18 assume !(0 != activate_threads_~tmp~1#1); 160380#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160377#L298-18 assume !(1 == ~t1_pc~0); 160375#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 160371#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 160363#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 160356#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 160348#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160347#L317-18 assume !(1 == ~t2_pc~0); 160346#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 160343#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160340#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160338#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 160330#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160324#L336-18 assume !(1 == ~t3_pc~0); 160318#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 160313#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160308#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 160303#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 160298#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160293#L355-18 assume !(1 == ~t4_pc~0); 160288#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 160282#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160275#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 160269#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 160263#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160258#L374-18 assume !(1 == ~t5_pc~0); 160253#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 160248#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160242#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 160237#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 160232#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160227#L649-3 assume !(1 == ~M_E~0); 159885#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 160215#L654-3 assume !(1 == ~T2_E~0); 160207#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 160199#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 160192#L669-3 assume !(1 == ~T5_E~0); 160186#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 160182#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 160178#L684-3 assume !(1 == ~E_3~0); 160173#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 160168#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 160163#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 160158#L439-1 assume !(0 == ~m_st~0); 159764#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 160142#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 160137#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 159807#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 159805#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159803#L279-21 assume 1 == ~m_pc~0; 159801#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 159799#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159797#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 159736#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159734#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159732#L298-21 assume !(1 == ~t1_pc~0); 159730#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 159727#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159725#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 159723#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 159721#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159719#L317-21 assume !(1 == ~t2_pc~0); 159717#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 159715#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159713#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159711#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 159709#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159707#L336-21 assume !(1 == ~t3_pc~0); 159705#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 159703#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159699#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159697#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 159695#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159693#L355-21 assume 1 == ~t4_pc~0; 159691#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 159692#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160098#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159681#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 159679#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159677#L374-21 assume !(1 == ~t5_pc~0); 159675#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 159673#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159670#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159668#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 159666#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 159663#L793 assume !(1 == ~M_E~0); 159661#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 159659#L798-1 assume !(1 == ~T2_E~0); 159657#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 159655#L808-1 assume !(1 == ~T4_E~0); 159653#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 159651#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 159649#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 159647#L828-1 assume !(1 == ~E_3~0); 159644#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 159642#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 159638#L843-1 assume { :end_inline_reset_time_events } true; 159637#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 159633#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 159630#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 159628#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 159626#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 159624#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 159620#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 159618#L932 assume !(0 != start_simulation_~tmp___0~1#1); 159616#L900-2 assume !false; 159613#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 159608#L561-1 assume !false; 159606#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 159603#L439 assume !(0 == ~m_st~0); 159604#L443 assume !(0 == ~t1_st~0); 159800#L447 assume !(0 == ~t2_st~0); 159798#L451 assume !(0 == ~t3_st~0); 159796#L455 assume !(0 == ~t4_st~0); 159794#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 159793#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 159791#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 159788#L486 assume !(0 != eval_~tmp~0#1); 159787#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159786#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 159785#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 159783#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 159781#L591-3 assume !(0 == ~T2_E~0); 159779#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 159777#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 159775#L606-3 assume !(0 == ~T5_E~0); 159773#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 159771#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 159769#L621-3 assume !(0 == ~E_3~0); 159767#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159765#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 159762#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159759#L279-18 assume 1 == ~m_pc~0; 159756#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 159753#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159752#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 159748#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159745#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159743#L298-18 assume !(1 == ~t1_pc~0); 159740#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 159735#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159733#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 159731#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 159728#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159726#L317-18 assume !(1 == ~t2_pc~0); 159724#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 159722#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159720#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159718#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 159716#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159714#L336-18 assume !(1 == ~t3_pc~0); 159712#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 159710#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159708#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159706#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 159704#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159702#L355-18 assume !(1 == ~t4_pc~0); 159698#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 159696#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159694#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159690#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 159687#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159685#L374-18 assume !(1 == ~t5_pc~0); 159683#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 159680#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159678#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159676#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 159674#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159671#L649-3 assume !(1 == ~M_E~0); 159669#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 159667#L654-3 assume !(1 == ~T2_E~0); 159665#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 159662#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 159660#L669-3 assume !(1 == ~T5_E~0); 159658#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 159656#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 159654#L684-3 assume !(1 == ~E_3~0); 159652#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 159650#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 159648#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 159645#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 159643#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 159641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 159639#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 159640#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159750#L279-21 assume !(1 == ~m_pc~0); 159751#L279-23 is_master_triggered_~__retres1~0#1 := 0; 162875#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 162873#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 162871#L720-21 assume !(0 != activate_threads_~tmp~1#1); 162869#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 162866#L298-21 assume !(1 == ~t1_pc~0); 162864#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 162861#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 162859#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 162857#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 162855#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162853#L317-21 assume !(1 == ~t2_pc~0); 162850#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 162848#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 162845#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162842#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 162838#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162834#L336-21 assume !(1 == ~t3_pc~0); 162830#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 162824#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 162820#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 162815#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 162810#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 162805#L355-21 assume !(1 == ~t4_pc~0); 162800#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 162803#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162797#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 162754#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 162751#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 162749#L374-21 assume !(1 == ~t5_pc~0); 162747#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 162745#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 162743#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 162741#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 162739#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 162736#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 162737#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 164504#L798-1 assume !(1 == ~T2_E~0); 164502#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 164499#L808-1 assume !(1 == ~T4_E~0); 164497#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 164495#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 164493#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 164491#L828-1 assume !(1 == ~E_3~0); 164490#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 164488#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 164487#L843-1 assume { :end_inline_reset_time_events } true; 164485#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 164481#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 164475#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 164471#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 164467#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 164461#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 164455#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 164448#L932 assume !(0 != start_simulation_~tmp___0~1#1); 158351#L900-2 [2024-10-13 17:46:02,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,802 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 5 times [2024-10-13 17:46:02,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014269186] [2024-10-13 17:46:02,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:02,810 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:02,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:02,819 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:02,820 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1511198758, now seen corresponding path program 1 times [2024-10-13 17:46:02,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740452097] [2024-10-13 17:46:02,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,875 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2024-10-13 17:46:02,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740452097] [2024-10-13 17:46:02,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740452097] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,876 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768003931] [2024-10-13 17:46:02,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,877 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:02,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:02,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:02,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:02,877 INFO L87 Difference]: Start difference. First operand 18736 states and 25446 transitions. cyclomatic complexity: 6726 Second operand has 3 states, 3 states have (on average 69.33333333333333) internal successors, (208), 3 states have internal predecessors, (208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,970 INFO L93 Difference]: Finished difference Result 34890 states and 46861 transitions. [2024-10-13 17:46:02,970 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34890 states and 46861 transitions. [2024-10-13 17:46:03,094 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 34552 [2024-10-13 17:46:03,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34890 states to 34890 states and 46861 transitions. [2024-10-13 17:46:03,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34890 [2024-10-13 17:46:03,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34890 [2024-10-13 17:46:03,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34890 states and 46861 transitions. [2024-10-13 17:46:03,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:03,237 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34890 states and 46861 transitions. [2024-10-13 17:46:03,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34890 states and 46861 transitions. [2024-10-13 17:46:03,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34890 to 32746. [2024-10-13 17:46:03,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32746 states, 32746 states have (on average 1.3489586514383436) internal successors, (44173), 32745 states have internal predecessors, (44173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:03,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32746 states to 32746 states and 44173 transitions. [2024-10-13 17:46:03,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32746 states and 44173 transitions. [2024-10-13 17:46:03,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:03,900 INFO L425 stractBuchiCegarLoop]: Abstraction has 32746 states and 44173 transitions. [2024-10-13 17:46:03,900 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-13 17:46:03,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32746 states and 44173 transitions. [2024-10-13 17:46:03,965 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32408 [2024-10-13 17:46:03,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:03,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:03,968 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:03,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:03,969 INFO L745 eck$LassoCheckResult]: Stem: 211924#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 211925#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 212058#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 212059#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 212077#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 212078#L401-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 211852#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 211853#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 212233#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 212234#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 212170#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 212171#L586 assume !(0 == ~M_E~0); 211875#L586-2 assume !(0 == ~T1_E~0); 211876#L591-1 assume !(0 == ~T2_E~0); 212006#L596-1 assume !(0 == ~T3_E~0); 212007#L601-1 assume !(0 == ~T4_E~0); 212064#L606-1 assume !(0 == ~T5_E~0); 212065#L611-1 assume !(0 == ~E_1~0); 212182#L616-1 assume !(0 == ~E_2~0); 212183#L621-1 assume !(0 == ~E_3~0); 211735#L626-1 assume !(0 == ~E_4~0); 211736#L631-1 assume !(0 == ~E_5~0); 211916#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 211917#L279 assume !(1 == ~m_pc~0); 212102#L279-2 is_master_triggered_~__retres1~0#1 := 0; 212103#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 211888#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 211889#L720 assume !(0 != activate_threads_~tmp~1#1); 212311#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 212312#L298 assume !(1 == ~t1_pc~0); 211684#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 211685#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 211708#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 211709#L728 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 211747#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 211882#L317 assume !(1 == ~t2_pc~0); 211883#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 212306#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 212307#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 211939#L736 assume !(0 != activate_threads_~tmp___1~0#1); 211940#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 212163#L336 assume !(1 == ~t3_pc~0); 212164#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 212313#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 212314#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 212112#L744 assume !(0 != activate_threads_~tmp___2~0#1); 212113#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 212249#L355 assume !(1 == ~t4_pc~0); 212250#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 212330#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 212331#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 212150#L752 assume !(0 != activate_threads_~tmp___3~0#1); 212151#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 212216#L374 assume !(1 == ~t5_pc~0); 212217#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 212235#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 212236#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 212272#L760 assume !(0 != activate_threads_~tmp___4~0#1); 212273#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 212277#L649 assume !(1 == ~M_E~0); 212278#L649-2 assume !(1 == ~T1_E~0); 211718#L654-1 assume !(1 == ~T2_E~0); 211719#L659-1 assume !(1 == ~T3_E~0); 211935#L664-1 assume !(1 == ~T4_E~0); 211936#L669-1 assume !(1 == ~T5_E~0); 212152#L674-1 assume !(1 == ~E_1~0); 212153#L679-1 assume !(1 == ~E_2~0); 211820#L684-1 assume !(1 == ~E_3~0); 211821#L689-1 assume !(1 == ~E_4~0); 211999#L694-1 assume !(1 == ~E_5~0); 211996#L699-1 assume { :end_inline_reset_delta_events } true; 211997#L900-2 [2024-10-13 17:46:03,969 INFO L747 eck$LassoCheckResult]: Loop: 211997#L900-2 assume !false; 222278#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 222270#L561-1 assume !false; 222264#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 222258#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 222252#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 222248#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 222241#L486 assume 0 != eval_~tmp~0#1; 222234#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 222226#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 222227#L65 assume 0 == ~m_pc~0; 221941#L92 assume !false; 222304#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 222296#L279-3 assume !(1 == ~m_pc~0); 222279#L279-5 is_master_triggered_~__retres1~0#1 := 0; 222271#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222265#is_master_triggered_returnLabel#2 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 222260#L720-3 assume !(0 != activate_threads_~tmp~1#1); 222253#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222249#L298-3 assume !(1 == ~t1_pc~0); 222245#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 222237#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222230#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 222222#L728-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 219517#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222210#L317-3 assume !(1 == ~t2_pc~0); 222205#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 222197#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222189#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 222179#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 222171#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222132#L336-3 assume !(1 == ~t3_pc~0); 222123#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 222115#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222103#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 222061#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 222041#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 222035#L355-3 assume !(1 == ~t4_pc~0); 222027#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 222017#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 222009#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 222000#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 221991#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221983#L374-3 assume !(1 == ~t5_pc~0); 221974#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 221966#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221960#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 221952#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 221946#L760-5 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 221939#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 221933#$Ultimate##223 assume !false; 221928#L85 ~m_pc~0 := 1;~m_st~0 := 2; 221923#master_returnLabel#1 assume { :end_inline_master } true; 221856#L494-2 havoc eval_~tmp_ndt_1~0#1; 219732#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 219345#L508 assume 0 != eval_~tmp_ndt_2~0#1;~t1_st~0 := 1;assume { :begin_inline_transmit1 } true; 219550#L106 assume 0 == ~t1_pc~0; 219545#L117-1 assume !false; 219542#L118 ~t1_pc~0 := 1;~t1_st~0 := 2; 219541#transmit1_returnLabel#1 assume { :end_inline_transmit1 } true; 219342#L508-2 havoc eval_~tmp_ndt_2~0#1; 219343#L505-1 assume !(0 == ~t2_st~0); 219329#L519-1 assume !(0 == ~t3_st~0); 219330#L533-1 assume !(0 == ~t4_st~0); 219265#L547-1 assume !(0 == ~t5_st~0); 219262#L561-1 assume !false; 219260#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 219257#L439 assume !(0 == ~m_st~0); 219254#L443 assume !(0 == ~t1_st~0); 219252#L447 assume !(0 == ~t2_st~0); 219250#L451 assume !(0 == ~t3_st~0); 219248#L455 assume !(0 == ~t4_st~0); 219245#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 219243#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 219241#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 219238#L486 assume !(0 != eval_~tmp~0#1); 219236#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 219234#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 219230#L586-3 assume !(0 == ~M_E~0); 219228#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 219226#L591-3 assume !(0 == ~T2_E~0); 219224#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 219221#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 219219#L606-3 assume !(0 == ~T5_E~0); 219217#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 219215#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 219213#L621-3 assume !(0 == ~E_3~0); 219211#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 219209#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 219207#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 219202#L279-18 assume 1 == ~m_pc~0; 219200#L280-6 assume !(1 == ~M_E~0); 219199#L279-20 is_master_triggered_~__retres1~0#1 := 0; 219198#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 219196#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 219195#L720-18 assume !(0 != activate_threads_~tmp~1#1); 219194#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 219193#L298-18 assume 1 == ~t1_pc~0; 219191#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 219189#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 219188#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 219187#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 219185#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 219183#L317-18 assume !(1 == ~t2_pc~0); 219181#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 219179#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219177#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 219175#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 219173#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 219171#L336-18 assume !(1 == ~t3_pc~0); 219169#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 219167#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 219165#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 219163#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 219161#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 219157#L355-18 assume 1 == ~t4_pc~0; 219155#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 219156#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 219197#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 219145#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 219143#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 219141#L374-18 assume !(1 == ~t5_pc~0); 219139#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 219137#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 219135#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 219133#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 219131#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219129#L649-3 assume !(1 == ~M_E~0); 216538#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 219127#L654-3 assume !(1 == ~T2_E~0); 219125#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 219123#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 219121#L669-3 assume !(1 == ~T5_E~0); 219119#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 219117#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 219115#L684-3 assume !(1 == ~E_3~0); 219113#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 219111#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 219109#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216782#L439-1 assume !(0 == ~m_st~0); 216779#L443-1 assume !(0 == ~t1_st~0); 216777#L447-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 216773#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 216771#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 216768#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 216501#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216764#L279-21 assume 1 == ~m_pc~0; 216761#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 216759#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216757#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 216739#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 216738#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216737#L298-21 assume !(1 == ~t1_pc~0); 216736#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 216734#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216732#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216730#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 216729#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216728#L317-21 assume !(1 == ~t2_pc~0); 216726#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 216724#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216722#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 216720#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 216718#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216716#L336-21 assume !(1 == ~t3_pc~0); 216714#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 216712#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216710#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 216708#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 216706#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216704#L355-21 assume 1 == ~t4_pc~0; 216702#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 216703#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216733#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 216691#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 216689#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216687#L374-21 assume !(1 == ~t5_pc~0); 216685#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 216683#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216680#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 216678#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 216676#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 216672#L793 assume !(1 == ~M_E~0); 216670#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 216668#L798-1 assume !(1 == ~T2_E~0); 216666#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 216664#L808-1 assume !(1 == ~T4_E~0); 216662#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 216660#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 216658#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 216656#L828-1 assume !(1 == ~E_3~0); 216654#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 216652#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 216354#L843-1 assume { :end_inline_reset_time_events } true; 216276#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216274#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 216273#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 216272#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 216270#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 216242#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 216235#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 216228#L932 assume !(0 != start_simulation_~tmp___0~1#1); 216219#L900-2 assume !false; 216209#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 216201#L561-1 assume !false; 216193#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216186#L439 assume !(0 == ~m_st~0); 216187#L443 assume !(0 == ~t1_st~0); 215238#L447 assume !(0 == ~t2_st~0); 215239#L451 assume !(0 == ~t3_st~0); 215240#L455 assume !(0 == ~t4_st~0); 215236#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 215237#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 216198#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 215228#L486 assume !(0 != eval_~tmp~0#1); 215229#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 216727#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 216725#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 216723#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 216721#L591-3 assume !(0 == ~T2_E~0); 216719#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 216717#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 216715#L606-3 assume !(0 == ~T5_E~0); 216713#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 216711#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 216709#L621-3 assume !(0 == ~E_3~0); 216707#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 216705#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 216701#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216698#L279-18 assume 1 == ~m_pc~0; 216695#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 216693#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216690#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 216688#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 216686#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216684#L298-18 assume 1 == ~t1_pc~0; 216682#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 216679#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216677#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216674#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 216675#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 218186#L317-18 assume !(1 == ~t2_pc~0); 218184#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 218183#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 218181#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 218179#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 218177#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 218175#L336-18 assume !(1 == ~t3_pc~0); 218173#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 218171#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 218169#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 218167#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 218165#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 218163#L355-18 assume 1 == ~t4_pc~0; 218161#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 218162#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 218197#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 218150#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 218148#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 218146#L374-18 assume !(1 == ~t5_pc~0); 218143#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 218141#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 218139#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 218137#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 218135#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 218132#L649-3 assume !(1 == ~M_E~0); 218130#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 218128#L654-3 assume !(1 == ~T2_E~0); 218125#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 218123#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 218121#L669-3 assume !(1 == ~T5_E~0); 218119#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 218117#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 218115#L684-3 assume !(1 == ~E_3~0); 218113#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 218111#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 218109#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 218106#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 218104#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 218103#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 218102#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 216802#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216800#L279-21 assume !(1 == ~m_pc~0); 216797#L279-23 is_master_triggered_~__retres1~0#1 := 0; 216793#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216789#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 216788#L720-21 assume !(0 != activate_threads_~tmp~1#1); 216787#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216786#L298-21 assume !(1 == ~t1_pc~0); 216785#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 216783#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216781#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216778#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 216032#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216772#L317-21 assume !(1 == ~t2_pc~0); 216770#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 216767#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216766#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 216763#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 216760#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216758#L336-21 assume !(1 == ~t3_pc~0); 216756#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 216755#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216754#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 216752#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 216751#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216749#L355-21 assume !(1 == ~t4_pc~0); 216747#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 216951#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216944#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 216352#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 216349#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216344#L374-21 assume !(1 == ~t5_pc~0); 216342#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 216340#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216337#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 216335#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 216333#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 216330#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 216331#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 222383#L798-1 assume !(1 == ~T2_E~0); 222377#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 222371#L808-1 assume !(1 == ~T4_E~0); 222362#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 222357#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 222351#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 222346#L828-1 assume !(1 == ~E_3~0); 222343#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 222338#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 222335#L843-1 assume { :end_inline_reset_time_events } true; 222334#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 222332#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 222331#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 222316#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 222310#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222303#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 222295#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 222294#L932 assume !(0 != start_simulation_~tmp___0~1#1); 211997#L900-2 [2024-10-13 17:46:03,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,970 INFO L85 PathProgramCache]: Analyzing trace with hash -148144228, now seen corresponding path program 1 times [2024-10-13 17:46:03,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137604888] [2024-10-13 17:46:03,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:03,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:03,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,990 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,991 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2137604888] [2024-10-13 17:46:03,991 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2137604888] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,991 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,991 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:03,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74843996] [2024-10-13 17:46:03,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,992 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:03,992 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,992 INFO L85 PathProgramCache]: Analyzing trace with hash -215099974, now seen corresponding path program 1 times [2024-10-13 17:46:03,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599488097] [2024-10-13 17:46:03,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:04,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:04,047 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2024-10-13 17:46:04,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:04,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599488097] [2024-10-13 17:46:04,048 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1599488097] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:04,048 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:04,048 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:04,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893243404] [2024-10-13 17:46:04,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:04,049 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:04,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:04,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:04,050 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:04,050 INFO L87 Difference]: Start difference. First operand 32746 states and 44173 transitions. cyclomatic complexity: 11443 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:04,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:04,117 INFO L93 Difference]: Finished difference Result 32676 states and 44077 transitions. [2024-10-13 17:46:04,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32676 states and 44077 transitions. [2024-10-13 17:46:04,349 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32408 [2024-10-13 17:46:04,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32676 states to 32676 states and 44077 transitions. [2024-10-13 17:46:04,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32676 [2024-10-13 17:46:04,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32676 [2024-10-13 17:46:04,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32676 states and 44077 transitions. [2024-10-13 17:46:04,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:04,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32676 states and 44077 transitions. [2024-10-13 17:46:04,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32676 states and 44077 transitions. [2024-10-13 17:46:04,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32676 to 32676. [2024-10-13 17:46:04,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32676 states, 32676 states have (on average 1.3489105153629575) internal successors, (44077), 32675 states have internal predecessors, (44077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:04,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32676 states to 32676 states and 44077 transitions. [2024-10-13 17:46:04,771 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32676 states and 44077 transitions. [2024-10-13 17:46:04,772 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:04,772 INFO L425 stractBuchiCegarLoop]: Abstraction has 32676 states and 44077 transitions. [2024-10-13 17:46:04,772 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-13 17:46:04,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32676 states and 44077 transitions. [2024-10-13 17:46:04,856 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32408 [2024-10-13 17:46:04,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:04,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:04,860 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:04,860 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:04,860 INFO L745 eck$LassoCheckResult]: Stem: 277344#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 277345#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 277471#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 277472#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 277490#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 277491#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 277279#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 277280#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 277607#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 277608#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 277565#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 277247#L586 assume !(0 == ~M_E~0); 277248#L586-2 assume !(0 == ~T1_E~0); 277301#L591-1 assume !(0 == ~T2_E~0); 277424#L596-1 assume !(0 == ~T3_E~0); 277425#L601-1 assume !(0 == ~T4_E~0); 277476#L606-1 assume !(0 == ~T5_E~0); 277477#L611-1 assume !(0 == ~E_1~0); 277575#L616-1 assume !(0 == ~E_2~0); 277576#L621-1 assume !(0 == ~E_3~0); 277165#L626-1 assume !(0 == ~E_4~0); 277166#L631-1 assume !(0 == ~E_5~0); 277339#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 277163#L279 assume !(1 == ~m_pc~0); 277164#L279-2 is_master_triggered_~__retres1~0#1 := 0; 277504#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 277313#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 277314#L720 assume !(0 != activate_threads_~tmp~1#1); 277503#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 277346#L298 assume !(1 == ~t1_pc~0); 277113#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 277114#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 277137#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 277138#L728 assume !(0 != activate_threads_~tmp___0~0#1); 277176#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 277307#L317 assume !(1 == ~t2_pc~0); 277308#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 277527#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 277475#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 277357#L736 assume !(0 != activate_threads_~tmp___1~0#1); 277358#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 277559#L336 assume !(1 == ~t3_pc~0); 277560#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 277646#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 277086#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 277087#L744 assume !(0 != activate_threads_~tmp___2~0#1); 277513#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 277571#L355 assume !(1 == ~t4_pc~0); 277423#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 277567#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 277208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 277209#L752 assume !(0 != activate_threads_~tmp___3~0#1); 277190#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 277191#L374 assume !(1 == ~t5_pc~0); 277330#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 277331#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 277319#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 277320#L760 assume !(0 != activate_threads_~tmp___4~0#1); 277456#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277457#L649 assume !(1 == ~M_E~0); 277635#L649-2 assume !(1 == ~T1_E~0); 277147#L654-1 assume !(1 == ~T2_E~0); 277148#L659-1 assume !(1 == ~T3_E~0); 277354#L664-1 assume !(1 == ~T4_E~0); 277139#L669-1 assume !(1 == ~T5_E~0); 277140#L674-1 assume !(1 == ~E_1~0); 277550#L679-1 assume !(1 == ~E_2~0); 277249#L684-1 assume !(1 == ~E_3~0); 277250#L689-1 assume !(1 == ~E_4~0); 277418#L694-1 assume !(1 == ~E_5~0); 277414#L699-1 assume { :end_inline_reset_delta_events } true; 277415#L900-2 [2024-10-13 17:46:04,861 INFO L747 eck$LassoCheckResult]: Loop: 277415#L900-2 assume !false; 286620#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 286616#L561-1 assume !false; 286615#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 286613#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 286612#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 286609#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 286607#L486 assume 0 != eval_~tmp~0#1; 286604#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 286601#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 286597#L65 assume 0 == ~m_pc~0; 286510#L92 assume !false; 286594#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286591#L279-3 assume !(1 == ~m_pc~0); 286589#L279-5 is_master_triggered_~__retres1~0#1 := 0; 286587#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 286584#is_master_triggered_returnLabel#2 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 286582#L720-3 assume !(0 != activate_threads_~tmp~1#1); 286580#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 286578#L298-3 assume !(1 == ~t1_pc~0); 286576#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 286573#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 286571#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 286569#L728-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 286565#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 286563#L317-3 assume !(1 == ~t2_pc~0); 286561#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 286559#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 286557#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 286555#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 286553#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 286550#L336-3 assume !(1 == ~t3_pc~0); 286548#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 286546#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 286543#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 286541#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 286539#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 286537#L355-3 assume !(1 == ~t4_pc~0); 286533#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 286531#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 286529#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 286527#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 286522#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 286520#L374-3 assume !(1 == ~t5_pc~0); 286518#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 286517#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 286514#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 286513#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 286512#L760-5 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 286508#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 286505#$Ultimate##223 assume !false; 286501#L85 ~m_pc~0 := 1;~m_st~0 := 2; 286498#master_returnLabel#1 assume { :end_inline_master } true; 286486#L494-2 havoc eval_~tmp_ndt_1~0#1; 286061#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 286481#L508 assume 0 != eval_~tmp_ndt_2~0#1;~t1_st~0 := 1;assume { :begin_inline_transmit1 } true; 286482#L106 assume 0 == ~t1_pc~0; 286958#L117-1 assume !false; 286956#L118 ~t1_pc~0 := 1;~t1_st~0 := 2; 286954#transmit1_returnLabel#1 assume { :end_inline_transmit1 } true; 286483#L508-2 havoc eval_~tmp_ndt_2~0#1; 286406#L505-1 assume !(0 == ~t2_st~0); 286407#L519-1 assume !(0 == ~t3_st~0); 286503#L533-1 assume !(0 == ~t4_st~0); 286499#L547-1 assume !(0 == ~t5_st~0); 286500#L561-1 assume !false; 287788#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 287519#L439 assume !(0 == ~m_st~0); 285883#L443 assume !(0 == ~t1_st~0); 288415#L447 assume !(0 == ~t2_st~0); 288416#L451 assume !(0 == ~t3_st~0); 288417#L455 assume !(0 == ~t4_st~0); 288413#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 288291#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 288292#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 288560#L486 assume !(0 != eval_~tmp~0#1); 288557#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 288555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 288553#L586-3 assume !(0 == ~M_E~0); 288551#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 288549#L591-3 assume !(0 == ~T2_E~0); 288547#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 288545#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 288473#L606-3 assume !(0 == ~T5_E~0); 288384#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 288383#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 288382#L621-3 assume !(0 == ~E_3~0); 288380#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 288379#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 288378#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 288375#L279-18 assume 1 == ~m_pc~0; 288373#L280-6 assume !(1 == ~M_E~0); 288371#L279-20 is_master_triggered_~__retres1~0#1 := 0; 288369#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 288367#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 288365#L720-18 assume !(0 != activate_threads_~tmp~1#1); 288363#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 288361#L298-18 assume !(1 == ~t1_pc~0); 288349#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 288347#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 288345#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 288341#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 288339#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 288337#L317-18 assume !(1 == ~t2_pc~0); 288335#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 288333#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 288331#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 288329#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 288327#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 288325#L336-18 assume !(1 == ~t3_pc~0); 288324#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 288322#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 288320#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 288319#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 288318#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 288198#L355-18 assume 1 == ~t4_pc~0; 288196#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 288195#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 288193#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 288191#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 288187#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 288184#L374-18 assume !(1 == ~t5_pc~0); 288181#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 288178#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 288175#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 288172#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 288169#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 288165#L649-3 assume !(1 == ~M_E~0); 287627#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 288130#L654-3 assume !(1 == ~T2_E~0); 288129#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 288128#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 288126#L669-3 assume !(1 == ~T5_E~0); 288124#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 288122#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 288120#L684-3 assume !(1 == ~E_3~0); 288118#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 288116#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 288114#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 287517#L439-1 assume !(0 == ~m_st~0); 287516#L443-1 assume !(0 == ~t1_st~0); 287515#L447-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 287511#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 287510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 282283#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 282282#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 282280#L279-21 assume 1 == ~m_pc~0; 282278#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 282277#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 282275#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 282266#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 282265#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282264#L298-21 assume 1 == ~t1_pc~0; 282260#L299-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 282258#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 282255#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 282203#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 282204#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 287406#L317-21 assume !(1 == ~t2_pc~0); 287405#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 287404#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 287402#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 287400#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 287398#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 287396#L336-21 assume !(1 == ~t3_pc~0); 287394#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 282848#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 282845#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 282843#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 282841#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 282839#L355-21 assume 1 == ~t4_pc~0; 282837#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 282838#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 283036#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 282826#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 282824#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 282821#L374-21 assume !(1 == ~t5_pc~0); 282819#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 282817#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 282815#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 282813#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 282811#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 282808#L793 assume !(1 == ~M_E~0); 282806#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 282803#L798-1 assume !(1 == ~T2_E~0); 282801#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 282799#L808-1 assume !(1 == ~T4_E~0); 282797#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 282795#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 282793#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 282791#L828-1 assume !(1 == ~E_3~0); 282789#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 282787#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 282775#L843-1 assume { :end_inline_reset_time_events } true; 282773#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 282771#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 282769#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 282767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 282765#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 282763#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 279512#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 279509#L932 assume !(0 != start_simulation_~tmp___0~1#1); 279507#L900-2 assume !false; 279505#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279500#L561-1 assume !false; 279498#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 279496#L439 assume !(0 == ~m_st~0); 279497#L443 assume !(0 == ~t1_st~0); 282206#L447 assume !(0 == ~t2_st~0); 282202#L451 assume !(0 == ~t3_st~0); 282200#L455 assume !(0 == ~t4_st~0); 282197#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 282195#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 282193#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 282191#L486 assume !(0 != eval_~tmp~0#1); 282189#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 282187#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282185#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 282183#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 282181#L591-3 assume !(0 == ~T2_E~0); 282179#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 282177#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 282175#L606-3 assume !(0 == ~T5_E~0); 282171#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 282169#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 282167#L621-3 assume !(0 == ~E_3~0); 282165#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 282162#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 282160#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 282157#L279-18 assume 1 == ~m_pc~0; 282154#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 282152#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 282150#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 282147#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 282145#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282142#L298-18 assume 1 == ~t1_pc~0; 282140#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 282137#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 282135#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 282132#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 282133#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 287403#L317-18 assume !(1 == ~t2_pc~0); 287401#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 287399#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 287397#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 287395#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 287393#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 287392#L336-18 assume !(1 == ~t3_pc~0); 287390#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 287388#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 287386#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 287384#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 287382#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 282834#L355-18 assume 1 == ~t4_pc~0; 282832#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 282833#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 283041#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 282822#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 282820#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 282818#L374-18 assume !(1 == ~t5_pc~0); 282816#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 282814#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 282812#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 282810#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 282807#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 282804#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 282805#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 287596#L654-3 assume !(1 == ~T2_E~0); 287584#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 287578#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 287573#L669-3 assume !(1 == ~T5_E~0); 287567#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 287561#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 287552#L684-3 assume !(1 == ~E_3~0); 287546#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 287541#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 287534#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 287527#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 287522#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 287518#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 280333#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 280330#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 280327#L279-21 assume !(1 == ~m_pc~0); 280325#L279-23 is_master_triggered_~__retres1~0#1 := 0; 280323#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 280321#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 280319#L720-21 assume !(0 != activate_threads_~tmp~1#1); 280318#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 280317#L298-21 assume !(1 == ~t1_pc~0); 280316#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 280313#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 280311#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 280304#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 280302#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 280300#L317-21 assume !(1 == ~t2_pc~0); 280298#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 280296#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 280294#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 280292#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 280290#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 280288#L336-21 assume !(1 == ~t3_pc~0); 280286#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 280284#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 280282#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 280280#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 280277#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280275#L355-21 assume 1 == ~t4_pc~0; 280272#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 280269#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 280267#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 280168#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 280166#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 280164#L374-21 assume !(1 == ~t5_pc~0); 280162#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 280160#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 280158#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 280156#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 280154#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 280150#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 280151#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 286664#L798-1 assume !(1 == ~T2_E~0); 286662#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 286658#L808-1 assume !(1 == ~T4_E~0); 286657#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 286655#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 286651#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 286647#L828-1 assume !(1 == ~E_3~0); 286645#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 286643#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 286641#L843-1 assume { :end_inline_reset_time_events } true; 286639#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 286636#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 286634#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 286632#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 286630#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 286628#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 286626#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 286623#L932 assume !(0 != start_simulation_~tmp___0~1#1); 277415#L900-2 [2024-10-13 17:46:04,861 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:04,862 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 6 times [2024-10-13 17:46:04,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:04,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282217291] [2024-10-13 17:46:04,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:04,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:04,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:04,869 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:04,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:04,879 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:04,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:04,880 INFO L85 PathProgramCache]: Analyzing trace with hash 248412479, now seen corresponding path program 1 times [2024-10-13 17:46:04,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:04,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566628880] [2024-10-13 17:46:04,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:04,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:04,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:04,933 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 131 trivial. 0 not checked. [2024-10-13 17:46:04,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:04,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566628880] [2024-10-13 17:46:04,934 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [566628880] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:04,934 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:04,934 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:04,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [518326378] [2024-10-13 17:46:04,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:04,935 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:04,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:04,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:04,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:04,935 INFO L87 Difference]: Start difference. First operand 32676 states and 44077 transitions. cyclomatic complexity: 11417 Second operand has 3 states, 3 states have (on average 72.66666666666667) internal successors, (218), 3 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:05,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:05,213 INFO L93 Difference]: Finished difference Result 36952 states and 49475 transitions. [2024-10-13 17:46:05,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36952 states and 49475 transitions. [2024-10-13 17:46:05,356 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 36342 [2024-10-13 17:46:05,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36952 states to 36952 states and 49475 transitions. [2024-10-13 17:46:05,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36952 [2024-10-13 17:46:05,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36952 [2024-10-13 17:46:05,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36952 states and 49475 transitions. [2024-10-13 17:46:05,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:05,506 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36952 states and 49475 transitions. [2024-10-13 17:46:05,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36952 states and 49475 transitions. [2024-10-13 17:46:05,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36952 to 35224. [2024-10-13 17:46:05,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35224 states, 35224 states have (on average 1.342806041335453) internal successors, (47299), 35223 states have internal predecessors, (47299), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:05,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35224 states to 35224 states and 47299 transitions. [2024-10-13 17:46:05,941 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35224 states and 47299 transitions. [2024-10-13 17:46:05,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:05,941 INFO L425 stractBuchiCegarLoop]: Abstraction has 35224 states and 47299 transitions. [2024-10-13 17:46:05,941 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-13 17:46:05,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35224 states and 47299 transitions. [2024-10-13 17:46:06,031 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 34614 [2024-10-13 17:46:06,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:06,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:06,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:06,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:06,033 INFO L745 eck$LassoCheckResult]: Stem: 346979#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 346980#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 347106#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 347107#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 347128#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 347129#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 346909#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 346910#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 347257#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 347258#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 347211#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 346877#L586 assume !(0 == ~M_E~0); 346878#L586-2 assume !(0 == ~T1_E~0); 346932#L591-1 assume !(0 == ~T2_E~0); 347059#L596-1 assume !(0 == ~T3_E~0); 347060#L601-1 assume !(0 == ~T4_E~0); 347113#L606-1 assume !(0 == ~T5_E~0); 347114#L611-1 assume !(0 == ~E_1~0); 347223#L616-1 assume !(0 == ~E_2~0); 347224#L621-1 assume !(0 == ~E_3~0); 346798#L626-1 assume !(0 == ~E_4~0); 346799#L631-1 assume !(0 == ~E_5~0); 346972#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 346796#L279 assume !(1 == ~m_pc~0); 346797#L279-2 is_master_triggered_~__retres1~0#1 := 0; 347145#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 346944#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 346945#L720 assume !(0 != activate_threads_~tmp~1#1); 347144#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 346981#L298 assume !(1 == ~t1_pc~0); 346746#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 346747#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 346770#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 346771#L728 assume !(0 != activate_threads_~tmp___0~0#1); 346807#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 346938#L317 assume !(1 == ~t2_pc~0); 346939#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 347168#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 347112#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 346992#L736 assume !(0 != activate_threads_~tmp___1~0#1); 346993#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 347205#L336 assume !(1 == ~t3_pc~0); 347206#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 347303#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 346719#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 346720#L744 assume !(0 != activate_threads_~tmp___2~0#1); 347153#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 347217#L355 assume !(1 == ~t4_pc~0); 347058#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 347214#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 346838#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 346839#L752 assume !(0 != activate_threads_~tmp___3~0#1); 346820#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 346821#L374 assume !(1 == ~t5_pc~0); 346965#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 346966#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 346951#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 346952#L760 assume !(0 != activate_threads_~tmp___4~0#1); 347094#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 347095#L649 assume !(1 == ~M_E~0); 347289#L649-2 assume !(1 == ~T1_E~0); 346780#L654-1 assume !(1 == ~T2_E~0); 346781#L659-1 assume !(1 == ~T3_E~0); 346989#L664-1 assume !(1 == ~T4_E~0); 346772#L669-1 assume !(1 == ~T5_E~0); 346773#L674-1 assume !(1 == ~E_1~0); 347195#L679-1 assume !(1 == ~E_2~0); 346879#L684-1 assume !(1 == ~E_3~0); 346880#L689-1 assume !(1 == ~E_4~0); 347053#L694-1 assume !(1 == ~E_5~0); 347050#L699-1 assume { :end_inline_reset_delta_events } true; 347051#L900-2 assume !false; 364361#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 364357#L561-1 [2024-10-13 17:46:06,033 INFO L747 eck$LassoCheckResult]: Loop: 364357#L561-1 assume !false; 364356#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 364354#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 364353#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 364351#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 364349#L486 assume 0 != eval_~tmp~0#1; 364346#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 364343#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 364341#L494-2 havoc eval_~tmp_ndt_1~0#1; 364339#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 364268#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 364337#L508-2 havoc eval_~tmp_ndt_2~0#1; 364381#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 364376#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 364374#L522-2 havoc eval_~tmp_ndt_3~0#1; 364367#L519-1 assume !(0 == ~t3_st~0); 364365#L533-1 assume !(0 == ~t4_st~0); 364359#L547-1 assume !(0 == ~t5_st~0); 364357#L561-1 [2024-10-13 17:46:06,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:06,034 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 1 times [2024-10-13 17:46:06,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:06,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812946575] [2024-10-13 17:46:06,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:06,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:06,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:06,042 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:06,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:06,053 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:06,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:06,053 INFO L85 PathProgramCache]: Analyzing trace with hash 990378971, now seen corresponding path program 1 times [2024-10-13 17:46:06,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:06,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750609917] [2024-10-13 17:46:06,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:06,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:06,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:06,057 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:06,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:06,059 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:06,059 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:06,059 INFO L85 PathProgramCache]: Analyzing trace with hash 597526840, now seen corresponding path program 1 times [2024-10-13 17:46:06,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:06,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569321828] [2024-10-13 17:46:06,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:06,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:06,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:06,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:06,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:06,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569321828] [2024-10-13 17:46:06,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569321828] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:06,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:06,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:06,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386897690] [2024-10-13 17:46:06,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:06,162 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:06,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:06,163 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:06,163 INFO L87 Difference]: Start difference. First operand 35224 states and 47299 transitions. cyclomatic complexity: 12095 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:06,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:06,413 INFO L93 Difference]: Finished difference Result 41005 states and 54644 transitions. [2024-10-13 17:46:06,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41005 states and 54644 transitions. [2024-10-13 17:46:06,550 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 39793 [2024-10-13 17:46:06,644 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41005 states to 41005 states and 54644 transitions. [2024-10-13 17:46:06,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41005 [2024-10-13 17:46:06,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41005 [2024-10-13 17:46:06,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41005 states and 54644 transitions. [2024-10-13 17:46:06,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:06,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41005 states and 54644 transitions. [2024-10-13 17:46:06,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41005 states and 54644 transitions. [2024-10-13 17:46:07,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41005 to 39447. [2024-10-13 17:46:07,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39447 states, 39447 states have (on average 1.336121885060968) internal successors, (52706), 39446 states have internal predecessors, (52706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:07,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39447 states to 39447 states and 52706 transitions. [2024-10-13 17:46:07,171 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39447 states and 52706 transitions. [2024-10-13 17:46:07,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:07,171 INFO L425 stractBuchiCegarLoop]: Abstraction has 39447 states and 52706 transitions. [2024-10-13 17:46:07,171 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-13 17:46:07,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39447 states and 52706 transitions. [2024-10-13 17:46:07,414 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 38235 [2024-10-13 17:46:07,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:07,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:07,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:07,414 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:07,415 INFO L745 eck$LassoCheckResult]: Stem: 423214#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 423215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 423338#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 423339#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 423357#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 423358#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 423148#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 423149#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 423488#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 423489#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 423441#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 423116#L586 assume !(0 == ~M_E~0); 423117#L586-2 assume !(0 == ~T1_E~0); 423171#L591-1 assume !(0 == ~T2_E~0); 423295#L596-1 assume !(0 == ~T3_E~0); 423296#L601-1 assume !(0 == ~T4_E~0); 423343#L606-1 assume !(0 == ~T5_E~0); 423344#L611-1 assume !(0 == ~E_1~0); 423451#L616-1 assume !(0 == ~E_2~0); 423452#L621-1 assume !(0 == ~E_3~0); 423036#L626-1 assume !(0 == ~E_4~0); 423037#L631-1 assume !(0 == ~E_5~0); 423209#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 423034#L279 assume !(1 == ~m_pc~0); 423035#L279-2 is_master_triggered_~__retres1~0#1 := 0; 423376#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 423182#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 423183#L720 assume !(0 != activate_threads_~tmp~1#1); 423375#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 423216#L298 assume !(1 == ~t1_pc~0); 422984#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 422985#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 423008#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 423009#L728 assume !(0 != activate_threads_~tmp___0~0#1); 423045#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 423176#L317 assume !(1 == ~t2_pc~0); 423177#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 423398#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 423342#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 423227#L736 assume !(0 != activate_threads_~tmp___1~0#1); 423228#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 423435#L336 assume !(1 == ~t3_pc~0); 423436#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 423531#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 422957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 422958#L744 assume !(0 != activate_threads_~tmp___2~0#1); 423384#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 423445#L355 assume !(1 == ~t4_pc~0); 423294#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 423442#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 423077#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 423078#L752 assume !(0 != activate_threads_~tmp___3~0#1); 423059#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423060#L374 assume !(1 == ~t5_pc~0); 423202#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 423203#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 423188#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 423189#L760 assume !(0 != activate_threads_~tmp___4~0#1); 423326#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 423327#L649 assume !(1 == ~M_E~0); 423523#L649-2 assume !(1 == ~T1_E~0); 423018#L654-1 assume !(1 == ~T2_E~0); 423019#L659-1 assume !(1 == ~T3_E~0); 423224#L664-1 assume !(1 == ~T4_E~0); 423010#L669-1 assume !(1 == ~T5_E~0); 423011#L674-1 assume !(1 == ~E_1~0); 423424#L679-1 assume !(1 == ~E_2~0); 423118#L684-1 assume !(1 == ~E_3~0); 423119#L689-1 assume !(1 == ~E_4~0); 423289#L694-1 assume !(1 == ~E_5~0); 423285#L699-1 assume { :end_inline_reset_delta_events } true; 423286#L900-2 assume !false; 446598#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 446594#L561-1 [2024-10-13 17:46:07,415 INFO L747 eck$LassoCheckResult]: Loop: 446594#L561-1 assume !false; 446593#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 446591#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 446590#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 446588#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 446586#L486 assume 0 != eval_~tmp~0#1; 446584#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 446582#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 446581#L494-2 havoc eval_~tmp_ndt_1~0#1; 446579#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 445938#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 446577#L508-2 havoc eval_~tmp_ndt_2~0#1; 446618#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 446616#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 446613#L522-2 havoc eval_~tmp_ndt_3~0#1; 446611#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 446608#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 446606#L536-2 havoc eval_~tmp_ndt_4~0#1; 446603#L533-1 assume !(0 == ~t4_st~0); 446596#L547-1 assume !(0 == ~t5_st~0); 446594#L561-1 [2024-10-13 17:46:07,416 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:07,416 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 2 times [2024-10-13 17:46:07,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:07,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316342885] [2024-10-13 17:46:07,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:07,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:07,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:07,425 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:07,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:07,435 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:07,435 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:07,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1898656693, now seen corresponding path program 1 times [2024-10-13 17:46:07,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:07,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924428804] [2024-10-13 17:46:07,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:07,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:07,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:07,439 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:07,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:07,441 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:07,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:07,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1472432536, now seen corresponding path program 1 times [2024-10-13 17:46:07,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:07,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012433186] [2024-10-13 17:46:07,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:07,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:07,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:07,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:07,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:07,476 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1012433186] [2024-10-13 17:46:07,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1012433186] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:07,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:07,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:07,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070604079] [2024-10-13 17:46:07,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:07,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:07,537 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:07,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:07,537 INFO L87 Difference]: Start difference. First operand 39447 states and 52706 transitions. cyclomatic complexity: 13281 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:07,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:07,734 INFO L93 Difference]: Finished difference Result 69500 states and 92591 transitions. [2024-10-13 17:46:07,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69500 states and 92591 transitions. [2024-10-13 17:46:08,035 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 67154 [2024-10-13 17:46:08,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69500 states to 69500 states and 92591 transitions. [2024-10-13 17:46:08,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69500 [2024-10-13 17:46:08,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69500 [2024-10-13 17:46:08,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69500 states and 92591 transitions. [2024-10-13 17:46:08,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:08,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69500 states and 92591 transitions. [2024-10-13 17:46:08,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69500 states and 92591 transitions. [2024-10-13 17:46:09,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69500 to 67526. [2024-10-13 17:46:09,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67526 states, 67526 states have (on average 1.3363889464798744) internal successors, (90241), 67525 states have internal predecessors, (90241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:09,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67526 states to 67526 states and 90241 transitions. [2024-10-13 17:46:09,193 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67526 states and 90241 transitions. [2024-10-13 17:46:09,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:09,194 INFO L425 stractBuchiCegarLoop]: Abstraction has 67526 states and 90241 transitions. [2024-10-13 17:46:09,194 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-13 17:46:09,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67526 states and 90241 transitions. [2024-10-13 17:46:09,370 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 65180 [2024-10-13 17:46:09,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:09,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:09,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:09,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:09,371 INFO L745 eck$LassoCheckResult]: Stem: 532176#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 532177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 532313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 532314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 532333#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 532334#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 532104#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 532105#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 532478#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 532479#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 532418#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 532069#L586 assume !(0 == ~M_E~0); 532070#L586-2 assume !(0 == ~T1_E~0); 532129#L591-1 assume !(0 == ~T2_E~0); 532266#L596-1 assume !(0 == ~T3_E~0); 532267#L601-1 assume !(0 == ~T4_E~0); 532318#L606-1 assume !(0 == ~T5_E~0); 532319#L611-1 assume !(0 == ~E_1~0); 532433#L616-1 assume !(0 == ~E_2~0); 532434#L621-1 assume !(0 == ~E_3~0); 531990#L626-1 assume !(0 == ~E_4~0); 531991#L631-1 assume !(0 == ~E_5~0); 532169#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 531988#L279 assume !(1 == ~m_pc~0); 531989#L279-2 is_master_triggered_~__retres1~0#1 := 0; 532351#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 532140#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 532141#L720 assume !(0 != activate_threads_~tmp~1#1); 532350#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 532178#L298 assume !(1 == ~t1_pc~0); 531937#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 531938#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 531961#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 531962#L728 assume !(0 != activate_threads_~tmp___0~0#1); 532000#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 532134#L317 assume !(1 == ~t2_pc~0); 532135#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 532373#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 532317#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 532187#L736 assume !(0 != activate_threads_~tmp___1~0#1); 532188#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 532410#L336 assume !(1 == ~t3_pc~0); 532411#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 532537#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 531911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 531912#L744 assume !(0 != activate_threads_~tmp___2~0#1); 532359#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 532424#L355 assume !(1 == ~t4_pc~0); 532263#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 532423#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 532031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 532032#L752 assume !(0 != activate_threads_~tmp___3~0#1); 532013#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 532014#L374 assume !(1 == ~t5_pc~0); 532157#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 532158#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 532146#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 532147#L760 assume !(0 != activate_threads_~tmp___4~0#1); 532302#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 532303#L649 assume !(1 == ~M_E~0); 532523#L649-2 assume !(1 == ~T1_E~0); 531971#L654-1 assume !(1 == ~T2_E~0); 531972#L659-1 assume !(1 == ~T3_E~0); 532186#L664-1 assume !(1 == ~T4_E~0); 531963#L669-1 assume !(1 == ~T5_E~0); 531964#L674-1 assume !(1 == ~E_1~0); 532401#L679-1 assume !(1 == ~E_2~0); 532073#L684-1 assume !(1 == ~E_3~0); 532074#L689-1 assume !(1 == ~E_4~0); 532259#L694-1 assume !(1 == ~E_5~0); 532257#L699-1 assume { :end_inline_reset_delta_events } true; 532258#L900-2 assume !false; 566662#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 566657#L561-1 [2024-10-13 17:46:09,372 INFO L747 eck$LassoCheckResult]: Loop: 566657#L561-1 assume !false; 566654#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 566651#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 566649#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 566647#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 566644#L486 assume 0 != eval_~tmp~0#1; 566640#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 566638#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 566639#L494-2 havoc eval_~tmp_ndt_1~0#1; 566710#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 566692#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 566702#L508-2 havoc eval_~tmp_ndt_2~0#1; 566703#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 566693#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 566694#L522-2 havoc eval_~tmp_ndt_3~0#1; 566686#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 566682#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 566680#L536-2 havoc eval_~tmp_ndt_4~0#1; 566678#L533-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 566674#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 566672#L550-2 havoc eval_~tmp_ndt_5~0#1; 566660#L547-1 assume !(0 == ~t5_st~0); 566657#L561-1 [2024-10-13 17:46:09,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:09,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 3 times [2024-10-13 17:46:09,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:09,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575397328] [2024-10-13 17:46:09,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:09,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:09,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:09,379 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:09,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:09,387 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:09,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:09,388 INFO L85 PathProgramCache]: Analyzing trace with hash 746708699, now seen corresponding path program 1 times [2024-10-13 17:46:09,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:09,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838805376] [2024-10-13 17:46:09,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:09,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:09,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:09,391 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:09,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:09,393 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:09,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:09,393 INFO L85 PathProgramCache]: Analyzing trace with hash -1968736840, now seen corresponding path program 1 times [2024-10-13 17:46:09,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:09,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717077131] [2024-10-13 17:46:09,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:09,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:09,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:09,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:09,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:09,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717077131] [2024-10-13 17:46:09,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717077131] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:09,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:09,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:09,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604126869] [2024-10-13 17:46:09,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:09,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:09,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:09,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:09,828 INFO L87 Difference]: Start difference. First operand 67526 states and 90241 transitions. cyclomatic complexity: 22737 Second operand has 3 states, 2 states have (on average 47.5) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:10,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:10,001 INFO L93 Difference]: Finished difference Result 79878 states and 106420 transitions. [2024-10-13 17:46:10,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79878 states and 106420 transitions. [2024-10-13 17:46:10,285 INFO L131 ngComponentsAnalysis]: Automaton has 23 accepting balls. 75556 [2024-10-13 17:46:10,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79878 states to 79878 states and 106420 transitions. [2024-10-13 17:46:10,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79878 [2024-10-13 17:46:10,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79878 [2024-10-13 17:46:10,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79878 states and 106420 transitions. [2024-10-13 17:46:10,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:10,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79878 states and 106420 transitions. [2024-10-13 17:46:10,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79878 states and 106420 transitions. [2024-10-13 17:46:11,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79878 to 79878. [2024-10-13 17:46:11,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79878 states, 79878 states have (on average 1.3322817296376974) internal successors, (106420), 79877 states have internal predecessors, (106420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:11,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79878 states to 79878 states and 106420 transitions. [2024-10-13 17:46:11,507 INFO L240 hiAutomatonCegarLoop]: Abstraction has 79878 states and 106420 transitions. [2024-10-13 17:46:11,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:11,508 INFO L425 stractBuchiCegarLoop]: Abstraction has 79878 states and 106420 transitions. [2024-10-13 17:46:11,508 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-13 17:46:11,508 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79878 states and 106420 transitions. [2024-10-13 17:46:11,985 INFO L131 ngComponentsAnalysis]: Automaton has 23 accepting balls. 75556 [2024-10-13 17:46:11,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:11,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:11,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:11,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:11,986 INFO L745 eck$LassoCheckResult]: Stem: 679577#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 679578#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 679708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 679709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 679728#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 679729#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 679512#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 679513#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 679856#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 679857#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 679810#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 679480#L586 assume !(0 == ~M_E~0); 679481#L586-2 assume !(0 == ~T1_E~0); 679534#L591-1 assume !(0 == ~T2_E~0); 679660#L596-1 assume !(0 == ~T3_E~0); 679661#L601-1 assume !(0 == ~T4_E~0); 679715#L606-1 assume !(0 == ~T5_E~0); 679716#L611-1 assume !(0 == ~E_1~0); 679819#L616-1 assume !(0 == ~E_2~0); 679820#L621-1 assume !(0 == ~E_3~0); 679401#L626-1 assume !(0 == ~E_4~0); 679402#L631-1 assume !(0 == ~E_5~0); 679572#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 679399#L279 assume !(1 == ~m_pc~0); 679400#L279-2 is_master_triggered_~__retres1~0#1 := 0; 679747#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 679545#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 679546#L720 assume !(0 != activate_threads_~tmp~1#1); 679746#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 679579#L298 assume !(1 == ~t1_pc~0); 679349#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 679350#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 679373#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 679374#L728 assume !(0 != activate_threads_~tmp___0~0#1); 679411#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 679539#L317 assume !(1 == ~t2_pc~0); 679540#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 679768#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 679714#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 679590#L736 assume !(0 != activate_threads_~tmp___1~0#1); 679591#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 679804#L336 assume !(1 == ~t3_pc~0); 679805#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 679906#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 679323#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 679324#L744 assume !(0 != activate_threads_~tmp___2~0#1); 679756#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 679815#L355 assume !(1 == ~t4_pc~0); 679659#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 679812#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 679441#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 679442#L752 assume !(0 != activate_threads_~tmp___3~0#1); 679424#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 679425#L374 assume !(1 == ~t5_pc~0); 679565#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 679566#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 679551#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 679552#L760 assume !(0 != activate_threads_~tmp___4~0#1); 679695#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 679696#L649 assume !(1 == ~M_E~0); 679896#L649-2 assume !(1 == ~T1_E~0); 679383#L654-1 assume !(1 == ~T2_E~0); 679384#L659-1 assume !(1 == ~T3_E~0); 679587#L664-1 assume !(1 == ~T4_E~0); 679375#L669-1 assume !(1 == ~T5_E~0); 679376#L674-1 assume !(1 == ~E_1~0); 679795#L679-1 assume !(1 == ~E_2~0); 679482#L684-1 assume !(1 == ~E_3~0); 679483#L689-1 assume !(1 == ~E_4~0); 679653#L694-1 assume !(1 == ~E_5~0); 679650#L699-1 assume { :end_inline_reset_delta_events } true; 679651#L900-2 assume !false; 686681#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 686558#L561-1 [2024-10-13 17:46:11,987 INFO L747 eck$LassoCheckResult]: Loop: 686558#L561-1 assume !false; 686557#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 686554#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 686528#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 686524#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 686520#L486 assume 0 != eval_~tmp~0#1; 686515#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 686510#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 686505#L494-2 havoc eval_~tmp_ndt_1~0#1; 686500#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 686467#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 686495#L508-2 havoc eval_~tmp_ndt_2~0#1; 686706#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 686702#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 686701#L522-2 havoc eval_~tmp_ndt_3~0#1; 686698#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 686695#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 686693#L536-2 havoc eval_~tmp_ndt_4~0#1; 686691#L533-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 686536#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 686688#L550-2 havoc eval_~tmp_ndt_5~0#1; 686686#L547-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 686684#L564 assume !(0 != eval_~tmp_ndt_6~0#1); 686680#L564-2 havoc eval_~tmp_ndt_6~0#1; 686558#L561-1 [2024-10-13 17:46:11,988 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:11,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 4 times [2024-10-13 17:46:11,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:11,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530286300] [2024-10-13 17:46:11,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:11,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:11,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:11,997 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:12,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,008 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:12,008 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:12,008 INFO L85 PathProgramCache]: Analyzing trace with hash 327523058, now seen corresponding path program 1 times [2024-10-13 17:46:12,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:12,008 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373219662] [2024-10-13 17:46:12,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:12,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:12,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,012 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:12,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,014 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:12,015 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:12,015 INFO L85 PathProgramCache]: Analyzing trace with hash 2124476047, now seen corresponding path program 1 times [2024-10-13 17:46:12,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:12,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244101272] [2024-10-13 17:46:12,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:12,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:12,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,024 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:12,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,036 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:13,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:13,096 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:13,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:13,254 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.10 05:46:13 BoogieIcfgContainer [2024-10-13 17:46:13,256 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-10-13 17:46:13,256 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-10-13 17:46:13,256 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-10-13 17:46:13,257 INFO L274 PluginConnector]: Witness Printer initialized [2024-10-13 17:46:13,257 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:45:57" (3/4) ... [2024-10-13 17:46:13,258 INFO L136 WitnessPrinter]: Generating witness for non-termination counterexample [2024-10-13 17:46:13,329 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-10-13 17:46:13,329 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-10-13 17:46:13,330 INFO L158 Benchmark]: Toolchain (without parser) took 17625.85ms. Allocated memory was 176.2MB in the beginning and 11.6GB in the end (delta: 11.4GB). Free memory was 107.5MB in the beginning and 10.1GB in the end (delta: -10.0GB). Peak memory consumption was 1.4GB. Max. memory is 16.1GB. [2024-10-13 17:46:13,330 INFO L158 Benchmark]: CDTParser took 0.10ms. Allocated memory is still 176.2MB. Free memory was 133.6MB in the beginning and 133.4MB in the end (delta: 160.8kB). There was no memory consumed. Max. memory is 16.1GB. [2024-10-13 17:46:13,330 INFO L158 Benchmark]: CACSL2BoogieTranslator took 294.85ms. Allocated memory is still 176.2MB. Free memory was 107.3MB in the beginning and 89.6MB in the end (delta: 17.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-10-13 17:46:13,330 INFO L158 Benchmark]: Boogie Procedure Inliner took 97.52ms. Allocated memory is still 176.2MB. Free memory was 89.4MB in the beginning and 145.0MB in the end (delta: -55.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-10-13 17:46:13,330 INFO L158 Benchmark]: Boogie Preprocessor took 65.57ms. Allocated memory is still 176.2MB. Free memory was 145.0MB in the beginning and 138.7MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-10-13 17:46:13,331 INFO L158 Benchmark]: RCFGBuilder took 929.54ms. Allocated memory is still 176.2MB. Free memory was 138.7MB in the beginning and 68.2MB in the end (delta: 70.5MB). Peak memory consumption was 69.2MB. Max. memory is 16.1GB. [2024-10-13 17:46:13,331 INFO L158 Benchmark]: BuchiAutomizer took 16159.47ms. Allocated memory was 176.2MB in the beginning and 11.6GB in the end (delta: 11.4GB). Free memory was 68.1MB in the beginning and 10.1GB in the end (delta: -10.1GB). Peak memory consumption was 1.4GB. Max. memory is 16.1GB. [2024-10-13 17:46:13,331 INFO L158 Benchmark]: Witness Printer took 72.96ms. Allocated memory is still 11.6GB. Free memory was 10.1GB in the beginning and 10.1GB in the end (delta: 11.5MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2024-10-13 17:46:13,332 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10ms. Allocated memory is still 176.2MB. Free memory was 133.6MB in the beginning and 133.4MB in the end (delta: 160.8kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 294.85ms. Allocated memory is still 176.2MB. Free memory was 107.3MB in the beginning and 89.6MB in the end (delta: 17.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 97.52ms. Allocated memory is still 176.2MB. Free memory was 89.4MB in the beginning and 145.0MB in the end (delta: -55.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 65.57ms. Allocated memory is still 176.2MB. Free memory was 145.0MB in the beginning and 138.7MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 929.54ms. Allocated memory is still 176.2MB. Free memory was 138.7MB in the beginning and 68.2MB in the end (delta: 70.5MB). Peak memory consumption was 69.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 16159.47ms. Allocated memory was 176.2MB in the beginning and 11.6GB in the end (delta: 11.4GB). Free memory was 68.1MB in the beginning and 10.1GB in the end (delta: -10.1GB). Peak memory consumption was 1.4GB. Max. memory is 16.1GB. * Witness Printer took 72.96ms. Allocated memory is still 11.6GB. Free memory was 10.1GB in the beginning and 10.1GB in the end (delta: 11.5MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 79878 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 16.0s and 24 iterations. TraceHistogramMax:3. Analysis of lassos took 3.8s. Construction of modules took 0.5s. Büchi inclusion checks took 9.9s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 5.0s AutomataMinimizationTime, 23 MinimizatonAttempts, 16225 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 2.7s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 14676 SdHoareTripleChecker+Valid, 0.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 14676 mSDsluCounter, 31630 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 14211 mSDsCounter, 268 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 687 IncrementalHoareTripleChecker+Invalid, 955 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 268 mSolverCounterUnsat, 17419 mSDtfsCounter, 687 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc3 concLT0 SILN0 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 481]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 481]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-10-13 17:46:13,357 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)