./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a046e57d Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-mul-div-a046e57-m [2024-10-13 17:45:55,549 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-13 17:45:55,614 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-13 17:45:55,618 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-13 17:45:55,618 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-13 17:45:55,643 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-13 17:45:55,643 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-13 17:45:55,644 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-13 17:45:55,644 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-13 17:45:55,645 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-13 17:45:55,645 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-13 17:45:55,646 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-13 17:45:55,646 INFO L153 SettingsManager]: * Use SBE=true [2024-10-13 17:45:55,647 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-13 17:45:55,647 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-13 17:45:55,647 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-13 17:45:55,648 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-13 17:45:55,648 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-13 17:45:55,648 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-13 17:45:55,649 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-13 17:45:55,649 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-13 17:45:55,653 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-13 17:45:55,654 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-13 17:45:55,654 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-13 17:45:55,654 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-13 17:45:55,654 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-13 17:45:55,655 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-13 17:45:55,655 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-13 17:45:55,655 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-13 17:45:55,655 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-13 17:45:55,656 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-13 17:45:55,656 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-13 17:45:55,656 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-13 17:45:55,657 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-13 17:45:55,657 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-13 17:45:55,660 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-13 17:45:55,660 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-13 17:45:55,661 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-13 17:45:55,662 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-13 17:45:55,662 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2024-10-13 17:45:55,914 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-13 17:45:55,944 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-13 17:45:55,947 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-13 17:45:55,949 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-13 17:45:55,949 INFO L274 PluginConnector]: CDTParser initialized [2024-10-13 17:45:55,950 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c [2024-10-13 17:45:57,427 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-13 17:45:57,650 INFO L384 CDTParser]: Found 1 translation units. [2024-10-13 17:45:57,651 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c [2024-10-13 17:45:57,664 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0cad2fba8/760060fd89d843e1b16be42efd07a2cd/FLAG5d8f46292 [2024-10-13 17:45:57,681 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0cad2fba8/760060fd89d843e1b16be42efd07a2cd [2024-10-13 17:45:57,684 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-13 17:45:57,686 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-13 17:45:57,687 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-13 17:45:57,687 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-13 17:45:57,691 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-13 17:45:57,692 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,692 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3c02525a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57, skipping insertion in model container [2024-10-13 17:45:57,693 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,732 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-13 17:45:57,994 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:45:58,026 INFO L200 MainTranslator]: Completed pre-run [2024-10-13 17:45:58,104 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:45:58,133 INFO L204 MainTranslator]: Completed translation [2024-10-13 17:45:58,134 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58 WrapperNode [2024-10-13 17:45:58,134 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-13 17:45:58,135 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-13 17:45:58,135 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-13 17:45:58,135 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-13 17:45:58,141 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,150 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,232 INFO L138 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 125, statements flattened = 1861 [2024-10-13 17:45:58,233 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-13 17:45:58,234 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-13 17:45:58,234 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-13 17:45:58,234 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-13 17:45:58,245 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,245 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,255 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,288 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-13 17:45:58,289 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,289 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,323 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,348 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,354 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,359 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,382 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-13 17:45:58,384 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-13 17:45:58,384 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-13 17:45:58,384 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-13 17:45:58,385 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (1/1) ... [2024-10-13 17:45:58,391 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:45:58,406 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:45:58,422 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:45:58,426 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-13 17:45:58,473 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-13 17:45:58,473 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-13 17:45:58,474 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-13 17:45:58,474 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-13 17:45:58,580 INFO L238 CfgBuilder]: Building ICFG [2024-10-13 17:45:58,582 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-13 17:46:00,015 INFO L? ?]: Removed 360 outVars from TransFormulas that were not future-live. [2024-10-13 17:46:00,015 INFO L287 CfgBuilder]: Performing block encoding [2024-10-13 17:46:00,052 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-13 17:46:00,053 INFO L314 CfgBuilder]: Removed 11 assume(true) statements. [2024-10-13 17:46:00,054 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:46:00 BoogieIcfgContainer [2024-10-13 17:46:00,054 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-13 17:46:00,055 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-13 17:46:00,055 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-13 17:46:00,059 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-13 17:46:00,059 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:46:00,060 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 05:45:57" (1/3) ... [2024-10-13 17:46:00,061 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7616f9a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:46:00, skipping insertion in model container [2024-10-13 17:46:00,061 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:46:00,061 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:58" (2/3) ... [2024-10-13 17:46:00,061 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7616f9a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:46:00, skipping insertion in model container [2024-10-13 17:46:00,061 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:46:00,062 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:46:00" (3/3) ... [2024-10-13 17:46:00,063 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2024-10-13 17:46:00,128 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-13 17:46:00,129 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-13 17:46:00,129 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-13 17:46:00,129 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-13 17:46:00,129 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-13 17:46:00,129 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-13 17:46:00,129 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-13 17:46:00,129 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-13 17:46:00,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 679 [2024-10-13 17:46:00,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,204 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-13 17:46:00,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 679 [2024-10-13 17:46:00,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,236 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,246 INFO L745 eck$LassoCheckResult]: Stem: 107#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 718#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 570#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 715#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 650#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 612#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 643#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 193#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 549#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 240#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 138#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 601#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 122#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 689#L754true assume !(0 == ~M_E~0); 737#L754-2true assume !(0 == ~T1_E~0); 509#L759-1true assume !(0 == ~T2_E~0); 376#L764-1true assume !(0 == ~T3_E~0); 339#L769-1true assume !(0 == ~T4_E~0); 377#L774-1true assume !(0 == ~T5_E~0); 636#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 519#L784-1true assume !(0 == ~T7_E~0); 337#L789-1true assume !(0 == ~E_1~0); 424#L794-1true assume !(0 == ~E_2~0); 765#L799-1true assume !(0 == ~E_3~0); 346#L804-1true assume !(0 == ~E_4~0); 372#L809-1true assume !(0 == ~E_5~0); 550#L814-1true assume !(0 == ~E_6~0); 9#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 171#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137#L361true assume 1 == ~m_pc~0; 676#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 712#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 499#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 633#L930true assume !(0 != activate_threads_~tmp~1#1); 272#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134#L380true assume !(1 == ~t1_pc~0); 766#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 644#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 770#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 460#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 438#L399true assume 1 == ~t2_pc~0; 638#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 654#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175#L946true assume !(0 != activate_threads_~tmp___1~0#1); 414#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13#L418true assume !(1 == ~t3_pc~0); 698#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 552#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 777#L954true assume !(0 != activate_threads_~tmp___2~0#1); 361#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 691#L437true assume 1 == ~t4_pc~0; 755#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 494#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209#L962true assume !(0 != activate_threads_~tmp___3~0#1); 592#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478#L456true assume !(1 == ~t5_pc~0); 330#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 681#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 502#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 410#L970true assume !(0 != activate_threads_~tmp___4~0#1); 734#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45#L475true assume 1 == ~t6_pc~0; 221#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 402#L978true assume !(0 != activate_threads_~tmp___5~0#1); 351#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 547#L494true assume 1 == ~t7_pc~0; 304#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 316#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 731#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 378#L986true assume !(0 != activate_threads_~tmp___6~0#1); 761#L986-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 668#L837true assume !(1 == ~M_E~0); 569#L837-2true assume !(1 == ~T1_E~0); 433#L842-1true assume !(1 == ~T2_E~0); 216#L847-1true assume !(1 == ~T3_E~0); 265#L852-1true assume !(1 == ~T4_E~0); 781#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 182#L862-1true assume !(1 == ~T6_E~0); 189#L867-1true assume !(1 == ~T7_E~0); 239#L872-1true assume !(1 == ~E_1~0); 391#L877-1true assume !(1 == ~E_2~0); 578#L882-1true assume !(1 == ~E_3~0); 707#L887-1true assume !(1 == ~E_4~0); 454#L892-1true assume !(1 == ~E_5~0); 660#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 199#L902-1true assume !(1 == ~E_7~0); 477#L907-1true assume { :end_inline_reset_delta_events } true; 230#L1148-2true [2024-10-13 17:46:00,248 INFO L747 eck$LassoCheckResult]: Loop: 230#L1148-2true assume !false; 10#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 422#L729-1true assume false; 455#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 271#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 16#L754-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 530#L759-3true assume !(0 == ~T2_E~0); 225#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 616#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 362#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 94#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 14#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 774#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 11#L794-3true assume 0 == ~E_2~0;~E_2~0 := 1; 35#L799-3true assume !(0 == ~E_3~0); 150#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 293#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 33#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 526#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 487#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 236#L361-24true assume !(1 == ~m_pc~0); 532#L361-26true is_master_triggered_~__retres1~0#1 := 0; 301#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 553#L930-24true assume !(0 != activate_threads_~tmp~1#1); 584#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343#L380-24true assume 1 == ~t1_pc~0; 585#L381-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 625#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 439#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505#L399-24true assume !(1 == ~t2_pc~0); 154#L399-26true is_transmit2_triggered_~__retres1~2#1 := 0; 110#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 381#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 142#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 624#L418-24true assume 1 == ~t3_pc~0; 551#L419-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 185#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 591#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 412#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 556#L437-24true assume !(1 == ~t4_pc~0); 784#L437-26true is_transmit4_triggered_~__retres1~4#1 := 0; 740#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 350#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 645#L456-24true assume !(1 == ~t5_pc~0); 738#L456-26true is_transmit5_triggered_~__retres1~5#1 := 0; 307#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 533#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 574#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 273#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 769#L475-24true assume 1 == ~t6_pc~0; 15#L476-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 315#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 347#L978-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 309#L494-24true assume 1 == ~t7_pc~0; 248#L495-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 174#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 257#is_transmit7_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 490#L986-26true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515#L837-3true assume 1 == ~M_E~0;~M_E~0 := 2; 670#L837-5true assume !(1 == ~T1_E~0); 269#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 608#L847-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 408#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 313#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 746#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 703#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 247#L872-3true assume 1 == ~E_1~0;~E_1~0 := 2; 306#L877-3true assume !(1 == ~E_2~0); 728#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 354#L887-3true assume 1 == ~E_4~0;~E_4~0 := 2; 104#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 514#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 773#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 196#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 581#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 365#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 155#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 686#L1167true assume !(0 == start_simulation_~tmp~3#1); 233#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 745#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 254#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 308#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 282#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 121#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 230#L1148-2true [2024-10-13 17:46:00,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,259 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2024-10-13 17:46:00,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109824045] [2024-10-13 17:46:00,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109824045] [2024-10-13 17:46:00,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109824045] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065225249] [2024-10-13 17:46:00,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,567 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,570 INFO L85 PathProgramCache]: Analyzing trace with hash 661713836, now seen corresponding path program 1 times [2024-10-13 17:46:00,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858062895] [2024-10-13 17:46:00,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858062895] [2024-10-13 17:46:00,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858062895] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:00,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915192063] [2024-10-13 17:46:00,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,629 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:00,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:00,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:00,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:00,666 INFO L87 Difference]: Start difference. First operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,737 INFO L93 Difference]: Finished difference Result 782 states and 1162 transitions. [2024-10-13 17:46:00,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 782 states and 1162 transitions. [2024-10-13 17:46:00,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:00,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 782 states to 776 states and 1156 transitions. [2024-10-13 17:46:00,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2024-10-13 17:46:00,763 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2024-10-13 17:46:00,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1156 transitions. [2024-10-13 17:46:00,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1156 transitions. [2024-10-13 17:46:00,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1156 transitions. [2024-10-13 17:46:00,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2024-10-13 17:46:00,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4896907216494846) internal successors, (1156), 775 states have internal predecessors, (1156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1156 transitions. [2024-10-13 17:46:00,846 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1156 transitions. [2024-10-13 17:46:00,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,852 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1156 transitions. [2024-10-13 17:46:00,852 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-13 17:46:00,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1156 transitions. [2024-10-13 17:46:00,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:00,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,861 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,861 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,862 INFO L745 eck$LassoCheckResult]: Stem: 1790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2318#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2319#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2338#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2330#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2331#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1939#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1940#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2009#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1853#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1854#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1820#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1821#L754 assume !(0 == ~M_E~0); 2346#L754-2 assume !(0 == ~T1_E~0); 2288#L759-1 assume !(0 == ~T2_E~0); 2170#L764-1 assume !(0 == ~T3_E~0); 2135#L769-1 assume !(0 == ~T4_E~0); 2136#L774-1 assume !(0 == ~T5_E~0); 2171#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2293#L784-1 assume !(0 == ~T7_E~0); 2132#L789-1 assume !(0 == ~E_1~0); 2133#L794-1 assume !(0 == ~E_2~0); 2207#L799-1 assume !(0 == ~E_3~0); 2143#L804-1 assume !(0 == ~E_4~0); 2144#L809-1 assume !(0 == ~E_5~0); 2165#L814-1 assume !(0 == ~E_6~0); 1591#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1592#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1850#L361 assume 1 == ~m_pc~0; 1851#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2314#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2274#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2275#L930 assume !(0 != activate_threads_~tmp~1#1); 2052#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1844#L380 assume !(1 == ~t1_pc~0); 1845#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2213#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1613#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1614#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2233#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2214#L399 assume 1 == ~t2_pc~0; 2215#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1762#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1915#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1916#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1599#L418 assume !(1 == ~t3_pc~0); 1578#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1579#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1589#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1590#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2155#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2156#L437 assume 1 == ~t4_pc~0; 2347#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2269#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1672#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1673#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1968#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2251#L456 assume !(1 == ~t5_pc~0); 1776#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1775#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2196#L970 assume !(0 != activate_threads_~tmp___4~0#1); 2197#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1666#L475 assume 1 == ~t6_pc~0; 1667#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1708#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1908#L978 assume !(0 != activate_threads_~tmp___5~0#1); 2148#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2149#L494 assume 1 == ~t7_pc~0; 2097#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1893#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2172#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2173#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2343#L837 assume !(1 == ~M_E~0); 2317#L837-2 assume !(1 == ~T1_E~0); 2210#L842-1 assume !(1 == ~T2_E~0); 1975#L847-1 assume !(1 == ~T3_E~0); 1976#L852-1 assume !(1 == ~T4_E~0); 2042#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1928#L862-1 assume !(1 == ~T6_E~0); 1929#L867-1 assume !(1 == ~T7_E~0); 1935#L872-1 assume !(1 == ~E_1~0); 2008#L877-1 assume !(1 == ~E_2~0); 2185#L882-1 assume !(1 == ~E_3~0); 2322#L887-1 assume !(1 == ~E_4~0); 2229#L892-1 assume !(1 == ~E_5~0); 2230#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1951#L902-1 assume !(1 == ~E_7~0); 1952#L907-1 assume { :end_inline_reset_delta_events } true; 1819#L1148-2 [2024-10-13 17:46:00,865 INFO L747 eck$LassoCheckResult]: Loop: 1819#L1148-2 assume !false; 1593#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1594#L729-1 assume !false; 2205#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1792#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1793#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1941#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1837#L626 assume !(0 != eval_~tmp~0#1); 1838#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2051#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1866#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1605#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1606#L759-3 assume !(0 == ~T2_E~0); 1987#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1988#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2157#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1765#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1600#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1601#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1595#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1596#L799-3 assume !(0 == ~E_3~0); 1647#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1873#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1643#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1644#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2261#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2005#L361-24 assume 1 == ~m_pc~0; 1749#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1750#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1695#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1696#L930-24 assume !(0 != activate_threads_~tmp~1#1); 2306#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2140#L380-24 assume 1 == ~t1_pc~0; 2141#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1678#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2087#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1862#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1863#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2216#L399-24 assume !(1 == ~t2_pc~0); 1881#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1797#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1798#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2041#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1859#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1860#L418-24 assume 1 == ~t3_pc~0; 2305#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1642#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1932#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1768#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1769#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2199#L437-24 assume 1 == ~t4_pc~0; 2265#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2267#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2040#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1752#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1753#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2147#L456-24 assume 1 == ~t5_pc~0; 2121#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2101#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2102#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2300#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2053#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2054#L475-24 assume 1 == ~t6_pc~0; 1602#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1603#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1745#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1746#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1584#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1585#L494-24 assume 1 == ~t7_pc~0; 2024#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1913#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1914#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1856#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1857#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2264#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2291#L837-5 assume !(1 == ~T1_E~0); 2048#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2049#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2195#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2105#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2106#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2348#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2022#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2023#L877-3 assume !(1 == ~E_2~0); 2100#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2151#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1784#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1785#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2290#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1945#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1946#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1598#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1882#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1883#L1167 assume !(0 == start_simulation_~tmp~3#1); 2000#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2001#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1806#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1612#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1982#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1983#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1818#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1819#L1148-2 [2024-10-13 17:46:00,865 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,865 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2024-10-13 17:46:00,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952999948] [2024-10-13 17:46:00,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,006 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952999948] [2024-10-13 17:46:01,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952999948] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,006 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,006 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440335741] [2024-10-13 17:46:01,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,007 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,008 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,008 INFO L85 PathProgramCache]: Analyzing trace with hash -716299096, now seen corresponding path program 1 times [2024-10-13 17:46:01,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1060997481] [2024-10-13 17:46:01,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,156 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1060997481] [2024-10-13 17:46:01,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1060997481] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446450553] [2024-10-13 17:46:01,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,160 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,160 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,161 INFO L87 Difference]: Start difference. First operand 776 states and 1156 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,179 INFO L93 Difference]: Finished difference Result 776 states and 1155 transitions. [2024-10-13 17:46:01,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1155 transitions. [2024-10-13 17:46:01,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1155 transitions. [2024-10-13 17:46:01,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2024-10-13 17:46:01,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2024-10-13 17:46:01,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1155 transitions. [2024-10-13 17:46:01,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1155 transitions. [2024-10-13 17:46:01,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1155 transitions. [2024-10-13 17:46:01,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2024-10-13 17:46:01,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4884020618556701) internal successors, (1155), 775 states have internal predecessors, (1155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1155 transitions. [2024-10-13 17:46:01,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1155 transitions. [2024-10-13 17:46:01,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,214 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1155 transitions. [2024-10-13 17:46:01,214 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-13 17:46:01,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1155 transitions. [2024-10-13 17:46:01,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,222 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,222 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,225 INFO L745 eck$LassoCheckResult]: Stem: 3349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3897#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3889#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3890#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3498#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3499#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3568#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3412#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3413#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3379#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3380#L754 assume !(0 == ~M_E~0); 3905#L754-2 assume !(0 == ~T1_E~0); 3847#L759-1 assume !(0 == ~T2_E~0); 3729#L764-1 assume !(0 == ~T3_E~0); 3694#L769-1 assume !(0 == ~T4_E~0); 3695#L774-1 assume !(0 == ~T5_E~0); 3730#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3852#L784-1 assume !(0 == ~T7_E~0); 3691#L789-1 assume !(0 == ~E_1~0); 3692#L794-1 assume !(0 == ~E_2~0); 3766#L799-1 assume !(0 == ~E_3~0); 3702#L804-1 assume !(0 == ~E_4~0); 3703#L809-1 assume !(0 == ~E_5~0); 3724#L814-1 assume !(0 == ~E_6~0); 3150#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3151#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3409#L361 assume 1 == ~m_pc~0; 3410#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3873#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3833#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3834#L930 assume !(0 != activate_threads_~tmp~1#1); 3611#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3403#L380 assume !(1 == ~t1_pc~0); 3404#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3772#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3172#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3173#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3792#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3773#L399 assume 1 == ~t2_pc~0; 3774#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3321#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3474#L946 assume !(0 != activate_threads_~tmp___1~0#1); 3475#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3158#L418 assume !(1 == ~t3_pc~0); 3137#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3138#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3149#L954 assume !(0 != activate_threads_~tmp___2~0#1); 3714#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3715#L437 assume 1 == ~t4_pc~0; 3906#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3828#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3232#L962 assume !(0 != activate_threads_~tmp___3~0#1); 3527#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3810#L456 assume !(1 == ~t5_pc~0); 3335#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3334#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3837#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3755#L970 assume !(0 != activate_threads_~tmp___4~0#1); 3756#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3225#L475 assume 1 == ~t6_pc~0; 3226#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3267#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3268#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3467#L978 assume !(0 != activate_threads_~tmp___5~0#1); 3707#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3708#L494 assume 1 == ~t7_pc~0; 3656#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3452#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3667#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3731#L986 assume !(0 != activate_threads_~tmp___6~0#1); 3732#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3902#L837 assume !(1 == ~M_E~0); 3876#L837-2 assume !(1 == ~T1_E~0); 3769#L842-1 assume !(1 == ~T2_E~0); 3534#L847-1 assume !(1 == ~T3_E~0); 3535#L852-1 assume !(1 == ~T4_E~0); 3601#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3487#L862-1 assume !(1 == ~T6_E~0); 3488#L867-1 assume !(1 == ~T7_E~0); 3494#L872-1 assume !(1 == ~E_1~0); 3567#L877-1 assume !(1 == ~E_2~0); 3744#L882-1 assume !(1 == ~E_3~0); 3881#L887-1 assume !(1 == ~E_4~0); 3788#L892-1 assume !(1 == ~E_5~0); 3789#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3510#L902-1 assume !(1 == ~E_7~0); 3511#L907-1 assume { :end_inline_reset_delta_events } true; 3378#L1148-2 [2024-10-13 17:46:01,225 INFO L747 eck$LassoCheckResult]: Loop: 3378#L1148-2 assume !false; 3152#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3153#L729-1 assume !false; 3764#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3351#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3352#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3500#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3396#L626 assume !(0 != eval_~tmp~0#1); 3397#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3425#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3164#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3165#L759-3 assume !(0 == ~T2_E~0); 3546#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3547#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3716#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3324#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3159#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3160#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3154#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3155#L799-3 assume !(0 == ~E_3~0); 3206#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3432#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3202#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3203#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3820#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3564#L361-24 assume 1 == ~m_pc~0; 3308#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3309#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3254#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3255#L930-24 assume !(0 != activate_threads_~tmp~1#1); 3865#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3699#L380-24 assume 1 == ~t1_pc~0; 3700#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3237#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3646#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3421#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3422#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3775#L399-24 assume !(1 == ~t2_pc~0); 3440#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 3356#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3357#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3600#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3418#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3419#L418-24 assume !(1 == ~t3_pc~0); 3200#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 3201#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3491#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3327#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3328#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3758#L437-24 assume 1 == ~t4_pc~0; 3824#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3826#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3599#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3311#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3312#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3706#L456-24 assume 1 == ~t5_pc~0; 3680#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3660#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3661#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3859#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3612#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3613#L475-24 assume 1 == ~t6_pc~0; 3161#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3162#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3304#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3305#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3143#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3144#L494-24 assume !(1 == ~t7_pc~0); 3492#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 3472#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3473#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3415#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3416#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3823#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3850#L837-5 assume !(1 == ~T1_E~0); 3607#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3608#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3754#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3664#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3665#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3907#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3581#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3582#L877-3 assume !(1 == ~E_2~0); 3659#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3710#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3343#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3344#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3849#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3504#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3505#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3157#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3442#L1167 assume !(0 == start_simulation_~tmp~3#1); 3559#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3560#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3365#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3171#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3541#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3542#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3377#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3378#L1148-2 [2024-10-13 17:46:01,226 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,229 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2024-10-13 17:46:01,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444629066] [2024-10-13 17:46:01,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,314 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444629066] [2024-10-13 17:46:01,315 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1444629066] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,315 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,315 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269604351] [2024-10-13 17:46:01,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,315 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,316 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,316 INFO L85 PathProgramCache]: Analyzing trace with hash 808370534, now seen corresponding path program 1 times [2024-10-13 17:46:01,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864939359] [2024-10-13 17:46:01,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864939359] [2024-10-13 17:46:01,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864939359] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792519582] [2024-10-13 17:46:01,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,415 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,416 INFO L87 Difference]: Start difference. First operand 776 states and 1155 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,432 INFO L93 Difference]: Finished difference Result 776 states and 1154 transitions. [2024-10-13 17:46:01,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1154 transitions. [2024-10-13 17:46:01,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1154 transitions. [2024-10-13 17:46:01,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2024-10-13 17:46:01,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2024-10-13 17:46:01,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1154 transitions. [2024-10-13 17:46:01,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1154 transitions. [2024-10-13 17:46:01,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1154 transitions. [2024-10-13 17:46:01,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2024-10-13 17:46:01,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4871134020618557) internal successors, (1154), 775 states have internal predecessors, (1154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1154 transitions. [2024-10-13 17:46:01,456 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1154 transitions. [2024-10-13 17:46:01,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,458 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1154 transitions. [2024-10-13 17:46:01,458 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-13 17:46:01,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1154 transitions. [2024-10-13 17:46:01,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,466 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,467 INFO L745 eck$LassoCheckResult]: Stem: 4908#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 4909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5456#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5448#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5449#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5057#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5058#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5127#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4971#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4972#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4938#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4939#L754 assume !(0 == ~M_E~0); 5464#L754-2 assume !(0 == ~T1_E~0); 5406#L759-1 assume !(0 == ~T2_E~0); 5288#L764-1 assume !(0 == ~T3_E~0); 5254#L769-1 assume !(0 == ~T4_E~0); 5255#L774-1 assume !(0 == ~T5_E~0); 5289#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5411#L784-1 assume !(0 == ~T7_E~0); 5251#L789-1 assume !(0 == ~E_1~0); 5252#L794-1 assume !(0 == ~E_2~0); 5325#L799-1 assume !(0 == ~E_3~0); 5261#L804-1 assume !(0 == ~E_4~0); 5262#L809-1 assume !(0 == ~E_5~0); 5283#L814-1 assume !(0 == ~E_6~0); 4711#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4712#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4968#L361 assume 1 == ~m_pc~0; 4969#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5432#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5392#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5393#L930 assume !(0 != activate_threads_~tmp~1#1); 5170#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4962#L380 assume !(1 == ~t1_pc~0); 4963#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5331#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4732#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5351#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5332#L399 assume 1 == ~t2_pc~0; 5333#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4880#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5040#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5033#L946 assume !(0 != activate_threads_~tmp___1~0#1); 5034#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4717#L418 assume !(1 == ~t3_pc~0); 4696#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4697#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4707#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4708#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5273#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5274#L437 assume 1 == ~t4_pc~0; 5465#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5388#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4791#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4792#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5086#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5374#L456 assume !(1 == ~t5_pc~0); 4894#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4893#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5315#L970 assume !(0 != activate_threads_~tmp___4~0#1); 5316#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4784#L475 assume 1 == ~t6_pc~0; 4785#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4826#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4827#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5026#L978 assume !(0 != activate_threads_~tmp___5~0#1); 5266#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5267#L494 assume 1 == ~t7_pc~0; 5215#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5011#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5226#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5290#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5291#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5461#L837 assume !(1 == ~M_E~0); 5435#L837-2 assume !(1 == ~T1_E~0); 5328#L842-1 assume !(1 == ~T2_E~0); 5093#L847-1 assume !(1 == ~T3_E~0); 5094#L852-1 assume !(1 == ~T4_E~0); 5160#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5046#L862-1 assume !(1 == ~T6_E~0); 5047#L867-1 assume !(1 == ~T7_E~0); 5053#L872-1 assume !(1 == ~E_1~0); 5126#L877-1 assume !(1 == ~E_2~0); 5304#L882-1 assume !(1 == ~E_3~0); 5440#L887-1 assume !(1 == ~E_4~0); 5347#L892-1 assume !(1 == ~E_5~0); 5348#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5069#L902-1 assume !(1 == ~E_7~0); 5070#L907-1 assume { :end_inline_reset_delta_events } true; 4937#L1148-2 [2024-10-13 17:46:01,467 INFO L747 eck$LassoCheckResult]: Loop: 4937#L1148-2 assume !false; 4713#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4714#L729-1 assume !false; 5323#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4910#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4911#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5064#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4957#L626 assume !(0 != eval_~tmp~0#1); 4958#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5169#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4984#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4723#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4724#L759-3 assume !(0 == ~T2_E~0); 5106#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5107#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5275#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4883#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4718#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4719#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4709#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4710#L799-3 assume !(0 == ~E_3~0); 4765#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4991#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4761#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4762#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5379#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5123#L361-24 assume 1 == ~m_pc~0; 4867#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4868#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4813#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4814#L930-24 assume !(0 != activate_threads_~tmp~1#1); 5424#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5258#L380-24 assume 1 == ~t1_pc~0; 5259#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4796#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5205#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4980#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4981#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5334#L399-24 assume !(1 == ~t2_pc~0); 4999#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4915#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4916#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5159#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4977#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4978#L418-24 assume !(1 == ~t3_pc~0); 4759#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4760#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5050#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4886#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4887#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5317#L437-24 assume 1 == ~t4_pc~0; 5383#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5385#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5158#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4870#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4871#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5265#L456-24 assume 1 == ~t5_pc~0; 5239#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5219#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5220#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5418#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5171#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5172#L475-24 assume 1 == ~t6_pc~0; 4720#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4721#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4863#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4864#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4702#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4703#L494-24 assume 1 == ~t7_pc~0; 5142#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5031#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4974#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4975#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5382#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5409#L837-5 assume !(1 == ~T1_E~0); 5166#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5167#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5313#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5223#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5224#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5466#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5137#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5138#L877-3 assume !(1 == ~E_2~0); 5218#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5269#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4902#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4903#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5408#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5062#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5063#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4716#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5000#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5001#L1167 assume !(0 == start_simulation_~tmp~3#1); 5118#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5119#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4924#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4729#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4730#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5100#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5101#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4936#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4937#L1148-2 [2024-10-13 17:46:01,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,469 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2024-10-13 17:46:01,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383429238] [2024-10-13 17:46:01,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1383429238] [2024-10-13 17:46:01,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1383429238] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [759026587] [2024-10-13 17:46:01,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,524 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,525 INFO L85 PathProgramCache]: Analyzing trace with hash -1857946489, now seen corresponding path program 1 times [2024-10-13 17:46:01,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952535272] [2024-10-13 17:46:01,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952535272] [2024-10-13 17:46:01,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952535272] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958135688] [2024-10-13 17:46:01,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,597 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,598 INFO L87 Difference]: Start difference. First operand 776 states and 1154 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,613 INFO L93 Difference]: Finished difference Result 776 states and 1153 transitions. [2024-10-13 17:46:01,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1153 transitions. [2024-10-13 17:46:01,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1153 transitions. [2024-10-13 17:46:01,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2024-10-13 17:46:01,622 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2024-10-13 17:46:01,622 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1153 transitions. [2024-10-13 17:46:01,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,624 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1153 transitions. [2024-10-13 17:46:01,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1153 transitions. [2024-10-13 17:46:01,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2024-10-13 17:46:01,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4858247422680413) internal successors, (1153), 775 states have internal predecessors, (1153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1153 transitions. [2024-10-13 17:46:01,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1153 transitions. [2024-10-13 17:46:01,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,641 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1153 transitions. [2024-10-13 17:46:01,641 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-13 17:46:01,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1153 transitions. [2024-10-13 17:46:01,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,650 INFO L745 eck$LassoCheckResult]: Stem: 6467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6995#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6996#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7015#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 7007#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7008#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6616#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6617#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6686#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6530#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6531#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6497#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6498#L754 assume !(0 == ~M_E~0); 7023#L754-2 assume !(0 == ~T1_E~0); 6965#L759-1 assume !(0 == ~T2_E~0); 6847#L764-1 assume !(0 == ~T3_E~0); 6812#L769-1 assume !(0 == ~T4_E~0); 6813#L774-1 assume !(0 == ~T5_E~0); 6848#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6970#L784-1 assume !(0 == ~T7_E~0); 6809#L789-1 assume !(0 == ~E_1~0); 6810#L794-1 assume !(0 == ~E_2~0); 6884#L799-1 assume !(0 == ~E_3~0); 6820#L804-1 assume !(0 == ~E_4~0); 6821#L809-1 assume !(0 == ~E_5~0); 6842#L814-1 assume !(0 == ~E_6~0); 6268#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6269#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6527#L361 assume 1 == ~m_pc~0; 6528#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6991#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6951#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6952#L930 assume !(0 != activate_threads_~tmp~1#1); 6729#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6521#L380 assume !(1 == ~t1_pc~0); 6522#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6890#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6290#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6291#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6910#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6891#L399 assume 1 == ~t2_pc~0; 6892#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6439#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6599#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6592#L946 assume !(0 != activate_threads_~tmp___1~0#1); 6593#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6276#L418 assume !(1 == ~t3_pc~0); 6255#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6256#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6267#L954 assume !(0 != activate_threads_~tmp___2~0#1); 6832#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6833#L437 assume 1 == ~t4_pc~0; 7024#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6946#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6349#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6350#L962 assume !(0 != activate_threads_~tmp___3~0#1); 6645#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6930#L456 assume !(1 == ~t5_pc~0); 6453#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6452#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6955#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6874#L970 assume !(0 != activate_threads_~tmp___4~0#1); 6875#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6343#L475 assume 1 == ~t6_pc~0; 6344#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6385#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6386#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6585#L978 assume !(0 != activate_threads_~tmp___5~0#1); 6825#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6826#L494 assume 1 == ~t7_pc~0; 6774#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6570#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6785#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6849#L986 assume !(0 != activate_threads_~tmp___6~0#1); 6850#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7020#L837 assume !(1 == ~M_E~0); 6994#L837-2 assume !(1 == ~T1_E~0); 6887#L842-1 assume !(1 == ~T2_E~0); 6652#L847-1 assume !(1 == ~T3_E~0); 6653#L852-1 assume !(1 == ~T4_E~0); 6719#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6605#L862-1 assume !(1 == ~T6_E~0); 6606#L867-1 assume !(1 == ~T7_E~0); 6612#L872-1 assume !(1 == ~E_1~0); 6685#L877-1 assume !(1 == ~E_2~0); 6862#L882-1 assume !(1 == ~E_3~0); 6999#L887-1 assume !(1 == ~E_4~0); 6906#L892-1 assume !(1 == ~E_5~0); 6907#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6628#L902-1 assume !(1 == ~E_7~0); 6629#L907-1 assume { :end_inline_reset_delta_events } true; 6496#L1148-2 [2024-10-13 17:46:01,654 INFO L747 eck$LassoCheckResult]: Loop: 6496#L1148-2 assume !false; 6270#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6271#L729-1 assume !false; 6882#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6469#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6470#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6620#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6514#L626 assume !(0 != eval_~tmp~0#1); 6515#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6728#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6543#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6282#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6283#L759-3 assume !(0 == ~T2_E~0); 6664#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6665#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6834#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6442#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6277#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6278#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6272#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6273#L799-3 assume !(0 == ~E_3~0); 6324#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6550#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6320#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6321#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6938#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6682#L361-24 assume 1 == ~m_pc~0; 6426#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6427#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6373#L930-24 assume !(0 != activate_threads_~tmp~1#1); 6983#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6817#L380-24 assume 1 == ~t1_pc~0; 6818#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6355#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6764#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6539#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6540#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6893#L399-24 assume !(1 == ~t2_pc~0); 6558#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 6474#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6475#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6718#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6536#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6537#L418-24 assume 1 == ~t3_pc~0; 6982#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6319#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6609#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6445#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6446#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6876#L437-24 assume 1 == ~t4_pc~0; 6942#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6944#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6717#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6429#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6430#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6824#L456-24 assume 1 == ~t5_pc~0; 6798#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6778#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6779#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6977#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6730#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6731#L475-24 assume 1 == ~t6_pc~0; 6279#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6280#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6422#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6423#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6261#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6262#L494-24 assume !(1 == ~t7_pc~0); 6610#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 6590#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6591#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6533#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6534#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6941#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6968#L837-5 assume !(1 == ~T1_E~0); 6725#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6726#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6872#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6782#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6783#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7025#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6696#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6697#L877-3 assume !(1 == ~E_2~0); 6777#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6828#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6461#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6462#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6967#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6618#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6619#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6275#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6559#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6560#L1167 assume !(0 == start_simulation_~tmp~3#1); 6677#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6678#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6480#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6289#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6659#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6660#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6495#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6496#L1148-2 [2024-10-13 17:46:01,655 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,655 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2024-10-13 17:46:01,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317277282] [2024-10-13 17:46:01,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317277282] [2024-10-13 17:46:01,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317277282] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,702 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,702 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494991349] [2024-10-13 17:46:01,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,703 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,704 INFO L85 PathProgramCache]: Analyzing trace with hash 1950017927, now seen corresponding path program 1 times [2024-10-13 17:46:01,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643616811] [2024-10-13 17:46:01,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,768 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,768 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643616811] [2024-10-13 17:46:01,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643616811] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,768 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729689957] [2024-10-13 17:46:01,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,769 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,770 INFO L87 Difference]: Start difference. First operand 776 states and 1153 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,788 INFO L93 Difference]: Finished difference Result 776 states and 1152 transitions. [2024-10-13 17:46:01,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1152 transitions. [2024-10-13 17:46:01,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1152 transitions. [2024-10-13 17:46:01,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2024-10-13 17:46:01,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2024-10-13 17:46:01,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1152 transitions. [2024-10-13 17:46:01,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1152 transitions. [2024-10-13 17:46:01,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1152 transitions. [2024-10-13 17:46:01,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2024-10-13 17:46:01,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4845360824742269) internal successors, (1152), 775 states have internal predecessors, (1152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1152 transitions. [2024-10-13 17:46:01,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1152 transitions. [2024-10-13 17:46:01,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,810 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1152 transitions. [2024-10-13 17:46:01,810 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-13 17:46:01,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1152 transitions. [2024-10-13 17:46:01,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,815 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,817 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,817 INFO L745 eck$LassoCheckResult]: Stem: 8026#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8574#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8566#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8567#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8175#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8176#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8245#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8089#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8090#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8056#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8057#L754 assume !(0 == ~M_E~0); 8582#L754-2 assume !(0 == ~T1_E~0); 8524#L759-1 assume !(0 == ~T2_E~0); 8406#L764-1 assume !(0 == ~T3_E~0); 8371#L769-1 assume !(0 == ~T4_E~0); 8372#L774-1 assume !(0 == ~T5_E~0); 8407#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8529#L784-1 assume !(0 == ~T7_E~0); 8368#L789-1 assume !(0 == ~E_1~0); 8369#L794-1 assume !(0 == ~E_2~0); 8443#L799-1 assume !(0 == ~E_3~0); 8379#L804-1 assume !(0 == ~E_4~0); 8380#L809-1 assume !(0 == ~E_5~0); 8401#L814-1 assume !(0 == ~E_6~0); 7827#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7828#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8086#L361 assume 1 == ~m_pc~0; 8087#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8550#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8510#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8511#L930 assume !(0 != activate_threads_~tmp~1#1); 8288#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8080#L380 assume !(1 == ~t1_pc~0); 8081#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8449#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7849#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7850#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8469#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8450#L399 assume 1 == ~t2_pc~0; 8451#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7998#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8151#L946 assume !(0 != activate_threads_~tmp___1~0#1); 8152#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7835#L418 assume !(1 == ~t3_pc~0); 7814#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7815#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7825#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7826#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8391#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8392#L437 assume 1 == ~t4_pc~0; 8583#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8505#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7908#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7909#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8204#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8487#L456 assume !(1 == ~t5_pc~0); 8012#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8011#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8514#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8432#L970 assume !(0 != activate_threads_~tmp___4~0#1); 8433#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7902#L475 assume 1 == ~t6_pc~0; 7903#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7944#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8144#L978 assume !(0 != activate_threads_~tmp___5~0#1); 8384#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8385#L494 assume 1 == ~t7_pc~0; 8333#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8129#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8344#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8408#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8409#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8579#L837 assume !(1 == ~M_E~0); 8553#L837-2 assume !(1 == ~T1_E~0); 8446#L842-1 assume !(1 == ~T2_E~0); 8211#L847-1 assume !(1 == ~T3_E~0); 8212#L852-1 assume !(1 == ~T4_E~0); 8278#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8164#L862-1 assume !(1 == ~T6_E~0); 8165#L867-1 assume !(1 == ~T7_E~0); 8171#L872-1 assume !(1 == ~E_1~0); 8244#L877-1 assume !(1 == ~E_2~0); 8421#L882-1 assume !(1 == ~E_3~0); 8558#L887-1 assume !(1 == ~E_4~0); 8465#L892-1 assume !(1 == ~E_5~0); 8466#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8187#L902-1 assume !(1 == ~E_7~0); 8188#L907-1 assume { :end_inline_reset_delta_events } true; 8055#L1148-2 [2024-10-13 17:46:01,818 INFO L747 eck$LassoCheckResult]: Loop: 8055#L1148-2 assume !false; 7829#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7830#L729-1 assume !false; 8441#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8028#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8029#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8177#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8073#L626 assume !(0 != eval_~tmp~0#1); 8074#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8287#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8102#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7841#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7842#L759-3 assume !(0 == ~T2_E~0); 8223#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8224#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8393#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8001#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7836#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7837#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7831#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7832#L799-3 assume !(0 == ~E_3~0); 7883#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8109#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7879#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7880#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8497#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8241#L361-24 assume 1 == ~m_pc~0; 7985#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7986#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7931#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7932#L930-24 assume !(0 != activate_threads_~tmp~1#1); 8542#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8376#L380-24 assume 1 == ~t1_pc~0; 8377#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7914#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8323#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8098#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8099#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8452#L399-24 assume !(1 == ~t2_pc~0); 8117#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8033#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8034#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8277#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8095#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8096#L418-24 assume !(1 == ~t3_pc~0); 7877#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7878#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8168#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8004#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8005#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8435#L437-24 assume 1 == ~t4_pc~0; 8501#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8503#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8276#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7988#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7989#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8383#L456-24 assume 1 == ~t5_pc~0; 8357#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8337#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8338#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8536#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8289#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8290#L475-24 assume !(1 == ~t6_pc~0); 7840#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7839#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7981#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7982#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7820#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7821#L494-24 assume 1 == ~t7_pc~0; 8260#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8149#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8150#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8092#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8093#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8527#L837-5 assume !(1 == ~T1_E~0); 8284#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8285#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8431#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8341#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8342#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8584#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8258#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8259#L877-3 assume !(1 == ~E_2~0); 8336#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8387#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8020#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8021#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8526#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8181#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8182#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7834#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8118#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8119#L1167 assume !(0 == start_simulation_~tmp~3#1); 8236#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8237#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8042#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7848#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8218#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8219#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8054#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8055#L1148-2 [2024-10-13 17:46:01,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,819 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2024-10-13 17:46:01,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454086825] [2024-10-13 17:46:01,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454086825] [2024-10-13 17:46:01,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454086825] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684967385] [2024-10-13 17:46:01,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,857 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,858 INFO L85 PathProgramCache]: Analyzing trace with hash -1457955290, now seen corresponding path program 1 times [2024-10-13 17:46:01,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,858 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132462018] [2024-10-13 17:46:01,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132462018] [2024-10-13 17:46:01,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132462018] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995296849] [2024-10-13 17:46:01,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,905 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,906 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,906 INFO L87 Difference]: Start difference. First operand 776 states and 1152 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,921 INFO L93 Difference]: Finished difference Result 776 states and 1151 transitions. [2024-10-13 17:46:01,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1151 transitions. [2024-10-13 17:46:01,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1151 transitions. [2024-10-13 17:46:01,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2024-10-13 17:46:01,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2024-10-13 17:46:01,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1151 transitions. [2024-10-13 17:46:01,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1151 transitions. [2024-10-13 17:46:01,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1151 transitions. [2024-10-13 17:46:01,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2024-10-13 17:46:01,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4832474226804124) internal successors, (1151), 775 states have internal predecessors, (1151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1151 transitions. [2024-10-13 17:46:01,941 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1151 transitions. [2024-10-13 17:46:01,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,944 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1151 transitions. [2024-10-13 17:46:01,944 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-13 17:46:01,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1151 transitions. [2024-10-13 17:46:01,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:01,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,949 INFO L745 eck$LassoCheckResult]: Stem: 9585#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 9586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10114#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10133#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 10125#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10126#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9734#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9735#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9804#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9648#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9649#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9615#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9616#L754 assume !(0 == ~M_E~0); 10141#L754-2 assume !(0 == ~T1_E~0); 10083#L759-1 assume !(0 == ~T2_E~0); 9965#L764-1 assume !(0 == ~T3_E~0); 9930#L769-1 assume !(0 == ~T4_E~0); 9931#L774-1 assume !(0 == ~T5_E~0); 9966#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10088#L784-1 assume !(0 == ~T7_E~0); 9927#L789-1 assume !(0 == ~E_1~0); 9928#L794-1 assume !(0 == ~E_2~0); 10002#L799-1 assume !(0 == ~E_3~0); 9938#L804-1 assume !(0 == ~E_4~0); 9939#L809-1 assume !(0 == ~E_5~0); 9960#L814-1 assume !(0 == ~E_6~0); 9386#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9387#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9645#L361 assume 1 == ~m_pc~0; 9646#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10109#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10069#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10070#L930 assume !(0 != activate_threads_~tmp~1#1); 9847#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9639#L380 assume !(1 == ~t1_pc~0); 9640#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10008#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9408#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9409#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10028#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10009#L399 assume 1 == ~t2_pc~0; 10010#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9557#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9710#L946 assume !(0 != activate_threads_~tmp___1~0#1); 9711#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9394#L418 assume !(1 == ~t3_pc~0); 9373#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9374#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9385#L954 assume !(0 != activate_threads_~tmp___2~0#1); 9950#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9951#L437 assume 1 == ~t4_pc~0; 10142#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10064#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9467#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9468#L962 assume !(0 != activate_threads_~tmp___3~0#1); 9763#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10046#L456 assume !(1 == ~t5_pc~0); 9571#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9570#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10073#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9991#L970 assume !(0 != activate_threads_~tmp___4~0#1); 9992#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9461#L475 assume 1 == ~t6_pc~0; 9462#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9503#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9504#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9703#L978 assume !(0 != activate_threads_~tmp___5~0#1); 9943#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9944#L494 assume 1 == ~t7_pc~0; 9892#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9688#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9903#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9967#L986 assume !(0 != activate_threads_~tmp___6~0#1); 9968#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10138#L837 assume !(1 == ~M_E~0); 10112#L837-2 assume !(1 == ~T1_E~0); 10005#L842-1 assume !(1 == ~T2_E~0); 9770#L847-1 assume !(1 == ~T3_E~0); 9771#L852-1 assume !(1 == ~T4_E~0); 9837#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9723#L862-1 assume !(1 == ~T6_E~0); 9724#L867-1 assume !(1 == ~T7_E~0); 9730#L872-1 assume !(1 == ~E_1~0); 9803#L877-1 assume !(1 == ~E_2~0); 9980#L882-1 assume !(1 == ~E_3~0); 10117#L887-1 assume !(1 == ~E_4~0); 10024#L892-1 assume !(1 == ~E_5~0); 10025#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9746#L902-1 assume !(1 == ~E_7~0); 9747#L907-1 assume { :end_inline_reset_delta_events } true; 9614#L1148-2 [2024-10-13 17:46:01,950 INFO L747 eck$LassoCheckResult]: Loop: 9614#L1148-2 assume !false; 9388#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9389#L729-1 assume !false; 10000#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9587#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9588#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9632#L626 assume !(0 != eval_~tmp~0#1); 9633#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9661#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9400#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9401#L759-3 assume !(0 == ~T2_E~0); 9782#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9783#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9952#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9560#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9395#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9396#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9390#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9391#L799-3 assume !(0 == ~E_3~0); 9442#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9668#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9438#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9439#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10056#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9800#L361-24 assume 1 == ~m_pc~0; 9544#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9545#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9490#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9491#L930-24 assume !(0 != activate_threads_~tmp~1#1); 10101#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9935#L380-24 assume 1 == ~t1_pc~0; 9936#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9473#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9882#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9657#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9658#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10011#L399-24 assume !(1 == ~t2_pc~0); 9676#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 9592#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9593#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9836#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9654#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9655#L418-24 assume 1 == ~t3_pc~0; 10100#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9437#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9727#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9563#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9564#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9994#L437-24 assume 1 == ~t4_pc~0; 10060#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10062#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9835#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9547#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9548#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9942#L456-24 assume 1 == ~t5_pc~0; 9916#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9896#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9897#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10095#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9848#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9849#L475-24 assume 1 == ~t6_pc~0; 9397#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9398#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9540#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9541#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9379#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9380#L494-24 assume !(1 == ~t7_pc~0); 9728#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 9708#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9709#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9651#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9652#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10059#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10086#L837-5 assume !(1 == ~T1_E~0); 9843#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9844#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9990#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9900#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9901#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10143#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9817#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9818#L877-3 assume !(1 == ~E_2~0); 9895#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9946#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9579#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9580#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10085#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9740#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9741#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9393#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9677#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9678#L1167 assume !(0 == start_simulation_~tmp~3#1); 9795#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9796#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9601#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9406#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9407#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9777#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9778#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9613#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 9614#L1148-2 [2024-10-13 17:46:01,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2024-10-13 17:46:01,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605962019] [2024-10-13 17:46:01,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [605962019] [2024-10-13 17:46:02,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [605962019] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335643204] [2024-10-13 17:46:02,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,010 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:02,010 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,010 INFO L85 PathProgramCache]: Analyzing trace with hash 1950017927, now seen corresponding path program 2 times [2024-10-13 17:46:02,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516398463] [2024-10-13 17:46:02,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516398463] [2024-10-13 17:46:02,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [516398463] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882904046] [2024-10-13 17:46:02,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,063 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:02,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:02,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:02,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:02,064 INFO L87 Difference]: Start difference. First operand 776 states and 1151 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,080 INFO L93 Difference]: Finished difference Result 776 states and 1150 transitions. [2024-10-13 17:46:02,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1150 transitions. [2024-10-13 17:46:02,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:02,089 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1150 transitions. [2024-10-13 17:46:02,089 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2024-10-13 17:46:02,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2024-10-13 17:46:02,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1150 transitions. [2024-10-13 17:46:02,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:02,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1150 transitions. [2024-10-13 17:46:02,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1150 transitions. [2024-10-13 17:46:02,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2024-10-13 17:46:02,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.481958762886598) internal successors, (1150), 775 states have internal predecessors, (1150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1150 transitions. [2024-10-13 17:46:02,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1150 transitions. [2024-10-13 17:46:02,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:02,107 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1150 transitions. [2024-10-13 17:46:02,107 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-13 17:46:02,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1150 transitions. [2024-10-13 17:46:02,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2024-10-13 17:46:02,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:02,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:02,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,113 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,113 INFO L745 eck$LassoCheckResult]: Stem: 11144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11672#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11692#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11684#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11685#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11293#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11294#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11363#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11208#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11209#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11174#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11175#L754 assume !(0 == ~M_E~0); 11700#L754-2 assume !(0 == ~T1_E~0); 11642#L759-1 assume !(0 == ~T2_E~0); 11524#L764-1 assume !(0 == ~T3_E~0); 11490#L769-1 assume !(0 == ~T4_E~0); 11491#L774-1 assume !(0 == ~T5_E~0); 11525#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11647#L784-1 assume !(0 == ~T7_E~0); 11487#L789-1 assume !(0 == ~E_1~0); 11488#L794-1 assume !(0 == ~E_2~0); 11561#L799-1 assume !(0 == ~E_3~0); 11497#L804-1 assume !(0 == ~E_4~0); 11498#L809-1 assume !(0 == ~E_5~0); 11519#L814-1 assume !(0 == ~E_6~0); 10949#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10950#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11204#L361 assume 1 == ~m_pc~0; 11205#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11668#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11628#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11629#L930 assume !(0 != activate_threads_~tmp~1#1); 11406#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11198#L380 assume !(1 == ~t1_pc~0); 11199#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11567#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10967#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10968#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11587#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11568#L399 assume 1 == ~t2_pc~0; 11569#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11116#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11276#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11269#L946 assume !(0 != activate_threads_~tmp___1~0#1); 11270#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10953#L418 assume !(1 == ~t3_pc~0); 10932#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10933#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10943#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10944#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11509#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11510#L437 assume 1 == ~t4_pc~0; 11701#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11624#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11028#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11322#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11610#L456 assume !(1 == ~t5_pc~0); 11130#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11129#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11632#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11551#L970 assume !(0 != activate_threads_~tmp___4~0#1); 11552#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11020#L475 assume 1 == ~t6_pc~0; 11021#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11062#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11063#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11262#L978 assume !(0 != activate_threads_~tmp___5~0#1); 11502#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11503#L494 assume 1 == ~t7_pc~0; 11451#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11247#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11462#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11526#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11527#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11697#L837 assume !(1 == ~M_E~0); 11671#L837-2 assume !(1 == ~T1_E~0); 11564#L842-1 assume !(1 == ~T2_E~0); 11329#L847-1 assume !(1 == ~T3_E~0); 11330#L852-1 assume !(1 == ~T4_E~0); 11396#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11282#L862-1 assume !(1 == ~T6_E~0); 11283#L867-1 assume !(1 == ~T7_E~0); 11289#L872-1 assume !(1 == ~E_1~0); 11362#L877-1 assume !(1 == ~E_2~0); 11539#L882-1 assume !(1 == ~E_3~0); 11676#L887-1 assume !(1 == ~E_4~0); 11583#L892-1 assume !(1 == ~E_5~0); 11584#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11305#L902-1 assume !(1 == ~E_7~0); 11306#L907-1 assume { :end_inline_reset_delta_events } true; 11173#L1148-2 [2024-10-13 17:46:02,113 INFO L747 eck$LassoCheckResult]: Loop: 11173#L1148-2 assume !false; 10945#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10946#L729-1 assume !false; 11559#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11146#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11147#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11295#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11191#L626 assume !(0 != eval_~tmp~0#1); 11192#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11405#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11220#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10959#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10960#L759-3 assume !(0 == ~T2_E~0); 11341#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11342#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11511#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11119#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10954#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10955#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10947#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10948#L799-3 assume !(0 == ~E_3~0); 11001#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11227#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10997#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10998#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11615#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11359#L361-24 assume !(1 == ~m_pc~0); 11105#L361-26 is_master_triggered_~__retres1~0#1 := 0; 11104#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11049#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11050#L930-24 assume !(0 != activate_threads_~tmp~1#1); 11660#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11494#L380-24 assume 1 == ~t1_pc~0; 11495#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11032#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11441#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11216#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11217#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11570#L399-24 assume !(1 == ~t2_pc~0); 11235#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11151#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11152#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11395#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11213#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11214#L418-24 assume !(1 == ~t3_pc~0); 10995#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 10996#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11286#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11122#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11123#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11553#L437-24 assume 1 == ~t4_pc~0; 11619#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11621#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11394#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11106#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11107#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11501#L456-24 assume 1 == ~t5_pc~0; 11475#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11455#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11456#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11654#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11407#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11408#L475-24 assume 1 == ~t6_pc~0; 10956#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10957#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11099#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11100#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10938#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10939#L494-24 assume 1 == ~t7_pc~0; 11378#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11267#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11268#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11210#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11211#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11618#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11645#L837-5 assume !(1 == ~T1_E~0); 11402#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11403#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11549#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11459#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11460#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11702#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11376#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11377#L877-3 assume !(1 == ~E_2~0); 11454#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11505#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11138#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11139#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11644#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11299#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11300#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10952#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11236#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11237#L1167 assume !(0 == start_simulation_~tmp~3#1); 11354#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11355#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11160#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10965#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10966#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11336#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11337#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11172#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11173#L1148-2 [2024-10-13 17:46:02,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,115 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2024-10-13 17:46:02,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896160744] [2024-10-13 17:46:02,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896160744] [2024-10-13 17:46:02,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896160744] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,195 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,195 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014726067] [2024-10-13 17:46:02,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,196 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:02,196 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,196 INFO L85 PathProgramCache]: Analyzing trace with hash -1778828634, now seen corresponding path program 1 times [2024-10-13 17:46:02,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027329835] [2024-10-13 17:46:02,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027329835] [2024-10-13 17:46:02,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027329835] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928311046] [2024-10-13 17:46:02,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,248 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:02,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:02,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:46:02,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:46:02,249 INFO L87 Difference]: Start difference. First operand 776 states and 1150 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,354 INFO L93 Difference]: Finished difference Result 1464 states and 2164 transitions. [2024-10-13 17:46:02,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2164 transitions. [2024-10-13 17:46:02,362 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2024-10-13 17:46:02,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2164 transitions. [2024-10-13 17:46:02,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1464 [2024-10-13 17:46:02,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1464 [2024-10-13 17:46:02,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 2164 transitions. [2024-10-13 17:46:02,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:02,372 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2024-10-13 17:46:02,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2164 transitions. [2024-10-13 17:46:02,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464. [2024-10-13 17:46:02,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.4781420765027322) internal successors, (2164), 1463 states have internal predecessors, (2164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2164 transitions. [2024-10-13 17:46:02,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2024-10-13 17:46:02,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:46:02,405 INFO L425 stractBuchiCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2024-10-13 17:46:02,406 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-13 17:46:02,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2164 transitions. [2024-10-13 17:46:02,413 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2024-10-13 17:46:02,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:02,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:02,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,414 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,415 INFO L745 eck$LassoCheckResult]: Stem: 13395#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13396#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14004#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13990#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13991#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13547#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13548#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13625#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13459#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13460#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13425#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13426#L754 assume !(0 == ~M_E~0); 14022#L754-2 assume !(0 == ~T1_E~0); 13932#L759-1 assume !(0 == ~T2_E~0); 13799#L764-1 assume !(0 == ~T3_E~0); 13762#L769-1 assume !(0 == ~T4_E~0); 13763#L774-1 assume !(0 == ~T5_E~0); 13800#L779-1 assume !(0 == ~T6_E~0); 13940#L784-1 assume !(0 == ~T7_E~0); 13759#L789-1 assume !(0 == ~E_1~0); 13760#L794-1 assume !(0 == ~E_2~0); 13839#L799-1 assume !(0 == ~E_3~0); 13769#L804-1 assume !(0 == ~E_4~0); 13770#L809-1 assume !(0 == ~E_5~0); 13794#L814-1 assume !(0 == ~E_6~0); 13195#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13196#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13456#L361 assume 1 == ~m_pc~0; 13457#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13966#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13917#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13918#L930 assume !(0 != activate_threads_~tmp~1#1); 13671#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13450#L380 assume !(1 == ~t1_pc~0); 13451#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13848#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13217#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13218#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13873#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13849#L399 assume 1 == ~t2_pc~0; 13850#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13367#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13529#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13522#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13523#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13203#L418 assume !(1 == ~t3_pc~0); 13182#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13183#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13194#L954 assume !(0 != activate_threads_~tmp___2~0#1); 13782#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13783#L437 assume 1 == ~t4_pc~0; 14023#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13912#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13276#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13277#L962 assume !(0 != activate_threads_~tmp___3~0#1); 13576#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13897#L456 assume !(1 == ~t5_pc~0); 13381#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13380#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13921#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13828#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13829#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13270#L475 assume 1 == ~t6_pc~0; 13271#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13312#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13515#L978 assume !(0 != activate_threads_~tmp___5~0#1); 13775#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13776#L494 assume 1 == ~t7_pc~0; 13720#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13500#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13734#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13801#L986 assume !(0 != activate_threads_~tmp___6~0#1); 13802#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14012#L837 assume !(1 == ~M_E~0); 13971#L837-2 assume !(1 == ~T1_E~0); 13844#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13845#L847-1 assume !(1 == ~T3_E~0); 14069#L852-1 assume !(1 == ~T4_E~0); 14067#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14066#L862-1 assume !(1 == ~T6_E~0); 13536#L867-1 assume !(1 == ~T7_E~0); 13623#L872-1 assume !(1 == ~E_1~0); 13624#L877-1 assume !(1 == ~E_2~0); 13816#L882-1 assume !(1 == ~E_3~0); 13977#L887-1 assume !(1 == ~E_4~0); 14026#L892-1 assume !(1 == ~E_5~0); 14007#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13559#L902-1 assume !(1 == ~E_7~0); 13560#L907-1 assume { :end_inline_reset_delta_events } true; 13424#L1148-2 [2024-10-13 17:46:02,415 INFO L747 eck$LassoCheckResult]: Loop: 13424#L1148-2 assume !false; 13197#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13198#L729-1 assume !false; 14049#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14045#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13946#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13554#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13445#L626 assume !(0 != eval_~tmp~0#1); 13446#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13670#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13472#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13209#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13210#L759-3 assume !(0 == ~T2_E~0); 14036#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14213#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14212#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14211#L779-3 assume !(0 == ~T6_E~0); 14210#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14209#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14208#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14207#L799-3 assume !(0 == ~E_3~0); 14206#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14205#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14204#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14203#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14202#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14201#L361-24 assume 1 == ~m_pc~0; 13353#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13354#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13299#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13300#L930-24 assume !(0 != activate_threads_~tmp~1#1); 13957#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13766#L380-24 assume !(1 == ~t1_pc~0); 13281#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 13282#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13710#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13468#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13469#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13851#L399-24 assume !(1 == ~t2_pc~0); 13924#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 14188#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14187#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14186#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13465#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13466#L418-24 assume 1 == ~t3_pc~0; 14184#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14183#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14182#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14181#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14180#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14179#L437-24 assume !(1 == ~t4_pc~0); 14177#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14176#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14175#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14174#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14173#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14172#L456-24 assume 1 == ~t5_pc~0; 14170#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14169#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14168#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14167#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13672#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13673#L475-24 assume !(1 == ~t6_pc~0); 14034#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 13733#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13349#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13350#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13771#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14127#L494-24 assume !(1 == ~t7_pc~0); 13541#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 13519#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13520#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14118#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13906#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13907#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13937#L837-5 assume !(1 == ~T1_E~0); 13667#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13668#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14110#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14108#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14107#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14031#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14105#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14104#L877-3 assume !(1 == ~E_2~0); 14101#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14100#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14099#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13935#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13936#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13552#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13553#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14084#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 13490#L1167 assume !(0 == start_simulation_~tmp~3#1); 14082#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14081#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14073#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14071#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14070#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14068#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13423#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 13424#L1148-2 [2024-10-13 17:46:02,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,416 INFO L85 PathProgramCache]: Analyzing trace with hash -2141947347, now seen corresponding path program 1 times [2024-10-13 17:46:02,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479000035] [2024-10-13 17:46:02,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479000035] [2024-10-13 17:46:02,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [479000035] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:02,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457610390] [2024-10-13 17:46:02,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,469 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:02,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,470 INFO L85 PathProgramCache]: Analyzing trace with hash 596622562, now seen corresponding path program 1 times [2024-10-13 17:46:02,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852324866] [2024-10-13 17:46:02,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852324866] [2024-10-13 17:46:02,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852324866] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436114567] [2024-10-13 17:46:02,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,514 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:02,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:02,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:02,514 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:02,514 INFO L87 Difference]: Start difference. First operand 1464 states and 2164 transitions. cyclomatic complexity: 702 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,593 INFO L93 Difference]: Finished difference Result 1464 states and 2138 transitions. [2024-10-13 17:46:02,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2138 transitions. [2024-10-13 17:46:02,601 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2024-10-13 17:46:02,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2138 transitions. [2024-10-13 17:46:02,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1464 [2024-10-13 17:46:02,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1464 [2024-10-13 17:46:02,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 2138 transitions. [2024-10-13 17:46:02,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:02,609 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2024-10-13 17:46:02,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2138 transitions. [2024-10-13 17:46:02,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464. [2024-10-13 17:46:02,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.460382513661202) internal successors, (2138), 1463 states have internal predecessors, (2138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2138 transitions. [2024-10-13 17:46:02,631 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2024-10-13 17:46:02,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:02,633 INFO L425 stractBuchiCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2024-10-13 17:46:02,633 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-13 17:46:02,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2138 transitions. [2024-10-13 17:46:02,640 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2024-10-13 17:46:02,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:02,640 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:02,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,642 INFO L745 eck$LassoCheckResult]: Stem: 16327#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16893#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16922#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 16911#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16912#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16480#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16481#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16552#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16390#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16391#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16357#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16358#L754 assume !(0 == ~M_E~0); 16934#L754-2 assume !(0 == ~T1_E~0); 16860#L759-1 assume !(0 == ~T2_E~0); 16721#L764-1 assume !(0 == ~T3_E~0); 16681#L769-1 assume !(0 == ~T4_E~0); 16682#L774-1 assume !(0 == ~T5_E~0); 16722#L779-1 assume !(0 == ~T6_E~0); 16865#L784-1 assume !(0 == ~T7_E~0); 16678#L789-1 assume !(0 == ~E_1~0); 16679#L794-1 assume !(0 == ~E_2~0); 16764#L799-1 assume !(0 == ~E_3~0); 16689#L804-1 assume !(0 == ~E_4~0); 16690#L809-1 assume !(0 == ~E_5~0); 16716#L814-1 assume !(0 == ~E_6~0); 16130#L819-1 assume !(0 == ~E_7~0); 16131#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16387#L361 assume 1 == ~m_pc~0; 16388#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16888#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16846#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16847#L930 assume !(0 != activate_threads_~tmp~1#1); 16597#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16381#L380 assume !(1 == ~t1_pc~0); 16382#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16773#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16152#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16153#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16800#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16774#L399 assume 1 == ~t2_pc~0; 16775#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16299#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16456#L946 assume !(0 != activate_threads_~tmp___1~0#1); 16457#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16138#L418 assume !(1 == ~t3_pc~0); 16117#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16118#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16128#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16129#L954 assume !(0 != activate_threads_~tmp___2~0#1); 16702#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16703#L437 assume 1 == ~t4_pc~0; 16935#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16841#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16211#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16212#L962 assume !(0 != activate_threads_~tmp___3~0#1); 16510#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16820#L456 assume !(1 == ~t5_pc~0); 16313#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16312#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16850#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16752#L970 assume !(0 != activate_threads_~tmp___4~0#1); 16753#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16205#L475 assume 1 == ~t6_pc~0; 16206#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16247#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16449#L978 assume !(0 != activate_threads_~tmp___5~0#1); 16694#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16695#L494 assume !(1 == ~t7_pc~0); 16433#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16434#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16723#L986 assume !(0 != activate_threads_~tmp___6~0#1); 16724#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16928#L837 assume !(1 == ~M_E~0); 16892#L837-2 assume !(1 == ~T1_E~0); 16769#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16517#L847-1 assume !(1 == ~T3_E~0); 16518#L852-1 assume !(1 == ~T4_E~0); 16586#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16469#L862-1 assume !(1 == ~T6_E~0); 16470#L867-1 assume !(1 == ~T7_E~0); 16476#L872-1 assume !(1 == ~E_1~0); 16551#L877-1 assume !(1 == ~E_2~0); 16738#L882-1 assume !(1 == ~E_3~0); 16985#L887-1 assume !(1 == ~E_4~0); 16792#L892-1 assume !(1 == ~E_5~0); 16793#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16493#L902-1 assume !(1 == ~E_7~0); 16494#L907-1 assume { :end_inline_reset_delta_events } true; 16538#L1148-2 [2024-10-13 17:46:02,642 INFO L747 eck$LassoCheckResult]: Loop: 16538#L1148-2 assume !false; 16539#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16761#L729-1 assume !false; 16762#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16329#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16330#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16948#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16374#L626 assume !(0 != eval_~tmp~0#1); 16375#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16596#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16405#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16144#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16145#L759-3 assume !(0 == ~T2_E~0); 16945#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17451#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17450#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17449#L779-3 assume !(0 == ~T6_E~0); 17448#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17447#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17446#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17445#L799-3 assume !(0 == ~E_3~0); 17444#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17443#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17442#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17441#L819-3 assume !(0 == ~E_7~0); 17440#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17439#L361-24 assume 1 == ~m_pc~0; 17437#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17436#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17435#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17434#L930-24 assume !(0 != activate_threads_~tmp~1#1); 17433#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17432#L380-24 assume 1 == ~t1_pc~0; 17430#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17429#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17428#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17427#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17426#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17425#L399-24 assume !(1 == ~t2_pc~0); 17424#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 17422#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17421#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17420#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17419#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17418#L418-24 assume 1 == ~t3_pc~0; 17416#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17415#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17414#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17413#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17412#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17411#L437-24 assume !(1 == ~t4_pc~0); 17409#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 17408#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17407#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17406#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17405#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17404#L456-24 assume 1 == ~t5_pc~0; 17402#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17401#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17400#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17399#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17398#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17397#L475-24 assume !(1 == ~t6_pc~0); 17395#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 17394#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17393#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17392#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17391#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17390#L494-24 assume !(1 == ~t7_pc~0); 17388#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 17387#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17386#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17385#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17384#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17383#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17382#L837-5 assume !(1 == ~T1_E~0); 17381#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16593#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17380#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17379#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17378#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16942#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16565#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16566#L877-3 assume !(1 == ~E_2~0); 16645#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16697#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16321#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16322#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16862#L902-3 assume !(1 == ~E_7~0); 16487#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16488#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16137#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16422#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16423#L1167 assume !(0 == start_simulation_~tmp~3#1); 16543#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16544#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16343#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16982#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16981#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16979#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16977#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16961#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 16538#L1148-2 [2024-10-13 17:46:02,643 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1307665866, now seen corresponding path program 1 times [2024-10-13 17:46:02,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074527526] [2024-10-13 17:46:02,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,689 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074527526] [2024-10-13 17:46:02,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074527526] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:02,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978996640] [2024-10-13 17:46:02,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,691 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:02,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,691 INFO L85 PathProgramCache]: Analyzing trace with hash -482217473, now seen corresponding path program 1 times [2024-10-13 17:46:02,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384439465] [2024-10-13 17:46:02,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384439465] [2024-10-13 17:46:02,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384439465] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,732 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,732 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491240137] [2024-10-13 17:46:02,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,733 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:02,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:02,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:02,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:02,733 INFO L87 Difference]: Start difference. First operand 1464 states and 2138 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,831 INFO L93 Difference]: Finished difference Result 2793 states and 4040 transitions. [2024-10-13 17:46:02,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2793 states and 4040 transitions. [2024-10-13 17:46:02,850 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2676 [2024-10-13 17:46:02,863 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2793 states to 2793 states and 4040 transitions. [2024-10-13 17:46:02,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2793 [2024-10-13 17:46:02,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2793 [2024-10-13 17:46:02,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2793 states and 4040 transitions. [2024-10-13 17:46:02,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:02,871 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2793 states and 4040 transitions. [2024-10-13 17:46:02,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2793 states and 4040 transitions. [2024-10-13 17:46:02,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2793 to 2679. [2024-10-13 17:46:02,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2679 states, 2679 states have (on average 1.4497946995147444) internal successors, (3884), 2678 states have internal predecessors, (3884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2679 states to 2679 states and 3884 transitions. [2024-10-13 17:46:02,918 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2679 states and 3884 transitions. [2024-10-13 17:46:02,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:02,920 INFO L425 stractBuchiCegarLoop]: Abstraction has 2679 states and 3884 transitions. [2024-10-13 17:46:02,920 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-13 17:46:02,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2679 states and 3884 transitions. [2024-10-13 17:46:02,929 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2562 [2024-10-13 17:46:02,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:02,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:02,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,931 INFO L745 eck$LassoCheckResult]: Stem: 20589#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 21204#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21205#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21256#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 21238#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21239#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20743#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20744#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20818#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20651#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20652#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20619#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20620#L754 assume !(0 == ~M_E~0); 21273#L754-2 assume !(0 == ~T1_E~0); 21157#L759-1 assume !(0 == ~T2_E~0); 21013#L764-1 assume !(0 == ~T3_E~0); 20966#L769-1 assume !(0 == ~T4_E~0); 20967#L774-1 assume !(0 == ~T5_E~0); 21014#L779-1 assume !(0 == ~T6_E~0); 21165#L784-1 assume !(0 == ~T7_E~0); 20962#L789-1 assume !(0 == ~E_1~0); 20963#L794-1 assume !(0 == ~E_2~0); 21062#L799-1 assume !(0 == ~E_3~0); 20976#L804-1 assume !(0 == ~E_4~0); 20977#L809-1 assume !(0 == ~E_5~0); 21007#L814-1 assume !(0 == ~E_6~0); 20394#L819-1 assume !(0 == ~E_7~0); 20395#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20649#L361 assume !(1 == ~m_pc~0); 20650#L361-2 is_master_triggered_~__retres1~0#1 := 0; 21198#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21144#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21145#L930 assume !(0 != activate_threads_~tmp~1#1); 20870#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20643#L380 assume !(1 == ~t1_pc~0); 20644#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21073#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20417#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21096#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21074#L399 assume 1 == ~t2_pc~0; 21075#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20561#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20722#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20715#L946 assume !(0 != activate_threads_~tmp___1~0#1); 20716#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20402#L418 assume !(1 == ~t3_pc~0); 20381#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20382#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20392#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20393#L954 assume !(0 != activate_threads_~tmp___2~0#1); 20994#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20995#L437 assume 1 == ~t4_pc~0; 21275#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21137#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20475#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20476#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20773#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21116#L456 assume !(1 == ~t5_pc~0); 20575#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20574#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21148#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21049#L970 assume !(0 != activate_threads_~tmp___4~0#1); 21050#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20469#L475 assume 1 == ~t6_pc~0; 20470#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20510#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20511#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20708#L978 assume !(0 != activate_threads_~tmp___5~0#1); 20983#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20984#L494 assume !(1 == ~t7_pc~0); 20692#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20693#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20934#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21015#L986 assume !(0 != activate_threads_~tmp___6~0#1); 21016#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21264#L837 assume !(1 == ~M_E~0); 21203#L837-2 assume !(1 == ~T1_E~0); 21068#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20781#L847-1 assume !(1 == ~T3_E~0); 20782#L852-1 assume !(1 == ~T4_E~0); 22571#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22563#L862-1 assume !(1 == ~T6_E~0); 20729#L867-1 assume !(1 == ~T7_E~0); 22560#L872-1 assume !(1 == ~E_1~0); 22559#L877-1 assume !(1 == ~E_2~0); 22558#L882-1 assume !(1 == ~E_3~0); 22557#L887-1 assume !(1 == ~E_4~0); 22556#L892-1 assume !(1 == ~E_5~0); 22554#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 22552#L902-1 assume !(1 == ~E_7~0); 22551#L907-1 assume { :end_inline_reset_delta_events } true; 22549#L1148-2 [2024-10-13 17:46:02,932 INFO L747 eck$LassoCheckResult]: Loop: 22549#L1148-2 assume !false; 22528#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22527#L729-1 assume !false; 22526#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20591#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20592#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20745#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20746#L626 assume !(0 != eval_~tmp~0#1); 21091#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20664#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20408#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20409#L759-3 assume !(0 == ~T2_E~0); 22517#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22691#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22690#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22689#L779-3 assume !(0 == ~T6_E~0); 22688#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22687#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22686#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22685#L799-3 assume !(0 == ~E_3~0); 22684#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22683#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22682#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22681#L819-3 assume !(0 == ~E_7~0); 22680#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22679#L361-24 assume !(1 == ~m_pc~0); 22678#L361-26 is_master_triggered_~__retres1~0#1 := 0; 22677#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22676#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22675#L930-24 assume !(0 != activate_threads_~tmp~1#1); 22674#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22673#L380-24 assume !(1 == ~t1_pc~0); 22672#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22670#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22669#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22668#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22667#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22666#L399-24 assume 1 == ~t2_pc~0; 22664#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22663#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22662#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22661#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22660#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22659#L418-24 assume 1 == ~t3_pc~0; 22657#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20734#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20735#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20567#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20568#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21052#L437-24 assume !(1 == ~t4_pc~0); 22630#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 21287#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21288#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20553#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20554#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21250#L456-24 assume 1 == ~t5_pc~0; 21251#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22627#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22626#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21207#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21208#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22623#L475-24 assume 1 == ~t6_pc~0; 20405#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20406#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20546#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20547#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20978#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20924#L494-24 assume !(1 == ~t7_pc~0); 20834#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 20713#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20714#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22604#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21131#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21132#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21265#L837-5 assume !(1 == ~T1_E~0); 21266#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20865#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21232#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20929#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20930#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21294#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20831#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20832#L877-3 assume !(1 == ~E_2~0); 22591#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20987#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20988#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21160#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21161#L902-3 assume !(1 == ~E_7~0); 20750#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20751#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21000#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20680#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 20681#L1167 assume !(0 == start_simulation_~tmp~3#1); 21234#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21292#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20605#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 20415#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22555#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22553#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 22550#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 22549#L1148-2 [2024-10-13 17:46:02,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,932 INFO L85 PathProgramCache]: Analyzing trace with hash 2012584553, now seen corresponding path program 1 times [2024-10-13 17:46:02,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064659640] [2024-10-13 17:46:02,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064659640] [2024-10-13 17:46:03,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1064659640] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:03,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694699226] [2024-10-13 17:46:03,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,001 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:03,002 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,003 INFO L85 PathProgramCache]: Analyzing trace with hash -601253057, now seen corresponding path program 1 times [2024-10-13 17:46:03,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679475030] [2024-10-13 17:46:03,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:03,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:03,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [679475030] [2024-10-13 17:46:03,046 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [679475030] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,046 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:03,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406852709] [2024-10-13 17:46:03,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,047 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:03,047 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:03,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:03,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:03,049 INFO L87 Difference]: Start difference. First operand 2679 states and 3884 transitions. cyclomatic complexity: 1209 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:03,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:03,280 INFO L93 Difference]: Finished difference Result 2784 states and 3989 transitions. [2024-10-13 17:46:03,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2784 states and 3989 transitions. [2024-10-13 17:46:03,294 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2664 [2024-10-13 17:46:03,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2784 states to 2784 states and 3989 transitions. [2024-10-13 17:46:03,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2784 [2024-10-13 17:46:03,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2784 [2024-10-13 17:46:03,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2784 states and 3989 transitions. [2024-10-13 17:46:03,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:03,312 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2784 states and 3989 transitions. [2024-10-13 17:46:03,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2784 states and 3989 transitions. [2024-10-13 17:46:03,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2784 to 2784. [2024-10-13 17:46:03,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2784 states, 2784 states have (on average 1.432830459770115) internal successors, (3989), 2783 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:03,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2784 states to 2784 states and 3989 transitions. [2024-10-13 17:46:03,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2784 states and 3989 transitions. [2024-10-13 17:46:03,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:03,361 INFO L425 stractBuchiCegarLoop]: Abstraction has 2784 states and 3989 transitions. [2024-10-13 17:46:03,361 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-13 17:46:03,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2784 states and 3989 transitions. [2024-10-13 17:46:03,369 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2664 [2024-10-13 17:46:03,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:03,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:03,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:03,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:03,371 INFO L745 eck$LassoCheckResult]: Stem: 26063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 26064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 26620#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26621#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26657#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 26643#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26644#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26213#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26214#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26285#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26126#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26127#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26093#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26094#L754 assume !(0 == ~M_E~0); 26673#L754-2 assume !(0 == ~T1_E~0); 26585#L759-1 assume !(0 == ~T2_E~0); 26456#L764-1 assume !(0 == ~T3_E~0); 26419#L769-1 assume !(0 == ~T4_E~0); 26420#L774-1 assume !(0 == ~T5_E~0); 26457#L779-1 assume !(0 == ~T6_E~0); 26591#L784-1 assume !(0 == ~T7_E~0); 26416#L789-1 assume !(0 == ~E_1~0); 26417#L794-1 assume !(0 == ~E_2~0); 26498#L799-1 assume !(0 == ~E_3~0); 26427#L804-1 assume !(0 == ~E_4~0); 26428#L809-1 assume !(0 == ~E_5~0); 26451#L814-1 assume !(0 == ~E_6~0); 25870#L819-1 assume !(0 == ~E_7~0); 25871#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26123#L361 assume !(1 == ~m_pc~0); 26124#L361-2 is_master_triggered_~__retres1~0#1 := 0; 26616#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26572#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26573#L930 assume !(0 != activate_threads_~tmp~1#1); 26330#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26117#L380 assume !(1 == ~t1_pc~0); 26118#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26654#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25888#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25889#L938 assume !(0 != activate_threads_~tmp___0~0#1); 26528#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26508#L399 assume 1 == ~t2_pc~0; 26509#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26035#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26194#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26187#L946 assume !(0 != activate_threads_~tmp___1~0#1); 26188#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25874#L418 assume !(1 == ~t3_pc~0); 25853#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25854#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25865#L954 assume !(0 != activate_threads_~tmp___2~0#1); 26440#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26441#L437 assume 1 == ~t4_pc~0; 26674#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26567#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25947#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25948#L962 assume !(0 != activate_threads_~tmp___3~0#1); 26242#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26553#L456 assume !(1 == ~t5_pc~0); 26049#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26048#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26576#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26488#L970 assume !(0 != activate_threads_~tmp___4~0#1); 26489#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25941#L475 assume 1 == ~t6_pc~0; 25942#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25984#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25985#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26180#L978 assume !(0 != activate_threads_~tmp___5~0#1); 26432#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26433#L494 assume !(1 == ~t7_pc~0); 26164#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26165#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26387#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26458#L986 assume !(0 != activate_threads_~tmp___6~0#1); 26459#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26665#L837 assume !(1 == ~M_E~0); 26619#L837-2 assume !(1 == ~T1_E~0); 26503#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26504#L847-1 assume !(1 == ~T3_E~0); 27827#L852-1 assume !(1 == ~T4_E~0); 27825#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27823#L862-1 assume !(1 == ~T6_E~0); 26202#L867-1 assume !(1 == ~T7_E~0); 27820#L872-1 assume !(1 == ~E_1~0); 27817#L877-1 assume !(1 == ~E_2~0); 27815#L882-1 assume !(1 == ~E_3~0); 27813#L887-1 assume !(1 == ~E_4~0); 27811#L892-1 assume !(1 == ~E_5~0); 27809#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 27807#L902-1 assume !(1 == ~E_7~0); 27804#L907-1 assume { :end_inline_reset_delta_events } true; 27801#L1148-2 [2024-10-13 17:46:03,371 INFO L747 eck$LassoCheckResult]: Loop: 27801#L1148-2 assume !false; 27721#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27719#L729-1 assume !false; 27716#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27708#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 26774#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26775#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26737#L626 assume !(0 != eval_~tmp~0#1); 26525#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26329#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26138#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25880#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25881#L759-3 assume !(0 == ~T2_E~0); 26262#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26263#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26442#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26038#L779-3 assume !(0 == ~T6_E~0); 25875#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25876#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25866#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25867#L799-3 assume !(0 == ~E_3~0); 25922#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26145#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25918#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25919#L819-3 assume !(0 == ~E_7~0); 26559#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26280#L361-24 assume !(1 == ~m_pc~0); 26281#L361-26 is_master_triggered_~__retres1~0#1 := 0; 28547#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28421#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28420#L930-24 assume !(0 != activate_threads_~tmp~1#1); 28419#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28418#L380-24 assume !(1 == ~t1_pc~0); 28416#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 28414#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28412#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28411#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 28409#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28408#L399-24 assume 1 == ~t2_pc~0; 28406#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28405#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28404#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28403#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28401#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28400#L418-24 assume 1 == ~t3_pc~0; 28398#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28397#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28396#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28394#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28392#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28390#L437-24 assume !(1 == ~t4_pc~0); 28387#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 28386#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28382#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28380#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28378#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28376#L456-24 assume 1 == ~t5_pc~0; 28372#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28370#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28368#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28365#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28363#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28361#L475-24 assume !(1 == ~t6_pc~0); 28358#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 28356#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28354#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28351#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28349#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28347#L494-24 assume !(1 == ~t7_pc~0); 28344#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 28210#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28161#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28153#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28146#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28137#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28130#L837-5 assume !(1 == ~T1_E~0); 28123#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26326#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28115#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28110#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28103#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26682#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28091#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28084#L877-3 assume !(1 == ~E_2~0); 28079#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28067#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28056#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28051#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28048#L902-3 assume !(1 == ~E_7~0); 28046#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27895#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27889#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27880#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 27871#L1167 assume !(0 == start_simulation_~tmp~3#1); 27866#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27860#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27852#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27851#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 27850#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27848#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27846#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 27803#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 27801#L1148-2 [2024-10-13 17:46:03,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,372 INFO L85 PathProgramCache]: Analyzing trace with hash -1406363737, now seen corresponding path program 1 times [2024-10-13 17:46:03,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283112220] [2024-10-13 17:46:03,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:03,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:03,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,416 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [283112220] [2024-10-13 17:46:03,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [283112220] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,419 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,419 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:03,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469408840] [2024-10-13 17:46:03,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,419 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:03,420 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,420 INFO L85 PathProgramCache]: Analyzing trace with hash -933229284, now seen corresponding path program 1 times [2024-10-13 17:46:03,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882083132] [2024-10-13 17:46:03,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:03,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:03,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882083132] [2024-10-13 17:46:03,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882083132] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:03,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58216983] [2024-10-13 17:46:03,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,459 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:03,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:03,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:03,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:03,461 INFO L87 Difference]: Start difference. First operand 2784 states and 3989 transitions. cyclomatic complexity: 1209 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:03,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:03,551 INFO L93 Difference]: Finished difference Result 5175 states and 7372 transitions. [2024-10-13 17:46:03,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5175 states and 7372 transitions. [2024-10-13 17:46:03,577 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5044 [2024-10-13 17:46:03,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5175 states to 5175 states and 7372 transitions. [2024-10-13 17:46:03,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5175 [2024-10-13 17:46:03,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5175 [2024-10-13 17:46:03,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5175 states and 7372 transitions. [2024-10-13 17:46:03,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:03,619 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5175 states and 7372 transitions. [2024-10-13 17:46:03,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5175 states and 7372 transitions. [2024-10-13 17:46:03,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5175 to 5167. [2024-10-13 17:46:03,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5167 states, 5167 states have (on average 1.4251983742984324) internal successors, (7364), 5166 states have internal predecessors, (7364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:03,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5167 states to 5167 states and 7364 transitions. [2024-10-13 17:46:03,774 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5167 states and 7364 transitions. [2024-10-13 17:46:03,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:03,776 INFO L425 stractBuchiCegarLoop]: Abstraction has 5167 states and 7364 transitions. [2024-10-13 17:46:03,777 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-13 17:46:03,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5167 states and 7364 transitions. [2024-10-13 17:46:03,798 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5036 [2024-10-13 17:46:03,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:03,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:03,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:03,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:03,800 INFO L745 eck$LassoCheckResult]: Stem: 34031#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 34032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 34604#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34605#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34639#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 34626#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34627#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34184#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34185#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34258#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34096#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34097#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34064#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34065#L754 assume !(0 == ~M_E~0); 34654#L754-2 assume !(0 == ~T1_E~0); 34565#L759-1 assume !(0 == ~T2_E~0); 34435#L764-1 assume !(0 == ~T3_E~0); 34394#L769-1 assume !(0 == ~T4_E~0); 34395#L774-1 assume !(0 == ~T5_E~0); 34436#L779-1 assume !(0 == ~T6_E~0); 34575#L784-1 assume !(0 == ~T7_E~0); 34392#L789-1 assume !(0 == ~E_1~0); 34393#L794-1 assume !(0 == ~E_2~0); 34480#L799-1 assume !(0 == ~E_3~0); 34402#L804-1 assume !(0 == ~E_4~0); 34403#L809-1 assume !(0 == ~E_5~0); 34430#L814-1 assume !(0 == ~E_6~0); 33834#L819-1 assume !(0 == ~E_7~0); 33835#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34094#L361 assume !(1 == ~m_pc~0); 34095#L361-2 is_master_triggered_~__retres1~0#1 := 0; 34600#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34553#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34554#L930 assume !(0 != activate_threads_~tmp~1#1); 34307#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34088#L380 assume !(1 == ~t1_pc~0); 34089#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34676#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33854#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33855#L938 assume !(0 != activate_threads_~tmp___0~0#1); 34511#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34490#L399 assume !(1 == ~t2_pc~0); 34002#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34003#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34166#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34159#L946 assume !(0 != activate_threads_~tmp___1~0#1); 34160#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33840#L418 assume !(1 == ~t3_pc~0); 33819#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33820#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33830#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33831#L954 assume !(0 != activate_threads_~tmp___2~0#1); 34419#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34420#L437 assume 1 == ~t4_pc~0; 34655#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34547#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33913#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33914#L962 assume !(0 != activate_threads_~tmp___3~0#1); 34214#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34530#L456 assume !(1 == ~t5_pc~0); 34017#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 34016#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34557#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34470#L970 assume !(0 != activate_threads_~tmp___4~0#1); 34471#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33907#L475 assume 1 == ~t6_pc~0; 33908#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33950#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33951#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34152#L978 assume !(0 != activate_threads_~tmp___5~0#1); 34408#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34409#L494 assume !(1 == ~t7_pc~0); 34136#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34137#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34364#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34437#L986 assume !(0 != activate_threads_~tmp___6~0#1); 34438#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34648#L837 assume !(1 == ~M_E~0); 34603#L837-2 assume !(1 == ~T1_E~0); 34485#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34486#L847-1 assume !(1 == ~T3_E~0); 34295#L852-1 assume !(1 == ~T4_E~0); 34296#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34172#L862-1 assume !(1 == ~T6_E~0); 34173#L867-1 assume !(1 == ~T7_E~0); 34180#L872-1 assume !(1 == ~E_1~0); 34257#L877-1 assume !(1 == ~E_2~0); 34451#L882-1 assume !(1 == ~E_3~0); 34662#L887-1 assume !(1 == ~E_4~0); 34504#L892-1 assume !(1 == ~E_5~0); 34505#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 34645#L902-1 assume !(1 == ~E_7~0); 36459#L907-1 assume { :end_inline_reset_delta_events } true; 36449#L1148-2 [2024-10-13 17:46:03,800 INFO L747 eck$LassoCheckResult]: Loop: 36449#L1148-2 assume !false; 36443#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36440#L729-1 assume !false; 34674#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34033#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34034#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34188#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34081#L626 assume !(0 != eval_~tmp~0#1); 34082#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34306#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34109#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33846#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33847#L759-3 assume !(0 == ~T2_E~0); 34235#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34236#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34421#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34008#L779-3 assume !(0 == ~T6_E~0); 33841#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33842#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33836#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33837#L799-3 assume !(0 == ~E_3~0); 33888#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34116#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33886#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33887#L819-3 assume !(0 == ~E_7~0); 34539#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34252#L361-24 assume !(1 == ~m_pc~0); 34253#L361-26 is_master_triggered_~__retres1~0#1 := 0; 34349#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33937#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33938#L930-24 assume !(0 != activate_threads_~tmp~1#1); 34592#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34399#L380-24 assume 1 == ~t1_pc~0; 34400#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34612#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38771#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38770#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34106#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34492#L399-24 assume !(1 == ~t2_pc~0); 34123#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 34039#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34040#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34294#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34102#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34103#L418-24 assume !(1 == ~t3_pc~0); 33882#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 33883#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34175#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34006#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34007#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34472#L437-24 assume !(1 == ~t4_pc~0); 34544#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 34545#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34293#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33995#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33996#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34407#L456-24 assume 1 == ~t5_pc~0; 34379#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34357#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34358#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38788#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38785#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38783#L475-24 assume !(1 == ~t6_pc~0); 38780#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 38778#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38776#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38774#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38719#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38594#L494-24 assume !(1 == ~t7_pc~0); 34177#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 34155#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34156#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34099#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34100#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34542#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34570#L837-5 assume !(1 == ~T1_E~0); 34301#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34302#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34467#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34361#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34362#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34659#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34268#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34269#L877-3 assume !(1 == ~E_2~0); 34356#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34412#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34027#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34028#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34569#L902-3 assume !(1 == ~E_7~0); 34186#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34187#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 33839#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34124#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 34125#L1167 assume !(0 == start_simulation_~tmp~3#1); 34247#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34248#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 36553#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 36551#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 36549#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36548#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36547#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 36458#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 36449#L1148-2 [2024-10-13 17:46:03,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,801 INFO L85 PathProgramCache]: Analyzing trace with hash -2107931962, now seen corresponding path program 1 times [2024-10-13 17:46:03,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987090403] [2024-10-13 17:46:03,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:03,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:03,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987090403] [2024-10-13 17:46:03,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987090403] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,855 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,855 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:03,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603228892] [2024-10-13 17:46:03,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,855 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:03,856 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1544747011, now seen corresponding path program 1 times [2024-10-13 17:46:03,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211332461] [2024-10-13 17:46:03,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:03,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:03,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211332461] [2024-10-13 17:46:03,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211332461] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:03,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308954582] [2024-10-13 17:46:03,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,901 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:03,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:03,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:03,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:03,902 INFO L87 Difference]: Start difference. First operand 5167 states and 7364 transitions. cyclomatic complexity: 2205 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:04,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:04,003 INFO L93 Difference]: Finished difference Result 9674 states and 13721 transitions. [2024-10-13 17:46:04,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9674 states and 13721 transitions. [2024-10-13 17:46:04,053 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9512 [2024-10-13 17:46:04,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9674 states to 9674 states and 13721 transitions. [2024-10-13 17:46:04,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9674 [2024-10-13 17:46:04,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9674 [2024-10-13 17:46:04,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9674 states and 13721 transitions. [2024-10-13 17:46:04,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:04,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9674 states and 13721 transitions. [2024-10-13 17:46:04,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9674 states and 13721 transitions. [2024-10-13 17:46:04,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9674 to 9658. [2024-10-13 17:46:04,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9658 states, 9658 states have (on average 1.419030855249534) internal successors, (13705), 9657 states have internal predecessors, (13705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:04,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9658 states to 9658 states and 13705 transitions. [2024-10-13 17:46:04,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9658 states and 13705 transitions. [2024-10-13 17:46:04,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:04,449 INFO L425 stractBuchiCegarLoop]: Abstraction has 9658 states and 13705 transitions. [2024-10-13 17:46:04,449 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-13 17:46:04,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9658 states and 13705 transitions. [2024-10-13 17:46:04,492 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9496 [2024-10-13 17:46:04,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:04,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:04,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:04,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:04,495 INFO L745 eck$LassoCheckResult]: Stem: 48882#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 48883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 49479#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49480#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49523#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 49505#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49506#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49036#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49037#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49108#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48948#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48949#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48915#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48916#L754 assume !(0 == ~M_E~0); 49540#L754-2 assume !(0 == ~T1_E~0); 49430#L759-1 assume !(0 == ~T2_E~0); 49296#L764-1 assume !(0 == ~T3_E~0); 49248#L769-1 assume !(0 == ~T4_E~0); 49249#L774-1 assume !(0 == ~T5_E~0); 49297#L779-1 assume !(0 == ~T6_E~0); 49440#L784-1 assume !(0 == ~T7_E~0); 49245#L789-1 assume !(0 == ~E_1~0); 49246#L794-1 assume !(0 == ~E_2~0); 49341#L799-1 assume !(0 == ~E_3~0); 49258#L804-1 assume !(0 == ~E_4~0); 49259#L809-1 assume !(0 == ~E_5~0); 49288#L814-1 assume !(0 == ~E_6~0); 48679#L819-1 assume !(0 == ~E_7~0); 48680#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48946#L361 assume !(1 == ~m_pc~0); 48947#L361-2 is_master_triggered_~__retres1~0#1 := 0; 49472#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49417#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49418#L930 assume !(0 != activate_threads_~tmp~1#1); 49154#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48940#L380 assume !(1 == ~t1_pc~0); 48941#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49569#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48701#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48702#L938 assume !(0 != activate_threads_~tmp___0~0#1); 49372#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49352#L399 assume !(1 == ~t2_pc~0); 48850#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48851#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49018#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49011#L946 assume !(0 != activate_threads_~tmp___1~0#1); 49012#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48687#L418 assume !(1 == ~t3_pc~0); 48667#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48668#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48677#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48678#L954 assume !(0 != activate_threads_~tmp___2~0#1); 49275#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49276#L437 assume !(1 == ~t4_pc~0); 49507#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49412#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48760#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48761#L962 assume !(0 != activate_threads_~tmp___3~0#1); 49065#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49391#L456 assume !(1 == ~t5_pc~0); 48865#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48864#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49421#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49327#L970 assume !(0 != activate_threads_~tmp___4~0#1); 49328#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48754#L475 assume 1 == ~t6_pc~0; 48755#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48797#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48798#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49004#L978 assume !(0 != activate_threads_~tmp___5~0#1); 49264#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49265#L494 assume !(1 == ~t7_pc~0); 48988#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 48989#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49215#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49298#L986 assume !(0 != activate_threads_~tmp___6~0#1); 49299#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49530#L837 assume !(1 == ~M_E~0); 49478#L837-2 assume !(1 == ~T1_E~0); 49347#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49074#L847-1 assume !(1 == ~T3_E~0); 49075#L852-1 assume !(1 == ~T4_E~0); 49144#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49024#L862-1 assume !(1 == ~T6_E~0); 49025#L867-1 assume !(1 == ~T7_E~0); 49032#L872-1 assume !(1 == ~E_1~0); 49107#L877-1 assume !(1 == ~E_2~0); 49312#L882-1 assume !(1 == ~E_3~0); 49486#L887-1 assume !(1 == ~E_4~0); 49367#L892-1 assume !(1 == ~E_5~0); 49368#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 49047#L902-1 assume !(1 == ~E_7~0); 49048#L907-1 assume { :end_inline_reset_delta_events } true; 53788#L1148-2 [2024-10-13 17:46:04,495 INFO L747 eck$LassoCheckResult]: Loop: 53788#L1148-2 assume !false; 53782#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53779#L729-1 assume !false; 53775#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 53763#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 53756#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53751#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53746#L626 assume !(0 != eval_~tmp~0#1); 53747#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54525#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54523#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54521#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54519#L759-3 assume !(0 == ~T2_E~0); 54517#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54516#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54507#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54505#L779-3 assume !(0 == ~T6_E~0); 54503#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54500#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54486#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54477#L799-3 assume !(0 == ~E_3~0); 54468#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54460#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54454#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54449#L819-3 assume !(0 == ~E_7~0); 54447#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54445#L361-24 assume !(1 == ~m_pc~0); 54444#L361-26 is_master_triggered_~__retres1~0#1 := 0; 54434#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54431#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54428#L930-24 assume !(0 != activate_threads_~tmp~1#1); 54424#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54414#L380-24 assume !(1 == ~t1_pc~0); 54410#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 54408#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54406#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54404#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 54401#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54399#L399-24 assume !(1 == ~t2_pc~0); 54397#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 54395#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54393#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54391#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54389#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54387#L418-24 assume 1 == ~t3_pc~0; 54384#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54382#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54380#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54378#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54377#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54376#L437-24 assume !(1 == ~t4_pc~0); 54374#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 54372#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54360#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54355#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54350#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54344#L456-24 assume 1 == ~t5_pc~0; 54337#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54331#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54325#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54319#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54313#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54306#L475-24 assume !(1 == ~t6_pc~0); 54297#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 54289#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54281#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54274#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54267#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54257#L494-24 assume !(1 == ~t7_pc~0); 54250#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 54243#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54236#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54229#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54221#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54214#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54208#L837-5 assume !(1 == ~T1_E~0); 54202#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54048#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54039#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54031#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54023#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54013#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54006#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53999#L877-3 assume !(1 == ~E_2~0); 53988#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53981#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53974#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53968#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53962#L902-3 assume !(1 == ~E_7~0); 53957#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 53948#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 53938#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53931#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 53924#L1167 assume !(0 == start_simulation_~tmp~3#1); 53918#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 53824#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 53815#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53813#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 53811#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53809#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53807#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 53796#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 53788#L1148-2 [2024-10-13 17:46:04,496 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:04,496 INFO L85 PathProgramCache]: Analyzing trace with hash -1707940763, now seen corresponding path program 1 times [2024-10-13 17:46:04,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:04,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075728264] [2024-10-13 17:46:04,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:04,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:04,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:04,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:04,551 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:04,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075728264] [2024-10-13 17:46:04,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075728264] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:04,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:04,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:04,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [776784818] [2024-10-13 17:46:04,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:04,553 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:04,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:04,553 INFO L85 PathProgramCache]: Analyzing trace with hash -228310597, now seen corresponding path program 1 times [2024-10-13 17:46:04,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:04,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500375926] [2024-10-13 17:46:04,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:04,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:04,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:04,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:04,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:04,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500375926] [2024-10-13 17:46:04,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500375926] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:04,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:04,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:04,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81921197] [2024-10-13 17:46:04,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:04,714 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:04,714 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:04,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:04,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:04,714 INFO L87 Difference]: Start difference. First operand 9658 states and 13705 transitions. cyclomatic complexity: 4063 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:04,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:04,843 INFO L93 Difference]: Finished difference Result 18129 states and 25606 transitions. [2024-10-13 17:46:04,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18129 states and 25606 transitions. [2024-10-13 17:46:04,933 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17888 [2024-10-13 17:46:04,992 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18129 states to 18129 states and 25606 transitions. [2024-10-13 17:46:04,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18129 [2024-10-13 17:46:05,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18129 [2024-10-13 17:46:05,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18129 states and 25606 transitions. [2024-10-13 17:46:05,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:05,031 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18129 states and 25606 transitions. [2024-10-13 17:46:05,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18129 states and 25606 transitions. [2024-10-13 17:46:05,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18129 to 18097. [2024-10-13 17:46:05,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18097 states, 18097 states have (on average 1.413162402608167) internal successors, (25574), 18096 states have internal predecessors, (25574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:05,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18097 states to 18097 states and 25574 transitions. [2024-10-13 17:46:05,420 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18097 states and 25574 transitions. [2024-10-13 17:46:05,421 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:05,421 INFO L425 stractBuchiCegarLoop]: Abstraction has 18097 states and 25574 transitions. [2024-10-13 17:46:05,421 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-13 17:46:05,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18097 states and 25574 transitions. [2024-10-13 17:46:05,478 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17856 [2024-10-13 17:46:05,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:05,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:05,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:05,480 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:05,480 INFO L745 eck$LassoCheckResult]: Stem: 76668#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 76669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 77269#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77270#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77315#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 77297#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77298#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76826#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76827#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76896#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76734#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76735#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76701#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76702#L754 assume !(0 == ~M_E~0); 77333#L754-2 assume !(0 == ~T1_E~0); 77229#L759-1 assume !(0 == ~T2_E~0); 77077#L764-1 assume !(0 == ~T3_E~0); 77034#L769-1 assume !(0 == ~T4_E~0); 77035#L774-1 assume !(0 == ~T5_E~0); 77078#L779-1 assume !(0 == ~T6_E~0); 77235#L784-1 assume !(0 == ~T7_E~0); 77031#L789-1 assume !(0 == ~E_1~0); 77032#L794-1 assume !(0 == ~E_2~0); 77129#L799-1 assume !(0 == ~E_3~0); 77041#L804-1 assume !(0 == ~E_4~0); 77042#L809-1 assume !(0 == ~E_5~0); 77072#L814-1 assume !(0 == ~E_6~0); 76477#L819-1 assume !(0 == ~E_7~0); 76478#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76731#L361 assume !(1 == ~m_pc~0); 76732#L361-2 is_master_triggered_~__retres1~0#1 := 0; 77263#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77215#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77216#L930 assume !(0 != activate_threads_~tmp~1#1); 76944#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76725#L380 assume !(1 == ~t1_pc~0); 76726#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77370#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76495#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76496#L938 assume !(0 != activate_threads_~tmp___0~0#1); 77166#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77142#L399 assume !(1 == ~t2_pc~0); 76639#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76640#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76805#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76798#L946 assume !(0 != activate_threads_~tmp___1~0#1); 76799#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76481#L418 assume !(1 == ~t3_pc~0); 76461#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76462#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76471#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76472#L954 assume !(0 != activate_threads_~tmp___2~0#1); 77058#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77059#L437 assume !(1 == ~t4_pc~0); 77299#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77210#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76555#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76556#L962 assume !(0 != activate_threads_~tmp___3~0#1); 76854#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77194#L456 assume !(1 == ~t5_pc~0); 76654#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76653#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77220#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77114#L970 assume !(0 != activate_threads_~tmp___4~0#1); 77115#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76547#L475 assume !(1 == ~t6_pc~0); 76548#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76589#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76590#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76790#L978 assume !(0 != activate_threads_~tmp___5~0#1); 77046#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77047#L494 assume !(1 == ~t7_pc~0); 76774#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76775#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77001#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77079#L986 assume !(0 != activate_threads_~tmp___6~0#1); 77080#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77322#L837 assume !(1 == ~M_E~0); 77268#L837-2 assume !(1 == ~T1_E~0); 77135#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76861#L847-1 assume !(1 == ~T3_E~0); 76862#L852-1 assume !(1 == ~T4_E~0); 76934#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76811#L862-1 assume !(1 == ~T6_E~0); 76812#L867-1 assume !(1 == ~T7_E~0); 76822#L872-1 assume !(1 == ~E_1~0); 76895#L877-1 assume !(1 == ~E_2~0); 77096#L882-1 assume !(1 == ~E_3~0); 77277#L887-1 assume !(1 == ~E_4~0); 77340#L892-1 assume !(1 == ~E_5~0); 82074#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 76838#L902-1 assume !(1 == ~E_7~0); 76839#L907-1 assume { :end_inline_reset_delta_events } true; 77188#L1148-2 [2024-10-13 17:46:05,480 INFO L747 eck$LassoCheckResult]: Loop: 77188#L1148-2 assume !false; 81150#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81149#L729-1 assume !false; 81144#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 81125#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 81121#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 81113#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 81114#L626 assume !(0 != eval_~tmp~0#1); 82012#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89130#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89125#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 89120#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 89115#L759-3 assume !(0 == ~T2_E~0); 89110#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89106#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 89102#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 89096#L779-3 assume !(0 == ~T6_E~0); 89090#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 89086#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 89081#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 89080#L799-3 assume !(0 == ~E_3~0); 89079#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 89078#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 89077#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 89076#L819-3 assume !(0 == ~E_7~0); 89074#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89072#L361-24 assume !(1 == ~m_pc~0); 89070#L361-26 is_master_triggered_~__retres1~0#1 := 0; 89068#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89066#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 89064#L930-24 assume !(0 != activate_threads_~tmp~1#1); 89062#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89060#L380-24 assume 1 == ~t1_pc~0; 89058#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 89056#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89054#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88803#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88802#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88801#L399-24 assume !(1 == ~t2_pc~0); 88799#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 88797#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88796#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88795#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88793#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88790#L418-24 assume 1 == ~t3_pc~0; 88787#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88785#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88783#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88781#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88779#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88776#L437-24 assume !(1 == ~t4_pc~0); 88774#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 88772#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88770#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88768#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88765#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88763#L456-24 assume !(1 == ~t5_pc~0); 88761#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 88758#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88756#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88754#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88753#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88749#L475-24 assume !(1 == ~t6_pc~0); 88747#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 88745#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88742#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88741#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88740#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82737#L494-24 assume !(1 == ~t7_pc~0); 82734#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 82732#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82730#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82727#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82725#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82723#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 82721#L837-5 assume !(1 == ~T1_E~0); 82719#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82168#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82715#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82713#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82711#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 82159#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 82708#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 82706#L877-3 assume !(1 == ~E_2~0); 82703#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82701#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82699#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82697#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 82695#L902-3 assume !(1 == ~E_7~0); 82694#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 82690#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 82684#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 82682#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 82679#L1167 assume !(0 == start_simulation_~tmp~3#1); 82676#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 82671#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 82662#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 82660#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 82657#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82654#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82652#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 82648#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 77188#L1148-2 [2024-10-13 17:46:05,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:05,481 INFO L85 PathProgramCache]: Analyzing trace with hash -2016379772, now seen corresponding path program 1 times [2024-10-13 17:46:05,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:05,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344739187] [2024-10-13 17:46:05,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:05,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:05,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:05,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:05,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:05,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344739187] [2024-10-13 17:46:05,642 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344739187] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:05,642 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:05,642 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:05,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775475392] [2024-10-13 17:46:05,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:05,643 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:05,643 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:05,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1711104387, now seen corresponding path program 1 times [2024-10-13 17:46:05,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:05,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139316393] [2024-10-13 17:46:05,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:05,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:05,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:05,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:05,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:05,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139316393] [2024-10-13 17:46:05,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139316393] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:05,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:05,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:05,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100527934] [2024-10-13 17:46:05,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:05,688 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:05,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:05,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:05,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:05,690 INFO L87 Difference]: Start difference. First operand 18097 states and 25574 transitions. cyclomatic complexity: 7509 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:05,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:05,774 INFO L93 Difference]: Finished difference Result 18093 states and 25485 transitions. [2024-10-13 17:46:05,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18093 states and 25485 transitions. [2024-10-13 17:46:05,866 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17856 [2024-10-13 17:46:05,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18093 states to 18093 states and 25485 transitions. [2024-10-13 17:46:05,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18093 [2024-10-13 17:46:05,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18093 [2024-10-13 17:46:05,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18093 states and 25485 transitions. [2024-10-13 17:46:06,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:06,059 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18093 states and 25485 transitions. [2024-10-13 17:46:06,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18093 states and 25485 transitions. [2024-10-13 17:46:06,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18093 to 9092. [2024-10-13 17:46:06,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.4083809942806864) internal successors, (12805), 9091 states have internal predecessors, (12805), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:06,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12805 transitions. [2024-10-13 17:46:06,303 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12805 transitions. [2024-10-13 17:46:06,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:06,304 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12805 transitions. [2024-10-13 17:46:06,304 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-13 17:46:06,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12805 transitions. [2024-10-13 17:46:06,331 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2024-10-13 17:46:06,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:06,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:06,333 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:06,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:06,333 INFO L745 eck$LassoCheckResult]: Stem: 112870#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 112871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 113440#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113441#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113474#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 113460#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 113461#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113023#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 113024#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 113094#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112936#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 112937#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 112903#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112904#L754 assume !(0 == ~M_E~0); 113486#L754-2 assume !(0 == ~T1_E~0); 113404#L759-1 assume !(0 == ~T2_E~0); 113267#L764-1 assume !(0 == ~T3_E~0); 113227#L769-1 assume !(0 == ~T4_E~0); 113228#L774-1 assume !(0 == ~T5_E~0); 113268#L779-1 assume !(0 == ~T6_E~0); 113412#L784-1 assume !(0 == ~T7_E~0); 113224#L789-1 assume !(0 == ~E_1~0); 113225#L794-1 assume !(0 == ~E_2~0); 113315#L799-1 assume !(0 == ~E_3~0); 113235#L804-1 assume !(0 == ~E_4~0); 113236#L809-1 assume !(0 == ~E_5~0); 113262#L814-1 assume !(0 == ~E_6~0); 112675#L819-1 assume !(0 == ~E_7~0); 112676#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112933#L361 assume !(1 == ~m_pc~0); 112934#L361-2 is_master_triggered_~__retres1~0#1 := 0; 113436#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 113392#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 113393#L930 assume !(0 != activate_threads_~tmp~1#1); 113137#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112927#L380 assume !(1 == ~t1_pc~0); 112928#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 113507#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112694#L938 assume !(0 != activate_threads_~tmp___0~0#1); 113344#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113324#L399 assume !(1 == ~t2_pc~0); 112839#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112840#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113003#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112996#L946 assume !(0 != activate_threads_~tmp___1~0#1); 112997#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112679#L418 assume !(1 == ~t3_pc~0); 112658#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112659#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112669#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 112670#L954 assume !(0 != activate_threads_~tmp___2~0#1); 113248#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113249#L437 assume !(1 == ~t4_pc~0); 113462#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 113386#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112752#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 112753#L962 assume !(0 != activate_threads_~tmp___3~0#1); 113052#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113370#L456 assume !(1 == ~t5_pc~0); 112853#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 112852#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 113396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 113302#L970 assume !(0 != activate_threads_~tmp___4~0#1); 113303#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112745#L475 assume !(1 == ~t6_pc~0); 112746#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 112788#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112789#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112989#L978 assume !(0 != activate_threads_~tmp___5~0#1); 113240#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113241#L494 assume !(1 == ~t7_pc~0); 112973#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 112974#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 113194#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 113269#L986 assume !(0 != activate_threads_~tmp___6~0#1); 113270#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113482#L837 assume !(1 == ~M_E~0); 113439#L837-2 assume !(1 == ~T1_E~0); 113320#L842-1 assume !(1 == ~T2_E~0); 113061#L847-1 assume !(1 == ~T3_E~0); 113062#L852-1 assume !(1 == ~T4_E~0); 113127#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 113009#L862-1 assume !(1 == ~T6_E~0); 113010#L867-1 assume !(1 == ~T7_E~0); 113019#L872-1 assume !(1 == ~E_1~0); 113093#L877-1 assume !(1 == ~E_2~0); 113284#L882-1 assume !(1 == ~E_3~0); 113445#L887-1 assume !(1 == ~E_4~0); 113339#L892-1 assume !(1 == ~E_5~0); 113340#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 113036#L902-1 assume !(1 == ~E_7~0); 113037#L907-1 assume { :end_inline_reset_delta_events } true; 113364#L1148-2 [2024-10-13 17:46:06,334 INFO L747 eck$LassoCheckResult]: Loop: 113364#L1148-2 assume !false; 115376#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 115375#L729-1 assume !false; 115374#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 115259#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 115253#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 115251#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 115248#L626 assume !(0 != eval_~tmp~0#1); 115249#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 115722#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 115720#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 115718#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 115716#L759-3 assume !(0 == ~T2_E~0); 115714#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 115712#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 115710#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 115708#L779-3 assume !(0 == ~T6_E~0); 115706#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 115704#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 115702#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 115700#L799-3 assume !(0 == ~E_3~0); 115698#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 115696#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 115694#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 115692#L819-3 assume !(0 == ~E_7~0); 115690#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115689#L361-24 assume !(1 == ~m_pc~0); 115688#L361-26 is_master_triggered_~__retres1~0#1 := 0; 115687#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115686#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115685#L930-24 assume !(0 != activate_threads_~tmp~1#1); 115684#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115683#L380-24 assume !(1 == ~t1_pc~0); 115681#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 115679#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115677#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 115676#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 115674#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115673#L399-24 assume !(1 == ~t2_pc~0); 115672#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 115671#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115669#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 115668#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 115667#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115666#L418-24 assume !(1 == ~t3_pc~0); 115665#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 115662#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115660#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 115658#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 115656#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 115654#L437-24 assume !(1 == ~t4_pc~0); 115652#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 115648#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115646#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 115644#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 115642#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115639#L456-24 assume !(1 == ~t5_pc~0); 115637#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 115634#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115631#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 115629#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 115627#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 115625#L475-24 assume !(1 == ~t6_pc~0); 115623#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 115621#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 115618#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 115616#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 115614#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115612#L494-24 assume !(1 == ~t7_pc~0); 115609#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 115607#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 115605#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115603#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 115601#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115599#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 115597#L837-5 assume !(1 == ~T1_E~0); 115595#L842-3 assume !(1 == ~T2_E~0); 115592#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 115590#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 115588#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 115586#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 115584#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 115582#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 115579#L877-3 assume !(1 == ~E_2~0); 115577#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 115575#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 115573#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 115571#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 115569#L902-3 assume !(1 == ~E_7~0); 115566#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 115462#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 115456#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 115454#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 115451#L1167 assume !(0 == start_simulation_~tmp~3#1); 115448#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 115446#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 115437#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 115435#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 115433#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 115431#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 115429#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 115426#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 113364#L1148-2 [2024-10-13 17:46:06,334 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:06,334 INFO L85 PathProgramCache]: Analyzing trace with hash 1267470274, now seen corresponding path program 1 times [2024-10-13 17:46:06,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:06,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697463782] [2024-10-13 17:46:06,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:06,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:06,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:06,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:06,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:06,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697463782] [2024-10-13 17:46:06,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697463782] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:06,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:06,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:06,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909126736] [2024-10-13 17:46:06,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:06,378 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:06,378 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:06,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1679044151, now seen corresponding path program 1 times [2024-10-13 17:46:06,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:06,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281719237] [2024-10-13 17:46:06,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:06,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:06,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:06,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:06,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:06,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281719237] [2024-10-13 17:46:06,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281719237] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:06,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:06,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:06,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162023330] [2024-10-13 17:46:06,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:06,413 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:06,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:06,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:06,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:06,413 INFO L87 Difference]: Start difference. First operand 9092 states and 12805 transitions. cyclomatic complexity: 3729 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:06,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:06,466 INFO L93 Difference]: Finished difference Result 9092 states and 12755 transitions. [2024-10-13 17:46:06,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9092 states and 12755 transitions. [2024-10-13 17:46:06,500 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2024-10-13 17:46:06,525 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9092 states to 9092 states and 12755 transitions. [2024-10-13 17:46:06,526 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9092 [2024-10-13 17:46:06,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9092 [2024-10-13 17:46:06,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9092 states and 12755 transitions. [2024-10-13 17:46:06,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:06,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12755 transitions. [2024-10-13 17:46:06,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9092 states and 12755 transitions. [2024-10-13 17:46:06,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9092 to 9092. [2024-10-13 17:46:06,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.402881654201496) internal successors, (12755), 9091 states have internal predecessors, (12755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:06,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12755 transitions. [2024-10-13 17:46:06,746 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12755 transitions. [2024-10-13 17:46:06,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:06,747 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12755 transitions. [2024-10-13 17:46:06,747 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-13 17:46:06,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12755 transitions. [2024-10-13 17:46:06,773 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2024-10-13 17:46:06,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:06,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:06,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:06,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:06,775 INFO L745 eck$LassoCheckResult]: Stem: 131060#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 131061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 131660#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131661#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131699#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 131682#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131683#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131213#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131214#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131287#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131123#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131124#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131091#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131092#L754 assume !(0 == ~M_E~0); 131712#L754-2 assume !(0 == ~T1_E~0); 131617#L759-1 assume !(0 == ~T2_E~0); 131476#L764-1 assume !(0 == ~T3_E~0); 131428#L769-1 assume !(0 == ~T4_E~0); 131429#L774-1 assume !(0 == ~T5_E~0); 131477#L779-1 assume !(0 == ~T6_E~0); 131626#L784-1 assume !(0 == ~T7_E~0); 131425#L789-1 assume !(0 == ~E_1~0); 131426#L794-1 assume !(0 == ~E_2~0); 131524#L799-1 assume !(0 == ~E_3~0); 131436#L804-1 assume !(0 == ~E_4~0); 131437#L809-1 assume !(0 == ~E_5~0); 131471#L814-1 assume !(0 == ~E_6~0); 130861#L819-1 assume !(0 == ~E_7~0); 130862#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131121#L361 assume !(1 == ~m_pc~0); 131122#L361-2 is_master_triggered_~__retres1~0#1 := 0; 131654#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131603#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 131604#L930 assume !(0 != activate_threads_~tmp~1#1); 131331#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131115#L380 assume !(1 == ~t1_pc~0); 131116#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131696#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131697#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 131738#L938 assume !(0 != activate_threads_~tmp___0~0#1); 131558#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131534#L399 assume !(1 == ~t2_pc~0); 131028#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131029#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131192#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 131185#L946 assume !(0 != activate_threads_~tmp___1~0#1); 131186#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130869#L418 assume !(1 == ~t3_pc~0); 130849#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130850#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130859#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130860#L954 assume !(0 != activate_threads_~tmp___2~0#1); 131454#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131455#L437 assume !(1 == ~t4_pc~0); 131684#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131598#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130940#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130941#L962 assume !(0 != activate_threads_~tmp___3~0#1); 131242#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131578#L456 assume !(1 == ~t5_pc~0); 131043#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 131042#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 131607#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 131509#L970 assume !(0 != activate_threads_~tmp___4~0#1); 131510#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130935#L475 assume !(1 == ~t6_pc~0); 130936#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 130976#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130977#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131178#L978 assume !(0 != activate_threads_~tmp___5~0#1); 131443#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131444#L494 assume !(1 == ~t7_pc~0); 131162#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 131163#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131396#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131478#L986 assume !(0 != activate_threads_~tmp___6~0#1); 131479#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131705#L837 assume !(1 == ~M_E~0); 131659#L837-2 assume !(1 == ~T1_E~0); 131529#L842-1 assume !(1 == ~T2_E~0); 131251#L847-1 assume !(1 == ~T3_E~0); 131252#L852-1 assume !(1 == ~T4_E~0); 131321#L857-1 assume !(1 == ~T5_E~0); 131198#L862-1 assume !(1 == ~T6_E~0); 131199#L867-1 assume !(1 == ~T7_E~0); 131209#L872-1 assume !(1 == ~E_1~0); 131286#L877-1 assume !(1 == ~E_2~0); 131494#L882-1 assume !(1 == ~E_3~0); 131664#L887-1 assume !(1 == ~E_4~0); 131553#L892-1 assume !(1 == ~E_5~0); 131554#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 131224#L902-1 assume !(1 == ~E_7~0); 131225#L907-1 assume { :end_inline_reset_delta_events } true; 131577#L1148-2 [2024-10-13 17:46:06,776 INFO L747 eck$LassoCheckResult]: Loop: 131577#L1148-2 assume !false; 136421#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136420#L729-1 assume !false; 136419#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 136383#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 136377#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 136375#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 136372#L626 assume !(0 != eval_~tmp~0#1); 136373#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136654#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136652#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 136650#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136647#L759-3 assume !(0 == ~T2_E~0); 136645#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136643#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 136641#L774-3 assume !(0 == ~T5_E~0); 136639#L779-3 assume !(0 == ~T6_E~0); 136637#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136635#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 136633#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136631#L799-3 assume !(0 == ~E_3~0); 136629#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136627#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136625#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136622#L819-3 assume !(0 == ~E_7~0); 136620#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136618#L361-24 assume !(1 == ~m_pc~0); 136616#L361-26 is_master_triggered_~__retres1~0#1 := 0; 136614#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136612#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 136610#L930-24 assume !(0 != activate_threads_~tmp~1#1); 136608#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136606#L380-24 assume !(1 == ~t1_pc~0); 136602#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 136600#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136597#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 136595#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 136592#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136590#L399-24 assume !(1 == ~t2_pc~0); 136588#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 136586#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136584#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 136582#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136580#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136578#L418-24 assume !(1 == ~t3_pc~0); 136576#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 136573#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136571#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 136569#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136567#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136565#L437-24 assume !(1 == ~t4_pc~0); 136563#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 136561#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136559#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 136557#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136555#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136554#L456-24 assume 1 == ~t5_pc~0; 136552#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 136551#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136550#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 136549#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 136548#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136547#L475-24 assume !(1 == ~t6_pc~0); 136545#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 136544#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136543#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 136542#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136540#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 136538#L494-24 assume !(1 == ~t7_pc~0); 136535#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 136533#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 136531#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 136529#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 136528#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136524#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 136522#L837-5 assume !(1 == ~T1_E~0); 136520#L842-3 assume !(1 == ~T2_E~0); 136518#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 136515#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 136513#L857-3 assume !(1 == ~T5_E~0); 136511#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 136509#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 136507#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 136505#L877-3 assume !(1 == ~E_2~0); 136503#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 136501#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 136499#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 136496#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 136494#L902-3 assume !(1 == ~E_7~0); 136492#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 136480#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 136474#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 136471#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 136468#L1167 assume !(0 == start_simulation_~tmp~3#1); 136465#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 136463#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 136454#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 136452#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 136450#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 136448#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136446#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 136444#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 131577#L1148-2 [2024-10-13 17:46:06,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:06,776 INFO L85 PathProgramCache]: Analyzing trace with hash 1968534852, now seen corresponding path program 1 times [2024-10-13 17:46:06,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:06,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713056721] [2024-10-13 17:46:06,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:06,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:06,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:06,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:06,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:06,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713056721] [2024-10-13 17:46:06,834 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713056721] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:06,834 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:06,834 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:06,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323182975] [2024-10-13 17:46:06,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:06,835 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:06,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:06,835 INFO L85 PathProgramCache]: Analyzing trace with hash 595334364, now seen corresponding path program 1 times [2024-10-13 17:46:06,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:06,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118550763] [2024-10-13 17:46:06,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:06,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:06,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:06,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:06,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:06,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2118550763] [2024-10-13 17:46:06,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2118550763] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:06,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:06,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:06,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142664015] [2024-10-13 17:46:06,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:06,872 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:06,872 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:06,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:46:06,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:46:06,872 INFO L87 Difference]: Start difference. First operand 9092 states and 12755 transitions. cyclomatic complexity: 3679 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:07,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:07,119 INFO L93 Difference]: Finished difference Result 18501 states and 25862 transitions. [2024-10-13 17:46:07,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18501 states and 25862 transitions. [2024-10-13 17:46:07,212 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18184 [2024-10-13 17:46:07,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18501 states to 18501 states and 25862 transitions. [2024-10-13 17:46:07,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18501 [2024-10-13 17:46:07,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18501 [2024-10-13 17:46:07,302 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18501 states and 25862 transitions. [2024-10-13 17:46:07,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:07,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18501 states and 25862 transitions. [2024-10-13 17:46:07,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18501 states and 25862 transitions. [2024-10-13 17:46:07,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18501 to 10331. [2024-10-13 17:46:07,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10331 states, 10331 states have (on average 1.3969606040073566) internal successors, (14432), 10330 states have internal predecessors, (14432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:07,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10331 states to 10331 states and 14432 transitions. [2024-10-13 17:46:07,664 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14432 transitions. [2024-10-13 17:46:07,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:46:07,665 INFO L425 stractBuchiCegarLoop]: Abstraction has 10331 states and 14432 transitions. [2024-10-13 17:46:07,665 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-13 17:46:07,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10331 states and 14432 transitions. [2024-10-13 17:46:07,696 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096 [2024-10-13 17:46:07,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:07,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:07,698 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:07,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:07,699 INFO L745 eck$LassoCheckResult]: Stem: 158663#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 158664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 159274#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 159275#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 159321#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 159301#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 159302#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158820#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158821#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158895#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 158725#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 158726#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 158693#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158694#L754 assume !(0 == ~M_E~0); 159346#L754-2 assume !(0 == ~T1_E~0); 159221#L759-1 assume !(0 == ~T2_E~0); 159079#L764-1 assume !(0 == ~T3_E~0); 159036#L769-1 assume !(0 == ~T4_E~0); 159037#L774-1 assume !(0 == ~T5_E~0); 159080#L779-1 assume !(0 == ~T6_E~0); 159231#L784-1 assume !(0 == ~T7_E~0); 159033#L789-1 assume !(0 == ~E_1~0); 159034#L794-1 assume !(0 == ~E_2~0); 159131#L799-1 assume !(0 == ~E_3~0); 159044#L804-1 assume !(0 == ~E_4~0); 159045#L809-1 assume !(0 == ~E_5~0); 159074#L814-1 assume 0 == ~E_6~0;~E_6~0 := 1; 158464#L819-1 assume !(0 == ~E_7~0); 158465#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158723#L361 assume !(1 == ~m_pc~0); 158724#L361-2 is_master_triggered_~__retres1~0#1 := 0; 159356#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159357#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159311#L930 assume !(0 != activate_threads_~tmp~1#1); 159312#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158717#L380 assume !(1 == ~t1_pc~0); 158718#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 159400#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159398#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159378#L938 assume !(0 != activate_threads_~tmp___0~0#1); 159161#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159140#L399 assume !(1 == ~t2_pc~0); 159141#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 159323#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159324#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 158792#L946 assume !(0 != activate_threads_~tmp___1~0#1); 158793#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159393#L418 assume !(1 == ~t3_pc~0); 158452#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 158453#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159392#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159379#L954 assume !(0 != activate_threads_~tmp___2~0#1); 159380#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159347#L437 assume !(1 == ~t4_pc~0); 159348#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 159391#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158544#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158545#L962 assume !(0 != activate_threads_~tmp___3~0#1); 159287#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159179#L456 assume !(1 == ~t5_pc~0); 159180#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 159342#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159211#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159117#L970 assume !(0 != activate_threads_~tmp___4~0#1); 159118#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158539#L475 assume !(1 == ~t6_pc~0); 158540#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 158581#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 159111#L978 assume !(0 != activate_threads_~tmp___5~0#1); 159112#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 159252#L494 assume !(1 == ~t7_pc~0); 158988#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 159003#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 159004#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 159081#L986 assume !(0 != activate_threads_~tmp___6~0#1); 159082#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159333#L837 assume !(1 == ~M_E~0); 159334#L837-2 assume !(1 == ~T1_E~0); 159386#L842-1 assume !(1 == ~T2_E~0); 159385#L847-1 assume !(1 == ~T3_E~0); 158929#L852-1 assume !(1 == ~T4_E~0); 158930#L857-1 assume !(1 == ~T5_E~0); 158806#L862-1 assume !(1 == ~T6_E~0); 158807#L867-1 assume !(1 == ~T7_E~0); 159384#L872-1 assume !(1 == ~E_1~0); 159096#L877-1 assume !(1 == ~E_2~0); 159097#L882-1 assume !(1 == ~E_3~0); 159353#L887-1 assume !(1 == ~E_4~0); 159156#L892-1 assume !(1 == ~E_5~0); 159157#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 158831#L902-1 assume !(1 == ~E_7~0); 158832#L907-1 assume { :end_inline_reset_delta_events } true; 159178#L1148-2 [2024-10-13 17:46:07,699 INFO L747 eck$LassoCheckResult]: Loop: 159178#L1148-2 assume !false; 163254#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 163252#L729-1 assume !false; 163250#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 163238#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 163232#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 163229#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 163226#L626 assume !(0 != eval_~tmp~0#1); 163227#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 163700#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163698#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 163696#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 163694#L759-3 assume !(0 == ~T2_E~0); 163692#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 163690#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 163688#L774-3 assume !(0 == ~T5_E~0); 163686#L779-3 assume !(0 == ~T6_E~0); 163684#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 163682#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 163680#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 163678#L799-3 assume !(0 == ~E_3~0); 163676#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 163674#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 163671#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 163670#L819-3 assume !(0 == ~E_7~0); 163669#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163668#L361-24 assume !(1 == ~m_pc~0); 163667#L361-26 is_master_triggered_~__retres1~0#1 := 0; 163666#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163665#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 163664#L930-24 assume !(0 != activate_threads_~tmp~1#1); 163663#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163662#L380-24 assume 1 == ~t1_pc~0; 163660#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 163658#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163656#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 163654#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 163653#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163652#L399-24 assume !(1 == ~t2_pc~0); 163651#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 163650#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163649#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163648#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 163647#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163646#L418-24 assume 1 == ~t3_pc~0; 163644#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 163643#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163642#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 163641#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 163640#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163639#L437-24 assume !(1 == ~t4_pc~0); 163638#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 163637#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163636#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 163635#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 163634#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163633#L456-24 assume !(1 == ~t5_pc~0); 163632#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 163630#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163629#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163628#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 163627#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163626#L475-24 assume !(1 == ~t6_pc~0); 163625#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 163624#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163623#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163622#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 163621#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163620#L494-24 assume !(1 == ~t7_pc~0); 163618#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 163617#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 163616#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163615#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 163614#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163613#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 163612#L837-5 assume !(1 == ~T1_E~0); 163611#L842-3 assume !(1 == ~T2_E~0); 163610#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 163609#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 163608#L857-3 assume !(1 == ~T5_E~0); 163607#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 163606#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 163605#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 163604#L877-3 assume !(1 == ~E_2~0); 163603#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 163602#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 163601#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 163599#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 163597#L902-3 assume !(1 == ~E_7~0); 163595#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 163555#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 163550#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 163549#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 163546#L1167 assume !(0 == start_simulation_~tmp~3#1); 163543#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 163541#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 163532#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 163529#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 163527#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 163525#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 163523#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 163521#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 159178#L1148-2 [2024-10-13 17:46:07,699 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:07,700 INFO L85 PathProgramCache]: Analyzing trace with hash -1110278718, now seen corresponding path program 1 times [2024-10-13 17:46:07,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:07,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73056400] [2024-10-13 17:46:07,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:07,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:07,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:07,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:07,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:07,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73056400] [2024-10-13 17:46:07,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73056400] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:07,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:07,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:07,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250443155] [2024-10-13 17:46:07,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:07,754 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:07,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:07,755 INFO L85 PathProgramCache]: Analyzing trace with hash 254187967, now seen corresponding path program 1 times [2024-10-13 17:46:07,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:07,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943393449] [2024-10-13 17:46:07,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:07,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:07,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:07,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:07,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:07,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943393449] [2024-10-13 17:46:07,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943393449] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:07,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:07,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:07,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [391916042] [2024-10-13 17:46:07,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:07,791 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:07,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:07,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:46:07,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:46:07,792 INFO L87 Difference]: Start difference. First operand 10331 states and 14432 transitions. cyclomatic complexity: 4117 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:07,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:07,925 INFO L93 Difference]: Finished difference Result 17156 states and 23937 transitions. [2024-10-13 17:46:07,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17156 states and 23937 transitions. [2024-10-13 17:46:08,090 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 16912 [2024-10-13 17:46:08,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17156 states to 17156 states and 23937 transitions. [2024-10-13 17:46:08,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17156 [2024-10-13 17:46:08,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17156 [2024-10-13 17:46:08,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17156 states and 23937 transitions. [2024-10-13 17:46:08,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:08,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17156 states and 23937 transitions. [2024-10-13 17:46:08,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17156 states and 23937 transitions. [2024-10-13 17:46:08,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17156 to 9092. [2024-10-13 17:46:08,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.3916630004399473) internal successors, (12653), 9091 states have internal predecessors, (12653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:08,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12653 transitions. [2024-10-13 17:46:08,340 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12653 transitions. [2024-10-13 17:46:08,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:46:08,340 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12653 transitions. [2024-10-13 17:46:08,340 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-13 17:46:08,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12653 transitions. [2024-10-13 17:46:08,369 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2024-10-13 17:46:08,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:08,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:08,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:08,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:08,371 INFO L745 eck$LassoCheckResult]: Stem: 186160#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 186161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 186745#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186746#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186783#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 186769#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 186770#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 186314#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 186315#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 186386#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 186223#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 186224#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 186191#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 186192#L754 assume !(0 == ~M_E~0); 186798#L754-2 assume !(0 == ~T1_E~0); 186700#L759-1 assume !(0 == ~T2_E~0); 186565#L764-1 assume !(0 == ~T3_E~0); 186520#L769-1 assume !(0 == ~T4_E~0); 186521#L774-1 assume !(0 == ~T5_E~0); 186566#L779-1 assume !(0 == ~T6_E~0); 186710#L784-1 assume !(0 == ~T7_E~0); 186517#L789-1 assume !(0 == ~E_1~0); 186518#L794-1 assume !(0 == ~E_2~0); 186610#L799-1 assume !(0 == ~E_3~0); 186528#L804-1 assume !(0 == ~E_4~0); 186529#L809-1 assume !(0 == ~E_5~0); 186560#L814-1 assume !(0 == ~E_6~0); 185961#L819-1 assume !(0 == ~E_7~0); 185962#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186221#L361 assume !(1 == ~m_pc~0); 186222#L361-2 is_master_triggered_~__retres1~0#1 := 0; 186740#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186687#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 186688#L930 assume !(0 != activate_threads_~tmp~1#1); 186432#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186215#L380 assume !(1 == ~t1_pc~0); 186216#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 186779#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 186780#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 186821#L938 assume !(0 != activate_threads_~tmp___0~0#1); 186644#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186621#L399 assume !(1 == ~t2_pc~0); 186129#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 186130#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186293#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186286#L946 assume !(0 != activate_threads_~tmp___1~0#1); 186287#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185969#L418 assume !(1 == ~t3_pc~0); 185949#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185950#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 185959#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 185960#L954 assume !(0 != activate_threads_~tmp___2~0#1); 186545#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186546#L437 assume !(1 == ~t4_pc~0); 186771#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 186682#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 186039#L962 assume !(0 != activate_threads_~tmp___3~0#1); 186343#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186663#L456 assume !(1 == ~t5_pc~0); 186143#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 186142#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 186691#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 186597#L970 assume !(0 != activate_threads_~tmp___4~0#1); 186598#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 186033#L475 assume !(1 == ~t6_pc~0); 186034#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 186075#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186076#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 186279#L978 assume !(0 != activate_threads_~tmp___5~0#1); 186533#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 186534#L494 assume !(1 == ~t7_pc~0); 186263#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 186264#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 186491#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 186567#L986 assume !(0 != activate_threads_~tmp___6~0#1); 186568#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186791#L837 assume !(1 == ~M_E~0); 186744#L837-2 assume !(1 == ~T1_E~0); 186616#L842-1 assume !(1 == ~T2_E~0); 186352#L847-1 assume !(1 == ~T3_E~0); 186353#L852-1 assume !(1 == ~T4_E~0); 186421#L857-1 assume !(1 == ~T5_E~0); 186299#L862-1 assume !(1 == ~T6_E~0); 186300#L867-1 assume !(1 == ~T7_E~0); 186310#L872-1 assume !(1 == ~E_1~0); 186385#L877-1 assume !(1 == ~E_2~0); 186581#L882-1 assume !(1 == ~E_3~0); 186750#L887-1 assume !(1 == ~E_4~0); 186638#L892-1 assume !(1 == ~E_5~0); 186639#L897-1 assume !(1 == ~E_6~0); 186325#L902-1 assume !(1 == ~E_7~0); 186326#L907-1 assume { :end_inline_reset_delta_events } true; 186662#L1148-2 [2024-10-13 17:46:08,371 INFO L747 eck$LassoCheckResult]: Loop: 186662#L1148-2 assume !false; 191472#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 191470#L729-1 assume !false; 191468#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 191456#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 191450#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 191448#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 191446#L626 assume !(0 != eval_~tmp~0#1); 191447#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 192005#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 192004#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 192003#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 192002#L759-3 assume !(0 == ~T2_E~0); 192001#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 192000#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 191999#L774-3 assume !(0 == ~T5_E~0); 191998#L779-3 assume !(0 == ~T6_E~0); 191997#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 191996#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 191995#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 191994#L799-3 assume !(0 == ~E_3~0); 191993#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 191992#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 191991#L814-3 assume !(0 == ~E_6~0); 191990#L819-3 assume !(0 == ~E_7~0); 191989#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 191988#L361-24 assume !(1 == ~m_pc~0); 191986#L361-26 is_master_triggered_~__retres1~0#1 := 0; 191985#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 191984#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 191983#L930-24 assume !(0 != activate_threads_~tmp~1#1); 191982#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191980#L380-24 assume 1 == ~t1_pc~0; 191978#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 191979#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191981#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 191971#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 191969#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191967#L399-24 assume !(1 == ~t2_pc~0); 191965#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 191963#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191959#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 191957#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 191955#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 191953#L418-24 assume !(1 == ~t3_pc~0); 191950#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 191947#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191945#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 191943#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 191941#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 191939#L437-24 assume !(1 == ~t4_pc~0); 191937#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 191935#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 191933#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 191930#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 191928#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 191926#L456-24 assume 1 == ~t5_pc~0; 191923#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 191921#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 191919#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 191917#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 191915#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 191913#L475-24 assume !(1 == ~t6_pc~0); 191911#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 191909#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191907#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 191904#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 191902#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 191900#L494-24 assume !(1 == ~t7_pc~0); 191897#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 191895#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 191893#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 191891#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 191889#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 191887#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 191885#L837-5 assume !(1 == ~T1_E~0); 191883#L842-3 assume !(1 == ~T2_E~0); 191880#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 191878#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 191876#L857-3 assume !(1 == ~T5_E~0); 191874#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 191872#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 191870#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 191868#L877-3 assume !(1 == ~E_2~0); 191866#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 191864#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 191862#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 191860#L897-3 assume !(1 == ~E_6~0); 191858#L902-3 assume !(1 == ~E_7~0); 191856#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 191846#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 191840#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 191838#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 191836#L1167 assume !(0 == start_simulation_~tmp~3#1); 191834#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 191833#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 191825#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 191824#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 191823#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 191822#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191821#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 191820#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 186662#L1148-2 [2024-10-13 17:46:08,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:08,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times [2024-10-13 17:46:08,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:08,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506123472] [2024-10-13 17:46:08,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:08,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:08,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:08,384 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:08,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:08,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:08,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:08,441 INFO L85 PathProgramCache]: Analyzing trace with hash -619078589, now seen corresponding path program 1 times [2024-10-13 17:46:08,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:08,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933337196] [2024-10-13 17:46:08,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:08,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:08,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:08,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:08,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:08,485 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933337196] [2024-10-13 17:46:08,485 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1933337196] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:08,485 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:08,485 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:08,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447624903] [2024-10-13 17:46:08,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:08,485 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:08,485 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:08,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:08,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:08,486 INFO L87 Difference]: Start difference. First operand 9092 states and 12653 transitions. cyclomatic complexity: 3577 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:08,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:08,643 INFO L93 Difference]: Finished difference Result 10331 states and 14356 transitions. [2024-10-13 17:46:08,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10331 states and 14356 transitions. [2024-10-13 17:46:08,684 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096 [2024-10-13 17:46:08,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10331 states to 10331 states and 14356 transitions. [2024-10-13 17:46:08,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10331 [2024-10-13 17:46:08,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10331 [2024-10-13 17:46:08,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10331 states and 14356 transitions. [2024-10-13 17:46:08,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:08,730 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14356 transitions. [2024-10-13 17:46:08,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10331 states and 14356 transitions. [2024-10-13 17:46:08,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10331 to 10331. [2024-10-13 17:46:08,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10331 states, 10331 states have (on average 1.3896041041525506) internal successors, (14356), 10330 states have internal predecessors, (14356), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:08,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10331 states to 10331 states and 14356 transitions. [2024-10-13 17:46:08,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14356 transitions. [2024-10-13 17:46:08,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:08,852 INFO L425 stractBuchiCegarLoop]: Abstraction has 10331 states and 14356 transitions. [2024-10-13 17:46:08,852 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-13 17:46:08,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10331 states and 14356 transitions. [2024-10-13 17:46:08,883 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096 [2024-10-13 17:46:08,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:08,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:08,884 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:08,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:08,885 INFO L745 eck$LassoCheckResult]: Stem: 205590#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 205591#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 206192#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 206193#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 206234#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 206215#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 206216#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205750#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 205751#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 205821#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 205653#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 205654#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 205620#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205621#L754 assume !(0 == ~M_E~0); 206250#L754-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 206266#L759-1 assume !(0 == ~T2_E~0); 206003#L764-1 assume !(0 == ~T3_E~0); 206004#L769-1 assume !(0 == ~T4_E~0); 206005#L774-1 assume !(0 == ~T5_E~0); 206006#L779-1 assume !(0 == ~T6_E~0); 206159#L784-1 assume !(0 == ~T7_E~0); 206160#L789-1 assume !(0 == ~E_1~0); 206057#L794-1 assume !(0 == ~E_2~0); 206058#L799-1 assume !(0 == ~E_3~0); 205967#L804-1 assume !(0 == ~E_4~0); 205968#L809-1 assume !(0 == ~E_5~0); 206176#L814-1 assume !(0 == ~E_6~0); 206177#L819-1 assume !(0 == ~E_7~0); 205715#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205716#L361 assume !(1 == ~m_pc~0); 206187#L361-2 is_master_triggered_~__retres1~0#1 := 0; 206188#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206312#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 206226#L930 assume !(0 != activate_threads_~tmp~1#1); 206227#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205644#L380 assume !(1 == ~t1_pc~0); 205645#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 206310#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206307#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 206304#L938 assume !(0 != activate_threads_~tmp___0~0#1); 206303#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 206302#L399 assume !(1 == ~t2_pc~0); 205560#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 205561#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205728#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 205729#L946 assume !(0 != activate_threads_~tmp___1~0#1); 206301#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206300#L418 assume !(1 == ~t3_pc~0); 205378#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 205379#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206299#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 206298#L954 assume !(0 != activate_threads_~tmp___2~0#1); 205982#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 205983#L437 assume !(1 == ~t4_pc~0); 206217#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 206129#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206130#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 206296#L962 assume !(0 != activate_threads_~tmp___3~0#1); 206203#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206113#L456 assume !(1 == ~t5_pc~0); 206114#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 206247#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 206139#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 206042#L970 assume !(0 != activate_threads_~tmp___4~0#1); 206043#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 206292#L475 assume !(1 == ~t6_pc~0); 205917#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 205918#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 205711#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 205712#L978 assume !(0 != activate_threads_~tmp___5~0#1); 206035#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 206173#L494 assume !(1 == ~t7_pc~0); 205695#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 205696#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 205926#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 206007#L986 assume !(0 != activate_threads_~tmp___6~0#1); 206008#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206244#L837 assume !(1 == ~M_E~0); 206191#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 206063#L842-1 assume !(1 == ~T2_E~0); 205787#L847-1 assume !(1 == ~T3_E~0); 205788#L852-1 assume !(1 == ~T4_E~0); 205856#L857-1 assume !(1 == ~T5_E~0); 205735#L862-1 assume !(1 == ~T6_E~0); 205736#L867-1 assume !(1 == ~T7_E~0); 205746#L872-1 assume !(1 == ~E_1~0); 205820#L877-1 assume !(1 == ~E_2~0); 206025#L882-1 assume !(1 == ~E_3~0); 206196#L887-1 assume !(1 == ~E_4~0); 206085#L892-1 assume !(1 == ~E_5~0); 206086#L897-1 assume !(1 == ~E_6~0); 205762#L902-1 assume !(1 == ~E_7~0); 205763#L907-1 assume { :end_inline_reset_delta_events } true; 206107#L1148-2 [2024-10-13 17:46:08,885 INFO L747 eck$LassoCheckResult]: Loop: 206107#L1148-2 assume !false; 210082#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 210078#L729-1 assume !false; 210075#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 210032#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 210020#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 210015#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 210007#L626 assume !(0 != eval_~tmp~0#1); 210008#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 210632#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 210631#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 210629#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 210627#L759-3 assume !(0 == ~T2_E~0); 210625#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 210623#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 210621#L774-3 assume !(0 == ~T5_E~0); 210619#L779-3 assume !(0 == ~T6_E~0); 210617#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 210615#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 210613#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 210611#L799-3 assume !(0 == ~E_3~0); 210609#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 210607#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 210605#L814-3 assume !(0 == ~E_6~0); 210603#L819-3 assume !(0 == ~E_7~0); 210601#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210599#L361-24 assume !(1 == ~m_pc~0); 210597#L361-26 is_master_triggered_~__retres1~0#1 := 0; 210595#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210593#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 210591#L930-24 assume !(0 != activate_threads_~tmp~1#1); 210589#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210586#L380-24 assume !(1 == ~t1_pc~0); 210582#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 210580#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210579#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 210576#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 210573#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210571#L399-24 assume !(1 == ~t2_pc~0); 210569#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 210567#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 210565#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 210563#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 210561#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210559#L418-24 assume 1 == ~t3_pc~0; 210555#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 210553#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 210551#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 210549#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 210547#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 210545#L437-24 assume !(1 == ~t4_pc~0); 210543#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 210541#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 210539#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 210537#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 210535#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 210533#L456-24 assume !(1 == ~t5_pc~0); 210530#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 210527#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 210525#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 210523#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 210521#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 210519#L475-24 assume !(1 == ~t6_pc~0); 210517#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 210515#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 210513#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 210511#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 210509#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 210506#L494-24 assume !(1 == ~t7_pc~0); 210503#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 210501#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 210499#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 210497#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 210495#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210493#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 210492#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 210490#L842-3 assume !(1 == ~T2_E~0); 210489#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 210488#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 210487#L857-3 assume !(1 == ~T5_E~0); 210485#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 210483#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 210481#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 210479#L877-3 assume !(1 == ~E_2~0); 210477#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 210474#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 210472#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 210470#L897-3 assume !(1 == ~E_6~0); 210468#L902-3 assume !(1 == ~E_7~0); 210466#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 210352#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 210338#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 210335#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 210257#L1167 assume !(0 == start_simulation_~tmp~3#1); 210243#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 210233#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 210225#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 210224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 210223#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 210221#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 210111#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 210100#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 206107#L1148-2 [2024-10-13 17:46:08,888 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:08,888 INFO L85 PathProgramCache]: Analyzing trace with hash -1286806590, now seen corresponding path program 1 times [2024-10-13 17:46:08,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:08,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374498114] [2024-10-13 17:46:08,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:08,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:08,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:08,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:08,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:08,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1374498114] [2024-10-13 17:46:08,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1374498114] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:08,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:08,925 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:08,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [394512232] [2024-10-13 17:46:08,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:08,926 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:08,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:08,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1761092318, now seen corresponding path program 1 times [2024-10-13 17:46:08,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:08,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662060697] [2024-10-13 17:46:08,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:08,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:08,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:08,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:08,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:08,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662060697] [2024-10-13 17:46:08,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662060697] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:08,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:08,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:08,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977356377] [2024-10-13 17:46:08,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:08,961 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:08,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:08,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:08,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:08,961 INFO L87 Difference]: Start difference. First operand 10331 states and 14356 transitions. cyclomatic complexity: 4041 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:09,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:09,010 INFO L93 Difference]: Finished difference Result 9092 states and 12603 transitions. [2024-10-13 17:46:09,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9092 states and 12603 transitions. [2024-10-13 17:46:09,150 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2024-10-13 17:46:09,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9092 states to 9092 states and 12603 transitions. [2024-10-13 17:46:09,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9092 [2024-10-13 17:46:09,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9092 [2024-10-13 17:46:09,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9092 states and 12603 transitions. [2024-10-13 17:46:09,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:09,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12603 transitions. [2024-10-13 17:46:09,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9092 states and 12603 transitions. [2024-10-13 17:46:09,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9092 to 9092. [2024-10-13 17:46:09,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.3861636603607568) internal successors, (12603), 9091 states have internal predecessors, (12603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:09,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12603 transitions. [2024-10-13 17:46:09,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12603 transitions. [2024-10-13 17:46:09,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:09,329 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12603 transitions. [2024-10-13 17:46:09,329 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-13 17:46:09,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12603 transitions. [2024-10-13 17:46:09,363 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2024-10-13 17:46:09,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:09,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:09,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:09,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:09,365 INFO L745 eck$LassoCheckResult]: Stem: 225016#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 225017#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 225590#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 225591#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 225628#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 225615#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 225616#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 225168#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 225169#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 225236#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 225078#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 225079#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 225046#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 225047#L754 assume !(0 == ~M_E~0); 225639#L754-2 assume !(0 == ~T1_E~0); 225543#L759-1 assume !(0 == ~T2_E~0); 225414#L764-1 assume !(0 == ~T3_E~0); 225370#L769-1 assume !(0 == ~T4_E~0); 225371#L774-1 assume !(0 == ~T5_E~0); 225415#L779-1 assume !(0 == ~T6_E~0); 225555#L784-1 assume !(0 == ~T7_E~0); 225367#L789-1 assume !(0 == ~E_1~0); 225368#L794-1 assume !(0 == ~E_2~0); 225458#L799-1 assume !(0 == ~E_3~0); 225378#L804-1 assume !(0 == ~E_4~0); 225379#L809-1 assume !(0 == ~E_5~0); 225409#L814-1 assume !(0 == ~E_6~0); 224820#L819-1 assume !(0 == ~E_7~0); 224821#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 225076#L361 assume !(1 == ~m_pc~0); 225077#L361-2 is_master_triggered_~__retres1~0#1 := 0; 225583#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 225528#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 225529#L930 assume !(0 != activate_threads_~tmp~1#1); 225280#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 225070#L380 assume !(1 == ~t1_pc~0); 225071#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 225625#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 225626#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 225663#L938 assume !(0 != activate_threads_~tmp___0~0#1); 225488#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 225469#L399 assume !(1 == ~t2_pc~0); 224987#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 224988#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 225149#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 225142#L946 assume !(0 != activate_threads_~tmp___1~0#1); 225143#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224828#L418 assume !(1 == ~t3_pc~0); 224808#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 224809#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224818#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 224819#L954 assume !(0 != activate_threads_~tmp___2~0#1); 225397#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 225398#L437 assume !(1 == ~t4_pc~0); 225617#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 225523#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224898#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 224899#L962 assume !(0 != activate_threads_~tmp___3~0#1); 225196#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 225505#L456 assume !(1 == ~t5_pc~0); 225002#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 225001#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 225533#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 225444#L970 assume !(0 != activate_threads_~tmp___4~0#1); 225445#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 224893#L475 assume !(1 == ~t6_pc~0); 224894#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 224935#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 224936#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 225135#L978 assume !(0 != activate_threads_~tmp___5~0#1); 225383#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 225384#L494 assume !(1 == ~t7_pc~0); 225119#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 225120#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 225338#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 225416#L986 assume !(0 != activate_threads_~tmp___6~0#1); 225417#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 225633#L837 assume !(1 == ~M_E~0); 225589#L837-2 assume !(1 == ~T1_E~0); 225464#L842-1 assume !(1 == ~T2_E~0); 225203#L847-1 assume !(1 == ~T3_E~0); 225204#L852-1 assume !(1 == ~T4_E~0); 225270#L857-1 assume !(1 == ~T5_E~0); 225155#L862-1 assume !(1 == ~T6_E~0); 225156#L867-1 assume !(1 == ~T7_E~0); 225164#L872-1 assume !(1 == ~E_1~0); 225235#L877-1 assume !(1 == ~E_2~0); 225431#L882-1 assume !(1 == ~E_3~0); 225594#L887-1 assume !(1 == ~E_4~0); 225483#L892-1 assume !(1 == ~E_5~0); 225484#L897-1 assume !(1 == ~E_6~0); 225179#L902-1 assume !(1 == ~E_7~0); 225180#L907-1 assume { :end_inline_reset_delta_events } true; 225504#L1148-2 [2024-10-13 17:46:09,366 INFO L747 eck$LassoCheckResult]: Loop: 225504#L1148-2 assume !false; 230046#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 230039#L729-1 assume !false; 230033#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 229478#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 229473#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 229471#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 229468#L626 assume !(0 != eval_~tmp~0#1); 229469#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231108#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 231106#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 231103#L754-5 assume !(0 == ~T1_E~0); 231101#L759-3 assume !(0 == ~T2_E~0); 231099#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 231097#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 231095#L774-3 assume !(0 == ~T5_E~0); 231093#L779-3 assume !(0 == ~T6_E~0); 231092#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 231091#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 231090#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 231089#L799-3 assume !(0 == ~E_3~0); 231088#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 231087#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 231086#L814-3 assume !(0 == ~E_6~0); 231085#L819-3 assume !(0 == ~E_7~0); 231084#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 231083#L361-24 assume !(1 == ~m_pc~0); 231081#L361-26 is_master_triggered_~__retres1~0#1 := 0; 231080#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 231079#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 231078#L930-24 assume !(0 != activate_threads_~tmp~1#1); 231077#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 231075#L380-24 assume 1 == ~t1_pc~0; 231073#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 231074#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 231076#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 231066#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 231064#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 231062#L399-24 assume !(1 == ~t2_pc~0); 231060#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 231058#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231054#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 231052#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 231050#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 231048#L418-24 assume !(1 == ~t3_pc~0); 231045#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 231042#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 231040#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 231038#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 231036#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 231034#L437-24 assume !(1 == ~t4_pc~0); 231032#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 231030#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 231028#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 231025#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 231023#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 231021#L456-24 assume !(1 == ~t5_pc~0); 231019#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 231016#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 231014#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 231012#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 231010#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 231008#L475-24 assume !(1 == ~t6_pc~0); 231006#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 231004#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 231002#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 230999#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 230997#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 230995#L494-24 assume !(1 == ~t7_pc~0); 230992#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 230990#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 230988#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 230986#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 230984#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 230982#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 230980#L837-5 assume !(1 == ~T1_E~0); 230978#L842-3 assume !(1 == ~T2_E~0); 230975#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 230973#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 230971#L857-3 assume !(1 == ~T5_E~0); 230969#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 230967#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 230965#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 230963#L877-3 assume !(1 == ~E_2~0); 230961#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 230959#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 230957#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 230955#L897-3 assume !(1 == ~E_6~0); 230953#L902-3 assume !(1 == ~E_7~0); 230951#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 230941#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 230935#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 230933#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 230931#L1167 assume !(0 == start_simulation_~tmp~3#1); 230926#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 230924#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 230906#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 230087#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 230083#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 230079#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 230078#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 230077#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 225504#L1148-2 [2024-10-13 17:46:09,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:09,366 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times [2024-10-13 17:46:09,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:09,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965816832] [2024-10-13 17:46:09,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:09,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:09,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:09,381 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:09,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:09,417 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:09,417 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:09,418 INFO L85 PathProgramCache]: Analyzing trace with hash 427301924, now seen corresponding path program 1 times [2024-10-13 17:46:09,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:09,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501109589] [2024-10-13 17:46:09,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:09,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:09,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:09,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:09,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:09,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501109589] [2024-10-13 17:46:09,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501109589] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:09,469 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:09,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:09,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674612822] [2024-10-13 17:46:09,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:09,470 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:09,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:09,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:09,471 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:09,471 INFO L87 Difference]: Start difference. First operand 9092 states and 12603 transitions. cyclomatic complexity: 3527 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:09,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:09,595 INFO L93 Difference]: Finished difference Result 13563 states and 18702 transitions. [2024-10-13 17:46:09,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13563 states and 18702 transitions. [2024-10-13 17:46:09,663 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13304 [2024-10-13 17:46:09,709 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13563 states to 13563 states and 18702 transitions. [2024-10-13 17:46:09,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13563 [2024-10-13 17:46:09,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13563 [2024-10-13 17:46:09,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13563 states and 18702 transitions. [2024-10-13 17:46:09,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:09,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13563 states and 18702 transitions. [2024-10-13 17:46:09,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13563 states and 18702 transitions. [2024-10-13 17:46:10,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13563 to 13555. [2024-10-13 17:46:10,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13555 states, 13555 states have (on average 1.3791220951678347) internal successors, (18694), 13554 states have internal predecessors, (18694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:10,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13555 states to 13555 states and 18694 transitions. [2024-10-13 17:46:10,113 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13555 states and 18694 transitions. [2024-10-13 17:46:10,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:10,114 INFO L425 stractBuchiCegarLoop]: Abstraction has 13555 states and 18694 transitions. [2024-10-13 17:46:10,114 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-13 17:46:10,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13555 states and 18694 transitions. [2024-10-13 17:46:10,153 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13296 [2024-10-13 17:46:10,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:10,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:10,156 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:10,156 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:10,156 INFO L745 eck$LassoCheckResult]: Stem: 247681#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 247682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 248287#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 248288#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 248327#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 248310#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 248311#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 247837#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 247838#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247906#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247741#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 247742#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 247710#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247711#L754 assume !(0 == ~M_E~0); 248344#L754-2 assume !(0 == ~T1_E~0); 248236#L759-1 assume !(0 == ~T2_E~0); 248090#L764-1 assume !(0 == ~T3_E~0); 248046#L769-1 assume !(0 == ~T4_E~0); 248047#L774-1 assume !(0 == ~T5_E~0); 248091#L779-1 assume !(0 == ~T6_E~0); 248245#L784-1 assume !(0 == ~T7_E~0); 248043#L789-1 assume !(0 == ~E_1~0); 248044#L794-1 assume 0 == ~E_2~0;~E_2~0 := 1; 248137#L799-1 assume !(0 == ~E_3~0); 248054#L804-1 assume !(0 == ~E_4~0); 248055#L809-1 assume !(0 == ~E_5~0); 248269#L814-1 assume !(0 == ~E_6~0); 248270#L819-1 assume !(0 == ~E_7~0); 247803#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247804#L361 assume !(1 == ~m_pc~0); 248281#L361-2 is_master_triggered_~__retres1~0#1 := 0; 248282#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 248223#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 248224#L930 assume !(0 != activate_threads_~tmp~1#1); 247952#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247953#L380 assume !(1 == ~t1_pc~0); 248149#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 248371#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 248405#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 248402#L938 assume !(0 != activate_threads_~tmp___0~0#1); 248401#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 248400#L399 assume !(1 == ~t2_pc~0); 247650#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 247651#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247817#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 247818#L946 assume !(0 != activate_threads_~tmp___1~0#1); 248399#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 248398#L418 assume !(1 == ~t3_pc~0); 247469#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 247470#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 248397#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 248374#L954 assume !(0 != activate_threads_~tmp___2~0#1); 248375#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 248345#L437 assume !(1 == ~t4_pc~0); 248346#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 248396#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247561#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247562#L962 assume !(0 != activate_threads_~tmp___3~0#1); 247865#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 248394#L456 assume !(1 == ~t5_pc~0); 247664#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 247663#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 248393#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 248392#L970 assume !(0 != activate_threads_~tmp___4~0#1); 248358#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 248359#L475 assume !(1 == ~t6_pc~0); 248005#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 248006#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247799#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 247800#L978 assume !(0 != activate_threads_~tmp___5~0#1); 248117#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 248267#L494 assume !(1 == ~t7_pc~0); 247999#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 248389#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 248388#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 248387#L986 assume !(0 != activate_threads_~tmp___6~0#1); 248386#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 248385#L837 assume !(1 == ~M_E~0); 248384#L837-2 assume !(1 == ~T1_E~0); 248383#L842-1 assume !(1 == ~T2_E~0); 248382#L847-1 assume !(1 == ~T3_E~0); 247941#L852-1 assume !(1 == ~T4_E~0); 247942#L857-1 assume !(1 == ~T5_E~0); 247824#L862-1 assume !(1 == ~T6_E~0); 247825#L867-1 assume !(1 == ~T7_E~0); 247833#L872-1 assume !(1 == ~E_1~0); 247905#L877-1 assume 1 == ~E_2~0;~E_2~0 := 2; 248106#L882-1 assume !(1 == ~E_3~0); 248294#L887-1 assume !(1 == ~E_4~0); 248168#L892-1 assume !(1 == ~E_5~0); 248169#L897-1 assume !(1 == ~E_6~0); 247848#L902-1 assume !(1 == ~E_7~0); 247849#L907-1 assume { :end_inline_reset_delta_events } true; 248191#L1148-2 [2024-10-13 17:46:10,156 INFO L747 eck$LassoCheckResult]: Loop: 248191#L1148-2 assume !false; 249932#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 249927#L729-1 assume !false; 249923#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 249911#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 249902#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 249898#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 249893#L626 assume !(0 != eval_~tmp~0#1); 249894#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 250849#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 250847#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 250844#L754-5 assume !(0 == ~T1_E~0); 250842#L759-3 assume !(0 == ~T2_E~0); 250840#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 250838#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 250836#L774-3 assume !(0 == ~T5_E~0); 250834#L779-3 assume !(0 == ~T6_E~0); 250833#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 250832#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 250830#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 250831#L799-3 assume !(0 == ~E_3~0); 251069#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 251067#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 251065#L814-3 assume !(0 == ~E_6~0); 251063#L819-3 assume !(0 == ~E_7~0); 251039#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 251031#L361-24 assume !(1 == ~m_pc~0); 251024#L361-26 is_master_triggered_~__retres1~0#1 := 0; 251016#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 251013#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 251011#L930-24 assume !(0 != activate_threads_~tmp~1#1); 250667#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 250664#L380-24 assume 1 == ~t1_pc~0; 250662#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 250663#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 250672#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 250651#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 250649#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 250646#L399-24 assume !(1 == ~t2_pc~0); 250644#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 250642#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 250640#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 250638#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 250636#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 250634#L418-24 assume !(1 == ~t3_pc~0); 250629#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 250626#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 250624#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 250621#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 250619#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 250617#L437-24 assume !(1 == ~t4_pc~0); 250615#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 250613#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 250611#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 250597#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 250592#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 250581#L456-24 assume !(1 == ~t5_pc~0); 250573#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 250565#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 250559#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 250555#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 250549#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 250543#L475-24 assume !(1 == ~t6_pc~0); 250536#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 250529#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 250523#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 250516#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 250511#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 250504#L494-24 assume !(1 == ~t7_pc~0); 250495#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 250488#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 250481#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 250474#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 250468#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 250462#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 250457#L837-5 assume !(1 == ~T1_E~0); 250450#L842-3 assume !(1 == ~T2_E~0); 250443#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 250437#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 250431#L857-3 assume !(1 == ~T5_E~0); 250424#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 250417#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 250411#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 250405#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 250399#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 250394#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 250390#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 250385#L897-3 assume !(1 == ~E_6~0); 250381#L902-3 assume !(1 == ~E_7~0); 250378#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 250320#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 250309#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 250302#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 250294#L1167 assume !(0 == start_simulation_~tmp~3#1); 250288#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 249998#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 249989#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 249988#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 249987#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 249985#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 249983#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 249981#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 248191#L1148-2 [2024-10-13 17:46:10,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:10,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1160880066, now seen corresponding path program 1 times [2024-10-13 17:46:10,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:10,157 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717343807] [2024-10-13 17:46:10,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:10,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:10,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:10,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:10,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:10,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717343807] [2024-10-13 17:46:10,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717343807] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:10,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:10,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:10,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406357816] [2024-10-13 17:46:10,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:10,195 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:10,195 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:10,195 INFO L85 PathProgramCache]: Analyzing trace with hash 2116245666, now seen corresponding path program 1 times [2024-10-13 17:46:10,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:10,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162823799] [2024-10-13 17:46:10,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:10,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:10,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:10,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:10,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:10,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162823799] [2024-10-13 17:46:10,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162823799] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:10,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:10,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:10,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296671874] [2024-10-13 17:46:10,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:10,251 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:10,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:10,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:10,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:10,252 INFO L87 Difference]: Start difference. First operand 13555 states and 18694 transitions. cyclomatic complexity: 5155 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:10,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:10,320 INFO L93 Difference]: Finished difference Result 9092 states and 12493 transitions. [2024-10-13 17:46:10,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9092 states and 12493 transitions. [2024-10-13 17:46:10,357 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2024-10-13 17:46:10,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9092 states to 9092 states and 12493 transitions. [2024-10-13 17:46:10,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9092 [2024-10-13 17:46:10,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9092 [2024-10-13 17:46:10,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9092 states and 12493 transitions. [2024-10-13 17:46:10,393 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:10,393 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12493 transitions. [2024-10-13 17:46:10,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9092 states and 12493 transitions. [2024-10-13 17:46:10,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9092 to 9092. [2024-10-13 17:46:10,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.3740651121865377) internal successors, (12493), 9091 states have internal predecessors, (12493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:10,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12493 transitions. [2024-10-13 17:46:10,631 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12493 transitions. [2024-10-13 17:46:10,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:10,632 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12493 transitions. [2024-10-13 17:46:10,632 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-13 17:46:10,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12493 transitions. [2024-10-13 17:46:10,649 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2024-10-13 17:46:10,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:10,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:10,651 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:10,652 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:10,652 INFO L745 eck$LassoCheckResult]: Stem: 270331#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 270332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 270900#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 270901#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 270941#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 270922#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 270923#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 270484#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 270485#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 270556#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 270395#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 270396#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 270363#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 270364#L754 assume !(0 == ~M_E~0); 270953#L754-2 assume !(0 == ~T1_E~0); 270857#L759-1 assume !(0 == ~T2_E~0); 270730#L764-1 assume !(0 == ~T3_E~0); 270688#L769-1 assume !(0 == ~T4_E~0); 270689#L774-1 assume !(0 == ~T5_E~0); 270731#L779-1 assume !(0 == ~T6_E~0); 270867#L784-1 assume !(0 == ~T7_E~0); 270684#L789-1 assume !(0 == ~E_1~0); 270685#L794-1 assume !(0 == ~E_2~0); 270776#L799-1 assume !(0 == ~E_3~0); 270695#L804-1 assume !(0 == ~E_4~0); 270696#L809-1 assume !(0 == ~E_5~0); 270725#L814-1 assume !(0 == ~E_6~0); 270141#L819-1 assume !(0 == ~E_7~0); 270142#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270392#L361 assume !(1 == ~m_pc~0); 270393#L361-2 is_master_triggered_~__retres1~0#1 := 0; 270896#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270845#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 270846#L930 assume !(0 != activate_threads_~tmp~1#1); 270599#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270386#L380 assume !(1 == ~t1_pc~0); 270387#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 270936#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270937#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270975#L938 assume !(0 != activate_threads_~tmp___0~0#1); 270805#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270785#L399 assume !(1 == ~t2_pc~0); 270301#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 270302#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270464#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270457#L946 assume !(0 != activate_threads_~tmp___1~0#1); 270458#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270145#L418 assume !(1 == ~t3_pc~0); 270125#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 270126#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270135#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270136#L954 assume !(0 != activate_threads_~tmp___2~0#1); 270710#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270711#L437 assume !(1 == ~t4_pc~0); 270924#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 270841#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270217#L962 assume !(0 != activate_threads_~tmp___3~0#1); 270513#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 270827#L456 assume !(1 == ~t5_pc~0); 270315#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 270314#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 270849#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 270763#L970 assume !(0 != activate_threads_~tmp___4~0#1); 270764#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 270209#L475 assume !(1 == ~t6_pc~0); 270210#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 270250#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 270251#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 270450#L978 assume !(0 != activate_threads_~tmp___5~0#1); 270701#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 270702#L494 assume !(1 == ~t7_pc~0); 270434#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 270435#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 270656#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 270732#L986 assume !(0 != activate_threads_~tmp___6~0#1); 270733#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 270949#L837 assume !(1 == ~M_E~0); 270899#L837-2 assume !(1 == ~T1_E~0); 270781#L842-1 assume !(1 == ~T2_E~0); 270522#L847-1 assume !(1 == ~T3_E~0); 270523#L852-1 assume !(1 == ~T4_E~0); 270589#L857-1 assume !(1 == ~T5_E~0); 270470#L862-1 assume !(1 == ~T6_E~0); 270471#L867-1 assume !(1 == ~T7_E~0); 270480#L872-1 assume !(1 == ~E_1~0); 270555#L877-1 assume !(1 == ~E_2~0); 270747#L882-1 assume !(1 == ~E_3~0); 270905#L887-1 assume !(1 == ~E_4~0); 270799#L892-1 assume !(1 == ~E_5~0); 270800#L897-1 assume !(1 == ~E_6~0); 270497#L902-1 assume !(1 == ~E_7~0); 270498#L907-1 assume { :end_inline_reset_delta_events } true; 270821#L1148-2 [2024-10-13 17:46:10,653 INFO L747 eck$LassoCheckResult]: Loop: 270821#L1148-2 assume !false; 278535#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 278533#L729-1 assume !false; 278531#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 277891#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 277885#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 277883#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 277882#L626 assume !(0 != eval_~tmp~0#1); 270801#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 270598#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 270407#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 270150#L754-5 assume !(0 == ~T1_E~0); 270151#L759-3 assume !(0 == ~T2_E~0); 270532#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 270533#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 270712#L774-3 assume !(0 == ~T5_E~0); 270307#L779-3 assume !(0 == ~T6_E~0); 270146#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 270147#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 270137#L794-3 assume !(0 == ~E_2~0); 270138#L799-3 assume !(0 == ~E_3~0); 270190#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 270414#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 270186#L814-3 assume !(0 == ~E_6~0); 270187#L819-3 assume !(0 == ~E_7~0); 270832#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270551#L361-24 assume !(1 == ~m_pc~0); 270552#L361-26 is_master_triggered_~__retres1~0#1 := 0; 270639#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270237#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 270238#L930-24 assume !(0 != activate_threads_~tmp~1#1); 270887#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270692#L380-24 assume 1 == ~t1_pc~0; 270693#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 270907#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 279083#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 279082#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 270404#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270786#L399-24 assume !(1 == ~t2_pc~0); 270421#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 270338#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270339#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270588#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 270400#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270401#L418-24 assume 1 == ~t3_pc~0; 270886#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 270185#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270474#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270305#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 270306#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270765#L437-24 assume !(1 == ~t4_pc~0); 270890#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 270964#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270587#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270294#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 270295#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 270700#L456-24 assume !(1 == ~t5_pc~0); 270672#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 270648#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 270649#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 270877#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 270600#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 270601#L475-24 assume !(1 == ~t6_pc~0); 270908#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 270655#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 270287#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 270288#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 270131#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 270132#L494-24 assume !(1 == ~t7_pc~0); 270475#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 270455#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 270456#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 270397#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 270398#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 270835#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 270863#L837-5 assume !(1 == ~T1_E~0); 270595#L842-3 assume !(1 == ~T2_E~0); 270596#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 270759#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 270652#L857-3 assume !(1 == ~T5_E~0); 270653#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 270958#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 270569#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 270570#L877-3 assume !(1 == ~E_2~0); 270647#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 270704#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 270325#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 270326#L897-3 assume !(1 == ~E_6~0); 270862#L902-3 assume !(1 == ~E_7~0); 278663#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278593#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278587#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278585#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 278582#L1167 assume !(0 == start_simulation_~tmp~3#1); 278579#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278577#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278569#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278565#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 278563#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 278561#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 278559#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 278556#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 270821#L1148-2 [2024-10-13 17:46:10,653 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:10,653 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times [2024-10-13 17:46:10,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:10,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219961019] [2024-10-13 17:46:10,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:10,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:10,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:10,665 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:10,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:10,690 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:10,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:10,691 INFO L85 PathProgramCache]: Analyzing trace with hash -1401161785, now seen corresponding path program 1 times [2024-10-13 17:46:10,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:10,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132106135] [2024-10-13 17:46:10,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:10,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:10,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:10,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:10,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:10,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132106135] [2024-10-13 17:46:10,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132106135] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:10,742 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:10,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:10,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41770285] [2024-10-13 17:46:10,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:10,743 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:10,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:10,743 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:10,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:10,744 INFO L87 Difference]: Start difference. First operand 9092 states and 12493 transitions. cyclomatic complexity: 3417 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:10,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:10,835 INFO L93 Difference]: Finished difference Result 9204 states and 12605 transitions. [2024-10-13 17:46:10,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9204 states and 12605 transitions. [2024-10-13 17:46:10,860 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9040 [2024-10-13 17:46:10,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9204 states to 9204 states and 12605 transitions. [2024-10-13 17:46:10,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9204 [2024-10-13 17:46:10,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9204 [2024-10-13 17:46:10,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9204 states and 12605 transitions. [2024-10-13 17:46:10,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:10,884 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9204 states and 12605 transitions. [2024-10-13 17:46:10,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9204 states and 12605 transitions. [2024-10-13 17:46:10,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9204 to 9140. [2024-10-13 17:46:10,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9140 states, 9140 states have (on average 1.3721006564551423) internal successors, (12541), 9139 states have internal predecessors, (12541), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:10,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9140 states to 9140 states and 12541 transitions. [2024-10-13 17:46:10,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9140 states and 12541 transitions. [2024-10-13 17:46:10,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:10,970 INFO L425 stractBuchiCegarLoop]: Abstraction has 9140 states and 12541 transitions. [2024-10-13 17:46:10,971 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-13 17:46:10,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9140 states and 12541 transitions. [2024-10-13 17:46:10,989 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8976 [2024-10-13 17:46:10,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:10,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:10,990 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:10,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:10,991 INFO L745 eck$LassoCheckResult]: Stem: 288636#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 288637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 289225#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 289226#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 289263#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 289247#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 289248#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 288784#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 288785#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 288856#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 288696#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 288697#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 288666#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 288667#L754 assume !(0 == ~M_E~0); 289276#L754-2 assume !(0 == ~T1_E~0); 289184#L759-1 assume !(0 == ~T2_E~0); 289042#L764-1 assume !(0 == ~T3_E~0); 288993#L769-1 assume !(0 == ~T4_E~0); 288994#L774-1 assume !(0 == ~T5_E~0); 289043#L779-1 assume !(0 == ~T6_E~0); 289192#L784-1 assume !(0 == ~T7_E~0); 288990#L789-1 assume !(0 == ~E_1~0); 288991#L794-1 assume !(0 == ~E_2~0); 289091#L799-1 assume !(0 == ~E_3~0); 289002#L804-1 assume !(0 == ~E_4~0); 289003#L809-1 assume !(0 == ~E_5~0); 289036#L814-1 assume !(0 == ~E_6~0); 288441#L819-1 assume !(0 == ~E_7~0); 288442#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 288694#L361 assume !(1 == ~m_pc~0); 288695#L361-2 is_master_triggered_~__retres1~0#1 := 0; 289220#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 289169#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 289170#L930 assume !(0 != activate_threads_~tmp~1#1); 288899#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 288688#L380 assume !(1 == ~t1_pc~0); 288689#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 289259#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 289260#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 289301#L938 assume !(0 != activate_threads_~tmp___0~0#1); 289124#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 289101#L399 assume !(1 == ~t2_pc~0); 288605#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 288606#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 288765#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 288758#L946 assume !(0 != activate_threads_~tmp___1~0#1); 288759#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 288449#L418 assume !(1 == ~t3_pc~0); 288429#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 288430#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 288439#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 288440#L954 assume !(0 != activate_threads_~tmp___2~0#1); 289022#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 289023#L437 assume !(1 == ~t4_pc~0); 289249#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 289163#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 288518#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 288519#L962 assume !(0 != activate_threads_~tmp___3~0#1); 288812#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 289143#L456 assume !(1 == ~t5_pc~0); 288619#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 288618#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 289173#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 289076#L970 assume !(0 != activate_threads_~tmp___4~0#1); 289077#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 288513#L475 assume !(1 == ~t6_pc~0); 288514#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 288556#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 288557#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 288751#L978 assume !(0 != activate_threads_~tmp___5~0#1); 289008#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 289009#L494 assume !(1 == ~t7_pc~0); 288735#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 288736#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 288959#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 289044#L986 assume !(0 != activate_threads_~tmp___6~0#1); 289045#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 289270#L837 assume !(1 == ~M_E~0); 289224#L837-2 assume !(1 == ~T1_E~0); 289097#L842-1 assume !(1 == ~T2_E~0); 288820#L847-1 assume !(1 == ~T3_E~0); 288821#L852-1 assume !(1 == ~T4_E~0); 288889#L857-1 assume !(1 == ~T5_E~0); 288771#L862-1 assume !(1 == ~T6_E~0); 288772#L867-1 assume !(1 == ~T7_E~0); 288780#L872-1 assume !(1 == ~E_1~0); 288855#L877-1 assume !(1 == ~E_2~0); 289061#L882-1 assume !(1 == ~E_3~0); 289229#L887-1 assume !(1 == ~E_4~0); 289117#L892-1 assume !(1 == ~E_5~0); 289118#L897-1 assume !(1 == ~E_6~0); 288795#L902-1 assume !(1 == ~E_7~0); 288796#L907-1 assume { :end_inline_reset_delta_events } true; 289142#L1148-2 [2024-10-13 17:46:10,992 INFO L747 eck$LassoCheckResult]: Loop: 289142#L1148-2 assume !false; 291205#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 291204#L729-1 assume !false; 291203#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 291198#L569 assume !(0 == ~m_st~0); 291199#L573 assume !(0 == ~t1_st~0); 291202#L577 assume !(0 == ~t2_st~0); 291196#L581 assume !(0 == ~t3_st~0); 291197#L585 assume !(0 == ~t4_st~0); 291201#L589 assume !(0 == ~t5_st~0); 291194#L593 assume !(0 == ~t6_st~0); 291195#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 291200#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 295711#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 295710#L626 assume !(0 != eval_~tmp~0#1); 295709#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 295708#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 295707#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 295706#L754-5 assume !(0 == ~T1_E~0); 295704#L759-3 assume !(0 == ~T2_E~0); 295702#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 295700#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 295698#L774-3 assume !(0 == ~T5_E~0); 295696#L779-3 assume !(0 == ~T6_E~0); 295694#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 295692#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 295690#L794-3 assume !(0 == ~E_2~0); 295688#L799-3 assume !(0 == ~E_3~0); 295686#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 295684#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 295682#L814-3 assume !(0 == ~E_6~0); 295680#L819-3 assume !(0 == ~E_7~0); 295678#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295676#L361-24 assume !(1 == ~m_pc~0); 295674#L361-26 is_master_triggered_~__retres1~0#1 := 0; 295672#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 295670#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 295668#L930-24 assume !(0 != activate_threads_~tmp~1#1); 295666#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 295664#L380-24 assume 1 == ~t1_pc~0; 295662#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 295663#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 295712#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 295652#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 295650#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 295646#L399-24 assume !(1 == ~t2_pc~0); 295644#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 295642#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 295640#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 295637#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 295635#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 295633#L418-24 assume 1 == ~t3_pc~0; 295630#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 295628#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 295626#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 295624#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 295622#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 295620#L437-24 assume !(1 == ~t4_pc~0); 295617#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 295615#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 295613#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 295611#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 295609#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 295607#L456-24 assume !(1 == ~t5_pc~0); 295604#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 295601#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 295599#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 295597#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 295595#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295593#L475-24 assume !(1 == ~t6_pc~0); 295590#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 295588#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 295586#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295584#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 295582#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 295580#L494-24 assume !(1 == ~t7_pc~0); 295577#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 295575#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 295573#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 295571#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 295569#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 295566#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 295564#L837-5 assume !(1 == ~T1_E~0); 295562#L842-3 assume !(1 == ~T2_E~0); 295560#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 295558#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 295556#L857-3 assume !(1 == ~T5_E~0); 295554#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 295552#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 295550#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 295548#L877-3 assume !(1 == ~E_2~0); 295546#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 295544#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 295542#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 295540#L897-3 assume !(1 == ~E_6~0); 295538#L902-3 assume !(1 == ~E_7~0); 295536#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 295517#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 295511#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 295507#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 295504#L1167 assume !(0 == start_simulation_~tmp~3#1); 295494#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 295492#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 295484#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 291529#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 291527#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 291525#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 291512#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 291214#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 289142#L1148-2 [2024-10-13 17:46:10,992 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:10,993 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times [2024-10-13 17:46:10,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:10,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114978864] [2024-10-13 17:46:10,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:10,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:11,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:11,076 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:11,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:11,093 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:11,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:11,094 INFO L85 PathProgramCache]: Analyzing trace with hash -713517365, now seen corresponding path program 1 times [2024-10-13 17:46:11,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:11,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120043737] [2024-10-13 17:46:11,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:11,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:11,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:11,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:11,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:11,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120043737] [2024-10-13 17:46:11,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2120043737] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:11,131 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:11,131 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:11,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896768306] [2024-10-13 17:46:11,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:11,132 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:11,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:11,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:11,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:11,132 INFO L87 Difference]: Start difference. First operand 9140 states and 12541 transitions. cyclomatic complexity: 3417 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:11,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:11,226 INFO L93 Difference]: Finished difference Result 17268 states and 23397 transitions. [2024-10-13 17:46:11,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17268 states and 23397 transitions. [2024-10-13 17:46:11,289 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17056 [2024-10-13 17:46:11,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17268 states to 17268 states and 23397 transitions. [2024-10-13 17:46:11,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17268 [2024-10-13 17:46:11,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17268 [2024-10-13 17:46:11,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17268 states and 23397 transitions. [2024-10-13 17:46:11,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:11,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17268 states and 23397 transitions. [2024-10-13 17:46:11,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17268 states and 23397 transitions. [2024-10-13 17:46:11,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17268 to 16832. [2024-10-13 17:46:11,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16832 states, 16832 states have (on average 1.356523288973384) internal successors, (22833), 16831 states have internal predecessors, (22833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:11,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16832 states to 16832 states and 22833 transitions. [2024-10-13 17:46:11,529 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16832 states and 22833 transitions. [2024-10-13 17:46:11,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:11,530 INFO L425 stractBuchiCegarLoop]: Abstraction has 16832 states and 22833 transitions. [2024-10-13 17:46:11,530 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-10-13 17:46:11,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16832 states and 22833 transitions. [2024-10-13 17:46:11,631 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16620 [2024-10-13 17:46:11,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:11,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:11,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:11,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:11,633 INFO L745 eck$LassoCheckResult]: Stem: 315052#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 315053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 315638#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 315639#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 315676#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 315663#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 315664#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 315203#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 315204#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 315274#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 315112#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 315113#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 315081#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 315082#L754 assume !(0 == ~M_E~0); 315695#L754-2 assume !(0 == ~T1_E~0); 315590#L759-1 assume !(0 == ~T2_E~0); 315452#L764-1 assume !(0 == ~T3_E~0); 315408#L769-1 assume !(0 == ~T4_E~0); 315409#L774-1 assume !(0 == ~T5_E~0); 315453#L779-1 assume !(0 == ~T6_E~0); 315599#L784-1 assume !(0 == ~T7_E~0); 315405#L789-1 assume !(0 == ~E_1~0); 315406#L794-1 assume !(0 == ~E_2~0); 315502#L799-1 assume !(0 == ~E_3~0); 315416#L804-1 assume !(0 == ~E_4~0); 315417#L809-1 assume !(0 == ~E_5~0); 315447#L814-1 assume !(0 == ~E_6~0); 314855#L819-1 assume !(0 == ~E_7~0); 314856#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 315110#L361 assume !(1 == ~m_pc~0); 315111#L361-2 is_master_triggered_~__retres1~0#1 := 0; 315633#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 315577#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 315578#L930 assume !(0 != activate_threads_~tmp~1#1); 315319#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 315104#L380 assume !(1 == ~t1_pc~0); 315105#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 315673#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 315674#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 315722#L938 assume !(0 != activate_threads_~tmp___0~0#1); 315530#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315511#L399 assume !(1 == ~t2_pc~0); 315021#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 315022#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 315184#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315177#L946 assume !(0 != activate_threads_~tmp___1~0#1); 315178#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 314863#L418 assume !(1 == ~t3_pc~0); 314843#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 314844#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 314853#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 314854#L954 assume !(0 != activate_threads_~tmp___2~0#1); 315433#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 315434#L437 assume !(1 == ~t4_pc~0); 315665#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 315571#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 314933#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 314934#L962 assume !(0 != activate_threads_~tmp___3~0#1); 315232#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 315550#L456 assume !(1 == ~t5_pc~0); 315035#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 315034#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 315581#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 315486#L970 assume !(0 != activate_threads_~tmp___4~0#1); 315487#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 314928#L475 assume !(1 == ~t6_pc~0); 314929#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 314970#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314971#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 315169#L978 assume !(0 != activate_threads_~tmp___5~0#1); 315423#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 315424#L494 assume !(1 == ~t7_pc~0); 315153#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 315154#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 315377#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 315454#L986 assume !(0 != activate_threads_~tmp___6~0#1); 315455#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 315685#L837 assume !(1 == ~M_E~0); 315637#L837-2 assume !(1 == ~T1_E~0); 315507#L842-1 assume !(1 == ~T2_E~0); 315242#L847-1 assume !(1 == ~T3_E~0); 315243#L852-1 assume !(1 == ~T4_E~0); 315309#L857-1 assume !(1 == ~T5_E~0); 315190#L862-1 assume !(1 == ~T6_E~0); 315191#L867-1 assume !(1 == ~T7_E~0); 315199#L872-1 assume !(1 == ~E_1~0); 315273#L877-1 assume !(1 == ~E_2~0); 315468#L882-1 assume !(1 == ~E_3~0); 315644#L887-1 assume !(1 == ~E_4~0); 315525#L892-1 assume !(1 == ~E_5~0); 315526#L897-1 assume !(1 == ~E_6~0); 315215#L902-1 assume !(1 == ~E_7~0); 315216#L907-1 assume { :end_inline_reset_delta_events } true; 315549#L1148-2 [2024-10-13 17:46:11,634 INFO L747 eck$LassoCheckResult]: Loop: 315549#L1148-2 assume !false; 325863#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 325861#L729-1 assume !false; 325859#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 325856#L569 assume !(0 == ~m_st~0); 325857#L573 assume !(0 == ~t1_st~0); 327248#L577 assume !(0 == ~t2_st~0); 327244#L581 assume !(0 == ~t3_st~0); 327245#L585 assume !(0 == ~t4_st~0); 327247#L589 assume !(0 == ~t5_st~0); 327242#L593 assume !(0 == ~t6_st~0); 327243#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 327246#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 327236#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 327237#L626 assume !(0 != eval_~tmp~0#1); 329784#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 329782#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 329780#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 329778#L754-5 assume !(0 == ~T1_E~0); 329776#L759-3 assume !(0 == ~T2_E~0); 329774#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 329771#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 329757#L774-3 assume !(0 == ~T5_E~0); 329750#L779-3 assume !(0 == ~T6_E~0); 329743#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 329736#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 329729#L794-3 assume !(0 == ~E_2~0); 329721#L799-3 assume !(0 == ~E_3~0); 329714#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 329706#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 329699#L814-3 assume !(0 == ~E_6~0); 329692#L819-3 assume !(0 == ~E_7~0); 329685#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 329671#L361-24 assume !(1 == ~m_pc~0); 329666#L361-26 is_master_triggered_~__retres1~0#1 := 0; 329661#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 329657#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 329650#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 329644#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 326207#L380-24 assume 1 == ~t1_pc~0; 326205#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 326206#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 326213#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 326196#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 326194#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326192#L399-24 assume !(1 == ~t2_pc~0); 326190#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 326188#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 326186#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 326183#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 326181#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326179#L418-24 assume 1 == ~t3_pc~0; 326176#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 326174#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 326172#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 326170#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 326168#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 326166#L437-24 assume !(1 == ~t4_pc~0); 326164#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 326162#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 326159#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 326157#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 326155#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 326153#L456-24 assume 1 == ~t5_pc~0; 326150#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 326148#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 326147#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 326146#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 326145#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 326144#L475-24 assume !(1 == ~t6_pc~0); 326142#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 326139#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 326137#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 326135#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 326133#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 326131#L494-24 assume !(1 == ~t7_pc~0); 325980#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 325972#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 325968#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 325966#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 325964#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 325962#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 325959#L837-5 assume !(1 == ~T1_E~0); 325957#L842-3 assume !(1 == ~T2_E~0); 325954#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 325952#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 325950#L857-3 assume !(1 == ~T5_E~0); 325948#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 325946#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 325944#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 325942#L877-3 assume !(1 == ~E_2~0); 325939#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 325937#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 325935#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 325933#L897-3 assume !(1 == ~E_6~0); 325931#L902-3 assume !(1 == ~E_7~0); 325929#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 325925#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 325923#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 325921#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 325918#L1167 assume !(0 == start_simulation_~tmp~3#1); 325915#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 325912#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 325909#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 325907#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 325905#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 325903#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 325901#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 325900#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 315549#L1148-2 [2024-10-13 17:46:11,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:11,634 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 5 times [2024-10-13 17:46:11,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:11,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37870663] [2024-10-13 17:46:11,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:11,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:11,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:11,646 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:11,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:11,665 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:11,666 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:11,666 INFO L85 PathProgramCache]: Analyzing trace with hash 517586606, now seen corresponding path program 1 times [2024-10-13 17:46:11,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:11,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659201368] [2024-10-13 17:46:11,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:11,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:11,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:11,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:11,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:11,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659201368] [2024-10-13 17:46:11,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1659201368] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:11,746 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:11,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:11,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958543934] [2024-10-13 17:46:11,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:11,747 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:11,747 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:11,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:11,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:11,747 INFO L87 Difference]: Start difference. First operand 16832 states and 22833 transitions. cyclomatic complexity: 6017 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:11,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:11,981 INFO L93 Difference]: Finished difference Result 15906 states and 21378 transitions. [2024-10-13 17:46:11,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15906 states and 21378 transitions. [2024-10-13 17:46:12,050 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15692 [2024-10-13 17:46:12,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15906 states to 15906 states and 21378 transitions. [2024-10-13 17:46:12,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15906 [2024-10-13 17:46:12,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15906 [2024-10-13 17:46:12,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15906 states and 21378 transitions. [2024-10-13 17:46:12,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:12,109 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15906 states and 21378 transitions. [2024-10-13 17:46:12,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15906 states and 21378 transitions. [2024-10-13 17:46:12,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15906 to 15906. [2024-10-13 17:46:12,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15906 states, 15906 states have (on average 1.3440211241041116) internal successors, (21378), 15905 states have internal predecessors, (21378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:12,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15906 states to 15906 states and 21378 transitions. [2024-10-13 17:46:12,312 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15906 states and 21378 transitions. [2024-10-13 17:46:12,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:12,313 INFO L425 stractBuchiCegarLoop]: Abstraction has 15906 states and 21378 transitions. [2024-10-13 17:46:12,314 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-10-13 17:46:12,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15906 states and 21378 transitions. [2024-10-13 17:46:12,355 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15692 [2024-10-13 17:46:12,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:12,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:12,356 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:12,356 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:12,356 INFO L745 eck$LassoCheckResult]: Stem: 347797#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 347798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 348391#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 348392#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 348427#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 348413#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 348414#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 347949#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 347950#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 348023#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 347857#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 347858#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 347826#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 347827#L754 assume !(0 == ~M_E~0); 348448#L754-2 assume !(0 == ~T1_E~0); 348345#L759-1 assume !(0 == ~T2_E~0); 348205#L764-1 assume !(0 == ~T3_E~0); 348159#L769-1 assume !(0 == ~T4_E~0); 348160#L774-1 assume !(0 == ~T5_E~0); 348206#L779-1 assume !(0 == ~T6_E~0); 348354#L784-1 assume !(0 == ~T7_E~0); 348156#L789-1 assume !(0 == ~E_1~0); 348157#L794-1 assume !(0 == ~E_2~0); 348255#L799-1 assume !(0 == ~E_3~0); 348168#L804-1 assume !(0 == ~E_4~0); 348169#L809-1 assume !(0 == ~E_5~0); 348200#L814-1 assume !(0 == ~E_6~0); 347601#L819-1 assume !(0 == ~E_7~0); 347602#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 347855#L361 assume !(1 == ~m_pc~0); 347856#L361-2 is_master_triggered_~__retres1~0#1 := 0; 348386#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 348331#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 348332#L930 assume !(0 != activate_threads_~tmp~1#1); 348068#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347849#L380 assume !(1 == ~t1_pc~0); 347850#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 348424#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 348425#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 348479#L938 assume !(0 != activate_threads_~tmp___0~0#1); 348286#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 348264#L399 assume !(1 == ~t2_pc~0); 347766#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 347767#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 347929#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 347922#L946 assume !(0 != activate_threads_~tmp___1~0#1); 347923#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 347609#L418 assume !(1 == ~t3_pc~0); 347589#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 347590#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 347599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 347600#L954 assume !(0 != activate_threads_~tmp___2~0#1); 348186#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 348187#L437 assume !(1 == ~t4_pc~0); 348415#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 348325#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 347678#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 347679#L962 assume !(0 != activate_threads_~tmp___3~0#1); 347979#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 348306#L456 assume !(1 == ~t5_pc~0); 347781#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 347780#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 348335#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 348240#L970 assume !(0 != activate_threads_~tmp___4~0#1); 348241#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 347673#L475 assume !(1 == ~t6_pc~0); 347674#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 347716#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 347717#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 347914#L978 assume !(0 != activate_threads_~tmp___5~0#1); 348174#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 348175#L494 assume !(1 == ~t7_pc~0); 347898#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 347899#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 348128#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 348207#L986 assume !(0 != activate_threads_~tmp___6~0#1); 348208#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 348437#L837 assume !(1 == ~M_E~0); 348390#L837-2 assume !(1 == ~T1_E~0); 348260#L842-1 assume !(1 == ~T2_E~0); 347988#L847-1 assume !(1 == ~T3_E~0); 347989#L852-1 assume !(1 == ~T4_E~0); 348058#L857-1 assume !(1 == ~T5_E~0); 347935#L862-1 assume !(1 == ~T6_E~0); 347936#L867-1 assume !(1 == ~T7_E~0); 347944#L872-1 assume !(1 == ~E_1~0); 348022#L877-1 assume !(1 == ~E_2~0); 348223#L882-1 assume !(1 == ~E_3~0); 348397#L887-1 assume !(1 == ~E_4~0); 348280#L892-1 assume !(1 == ~E_5~0); 348281#L897-1 assume !(1 == ~E_6~0); 347961#L902-1 assume !(1 == ~E_7~0); 347962#L907-1 assume { :end_inline_reset_delta_events } true; 348305#L1148-2 assume !false; 355673#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 355671#L729-1 [2024-10-13 17:46:12,357 INFO L747 eck$LassoCheckResult]: Loop: 355671#L729-1 assume !false; 355668#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 355665#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 355663#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 355661#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 355659#L626 assume 0 != eval_~tmp~0#1; 355657#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 355652#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 355650#L634-2 havoc eval_~tmp_ndt_1~0#1; 355647#L631-1 assume !(0 == ~t1_st~0); 355644#L645-1 assume !(0 == ~t2_st~0); 355645#L659-1 assume !(0 == ~t3_st~0); 355684#L673-1 assume !(0 == ~t4_st~0); 355681#L687-1 assume !(0 == ~t5_st~0); 355678#L701-1 assume !(0 == ~t6_st~0); 355675#L715-1 assume !(0 == ~t7_st~0); 355671#L729-1 [2024-10-13 17:46:12,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:12,357 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 1 times [2024-10-13 17:46:12,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:12,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345680076] [2024-10-13 17:46:12,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:12,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:12,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,370 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:12,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:12,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:12,390 INFO L85 PathProgramCache]: Analyzing trace with hash -1739844173, now seen corresponding path program 1 times [2024-10-13 17:46:12,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:12,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296004277] [2024-10-13 17:46:12,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:12,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:12,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,394 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:12,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,397 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:12,398 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:12,398 INFO L85 PathProgramCache]: Analyzing trace with hash 729268538, now seen corresponding path program 1 times [2024-10-13 17:46:12,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:12,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781968152] [2024-10-13 17:46:12,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:12,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:12,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:12,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:12,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:12,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781968152] [2024-10-13 17:46:12,448 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781968152] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:12,448 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:12,448 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:12,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685382727] [2024-10-13 17:46:12,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:12,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:12,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:12,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:12,565 INFO L87 Difference]: Start difference. First operand 15906 states and 21378 transitions. cyclomatic complexity: 5496 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:12,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:12,726 INFO L93 Difference]: Finished difference Result 30126 states and 40221 transitions. [2024-10-13 17:46:12,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30126 states and 40221 transitions. [2024-10-13 17:46:12,872 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 29704 [2024-10-13 17:46:12,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30126 states to 30126 states and 40221 transitions. [2024-10-13 17:46:12,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30126 [2024-10-13 17:46:12,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30126 [2024-10-13 17:46:12,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30126 states and 40221 transitions. [2024-10-13 17:46:12,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:12,998 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30126 states and 40221 transitions. [2024-10-13 17:46:13,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30126 states and 40221 transitions. [2024-10-13 17:46:13,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30126 to 28702. [2024-10-13 17:46:13,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28702 states, 28702 states have (on average 1.3372238868371542) internal successors, (38381), 28701 states have internal predecessors, (38381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:13,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28702 states to 28702 states and 38381 transitions. [2024-10-13 17:46:13,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28702 states and 38381 transitions. [2024-10-13 17:46:13,307 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:13,308 INFO L425 stractBuchiCegarLoop]: Abstraction has 28702 states and 38381 transitions. [2024-10-13 17:46:13,308 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-10-13 17:46:13,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28702 states and 38381 transitions. [2024-10-13 17:46:13,386 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28280 [2024-10-13 17:46:13,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:13,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:13,387 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:13,387 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:13,387 INFO L745 eck$LassoCheckResult]: Stem: 393836#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 393837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 394433#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 394434#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 394484#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 394462#L521-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 394463#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 393986#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 393987#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 394056#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 393896#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 393897#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 393865#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 393866#L754 assume !(0 == ~M_E~0); 394502#L754-2 assume !(0 == ~T1_E~0); 394387#L759-1 assume !(0 == ~T2_E~0); 394243#L764-1 assume !(0 == ~T3_E~0); 394197#L769-1 assume !(0 == ~T4_E~0); 394198#L774-1 assume !(0 == ~T5_E~0); 394244#L779-1 assume !(0 == ~T6_E~0); 394395#L784-1 assume !(0 == ~T7_E~0); 394194#L789-1 assume !(0 == ~E_1~0); 394195#L794-1 assume !(0 == ~E_2~0); 394294#L799-1 assume !(0 == ~E_3~0); 394205#L804-1 assume !(0 == ~E_4~0); 394206#L809-1 assume !(0 == ~E_5~0); 394238#L814-1 assume !(0 == ~E_6~0); 393641#L819-1 assume !(0 == ~E_7~0); 393642#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 393894#L361 assume !(1 == ~m_pc~0); 393895#L361-2 is_master_triggered_~__retres1~0#1 := 0; 394429#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 394374#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 394375#L930 assume !(0 != activate_threads_~tmp~1#1); 394102#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394103#L380 assume !(1 == ~t1_pc~0); 397595#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 397594#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 397593#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 397592#L938 assume !(0 != activate_threads_~tmp___0~0#1); 397590#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 397589#L399 assume !(1 == ~t2_pc~0); 397588#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 397587#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 397586#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 397585#L946 assume !(0 != activate_threads_~tmp___1~0#1); 397584#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 397583#L418 assume !(1 == ~t3_pc~0); 397581#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 397580#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 397579#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 397578#L954 assume !(0 != activate_threads_~tmp___2~0#1); 397577#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 397576#L437 assume !(1 == ~t4_pc~0); 397575#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 397574#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 397573#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 397572#L962 assume !(0 != activate_threads_~tmp___3~0#1); 397571#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 397570#L456 assume !(1 == ~t5_pc~0); 397568#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 397567#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 397566#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 397565#L970 assume !(0 != activate_threads_~tmp___4~0#1); 397564#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 397563#L475 assume !(1 == ~t6_pc~0); 397562#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 397561#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 397560#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 397559#L978 assume !(0 != activate_threads_~tmp___5~0#1); 397558#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 397557#L494 assume !(1 == ~t7_pc~0); 397555#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 397554#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 397553#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 397552#L986 assume !(0 != activate_threads_~tmp___6~0#1); 397551#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 397550#L837 assume !(1 == ~M_E~0); 397549#L837-2 assume !(1 == ~T1_E~0); 397548#L842-1 assume !(1 == ~T2_E~0); 397547#L847-1 assume !(1 == ~T3_E~0); 397546#L852-1 assume !(1 == ~T4_E~0); 397545#L857-1 assume !(1 == ~T5_E~0); 397544#L862-1 assume !(1 == ~T6_E~0); 397543#L867-1 assume !(1 == ~T7_E~0); 397542#L872-1 assume !(1 == ~E_1~0); 397541#L877-1 assume !(1 == ~E_2~0); 397540#L882-1 assume !(1 == ~E_3~0); 397539#L887-1 assume !(1 == ~E_4~0); 397538#L892-1 assume !(1 == ~E_5~0); 397537#L897-1 assume !(1 == ~E_6~0); 397536#L902-1 assume !(1 == ~E_7~0); 397535#L907-1 assume { :end_inline_reset_delta_events } true; 397534#L1148-2 assume !false; 397406#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 397403#L729-1 [2024-10-13 17:46:13,388 INFO L747 eck$LassoCheckResult]: Loop: 397403#L729-1 assume !false; 397402#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 397400#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 397396#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 397394#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 397392#L626 assume 0 != eval_~tmp~0#1; 397389#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 397386#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 397387#L634-2 havoc eval_~tmp_ndt_1~0#1; 397438#L631-1 assume !(0 == ~t1_st~0); 397433#L645-1 assume !(0 == ~t2_st~0); 397430#L659-1 assume !(0 == ~t3_st~0); 397418#L673-1 assume !(0 == ~t4_st~0); 397416#L687-1 assume !(0 == ~t5_st~0); 397411#L701-1 assume !(0 == ~t6_st~0); 397408#L715-1 assume !(0 == ~t7_st~0); 397403#L729-1 [2024-10-13 17:46:13,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:13,389 INFO L85 PathProgramCache]: Analyzing trace with hash -439660602, now seen corresponding path program 1 times [2024-10-13 17:46:13,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:13,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429913444] [2024-10-13 17:46:13,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:13,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:13,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:13,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:13,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:13,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429913444] [2024-10-13 17:46:13,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [429913444] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:13,419 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:13,419 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:13,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512599999] [2024-10-13 17:46:13,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:13,420 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:13,420 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:13,420 INFO L85 PathProgramCache]: Analyzing trace with hash -1739844173, now seen corresponding path program 2 times [2024-10-13 17:46:13,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:13,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561397853] [2024-10-13 17:46:13,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:13,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:13,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:13,425 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:13,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:13,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:13,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:13,513 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:13,513 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:13,514 INFO L87 Difference]: Start difference. First operand 28702 states and 38381 transitions. cyclomatic complexity: 9703 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:13,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:13,613 INFO L93 Difference]: Finished difference Result 28606 states and 38253 transitions. [2024-10-13 17:46:13,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28606 states and 38253 transitions. [2024-10-13 17:46:13,744 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28280 [2024-10-13 17:46:13,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28606 states to 28606 states and 38253 transitions. [2024-10-13 17:46:13,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28606 [2024-10-13 17:46:13,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28606 [2024-10-13 17:46:13,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28606 states and 38253 transitions. [2024-10-13 17:46:13,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:13,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28606 states and 38253 transitions. [2024-10-13 17:46:13,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28606 states and 38253 transitions. [2024-10-13 17:46:14,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28606 to 28606. [2024-10-13 17:46:14,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28606 states, 28606 states have (on average 1.3372369432986086) internal successors, (38253), 28605 states have internal predecessors, (38253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:14,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28606 states to 28606 states and 38253 transitions. [2024-10-13 17:46:14,168 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28606 states and 38253 transitions. [2024-10-13 17:46:14,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:14,169 INFO L425 stractBuchiCegarLoop]: Abstraction has 28606 states and 38253 transitions. [2024-10-13 17:46:14,169 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-10-13 17:46:14,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28606 states and 38253 transitions. [2024-10-13 17:46:14,249 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28280 [2024-10-13 17:46:14,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:14,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:14,250 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:14,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:14,251 INFO L745 eck$LassoCheckResult]: Stem: 451147#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 451148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 451749#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 451750#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 451788#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 451774#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 451775#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 451300#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 451301#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 451374#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 451209#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 451210#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 451178#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 451179#L754 assume !(0 == ~M_E~0); 451811#L754-2 assume !(0 == ~T1_E~0); 451706#L759-1 assume !(0 == ~T2_E~0); 451555#L764-1 assume !(0 == ~T3_E~0); 451512#L769-1 assume !(0 == ~T4_E~0); 451513#L774-1 assume !(0 == ~T5_E~0); 451556#L779-1 assume !(0 == ~T6_E~0); 451716#L784-1 assume !(0 == ~T7_E~0); 451509#L789-1 assume !(0 == ~E_1~0); 451510#L794-1 assume !(0 == ~E_2~0); 451608#L799-1 assume !(0 == ~E_3~0); 451520#L804-1 assume !(0 == ~E_4~0); 451521#L809-1 assume !(0 == ~E_5~0); 451549#L814-1 assume !(0 == ~E_6~0); 450955#L819-1 assume !(0 == ~E_7~0); 450956#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 451207#L361 assume !(1 == ~m_pc~0); 451208#L361-2 is_master_triggered_~__retres1~0#1 := 0; 451743#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 451690#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 451691#L930 assume !(0 != activate_threads_~tmp~1#1); 451417#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 451201#L380 assume !(1 == ~t1_pc~0); 451202#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 451785#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 451786#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 451838#L938 assume !(0 != activate_threads_~tmp___0~0#1); 451641#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 451617#L399 assume !(1 == ~t2_pc~0); 451118#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 451119#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 451280#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 451273#L946 assume !(0 != activate_threads_~tmp___1~0#1); 451274#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 450963#L418 assume !(1 == ~t3_pc~0); 450943#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 450944#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 450953#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 450954#L954 assume !(0 != activate_threads_~tmp___2~0#1); 451537#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 451538#L437 assume !(1 == ~t4_pc~0); 451776#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 451683#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 451034#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 451035#L962 assume !(0 != activate_threads_~tmp___3~0#1); 451330#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 451665#L456 assume !(1 == ~t5_pc~0); 451133#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 451132#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 451695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 451592#L970 assume !(0 != activate_threads_~tmp___4~0#1); 451593#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 451029#L475 assume !(1 == ~t6_pc~0); 451030#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 451069#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 451070#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 451266#L978 assume !(0 != activate_threads_~tmp___5~0#1); 451526#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 451527#L494 assume !(1 == ~t7_pc~0); 451250#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 451251#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 451481#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 451557#L986 assume !(0 != activate_threads_~tmp___6~0#1); 451558#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 451802#L837 assume !(1 == ~M_E~0); 451748#L837-2 assume !(1 == ~T1_E~0); 451613#L842-1 assume !(1 == ~T2_E~0); 451338#L847-1 assume !(1 == ~T3_E~0); 451339#L852-1 assume !(1 == ~T4_E~0); 451407#L857-1 assume !(1 == ~T5_E~0); 451286#L862-1 assume !(1 == ~T6_E~0); 451287#L867-1 assume !(1 == ~T7_E~0); 451296#L872-1 assume !(1 == ~E_1~0); 451373#L877-1 assume !(1 == ~E_2~0); 451572#L882-1 assume !(1 == ~E_3~0); 451754#L887-1 assume !(1 == ~E_4~0); 451634#L892-1 assume !(1 == ~E_5~0); 451635#L897-1 assume !(1 == ~E_6~0); 451312#L902-1 assume !(1 == ~E_7~0); 451313#L907-1 assume { :end_inline_reset_delta_events } true; 451664#L1148-2 assume !false; 455020#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 455019#L729-1 [2024-10-13 17:46:14,251 INFO L747 eck$LassoCheckResult]: Loop: 455019#L729-1 assume !false; 455016#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 455013#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 455002#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 454994#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 454987#L626 assume 0 != eval_~tmp~0#1; 454977#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 454969#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 454970#L634-2 havoc eval_~tmp_ndt_1~0#1; 455728#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 455719#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 455711#L648-2 havoc eval_~tmp_ndt_2~0#1; 455148#L645-1 assume !(0 == ~t2_st~0); 455144#L659-1 assume !(0 == ~t3_st~0); 455137#L673-1 assume !(0 == ~t4_st~0); 455135#L687-1 assume !(0 == ~t5_st~0); 455131#L701-1 assume !(0 == ~t6_st~0); 455022#L715-1 assume !(0 == ~t7_st~0); 455019#L729-1 [2024-10-13 17:46:14,252 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:14,252 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 2 times [2024-10-13 17:46:14,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:14,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322078995] [2024-10-13 17:46:14,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:14,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:14,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:14,269 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:14,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:14,289 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:14,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:14,290 INFO L85 PathProgramCache]: Analyzing trace with hash 230138997, now seen corresponding path program 1 times [2024-10-13 17:46:14,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:14,291 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044952760] [2024-10-13 17:46:14,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:14,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:14,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:14,295 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:14,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:14,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:14,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:14,299 INFO L85 PathProgramCache]: Analyzing trace with hash -2069460420, now seen corresponding path program 1 times [2024-10-13 17:46:14,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:14,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147565382] [2024-10-13 17:46:14,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:14,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:14,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:14,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:14,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:14,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147565382] [2024-10-13 17:46:14,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147565382] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:14,350 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:14,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:14,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39749605] [2024-10-13 17:46:14,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:14,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:14,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:14,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:14,449 INFO L87 Difference]: Start difference. First operand 28606 states and 38253 transitions. cyclomatic complexity: 9671 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:14,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:14,612 INFO L93 Difference]: Finished difference Result 38374 states and 51041 transitions. [2024-10-13 17:46:14,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38374 states and 51041 transitions. [2024-10-13 17:46:14,774 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 37968 [2024-10-13 17:46:14,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38374 states to 38374 states and 51041 transitions. [2024-10-13 17:46:14,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38374 [2024-10-13 17:46:14,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38374 [2024-10-13 17:46:14,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38374 states and 51041 transitions. [2024-10-13 17:46:14,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:14,925 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38374 states and 51041 transitions. [2024-10-13 17:46:14,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38374 states and 51041 transitions. [2024-10-13 17:46:15,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38374 to 37158. [2024-10-13 17:46:15,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37158 states, 37158 states have (on average 1.3309919801926906) internal successors, (49457), 37157 states have internal predecessors, (49457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:15,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37158 states to 37158 states and 49457 transitions. [2024-10-13 17:46:15,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37158 states and 49457 transitions. [2024-10-13 17:46:15,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:15,311 INFO L425 stractBuchiCegarLoop]: Abstraction has 37158 states and 49457 transitions. [2024-10-13 17:46:15,311 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-10-13 17:46:15,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37158 states and 49457 transitions. [2024-10-13 17:46:15,415 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36752 [2024-10-13 17:46:15,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:15,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:15,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:15,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:15,417 INFO L745 eck$LassoCheckResult]: Stem: 518139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 518140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 518756#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 518757#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 518819#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 518792#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 518793#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 518294#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 518295#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 518367#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 518201#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 518202#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 518171#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 518172#L754 assume !(0 == ~M_E~0); 518837#L754-2 assume !(0 == ~T1_E~0); 518701#L759-1 assume !(0 == ~T2_E~0); 518554#L764-1 assume !(0 == ~T3_E~0); 518511#L769-1 assume !(0 == ~T4_E~0); 518512#L774-1 assume !(0 == ~T5_E~0); 518555#L779-1 assume !(0 == ~T6_E~0); 518712#L784-1 assume !(0 == ~T7_E~0); 518508#L789-1 assume !(0 == ~E_1~0); 518509#L794-1 assume !(0 == ~E_2~0); 518607#L799-1 assume !(0 == ~E_3~0); 518520#L804-1 assume !(0 == ~E_4~0); 518521#L809-1 assume !(0 == ~E_5~0); 518549#L814-1 assume !(0 == ~E_6~0); 517943#L819-1 assume !(0 == ~E_7~0); 517944#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 518199#L361 assume !(1 == ~m_pc~0); 518200#L361-2 is_master_triggered_~__retres1~0#1 := 0; 518747#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518686#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 518687#L930 assume !(0 != activate_threads_~tmp~1#1); 518414#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 518193#L380 assume !(1 == ~t1_pc~0); 518194#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 518814#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 518815#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 518871#L938 assume !(0 != activate_threads_~tmp___0~0#1); 518641#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 518618#L399 assume !(1 == ~t2_pc~0); 518110#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 518111#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 518273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 518266#L946 assume !(0 != activate_threads_~tmp___1~0#1); 518267#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 517951#L418 assume !(1 == ~t3_pc~0); 517931#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 517932#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 517941#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 517942#L954 assume !(0 != activate_threads_~tmp___2~0#1); 518536#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 518537#L437 assume !(1 == ~t4_pc~0); 518794#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 518681#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 518023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 518024#L962 assume !(0 != activate_threads_~tmp___3~0#1); 518323#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 518661#L456 assume !(1 == ~t5_pc~0); 518125#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 518124#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 518692#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 518590#L970 assume !(0 != activate_threads_~tmp___4~0#1); 518591#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 518018#L475 assume !(1 == ~t6_pc~0); 518019#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 518060#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 518061#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 518259#L978 assume !(0 != activate_threads_~tmp___5~0#1); 518525#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 518526#L494 assume !(1 == ~t7_pc~0); 518243#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 518244#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 518477#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 518556#L986 assume !(0 != activate_threads_~tmp___6~0#1); 518557#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 518831#L837 assume !(1 == ~M_E~0); 518755#L837-2 assume !(1 == ~T1_E~0); 518613#L842-1 assume !(1 == ~T2_E~0); 518332#L847-1 assume !(1 == ~T3_E~0); 518333#L852-1 assume !(1 == ~T4_E~0); 518403#L857-1 assume !(1 == ~T5_E~0); 518279#L862-1 assume !(1 == ~T6_E~0); 518280#L867-1 assume !(1 == ~T7_E~0); 518290#L872-1 assume !(1 == ~E_1~0); 518366#L877-1 assume !(1 == ~E_2~0); 518572#L882-1 assume !(1 == ~E_3~0); 518764#L887-1 assume !(1 == ~E_4~0); 518633#L892-1 assume !(1 == ~E_5~0); 518634#L897-1 assume !(1 == ~E_6~0); 518305#L902-1 assume !(1 == ~E_7~0); 518306#L907-1 assume { :end_inline_reset_delta_events } true; 518660#L1148-2 assume !false; 532699#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 532698#L729-1 [2024-10-13 17:46:15,417 INFO L747 eck$LassoCheckResult]: Loop: 532698#L729-1 assume !false; 532696#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 532692#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 532690#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 532688#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 532686#L626 assume 0 != eval_~tmp~0#1; 532684#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 532681#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 532682#L634-2 havoc eval_~tmp_ndt_1~0#1; 532735#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 532733#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 532730#L648-2 havoc eval_~tmp_ndt_2~0#1; 532729#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 532727#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 532725#L662-2 havoc eval_~tmp_ndt_3~0#1; 532722#L659-1 assume !(0 == ~t3_st~0); 532712#L673-1 assume !(0 == ~t4_st~0); 532709#L687-1 assume !(0 == ~t5_st~0); 532705#L701-1 assume !(0 == ~t6_st~0); 532701#L715-1 assume !(0 == ~t7_st~0); 532698#L729-1 [2024-10-13 17:46:15,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:15,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 3 times [2024-10-13 17:46:15,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:15,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235348811] [2024-10-13 17:46:15,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:15,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:15,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:15,430 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:15,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:15,452 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:15,453 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:15,453 INFO L85 PathProgramCache]: Analyzing trace with hash -2126794573, now seen corresponding path program 1 times [2024-10-13 17:46:15,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:15,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215123188] [2024-10-13 17:46:15,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:15,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:15,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:15,457 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:15,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:15,462 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:15,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:15,463 INFO L85 PathProgramCache]: Analyzing trace with hash -133676870, now seen corresponding path program 1 times [2024-10-13 17:46:15,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:15,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382090179] [2024-10-13 17:46:15,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:15,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:15,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:15,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:15,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:15,507 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382090179] [2024-10-13 17:46:15,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382090179] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:15,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:15,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:15,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610995692] [2024-10-13 17:46:15,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:15,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:15,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:15,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:15,600 INFO L87 Difference]: Start difference. First operand 37158 states and 49457 transitions. cyclomatic complexity: 12323 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:15,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:15,849 INFO L93 Difference]: Finished difference Result 69846 states and 92717 transitions. [2024-10-13 17:46:15,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69846 states and 92717 transitions. [2024-10-13 17:46:16,125 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 69136 [2024-10-13 17:46:16,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69846 states to 69846 states and 92717 transitions. [2024-10-13 17:46:16,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69846 [2024-10-13 17:46:16,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69846 [2024-10-13 17:46:16,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69846 states and 92717 transitions. [2024-10-13 17:46:16,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:16,401 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69846 states and 92717 transitions. [2024-10-13 17:46:16,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69846 states and 92717 transitions. [2024-10-13 17:46:16,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69846 to 66870. [2024-10-13 17:46:17,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66870 states, 66870 states have (on average 1.3298190518917303) internal successors, (88925), 66869 states have internal predecessors, (88925), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:17,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66870 states to 66870 states and 88925 transitions. [2024-10-13 17:46:17,137 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66870 states and 88925 transitions. [2024-10-13 17:46:17,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:17,138 INFO L425 stractBuchiCegarLoop]: Abstraction has 66870 states and 88925 transitions. [2024-10-13 17:46:17,139 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-10-13 17:46:17,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66870 states and 88925 transitions. [2024-10-13 17:46:17,336 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 66160 [2024-10-13 17:46:17,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:17,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:17,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:17,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:17,338 INFO L745 eck$LassoCheckResult]: Stem: 625158#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 625159#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 625779#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 625780#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 625837#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 625810#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 625811#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 625312#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 625313#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 625387#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 625220#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 625221#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 625189#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 625190#L754 assume !(0 == ~M_E~0); 625854#L754-2 assume !(0 == ~T1_E~0); 625729#L759-1 assume !(0 == ~T2_E~0); 625583#L764-1 assume !(0 == ~T3_E~0); 625538#L769-1 assume !(0 == ~T4_E~0); 625539#L774-1 assume !(0 == ~T5_E~0); 625584#L779-1 assume !(0 == ~T6_E~0); 625738#L784-1 assume !(0 == ~T7_E~0); 625534#L789-1 assume !(0 == ~E_1~0); 625535#L794-1 assume !(0 == ~E_2~0); 625636#L799-1 assume !(0 == ~E_3~0); 625546#L804-1 assume !(0 == ~E_4~0); 625547#L809-1 assume !(0 == ~E_5~0); 625578#L814-1 assume !(0 == ~E_6~0); 624956#L819-1 assume !(0 == ~E_7~0); 624957#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 625218#L361 assume !(1 == ~m_pc~0); 625219#L361-2 is_master_triggered_~__retres1~0#1 := 0; 625774#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 625714#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 625715#L930 assume !(0 != activate_threads_~tmp~1#1); 625435#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 625212#L380 assume !(1 == ~t1_pc~0); 625213#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 625833#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 625834#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 625892#L938 assume !(0 != activate_threads_~tmp___0~0#1); 625668#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 625645#L399 assume !(1 == ~t2_pc~0); 625125#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 625126#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 625293#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 625286#L946 assume !(0 != activate_threads_~tmp___1~0#1); 625287#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 624964#L418 assume !(1 == ~t3_pc~0); 624943#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 624944#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 624954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 624955#L954 assume !(0 != activate_threads_~tmp___2~0#1); 625565#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 625566#L437 assume !(1 == ~t4_pc~0); 625812#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 625709#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 625036#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 625037#L962 assume !(0 != activate_threads_~tmp___3~0#1); 625341#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 625688#L456 assume !(1 == ~t5_pc~0); 625141#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 625140#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 625719#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 625618#L970 assume !(0 != activate_threads_~tmp___4~0#1); 625619#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 625031#L475 assume !(1 == ~t6_pc~0); 625032#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 625075#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 625076#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 625279#L978 assume !(0 != activate_threads_~tmp___5~0#1); 625553#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 625554#L494 assume !(1 == ~t7_pc~0); 625263#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 625264#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 625500#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 625585#L986 assume !(0 != activate_threads_~tmp___6~0#1); 625586#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 625847#L837 assume !(1 == ~M_E~0); 625778#L837-2 assume !(1 == ~T1_E~0); 625641#L842-1 assume !(1 == ~T2_E~0); 625350#L847-1 assume !(1 == ~T3_E~0); 625351#L852-1 assume !(1 == ~T4_E~0); 625424#L857-1 assume !(1 == ~T5_E~0); 625299#L862-1 assume !(1 == ~T6_E~0); 625300#L867-1 assume !(1 == ~T7_E~0); 625307#L872-1 assume !(1 == ~E_1~0); 625386#L877-1 assume !(1 == ~E_2~0); 625601#L882-1 assume !(1 == ~E_3~0); 625787#L887-1 assume !(1 == ~E_4~0); 625661#L892-1 assume !(1 == ~E_5~0); 625662#L897-1 assume !(1 == ~E_6~0); 625323#L902-1 assume !(1 == ~E_7~0); 625324#L907-1 assume { :end_inline_reset_delta_events } true; 625687#L1148-2 assume !false; 630057#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 630055#L729-1 [2024-10-13 17:46:17,338 INFO L747 eck$LassoCheckResult]: Loop: 630055#L729-1 assume !false; 630053#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 630049#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 630048#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 630044#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 630040#L626 assume 0 != eval_~tmp~0#1; 630035#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 630032#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 630030#L634-2 havoc eval_~tmp_ndt_1~0#1; 630027#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 629995#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 630024#L648-2 havoc eval_~tmp_ndt_2~0#1; 630477#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 630474#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 630472#L662-2 havoc eval_~tmp_ndt_3~0#1; 630468#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 630465#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 630463#L676-2 havoc eval_~tmp_ndt_4~0#1; 630459#L673-1 assume !(0 == ~t4_st~0); 630460#L687-1 assume !(0 == ~t5_st~0); 633696#L701-1 assume !(0 == ~t6_st~0); 630059#L715-1 assume !(0 == ~t7_st~0); 630055#L729-1 [2024-10-13 17:46:17,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:17,338 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 4 times [2024-10-13 17:46:17,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:17,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352949731] [2024-10-13 17:46:17,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:17,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:17,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:17,351 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:17,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:17,376 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:17,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:17,377 INFO L85 PathProgramCache]: Analyzing trace with hash 833736693, now seen corresponding path program 1 times [2024-10-13 17:46:17,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:17,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791940953] [2024-10-13 17:46:17,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:17,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:17,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:17,385 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:17,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:17,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:17,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:17,389 INFO L85 PathProgramCache]: Analyzing trace with hash 664435260, now seen corresponding path program 1 times [2024-10-13 17:46:17,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:17,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608285561] [2024-10-13 17:46:17,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:17,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:17,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:17,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:17,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:17,437 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1608285561] [2024-10-13 17:46:17,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1608285561] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:17,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:17,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:17,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190857081] [2024-10-13 17:46:17,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:17,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:17,542 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:17,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:17,542 INFO L87 Difference]: Start difference. First operand 66870 states and 88925 transitions. cyclomatic complexity: 22079 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:17,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:17,846 INFO L93 Difference]: Finished difference Result 91642 states and 121597 transitions. [2024-10-13 17:46:17,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91642 states and 121597 transitions. [2024-10-13 17:46:18,648 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 90724 [2024-10-13 17:46:18,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91642 states to 91642 states and 121597 transitions. [2024-10-13 17:46:18,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91642 [2024-10-13 17:46:18,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91642 [2024-10-13 17:46:18,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91642 states and 121597 transitions. [2024-10-13 17:46:18,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:18,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91642 states and 121597 transitions. [2024-10-13 17:46:18,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91642 states and 121597 transitions. [2024-10-13 17:46:19,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91642 to 89290. [2024-10-13 17:46:19,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89290 states, 89290 states have (on average 1.3284914324112442) internal successors, (118621), 89289 states have internal predecessors, (118621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:20,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89290 states to 89290 states and 118621 transitions. [2024-10-13 17:46:20,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 89290 states and 118621 transitions. [2024-10-13 17:46:20,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:20,403 INFO L425 stractBuchiCegarLoop]: Abstraction has 89290 states and 118621 transitions. [2024-10-13 17:46:20,403 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-10-13 17:46:20,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89290 states and 118621 transitions. [2024-10-13 17:46:20,626 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 88372 [2024-10-13 17:46:20,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:20,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:20,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:20,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:20,627 INFO L745 eck$LassoCheckResult]: Stem: 783675#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 783676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 784313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 784314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 784373#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 784344#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 784345#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 783832#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 783833#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 783906#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 783740#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 783741#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 783708#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 783709#L754 assume !(0 == ~M_E~0); 784398#L754-2 assume !(0 == ~T1_E~0); 784266#L759-1 assume !(0 == ~T2_E~0); 784103#L764-1 assume !(0 == ~T3_E~0); 784057#L769-1 assume !(0 == ~T4_E~0); 784058#L774-1 assume !(0 == ~T5_E~0); 784104#L779-1 assume !(0 == ~T6_E~0); 784277#L784-1 assume !(0 == ~T7_E~0); 784054#L789-1 assume !(0 == ~E_1~0); 784055#L794-1 assume !(0 == ~E_2~0); 784158#L799-1 assume !(0 == ~E_3~0); 784067#L804-1 assume !(0 == ~E_4~0); 784068#L809-1 assume !(0 == ~E_5~0); 784098#L814-1 assume !(0 == ~E_6~0); 783475#L819-1 assume !(0 == ~E_7~0); 783476#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 783738#L361 assume !(1 == ~m_pc~0); 783739#L361-2 is_master_triggered_~__retres1~0#1 := 0; 784307#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 784250#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 784251#L930 assume !(0 != activate_threads_~tmp~1#1); 783956#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783731#L380 assume !(1 == ~t1_pc~0); 783732#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 784434#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 783496#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 783497#L938 assume !(0 != activate_threads_~tmp___0~0#1); 784199#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 784170#L399 assume !(1 == ~t2_pc~0); 783643#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 783644#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 783813#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 783807#L946 assume !(0 != activate_threads_~tmp___1~0#1); 783808#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 783483#L418 assume !(1 == ~t3_pc~0); 783463#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 783464#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 783473#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 783474#L954 assume !(0 != activate_threads_~tmp___2~0#1); 784085#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 784086#L437 assume !(1 == ~t4_pc~0); 784346#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 784245#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 783555#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 783556#L962 assume !(0 != activate_threads_~tmp___3~0#1); 783862#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 784223#L456 assume !(1 == ~t5_pc~0); 783659#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 783658#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 784255#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 784140#L970 assume !(0 != activate_threads_~tmp___4~0#1); 784141#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 783550#L475 assume !(1 == ~t6_pc~0); 783551#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 783593#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 783594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 783800#L978 assume !(0 != activate_threads_~tmp___5~0#1); 784073#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 784074#L494 assume !(1 == ~t7_pc~0); 783784#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 783785#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 784022#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 784105#L986 assume !(0 != activate_threads_~tmp___6~0#1); 784106#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 784384#L837 assume !(1 == ~M_E~0); 784312#L837-2 assume !(1 == ~T1_E~0); 784166#L842-1 assume !(1 == ~T2_E~0); 783870#L847-1 assume !(1 == ~T3_E~0); 783871#L852-1 assume !(1 == ~T4_E~0); 783944#L857-1 assume !(1 == ~T5_E~0); 783819#L862-1 assume !(1 == ~T6_E~0); 783820#L867-1 assume !(1 == ~T7_E~0); 783828#L872-1 assume !(1 == ~E_1~0); 783905#L877-1 assume !(1 == ~E_2~0); 784120#L882-1 assume !(1 == ~E_3~0); 784319#L887-1 assume !(1 == ~E_4~0); 784188#L892-1 assume !(1 == ~E_5~0); 784189#L897-1 assume !(1 == ~E_6~0); 783844#L902-1 assume !(1 == ~E_7~0); 783845#L907-1 assume { :end_inline_reset_delta_events } true; 784222#L1148-2 assume !false; 807423#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 807421#L729-1 [2024-10-13 17:46:20,628 INFO L747 eck$LassoCheckResult]: Loop: 807421#L729-1 assume !false; 807419#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 807415#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 807413#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 807410#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 807406#L626 assume 0 != eval_~tmp~0#1; 807403#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 807400#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 807397#L634-2 havoc eval_~tmp_ndt_1~0#1; 807395#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 807349#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 807393#L648-2 havoc eval_~tmp_ndt_2~0#1; 822663#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 822656#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 822647#L662-2 havoc eval_~tmp_ndt_3~0#1; 792553#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 792550#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 792548#L676-2 havoc eval_~tmp_ndt_4~0#1; 792546#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 792542#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 792544#L690-2 havoc eval_~tmp_ndt_5~0#1; 804412#L687-1 assume !(0 == ~t5_st~0); 804407#L701-1 assume !(0 == ~t6_st~0); 804408#L715-1 assume !(0 == ~t7_st~0); 807421#L729-1 [2024-10-13 17:46:20,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:20,628 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 5 times [2024-10-13 17:46:20,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:20,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809809771] [2024-10-13 17:46:20,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:20,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:20,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:20,638 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:20,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:20,654 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:20,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:20,655 INFO L85 PathProgramCache]: Analyzing trace with hash 10984371, now seen corresponding path program 1 times [2024-10-13 17:46:20,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:20,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269708408] [2024-10-13 17:46:20,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:20,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:20,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:20,659 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:20,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:20,661 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:20,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:20,662 INFO L85 PathProgramCache]: Analyzing trace with hash 521064506, now seen corresponding path program 1 times [2024-10-13 17:46:20,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:20,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563492687] [2024-10-13 17:46:20,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:20,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:20,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:20,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:20,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:20,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563492687] [2024-10-13 17:46:20,694 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563492687] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:20,694 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:20,694 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:20,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9531117] [2024-10-13 17:46:20,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:20,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:20,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:20,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:20,790 INFO L87 Difference]: Start difference. First operand 89290 states and 118621 transitions. cyclomatic complexity: 29355 Second operand has 3 states, 3 states have (on average 39.666666666666664) internal successors, (119), 3 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:21,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:21,631 INFO L93 Difference]: Finished difference Result 162814 states and 215493 transitions. [2024-10-13 17:46:21,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162814 states and 215493 transitions. [2024-10-13 17:46:22,274 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 161080 [2024-10-13 17:46:22,625 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162814 states to 162814 states and 215493 transitions. [2024-10-13 17:46:22,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 162814 [2024-10-13 17:46:22,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 162814 [2024-10-13 17:46:22,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162814 states and 215493 transitions. [2024-10-13 17:46:22,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:22,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 162814 states and 215493 transitions. [2024-10-13 17:46:22,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162814 states and 215493 transitions. [2024-10-13 17:46:24,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162814 to 157774. [2024-10-13 17:46:24,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157774 states, 157774 states have (on average 1.3265873971630306) internal successors, (209301), 157773 states have internal predecessors, (209301), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:25,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157774 states to 157774 states and 209301 transitions. [2024-10-13 17:46:25,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 157774 states and 209301 transitions. [2024-10-13 17:46:25,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:25,044 INFO L425 stractBuchiCegarLoop]: Abstraction has 157774 states and 209301 transitions. [2024-10-13 17:46:25,044 INFO L332 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-10-13 17:46:25,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 157774 states and 209301 transitions. [2024-10-13 17:46:25,452 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 156040 [2024-10-13 17:46:25,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:25,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:25,453 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:25,453 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:25,454 INFO L745 eck$LassoCheckResult]: Stem: 1035785#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1035786#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1036447#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1036448#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1036512#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1036484#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1036485#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1035944#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1035945#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1036019#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1035849#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1035850#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1035818#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1035819#L754 assume !(0 == ~M_E~0); 1036535#L754-2 assume !(0 == ~T1_E~0); 1036390#L759-1 assume !(0 == ~T2_E~0); 1036221#L764-1 assume !(0 == ~T3_E~0); 1036173#L769-1 assume !(0 == ~T4_E~0); 1036174#L774-1 assume !(0 == ~T5_E~0); 1036222#L779-1 assume !(0 == ~T6_E~0); 1036401#L784-1 assume !(0 == ~T7_E~0); 1036170#L789-1 assume !(0 == ~E_1~0); 1036171#L794-1 assume !(0 == ~E_2~0); 1036281#L799-1 assume !(0 == ~E_3~0); 1036183#L804-1 assume !(0 == ~E_4~0); 1036184#L809-1 assume !(0 == ~E_5~0); 1036216#L814-1 assume !(0 == ~E_6~0); 1035588#L819-1 assume !(0 == ~E_7~0); 1035589#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1035847#L361 assume !(1 == ~m_pc~0); 1035848#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1036441#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1036376#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1036377#L930 assume !(0 != activate_threads_~tmp~1#1); 1036071#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1035841#L380 assume !(1 == ~t1_pc~0); 1035842#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1036577#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1035609#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1035610#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1036320#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1036292#L399 assume !(1 == ~t2_pc~0); 1035754#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1035755#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1035922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1035915#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1035916#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1035596#L418 assume !(1 == ~t3_pc~0); 1035575#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1035576#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1035586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1035587#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1036201#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1036202#L437 assume !(1 == ~t4_pc~0); 1036486#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1036371#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1035667#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1035668#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1035974#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1036346#L456 assume !(1 == ~t5_pc~0); 1035770#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1035769#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1036380#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1036262#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1036263#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1035662#L475 assume !(1 == ~t6_pc~0); 1035663#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1035704#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1035705#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1035908#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1036190#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1036191#L494 assume !(1 == ~t7_pc~0); 1035892#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1035893#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1036139#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1036223#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1036224#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1036523#L837 assume !(1 == ~M_E~0); 1036446#L837-2 assume !(1 == ~T1_E~0); 1036287#L842-1 assume !(1 == ~T2_E~0); 1035983#L847-1 assume !(1 == ~T3_E~0); 1035984#L852-1 assume !(1 == ~T4_E~0); 1036060#L857-1 assume !(1 == ~T5_E~0); 1035929#L862-1 assume !(1 == ~T6_E~0); 1035930#L867-1 assume !(1 == ~T7_E~0); 1035939#L872-1 assume !(1 == ~E_1~0); 1036018#L877-1 assume !(1 == ~E_2~0); 1036240#L882-1 assume !(1 == ~E_3~0); 1036460#L887-1 assume !(1 == ~E_4~0); 1036310#L892-1 assume !(1 == ~E_5~0); 1036311#L897-1 assume !(1 == ~E_6~0); 1035957#L902-1 assume !(1 == ~E_7~0); 1035958#L907-1 assume { :end_inline_reset_delta_events } true; 1036345#L1148-2 assume !false; 1066583#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1066581#L729-1 [2024-10-13 17:46:25,454 INFO L747 eck$LassoCheckResult]: Loop: 1066581#L729-1 assume !false; 1066579#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1066576#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1066574#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1066573#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1066572#L626 assume 0 != eval_~tmp~0#1; 1066569#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1066566#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1066302#L634-2 havoc eval_~tmp_ndt_1~0#1; 1066299#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1066296#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1066294#L648-2 havoc eval_~tmp_ndt_2~0#1; 1066292#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1066289#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1066287#L662-2 havoc eval_~tmp_ndt_3~0#1; 1066285#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1066242#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1066281#L676-2 havoc eval_~tmp_ndt_4~0#1; 1066605#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1066602#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1066600#L690-2 havoc eval_~tmp_ndt_5~0#1; 1066598#L687-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1066595#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 1066593#L704-2 havoc eval_~tmp_ndt_6~0#1; 1066589#L701-1 assume !(0 == ~t6_st~0); 1066585#L715-1 assume !(0 == ~t7_st~0); 1066581#L729-1 [2024-10-13 17:46:25,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:25,455 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 6 times [2024-10-13 17:46:25,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:25,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651827613] [2024-10-13 17:46:25,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:25,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:25,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:25,473 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:25,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:25,492 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:25,492 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:25,493 INFO L85 PathProgramCache]: Analyzing trace with hash 1752066933, now seen corresponding path program 1 times [2024-10-13 17:46:25,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:25,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133678320] [2024-10-13 17:46:25,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:25,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:25,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:25,497 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:25,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:25,500 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:25,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:25,500 INFO L85 PathProgramCache]: Analyzing trace with hash -1982162372, now seen corresponding path program 1 times [2024-10-13 17:46:25,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:25,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807005159] [2024-10-13 17:46:25,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:25,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:26,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:26,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:26,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:26,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807005159] [2024-10-13 17:46:26,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807005159] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:26,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:26,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:26,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [580696516] [2024-10-13 17:46:26,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:26,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:26,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:26,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:26,292 INFO L87 Difference]: Start difference. First operand 157774 states and 209301 transitions. cyclomatic complexity: 51551 Second operand has 3 states, 3 states have (on average 40.333333333333336) internal successors, (121), 3 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:27,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:27,013 INFO L93 Difference]: Finished difference Result 216142 states and 285669 transitions. [2024-10-13 17:46:27,013 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 216142 states and 285669 transitions. [2024-10-13 17:46:28,710 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 213880 [2024-10-13 17:46:29,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 216142 states to 216142 states and 285669 transitions. [2024-10-13 17:46:29,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 216142 [2024-10-13 17:46:29,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 216142 [2024-10-13 17:46:29,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 216142 states and 285669 transitions. [2024-10-13 17:46:29,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:29,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 216142 states and 285669 transitions. [2024-10-13 17:46:29,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216142 states and 285669 transitions. [2024-10-13 17:46:31,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216142 to 212974. [2024-10-13 17:46:31,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212974 states, 212974 states have (on average 1.3224008564425704) internal successors, (281637), 212973 states have internal predecessors, (281637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:32,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212974 states to 212974 states and 281637 transitions. [2024-10-13 17:46:32,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 212974 states and 281637 transitions. [2024-10-13 17:46:32,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:32,330 INFO L425 stractBuchiCegarLoop]: Abstraction has 212974 states and 281637 transitions. [2024-10-13 17:46:32,330 INFO L332 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-10-13 17:46:32,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212974 states and 281637 transitions. [2024-10-13 17:46:33,675 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 210712 [2024-10-13 17:46:33,675 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:33,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:33,678 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:33,678 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:33,679 INFO L745 eck$LassoCheckResult]: Stem: 1409707#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1409708#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1410351#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1410352#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1410416#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1410393#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1410394#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1409862#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1409863#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1409941#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1409770#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1409771#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1409739#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1409740#L754 assume !(0 == ~M_E~0); 1410446#L754-2 assume !(0 == ~T1_E~0); 1410305#L759-1 assume !(0 == ~T2_E~0); 1410146#L764-1 assume !(0 == ~T3_E~0); 1410090#L769-1 assume !(0 == ~T4_E~0); 1410091#L774-1 assume !(0 == ~T5_E~0); 1410147#L779-1 assume !(0 == ~T6_E~0); 1410313#L784-1 assume !(0 == ~T7_E~0); 1410087#L789-1 assume !(0 == ~E_1~0); 1410088#L794-1 assume !(0 == ~E_2~0); 1410198#L799-1 assume !(0 == ~E_3~0); 1410101#L804-1 assume !(0 == ~E_4~0); 1410102#L809-1 assume !(0 == ~E_5~0); 1410140#L814-1 assume !(0 == ~E_6~0); 1409511#L819-1 assume !(0 == ~E_7~0); 1409512#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1409768#L361 assume !(1 == ~m_pc~0); 1409769#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1410345#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1410290#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1410291#L930 assume !(0 != activate_threads_~tmp~1#1); 1409990#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1409762#L380 assume !(1 == ~t1_pc~0); 1409763#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1410492#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1409532#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1409533#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1410238#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1410210#L399 assume !(1 == ~t2_pc~0); 1409677#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1409678#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1409843#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1409836#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1409837#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1409519#L418 assume !(1 == ~t3_pc~0); 1409499#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1409500#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1409509#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1409510#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1410122#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1410123#L437 assume !(1 == ~t4_pc~0); 1410395#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1410285#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1409589#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1409590#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1409893#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1410261#L456 assume !(1 == ~t5_pc~0); 1409693#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1409692#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1410295#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1410182#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1410183#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1409584#L475 assume !(1 == ~t6_pc~0); 1409585#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1409628#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1409629#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1409829#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1410109#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1410110#L494 assume !(1 == ~t7_pc~0); 1409813#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1409814#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1410056#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1410148#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1410149#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1410432#L837 assume !(1 == ~M_E~0); 1410350#L837-2 assume !(1 == ~T1_E~0); 1410207#L842-1 assume !(1 == ~T2_E~0); 1409903#L847-1 assume !(1 == ~T3_E~0); 1409904#L852-1 assume !(1 == ~T4_E~0); 1409978#L857-1 assume !(1 == ~T5_E~0); 1409850#L862-1 assume !(1 == ~T6_E~0); 1409851#L867-1 assume !(1 == ~T7_E~0); 1409858#L872-1 assume !(1 == ~E_1~0); 1409940#L877-1 assume !(1 == ~E_2~0); 1410164#L882-1 assume !(1 == ~E_3~0); 1410361#L887-1 assume !(1 == ~E_4~0); 1410229#L892-1 assume !(1 == ~E_5~0); 1410230#L897-1 assume !(1 == ~E_6~0); 1409874#L902-1 assume !(1 == ~E_7~0); 1409875#L907-1 assume { :end_inline_reset_delta_events } true; 1410260#L1148-2 assume !false; 1459560#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1459558#L729-1 [2024-10-13 17:46:33,679 INFO L747 eck$LassoCheckResult]: Loop: 1459558#L729-1 assume !false; 1459556#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1459553#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1459551#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1459548#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1459546#L626 assume 0 != eval_~tmp~0#1; 1459543#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1459539#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1459537#L634-2 havoc eval_~tmp_ndt_1~0#1; 1423403#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1423400#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1423398#L648-2 havoc eval_~tmp_ndt_2~0#1; 1423396#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1423393#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1423391#L662-2 havoc eval_~tmp_ndt_3~0#1; 1423389#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1423362#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1423386#L676-2 havoc eval_~tmp_ndt_4~0#1; 1429405#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1429401#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1429350#L690-2 havoc eval_~tmp_ndt_5~0#1; 1429346#L687-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1423158#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 1429332#L704-2 havoc eval_~tmp_ndt_6~0#1; 1459571#L701-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1459568#L718 assume !(0 != eval_~tmp_ndt_7~0#1); 1459565#L718-2 havoc eval_~tmp_ndt_7~0#1; 1459562#L715-1 assume !(0 == ~t7_st~0); 1459558#L729-1 [2024-10-13 17:46:33,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:33,680 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 7 times [2024-10-13 17:46:33,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:33,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9649426] [2024-10-13 17:46:33,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:33,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:33,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:33,696 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:33,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:33,740 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:33,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:33,745 INFO L85 PathProgramCache]: Analyzing trace with hash 102487731, now seen corresponding path program 1 times [2024-10-13 17:46:33,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:33,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296682350] [2024-10-13 17:46:33,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:33,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:33,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:33,749 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:33,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:33,753 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:33,753 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:33,753 INFO L85 PathProgramCache]: Analyzing trace with hash 2100785082, now seen corresponding path program 1 times [2024-10-13 17:46:33,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:33,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158326397] [2024-10-13 17:46:33,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:33,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:33,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:33,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:33,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:33,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158326397] [2024-10-13 17:46:33,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158326397] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:33,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:33,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:33,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767317705] [2024-10-13 17:46:33,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:33,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:33,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:33,894 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:33,894 INFO L87 Difference]: Start difference. First operand 212974 states and 281637 transitions. cyclomatic complexity: 68687 Second operand has 3 states, 2 states have (on average 61.5) internal successors, (123), 3 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:35,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:35,764 INFO L93 Difference]: Finished difference Result 417924 states and 551751 transitions. [2024-10-13 17:46:35,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417924 states and 551751 transitions. [2024-10-13 17:46:38,353 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 413502 [2024-10-13 17:46:39,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417924 states to 417924 states and 551751 transitions. [2024-10-13 17:46:39,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 417924