./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a046e57d Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.dk.eval-mul-div-a046e57-m [2024-10-13 17:45:55,430 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-13 17:45:55,474 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-13 17:45:55,479 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-13 17:45:55,480 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-13 17:45:55,502 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-13 17:45:55,503 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-13 17:45:55,503 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-13 17:45:55,504 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-13 17:45:55,505 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-13 17:45:55,506 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-13 17:45:55,506 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-13 17:45:55,506 INFO L153 SettingsManager]: * Use SBE=true [2024-10-13 17:45:55,506 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-13 17:45:55,506 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-13 17:45:55,506 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-13 17:45:55,507 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-13 17:45:55,507 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-13 17:45:55,507 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-13 17:45:55,507 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-13 17:45:55,507 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-13 17:45:55,509 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-13 17:45:55,509 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-13 17:45:55,509 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-13 17:45:55,509 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-13 17:45:55,510 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-13 17:45:55,510 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-13 17:45:55,510 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-13 17:45:55,510 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-13 17:45:55,510 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-13 17:45:55,510 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-13 17:45:55,510 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-13 17:45:55,511 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-13 17:45:55,511 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-13 17:45:55,511 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-13 17:45:55,511 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-13 17:45:55,511 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-13 17:45:55,511 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-13 17:45:55,512 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-13 17:45:55,512 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2024-10-13 17:45:55,709 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-13 17:45:55,726 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-13 17:45:55,729 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-13 17:45:55,730 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-13 17:45:55,730 INFO L274 PluginConnector]: CDTParser initialized [2024-10-13 17:45:55,731 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c [2024-10-13 17:45:56,987 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-13 17:45:57,137 INFO L384 CDTParser]: Found 1 translation units. [2024-10-13 17:45:57,138 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c [2024-10-13 17:45:57,148 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fb757c26a/5fc03446b0ca4481b3bff0956430666a/FLAG32ec4fe82 [2024-10-13 17:45:57,541 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fb757c26a/5fc03446b0ca4481b3bff0956430666a [2024-10-13 17:45:57,543 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-13 17:45:57,544 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-13 17:45:57,545 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-13 17:45:57,545 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-13 17:45:57,550 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-13 17:45:57,551 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,553 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@685923de and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57, skipping insertion in model container [2024-10-13 17:45:57,553 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,592 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-13 17:45:57,790 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:45:57,803 INFO L200 MainTranslator]: Completed pre-run [2024-10-13 17:45:57,857 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-13 17:45:57,877 INFO L204 MainTranslator]: Completed translation [2024-10-13 17:45:57,877 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57 WrapperNode [2024-10-13 17:45:57,877 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-13 17:45:57,878 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-13 17:45:57,878 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-13 17:45:57,878 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-13 17:45:57,882 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,892 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,944 INFO L138 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 147, statements flattened = 2216 [2024-10-13 17:45:57,944 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-13 17:45:57,945 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-13 17:45:57,945 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-13 17:45:57,945 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-13 17:45:57,955 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,955 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,961 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,984 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-13 17:45:57,985 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:57,985 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:58,028 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:58,046 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:58,049 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:58,053 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:58,064 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-13 17:45:58,065 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-13 17:45:58,065 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-13 17:45:58,065 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-13 17:45:58,065 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (1/1) ... [2024-10-13 17:45:58,077 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:45:58,094 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:45:58,107 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:45:58,109 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-13 17:45:58,144 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-13 17:45:58,144 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-13 17:45:58,145 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-13 17:45:58,145 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-13 17:45:58,229 INFO L238 CfgBuilder]: Building ICFG [2024-10-13 17:45:58,232 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-13 17:45:59,380 INFO L? ?]: Removed 438 outVars from TransFormulas that were not future-live. [2024-10-13 17:45:59,381 INFO L287 CfgBuilder]: Performing block encoding [2024-10-13 17:45:59,404 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-13 17:45:59,405 INFO L314 CfgBuilder]: Removed 12 assume(true) statements. [2024-10-13 17:45:59,406 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:45:59 BoogieIcfgContainer [2024-10-13 17:45:59,406 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-13 17:45:59,407 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-13 17:45:59,407 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-13 17:45:59,410 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-13 17:45:59,410 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:59,410 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 05:45:57" (1/3) ... [2024-10-13 17:45:59,411 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@57d1af48 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:45:59, skipping insertion in model container [2024-10-13 17:45:59,411 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:59,411 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 05:45:57" (2/3) ... [2024-10-13 17:45:59,411 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@57d1af48 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 05:45:59, skipping insertion in model container [2024-10-13 17:45:59,411 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-13 17:45:59,411 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 05:45:59" (3/3) ... [2024-10-13 17:45:59,412 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2024-10-13 17:45:59,472 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-13 17:45:59,472 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-13 17:45:59,472 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-13 17:45:59,472 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-13 17:45:59,472 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-13 17:45:59,472 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-13 17:45:59,472 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-13 17:45:59,473 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-13 17:45:59,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:59,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2024-10-13 17:45:59,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:59,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:59,544 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:59,544 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:59,545 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-13 17:45:59,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:45:59,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2024-10-13 17:45:59,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:45:59,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:45:59,558 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:59,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:45:59,565 INFO L745 eck$LassoCheckResult]: Stem: 126#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 859#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 683#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 855#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 685#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 193#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 827#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 676#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 652#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 239#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 686#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 413#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 771#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 295#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 713#L838true assume !(0 == ~M_E~0); 422#L838-2true assume !(0 == ~T1_E~0); 25#L843-1true assume !(0 == ~T2_E~0); 83#L848-1true assume !(0 == ~T3_E~0); 435#L853-1true assume !(0 == ~T4_E~0); 287#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 2#L863-1true assume !(0 == ~T6_E~0); 764#L868-1true assume !(0 == ~T7_E~0); 884#L873-1true assume !(0 == ~T8_E~0); 758#L878-1true assume !(0 == ~E_1~0); 722#L883-1true assume !(0 == ~E_2~0); 797#L888-1true assume !(0 == ~E_3~0); 390#L893-1true assume !(0 == ~E_4~0); 798#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 928#L903-1true assume !(0 == ~E_6~0); 719#L908-1true assume !(0 == ~E_7~0); 506#L913-1true assume !(0 == ~E_8~0); 30#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 525#L402true assume !(1 == ~m_pc~0); 271#L402-2true is_master_triggered_~__retres1~0#1 := 0; 96#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 575#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 243#L1035true assume !(0 != activate_threads_~tmp~1#1); 279#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 710#L421true assume 1 == ~t1_pc~0; 826#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 900#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 787#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912#L440true assume 1 == ~t2_pc~0; 18#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 101#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 833#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 527#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213#L459true assume !(1 == ~t3_pc~0); 702#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 782#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 93#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 934#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98#L478true assume 1 == ~t4_pc~0; 394#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 674#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 50#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 432#L497true assume !(1 == ~t5_pc~0); 361#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 458#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 577#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 788#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 696#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 891#L516true assume 1 == ~t6_pc~0; 892#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 412#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 472#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406#L535true assume !(1 == ~t7_pc~0); 802#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 470#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 870#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 500#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 493#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 687#L554true assume 1 == ~t8_pc~0; 438#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 828#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 518#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 501#L1099-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7#L931true assume !(1 == ~M_E~0); 743#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 824#L936-1true assume !(1 == ~T2_E~0); 909#L941-1true assume !(1 == ~T3_E~0); 280#L946-1true assume !(1 == ~T4_E~0); 707#L951-1true assume !(1 == ~T5_E~0); 131#L956-1true assume !(1 == ~T6_E~0); 893#L961-1true assume !(1 == ~T7_E~0); 391#L966-1true assume !(1 == ~T8_E~0); 495#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 845#L976-1true assume !(1 == ~E_2~0); 463#L981-1true assume !(1 == ~E_3~0); 283#L986-1true assume !(1 == ~E_4~0); 146#L991-1true assume !(1 == ~E_5~0); 874#L996-1true assume !(1 == ~E_6~0); 776#L1001-1true assume !(1 == ~E_7~0); 431#L1006-1true assume !(1 == ~E_8~0); 708#L1011-1true assume { :end_inline_reset_delta_events } true; 36#L1272-2true [2024-10-13 17:45:59,568 INFO L747 eck$LassoCheckResult]: Loop: 36#L1272-2true assume !false; 427#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L813-1true assume false; 524#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 316#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 657#L838-3true assume 0 == ~M_E~0;~M_E~0 := 1; 478#L838-5true assume !(0 == ~T1_E~0); 808#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 350#L848-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 392#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 585#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 452#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 442#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 461#L873-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 160#L878-3true assume !(0 == ~E_1~0); 19#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 671#L888-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 298#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 796#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 303#L913-3true assume 0 == ~E_8~0;~E_8~0 := 1; 38#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 902#L402-27true assume 1 == ~m_pc~0; 14#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 850#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 748#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 640#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 673#L421-27true assume 1 == ~t1_pc~0; 504#L422-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 832#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 374#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 777#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 898#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407#L440-27true assume 1 == ~t2_pc~0; 880#L441-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 940#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 330#L1051-27true assume !(0 != activate_threads_~tmp___1~0#1); 420#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148#L459-27true assume !(1 == ~t3_pc~0); 662#L459-29true is_transmit3_triggered_~__retres1~3#1 := 0; 847#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 405#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 762#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 895#L478-27true assume !(1 == ~t4_pc~0); 141#L478-29true is_transmit4_triggered_~__retres1~4#1 := 0; 414#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 555#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 763#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607#L497-27true assume 1 == ~t5_pc~0; 840#L498-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 166#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 678#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 300#L516-27true assume !(1 == ~t6_pc~0); 418#L516-29true is_transmit6_triggered_~__retres1~6#1 := 0; 203#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 424#L1083-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 774#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254#L535-27true assume !(1 == ~t7_pc~0); 534#L535-29true is_transmit7_triggered_~__retres1~7#1 := 0; 937#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 225#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 786#L554-27true assume !(1 == ~t8_pc~0); 26#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 100#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 550#is_transmit8_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 335#L1099-27true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 158#L1099-29true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 529#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 91#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 223#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 311#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 531#L946-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 168#L951-3true assume !(1 == ~T5_E~0); 513#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 371#L961-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 232#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 726#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 411#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 35#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 159#L986-3true assume 1 == ~E_4~0;~E_4~0 := 2; 29#L991-3true assume !(1 == ~E_5~0); 482#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 611#L1001-3true assume 1 == ~E_7~0;~E_7~0 := 2; 215#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 516#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 314#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 183#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 792#L1291true assume !(0 == start_simulation_~tmp~3#1); 759#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 293#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 730#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 329#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 556#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 36#L1272-2true [2024-10-13 17:45:59,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:59,579 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2024-10-13 17:45:59,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:59,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637249132] [2024-10-13 17:45:59,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:59,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:59,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:59,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:59,839 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:59,839 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637249132] [2024-10-13 17:45:59,840 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637249132] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:59,840 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:59,840 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:45:59,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [12893974] [2024-10-13 17:45:59,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:59,846 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:45:59,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:45:59,847 INFO L85 PathProgramCache]: Analyzing trace with hash -651940443, now seen corresponding path program 1 times [2024-10-13 17:45:59,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:45:59,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812724024] [2024-10-13 17:45:59,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:45:59,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:45:59,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:45:59,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:45:59,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:45:59,884 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812724024] [2024-10-13 17:45:59,884 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [812724024] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:45:59,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:45:59,884 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:45:59,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1965073010] [2024-10-13 17:45:59,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:45:59,886 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:45:59,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:45:59,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:45:59,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:45:59,936 INFO L87 Difference]: Start difference. First operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,031 INFO L93 Difference]: Finished difference Result 939 states and 1394 transitions. [2024-10-13 17:46:00,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 939 states and 1394 transitions. [2024-10-13 17:46:00,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 939 states to 933 states and 1388 transitions. [2024-10-13 17:46:00,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:00,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:00,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1388 transitions. [2024-10-13 17:46:00,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,054 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-10-13 17:46:00,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1388 transitions. [2024-10-13 17:46:00,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:00,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.487674169346195) internal successors, (1388), 932 states have internal predecessors, (1388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1388 transitions. [2024-10-13 17:46:00,110 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-10-13 17:46:00,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,116 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-10-13 17:46:00,117 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-13 17:46:00,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1388 transitions. [2024-10-13 17:46:00,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,125 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,125 INFO L745 eck$LassoCheckResult]: Stem: 2139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2766#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2767#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2768#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2258#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2259#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2764#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2760#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2330#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2331#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2565#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2566#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2414#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2415#L838 assume !(0 == ~M_E~0); 2573#L838-2 assume !(0 == ~T1_E~0); 1938#L843-1 assume !(0 == ~T2_E~0); 1939#L848-1 assume !(0 == ~T3_E~0); 2059#L853-1 assume !(0 == ~T4_E~0); 2401#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1889#L863-1 assume !(0 == ~T6_E~0); 1890#L868-1 assume !(0 == ~T7_E~0); 2796#L873-1 assume !(0 == ~T8_E~0); 2794#L878-1 assume !(0 == ~E_1~0); 2785#L883-1 assume !(0 == ~E_2~0); 2786#L888-1 assume !(0 == ~E_3~0); 2534#L893-1 assume !(0 == ~E_4~0); 2535#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2806#L903-1 assume !(0 == ~E_6~0); 2783#L908-1 assume !(0 == ~E_7~0); 2664#L913-1 assume !(0 == ~E_8~0); 1950#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1951#L402 assume !(1 == ~m_pc~0); 2162#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2083#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2084#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2336#L1035 assume !(0 != activate_threads_~tmp~1#1); 2337#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2389#L421 assume 1 == ~t1_pc~0; 2779#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2797#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1953#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1954#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2443#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2804#L440 assume 1 == ~t2_pc~0; 1922#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2679#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2287#L459 assume !(1 == ~t3_pc~0); 2288#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2777#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1912#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2078#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2087#L478 assume 1 == ~t4_pc~0; 2088#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2539#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2032#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1992#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1993#L497 assume !(1 == ~t5_pc~0); 2042#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2043#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2610#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2716#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2773#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2774#L516 assume 1 == ~t6_pc~0; 2820#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2564#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2267#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2133#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2134#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2553#L535 assume !(1 == ~t7_pc~0); 2554#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2624#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2656#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2646#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2647#L554 assume 1 == ~t8_pc~0; 2589#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1914#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2672#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2221#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2222#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1900#L931 assume !(1 == ~M_E~0); 1901#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2792#L936-1 assume !(1 == ~T2_E~0); 2811#L941-1 assume !(1 == ~T3_E~0); 2390#L946-1 assume !(1 == ~T4_E~0); 2391#L951-1 assume !(1 == ~T5_E~0); 2148#L956-1 assume !(1 == ~T6_E~0); 2149#L961-1 assume !(1 == ~T7_E~0); 2536#L966-1 assume !(1 == ~T8_E~0); 2537#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2649#L976-1 assume !(1 == ~E_2~0); 2614#L981-1 assume !(1 == ~E_3~0); 2394#L986-1 assume !(1 == ~E_4~0); 2175#L991-1 assume !(1 == ~E_5~0); 2176#L996-1 assume !(1 == ~E_6~0); 2801#L1001-1 assume !(1 == ~E_7~0); 2584#L1006-1 assume !(1 == ~E_8~0); 2585#L1011-1 assume { :end_inline_reset_delta_events } true; 1961#L1272-2 [2024-10-13 17:46:00,126 INFO L747 eck$LassoCheckResult]: Loop: 1961#L1272-2 assume !false; 1962#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2198#L813-1 assume !false; 2734#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2735#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1964#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2303#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2304#L696 assume !(0 != eval_~tmp~0#1); 2677#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2444#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2445#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2633#L838-5 assume !(0 == ~T1_E~0); 2634#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2487#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2488#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2538#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2603#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2593#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2594#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2202#L878-3 assume !(0 == ~E_1~0); 1925#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1926#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1927#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1928#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2420#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2736#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2428#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1966#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1967#L402-27 assume 1 == ~m_pc~0; 1915#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1916#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2626#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2627#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2753#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2754#L421-27 assume !(1 == ~t1_pc~0); 2192#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2193#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2512#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2513#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2802#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2556#L440-27 assume !(1 == ~t2_pc~0); 2557#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2731#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2598#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2463#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 2464#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2178#L459-27 assume 1 == ~t3_pc~0; 2179#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2619#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2440#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2441#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2552#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2795#L478-27 assume !(1 == ~t4_pc~0); 2167#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2168#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2351#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2352#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2701#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2737#L497-27 assume 1 == ~t5_pc~0; 2738#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2211#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2212#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2154#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2155#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2422#L516-27 assume !(1 == ~t6_pc~0); 2423#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2275#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2276#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2575#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2576#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2355#L535-27 assume 1 == ~t7_pc~0; 2356#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2685#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2235#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2236#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2306#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2307#L554-27 assume !(1 == ~t8_pc~0); 1940#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1941#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2092#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2472#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2199#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2200#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2074#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2075#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2305#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2439#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2215#L951-3 assume !(1 == ~T5_E~0); 2216#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2510#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2315#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2316#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2563#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1959#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1960#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1948#L991-3 assume !(1 == ~E_5~0); 1949#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2639#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2292#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2293#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1987#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1988#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2242#L1291 assume !(0 == start_simulation_~tmp~3#1); 2507#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2410#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1893#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1894#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1952#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2376#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2377#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2462#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1961#L1272-2 [2024-10-13 17:46:00,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,126 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2024-10-13 17:46:00,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224386899] [2024-10-13 17:46:00,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [224386899] [2024-10-13 17:46:00,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [224386899] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998917163] [2024-10-13 17:46:00,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,186 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,187 INFO L85 PathProgramCache]: Analyzing trace with hash 56067214, now seen corresponding path program 1 times [2024-10-13 17:46:00,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108457947] [2024-10-13 17:46:00,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108457947] [2024-10-13 17:46:00,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108457947] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,295 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,295 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963220909] [2024-10-13 17:46:00,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,296 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:00,296 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:00,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:00,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:00,297 INFO L87 Difference]: Start difference. First operand 933 states and 1388 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,315 INFO L93 Difference]: Finished difference Result 933 states and 1387 transitions. [2024-10-13 17:46:00,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1387 transitions. [2024-10-13 17:46:00,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1387 transitions. [2024-10-13 17:46:00,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:00,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:00,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1387 transitions. [2024-10-13 17:46:00,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-10-13 17:46:00,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1387 transitions. [2024-10-13 17:46:00,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:00,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4866023579849947) internal successors, (1387), 932 states have internal predecessors, (1387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1387 transitions. [2024-10-13 17:46:00,340 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-10-13 17:46:00,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,342 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-10-13 17:46:00,342 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-13 17:46:00,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1387 transitions. [2024-10-13 17:46:00,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,347 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,347 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,347 INFO L745 eck$LassoCheckResult]: Stem: 4012#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4013#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4641#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4131#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4132#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4637#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4633#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4203#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4204#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4438#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4439#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4287#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4288#L838 assume !(0 == ~M_E~0); 4446#L838-2 assume !(0 == ~T1_E~0); 3811#L843-1 assume !(0 == ~T2_E~0); 3812#L848-1 assume !(0 == ~T3_E~0); 3932#L853-1 assume !(0 == ~T4_E~0); 4274#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3762#L863-1 assume !(0 == ~T6_E~0); 3763#L868-1 assume !(0 == ~T7_E~0); 4669#L873-1 assume !(0 == ~T8_E~0); 4667#L878-1 assume !(0 == ~E_1~0); 4658#L883-1 assume !(0 == ~E_2~0); 4659#L888-1 assume !(0 == ~E_3~0); 4407#L893-1 assume !(0 == ~E_4~0); 4408#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4679#L903-1 assume !(0 == ~E_6~0); 4656#L908-1 assume !(0 == ~E_7~0); 4537#L913-1 assume !(0 == ~E_8~0); 3823#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3824#L402 assume !(1 == ~m_pc~0); 4035#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3956#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3957#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4209#L1035 assume !(0 != activate_threads_~tmp~1#1); 4210#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4262#L421 assume 1 == ~t1_pc~0; 4652#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4670#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3827#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4316#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4677#L440 assume 1 == ~t2_pc~0; 3795#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3796#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4157#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4552#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4160#L459 assume !(1 == ~t3_pc~0); 4161#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3784#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3785#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3951#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3960#L478 assume 1 == ~t4_pc~0; 3961#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4412#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3905#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3865#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3866#L497 assume !(1 == ~t5_pc~0); 3915#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3916#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4483#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4589#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4646#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4647#L516 assume 1 == ~t6_pc~0; 4693#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4437#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4006#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4007#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4426#L535 assume !(1 == ~t7_pc~0); 4427#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4497#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4498#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4529#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4519#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4520#L554 assume 1 == ~t8_pc~0; 4462#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3787#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4545#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4094#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4095#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3773#L931 assume !(1 == ~M_E~0); 3774#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4665#L936-1 assume !(1 == ~T2_E~0); 4684#L941-1 assume !(1 == ~T3_E~0); 4263#L946-1 assume !(1 == ~T4_E~0); 4264#L951-1 assume !(1 == ~T5_E~0); 4021#L956-1 assume !(1 == ~T6_E~0); 4022#L961-1 assume !(1 == ~T7_E~0); 4409#L966-1 assume !(1 == ~T8_E~0); 4410#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4522#L976-1 assume !(1 == ~E_2~0); 4487#L981-1 assume !(1 == ~E_3~0); 4267#L986-1 assume !(1 == ~E_4~0); 4048#L991-1 assume !(1 == ~E_5~0); 4049#L996-1 assume !(1 == ~E_6~0); 4674#L1001-1 assume !(1 == ~E_7~0); 4457#L1006-1 assume !(1 == ~E_8~0); 4458#L1011-1 assume { :end_inline_reset_delta_events } true; 3834#L1272-2 [2024-10-13 17:46:00,347 INFO L747 eck$LassoCheckResult]: Loop: 3834#L1272-2 assume !false; 3835#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4071#L813-1 assume !false; 4607#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4608#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3837#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4176#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4177#L696 assume !(0 != eval_~tmp~0#1); 4550#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4318#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L838-5 assume !(0 == ~T1_E~0); 4507#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4360#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4361#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4411#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4476#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4466#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4467#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4075#L878-3 assume !(0 == ~E_1~0); 3798#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3799#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3800#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4293#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4609#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4301#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3839#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3840#L402-27 assume 1 == ~m_pc~0; 3788#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3789#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4499#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4500#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4626#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4627#L421-27 assume !(1 == ~t1_pc~0); 4065#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4066#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4386#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4675#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4429#L440-27 assume !(1 == ~t2_pc~0); 4430#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 4604#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4471#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4336#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 4337#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4051#L459-27 assume 1 == ~t3_pc~0; 4052#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4492#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4313#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4314#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4425#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4668#L478-27 assume !(1 == ~t4_pc~0); 4040#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4041#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4224#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4225#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4574#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4610#L497-27 assume 1 == ~t5_pc~0; 4611#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4084#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4085#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4027#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4028#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4295#L516-27 assume !(1 == ~t6_pc~0); 4296#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 4148#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4149#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4448#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4449#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4228#L535-27 assume 1 == ~t7_pc~0; 4229#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4558#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4108#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4109#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4179#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4180#L554-27 assume !(1 == ~t8_pc~0); 3813#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 3814#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3965#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4345#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4072#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4073#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3947#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3948#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4178#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4312#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4088#L951-3 assume !(1 == ~T5_E~0); 4089#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4383#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4188#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4189#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4436#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3832#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3833#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3821#L991-3 assume !(1 == ~E_5~0); 3822#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4512#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4165#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4166#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3860#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3861#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4115#L1291 assume !(0 == start_simulation_~tmp~3#1); 4380#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4283#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3766#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3825#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4249#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4250#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4335#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 3834#L1272-2 [2024-10-13 17:46:00,348 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2024-10-13 17:46:00,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428364004] [2024-10-13 17:46:00,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428364004] [2024-10-13 17:46:00,402 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428364004] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,402 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456175321] [2024-10-13 17:46:00,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,403 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,403 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,403 INFO L85 PathProgramCache]: Analyzing trace with hash 56067214, now seen corresponding path program 2 times [2024-10-13 17:46:00,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355998154] [2024-10-13 17:46:00,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [355998154] [2024-10-13 17:46:00,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [355998154] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953669316] [2024-10-13 17:46:00,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,444 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:00,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:00,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:00,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:00,445 INFO L87 Difference]: Start difference. First operand 933 states and 1387 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,462 INFO L93 Difference]: Finished difference Result 933 states and 1386 transitions. [2024-10-13 17:46:00,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1386 transitions. [2024-10-13 17:46:00,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1386 transitions. [2024-10-13 17:46:00,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:00,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:00,470 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1386 transitions. [2024-10-13 17:46:00,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,470 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-10-13 17:46:00,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1386 transitions. [2024-10-13 17:46:00,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:00,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4855305466237942) internal successors, (1386), 932 states have internal predecessors, (1386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1386 transitions. [2024-10-13 17:46:00,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-10-13 17:46:00,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,483 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-10-13 17:46:00,483 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-13 17:46:00,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1386 transitions. [2024-10-13 17:46:00,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,488 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,488 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,489 INFO L745 eck$LassoCheckResult]: Stem: 5885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6514#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 6004#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6005#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6510#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6506#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6076#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6077#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6311#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6312#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6160#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6161#L838 assume !(0 == ~M_E~0); 6319#L838-2 assume !(0 == ~T1_E~0); 5684#L843-1 assume !(0 == ~T2_E~0); 5685#L848-1 assume !(0 == ~T3_E~0); 5805#L853-1 assume !(0 == ~T4_E~0); 6147#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5635#L863-1 assume !(0 == ~T6_E~0); 5636#L868-1 assume !(0 == ~T7_E~0); 6542#L873-1 assume !(0 == ~T8_E~0); 6540#L878-1 assume !(0 == ~E_1~0); 6531#L883-1 assume !(0 == ~E_2~0); 6532#L888-1 assume !(0 == ~E_3~0); 6280#L893-1 assume !(0 == ~E_4~0); 6281#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6552#L903-1 assume !(0 == ~E_6~0); 6529#L908-1 assume !(0 == ~E_7~0); 6410#L913-1 assume !(0 == ~E_8~0); 5696#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5697#L402 assume !(1 == ~m_pc~0); 5908#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5829#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5830#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6082#L1035 assume !(0 != activate_threads_~tmp~1#1); 6083#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6135#L421 assume 1 == ~t1_pc~0; 6525#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6543#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5700#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6189#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6550#L440 assume 1 == ~t2_pc~0; 5668#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5669#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5839#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6030#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6425#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6033#L459 assume !(1 == ~t3_pc~0); 6034#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6523#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5657#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5658#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5824#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5833#L478 assume 1 == ~t4_pc~0; 5834#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6285#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5778#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5738#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5739#L497 assume !(1 == ~t5_pc~0); 5788#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5789#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6356#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6462#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6519#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6520#L516 assume 1 == ~t6_pc~0; 6566#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6310#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6013#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5879#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5880#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6299#L535 assume !(1 == ~t7_pc~0); 6300#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6370#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6371#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6402#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6392#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6393#L554 assume 1 == ~t8_pc~0; 6335#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5660#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6418#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5967#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5968#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5646#L931 assume !(1 == ~M_E~0); 5647#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6538#L936-1 assume !(1 == ~T2_E~0); 6557#L941-1 assume !(1 == ~T3_E~0); 6136#L946-1 assume !(1 == ~T4_E~0); 6137#L951-1 assume !(1 == ~T5_E~0); 5894#L956-1 assume !(1 == ~T6_E~0); 5895#L961-1 assume !(1 == ~T7_E~0); 6282#L966-1 assume !(1 == ~T8_E~0); 6283#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6395#L976-1 assume !(1 == ~E_2~0); 6360#L981-1 assume !(1 == ~E_3~0); 6140#L986-1 assume !(1 == ~E_4~0); 5921#L991-1 assume !(1 == ~E_5~0); 5922#L996-1 assume !(1 == ~E_6~0); 6547#L1001-1 assume !(1 == ~E_7~0); 6330#L1006-1 assume !(1 == ~E_8~0); 6331#L1011-1 assume { :end_inline_reset_delta_events } true; 5707#L1272-2 [2024-10-13 17:46:00,504 INFO L747 eck$LassoCheckResult]: Loop: 5707#L1272-2 assume !false; 5708#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5944#L813-1 assume !false; 6480#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6481#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5710#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6050#L696 assume !(0 != eval_~tmp~0#1); 6423#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6190#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6191#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6379#L838-5 assume !(0 == ~T1_E~0); 6380#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6233#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6234#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6284#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6349#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6339#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6340#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5948#L878-3 assume !(0 == ~E_1~0); 5671#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5672#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5673#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5674#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6166#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6482#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6174#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5712#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5713#L402-27 assume 1 == ~m_pc~0; 5661#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5662#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6373#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6499#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6500#L421-27 assume !(1 == ~t1_pc~0); 5938#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5939#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6258#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6259#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6548#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6302#L440-27 assume 1 == ~t2_pc~0; 6304#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6477#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6344#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6209#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 6210#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5924#L459-27 assume 1 == ~t3_pc~0; 5925#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6365#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6186#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6187#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6298#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6541#L478-27 assume 1 == ~t4_pc~0; 6560#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5914#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6097#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6098#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6447#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6483#L497-27 assume 1 == ~t5_pc~0; 6484#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5957#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5958#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5900#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5901#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6168#L516-27 assume !(1 == ~t6_pc~0); 6169#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 6021#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6022#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6321#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6322#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6101#L535-27 assume 1 == ~t7_pc~0; 6102#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6431#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5981#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5982#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6052#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6053#L554-27 assume !(1 == ~t8_pc~0); 5686#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5687#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5838#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6218#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5945#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5946#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5820#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5821#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6051#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6185#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5961#L951-3 assume !(1 == ~T5_E~0); 5962#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6256#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6061#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6062#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6309#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5705#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5706#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5694#L991-3 assume !(1 == ~E_5~0); 5695#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6385#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6038#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6039#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5733#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5734#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5988#L1291 assume !(0 == start_simulation_~tmp~3#1); 6253#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6156#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5639#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5698#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6122#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6123#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6208#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5707#L1272-2 [2024-10-13 17:46:00,506 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,506 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2024-10-13 17:46:00,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364409576] [2024-10-13 17:46:00,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364409576] [2024-10-13 17:46:00,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1364409576] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481602822] [2024-10-13 17:46:00,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,572 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,572 INFO L85 PathProgramCache]: Analyzing trace with hash -1847000368, now seen corresponding path program 1 times [2024-10-13 17:46:00,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400820254] [2024-10-13 17:46:00,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400820254] [2024-10-13 17:46:00,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400820254] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282561398] [2024-10-13 17:46:00,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,653 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:00,653 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:00,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:00,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:00,654 INFO L87 Difference]: Start difference. First operand 933 states and 1386 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,668 INFO L93 Difference]: Finished difference Result 933 states and 1385 transitions. [2024-10-13 17:46:00,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1385 transitions. [2024-10-13 17:46:00,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1385 transitions. [2024-10-13 17:46:00,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:00,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:00,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1385 transitions. [2024-10-13 17:46:00,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-10-13 17:46:00,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1385 transitions. [2024-10-13 17:46:00,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:00,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4844587352625938) internal successors, (1385), 932 states have internal predecessors, (1385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1385 transitions. [2024-10-13 17:46:00,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-10-13 17:46:00,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,689 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-10-13 17:46:00,689 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-13 17:46:00,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1385 transitions. [2024-10-13 17:46:00,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,694 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,695 INFO L745 eck$LassoCheckResult]: Stem: 7758#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8387#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7877#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7878#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8383#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8379#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7949#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7950#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8184#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8185#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8033#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8034#L838 assume !(0 == ~M_E~0); 8192#L838-2 assume !(0 == ~T1_E~0); 7557#L843-1 assume !(0 == ~T2_E~0); 7558#L848-1 assume !(0 == ~T3_E~0); 7678#L853-1 assume !(0 == ~T4_E~0); 8020#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7508#L863-1 assume !(0 == ~T6_E~0); 7509#L868-1 assume !(0 == ~T7_E~0); 8415#L873-1 assume !(0 == ~T8_E~0); 8413#L878-1 assume !(0 == ~E_1~0); 8404#L883-1 assume !(0 == ~E_2~0); 8405#L888-1 assume !(0 == ~E_3~0); 8153#L893-1 assume !(0 == ~E_4~0); 8154#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8425#L903-1 assume !(0 == ~E_6~0); 8402#L908-1 assume !(0 == ~E_7~0); 8283#L913-1 assume !(0 == ~E_8~0); 7569#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7570#L402 assume !(1 == ~m_pc~0); 7781#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7702#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7703#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7955#L1035 assume !(0 != activate_threads_~tmp~1#1); 7956#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8008#L421 assume 1 == ~t1_pc~0; 8398#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8416#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7573#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 8062#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L440 assume 1 == ~t2_pc~0; 7541#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7542#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7712#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7903#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 8298#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7906#L459 assume !(1 == ~t3_pc~0); 7907#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8396#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7530#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7531#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7697#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7706#L478 assume 1 == ~t4_pc~0; 7707#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8158#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7651#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7611#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7612#L497 assume !(1 == ~t5_pc~0); 7661#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7662#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8335#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 8392#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8393#L516 assume 1 == ~t6_pc~0; 8439#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8183#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7886#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7752#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7753#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8172#L535 assume !(1 == ~t7_pc~0); 8173#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8243#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8244#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8275#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 8265#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8266#L554 assume 1 == ~t8_pc~0; 8208#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7533#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8291#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7840#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7841#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7519#L931 assume !(1 == ~M_E~0); 7520#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8411#L936-1 assume !(1 == ~T2_E~0); 8430#L941-1 assume !(1 == ~T3_E~0); 8009#L946-1 assume !(1 == ~T4_E~0); 8010#L951-1 assume !(1 == ~T5_E~0); 7767#L956-1 assume !(1 == ~T6_E~0); 7768#L961-1 assume !(1 == ~T7_E~0); 8155#L966-1 assume !(1 == ~T8_E~0); 8156#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8268#L976-1 assume !(1 == ~E_2~0); 8233#L981-1 assume !(1 == ~E_3~0); 8013#L986-1 assume !(1 == ~E_4~0); 7794#L991-1 assume !(1 == ~E_5~0); 7795#L996-1 assume !(1 == ~E_6~0); 8420#L1001-1 assume !(1 == ~E_7~0); 8203#L1006-1 assume !(1 == ~E_8~0); 8204#L1011-1 assume { :end_inline_reset_delta_events } true; 7580#L1272-2 [2024-10-13 17:46:00,695 INFO L747 eck$LassoCheckResult]: Loop: 7580#L1272-2 assume !false; 7581#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7817#L813-1 assume !false; 8353#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8354#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7583#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7922#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7923#L696 assume !(0 != eval_~tmp~0#1); 8296#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8064#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8252#L838-5 assume !(0 == ~T1_E~0); 8253#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8106#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8107#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8157#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8222#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8212#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8213#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7821#L878-3 assume !(0 == ~E_1~0); 7544#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7545#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7546#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7547#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8039#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8355#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8047#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7585#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7586#L402-27 assume !(1 == ~m_pc~0); 7536#L402-29 is_master_triggered_~__retres1~0#1 := 0; 7535#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8245#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8246#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8372#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8373#L421-27 assume !(1 == ~t1_pc~0); 7811#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7812#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8131#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8132#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8421#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8175#L440-27 assume !(1 == ~t2_pc~0); 8176#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 8350#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8217#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8082#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 8083#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7797#L459-27 assume 1 == ~t3_pc~0; 7798#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8238#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8059#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8060#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8171#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8414#L478-27 assume 1 == ~t4_pc~0; 8433#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7787#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7970#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7971#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8320#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8356#L497-27 assume 1 == ~t5_pc~0; 8357#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7830#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7831#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7773#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7774#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8041#L516-27 assume !(1 == ~t6_pc~0); 8042#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 7894#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7895#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8194#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8195#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7974#L535-27 assume 1 == ~t7_pc~0; 7975#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8304#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7854#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7855#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7925#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7926#L554-27 assume 1 == ~t8_pc~0; 8128#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7560#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7711#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8091#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7818#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7819#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7693#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7694#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7924#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8058#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7834#L951-3 assume !(1 == ~T5_E~0); 7835#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8129#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7934#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7935#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8182#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7578#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7579#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L991-3 assume !(1 == ~E_5~0); 7568#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8258#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7911#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7912#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7606#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7607#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7861#L1291 assume !(0 == start_simulation_~tmp~3#1); 8126#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8029#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7512#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7513#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 7571#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7995#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7996#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8081#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 7580#L1272-2 [2024-10-13 17:46:00,698 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,698 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2024-10-13 17:46:00,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471072792] [2024-10-13 17:46:00,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471072792] [2024-10-13 17:46:00,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471072792] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739277109] [2024-10-13 17:46:00,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,738 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,738 INFO L85 PathProgramCache]: Analyzing trace with hash -1022505361, now seen corresponding path program 1 times [2024-10-13 17:46:00,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176580204] [2024-10-13 17:46:00,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176580204] [2024-10-13 17:46:00,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1176580204] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414022808] [2024-10-13 17:46:00,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,779 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:00,779 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:00,779 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:00,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:00,780 INFO L87 Difference]: Start difference. First operand 933 states and 1385 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,797 INFO L93 Difference]: Finished difference Result 933 states and 1384 transitions. [2024-10-13 17:46:00,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1384 transitions. [2024-10-13 17:46:00,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1384 transitions. [2024-10-13 17:46:00,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:00,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:00,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1384 transitions. [2024-10-13 17:46:00,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,804 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-10-13 17:46:00,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1384 transitions. [2024-10-13 17:46:00,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:00,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4833869239013933) internal successors, (1384), 932 states have internal predecessors, (1384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1384 transitions. [2024-10-13 17:46:00,814 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-10-13 17:46:00,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,815 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-10-13 17:46:00,816 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-13 17:46:00,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1384 transitions. [2024-10-13 17:46:00,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,820 INFO L745 eck$LassoCheckResult]: Stem: 9631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10258#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10259#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10260#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9750#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9751#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10256#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10252#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9822#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9823#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10057#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10058#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9906#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9907#L838 assume !(0 == ~M_E~0); 10065#L838-2 assume !(0 == ~T1_E~0); 9430#L843-1 assume !(0 == ~T2_E~0); 9431#L848-1 assume !(0 == ~T3_E~0); 9551#L853-1 assume !(0 == ~T4_E~0); 9893#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9381#L863-1 assume !(0 == ~T6_E~0); 9382#L868-1 assume !(0 == ~T7_E~0); 10288#L873-1 assume !(0 == ~T8_E~0); 10286#L878-1 assume !(0 == ~E_1~0); 10277#L883-1 assume !(0 == ~E_2~0); 10278#L888-1 assume !(0 == ~E_3~0); 10026#L893-1 assume !(0 == ~E_4~0); 10027#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10298#L903-1 assume !(0 == ~E_6~0); 10275#L908-1 assume !(0 == ~E_7~0); 10156#L913-1 assume !(0 == ~E_8~0); 9442#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9443#L402 assume !(1 == ~m_pc~0); 9654#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9575#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9576#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9828#L1035 assume !(0 != activate_threads_~tmp~1#1); 9829#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9881#L421 assume 1 == ~t1_pc~0; 10271#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10289#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9445#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9446#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9935#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10296#L440 assume 1 == ~t2_pc~0; 9414#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9415#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9585#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9776#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10171#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9779#L459 assume !(1 == ~t3_pc~0); 9780#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10269#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9404#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9570#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9579#L478 assume 1 == ~t4_pc~0; 9580#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10031#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9523#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9524#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9484#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9485#L497 assume !(1 == ~t5_pc~0); 9534#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9535#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10102#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10208#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10265#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10266#L516 assume 1 == ~t6_pc~0; 10312#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10056#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9759#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9625#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9626#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10045#L535 assume !(1 == ~t7_pc~0); 10046#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10116#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10148#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10138#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10139#L554 assume 1 == ~t8_pc~0; 10081#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9406#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10164#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9713#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9714#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9392#L931 assume !(1 == ~M_E~0); 9393#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10284#L936-1 assume !(1 == ~T2_E~0); 10303#L941-1 assume !(1 == ~T3_E~0); 9882#L946-1 assume !(1 == ~T4_E~0); 9883#L951-1 assume !(1 == ~T5_E~0); 9640#L956-1 assume !(1 == ~T6_E~0); 9641#L961-1 assume !(1 == ~T7_E~0); 10028#L966-1 assume !(1 == ~T8_E~0); 10029#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10141#L976-1 assume !(1 == ~E_2~0); 10106#L981-1 assume !(1 == ~E_3~0); 9886#L986-1 assume !(1 == ~E_4~0); 9667#L991-1 assume !(1 == ~E_5~0); 9668#L996-1 assume !(1 == ~E_6~0); 10293#L1001-1 assume !(1 == ~E_7~0); 10076#L1006-1 assume !(1 == ~E_8~0); 10077#L1011-1 assume { :end_inline_reset_delta_events } true; 9453#L1272-2 [2024-10-13 17:46:00,820 INFO L747 eck$LassoCheckResult]: Loop: 9453#L1272-2 assume !false; 9454#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9690#L813-1 assume !false; 10226#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10227#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9456#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9795#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9796#L696 assume !(0 != eval_~tmp~0#1); 10169#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9936#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9937#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10125#L838-5 assume !(0 == ~T1_E~0); 10126#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9979#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9980#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10030#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10095#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10085#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10086#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9694#L878-3 assume !(0 == ~E_1~0); 9417#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9418#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9419#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9420#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9912#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10228#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9920#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9458#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9459#L402-27 assume !(1 == ~m_pc~0); 9409#L402-29 is_master_triggered_~__retres1~0#1 := 0; 9408#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10118#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10119#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10245#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10246#L421-27 assume !(1 == ~t1_pc~0); 9684#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9685#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10004#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10005#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10294#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10048#L440-27 assume !(1 == ~t2_pc~0); 10049#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 10223#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10090#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9955#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 9956#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9670#L459-27 assume 1 == ~t3_pc~0; 9671#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10111#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9932#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9933#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10044#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10287#L478-27 assume 1 == ~t4_pc~0; 10306#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9660#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9843#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9844#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10193#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10229#L497-27 assume 1 == ~t5_pc~0; 10230#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9703#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9704#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9646#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9647#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9914#L516-27 assume !(1 == ~t6_pc~0); 9915#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9767#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9768#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10067#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10068#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9847#L535-27 assume 1 == ~t7_pc~0; 9848#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10177#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9727#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9728#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9798#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9799#L554-27 assume 1 == ~t8_pc~0; 10001#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9433#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9584#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9964#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9691#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9692#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9566#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9567#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9797#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9931#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9707#L951-3 assume !(1 == ~T5_E~0); 9708#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10002#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9807#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9808#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10055#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9451#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9452#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9440#L991-3 assume !(1 == ~E_5~0); 9441#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10131#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9784#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9785#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9479#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9480#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9734#L1291 assume !(0 == start_simulation_~tmp~3#1); 9999#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9902#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9385#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9386#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 9444#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9868#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9869#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9954#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9453#L1272-2 [2024-10-13 17:46:00,820 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,820 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2024-10-13 17:46:00,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520398877] [2024-10-13 17:46:00,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520398877] [2024-10-13 17:46:00,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520398877] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829873611] [2024-10-13 17:46:00,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,850 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,850 INFO L85 PathProgramCache]: Analyzing trace with hash -1022505361, now seen corresponding path program 2 times [2024-10-13 17:46:00,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163207838] [2024-10-13 17:46:00,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163207838] [2024-10-13 17:46:00,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1163207838] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334771503] [2024-10-13 17:46:00,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,905 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:00,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:00,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:00,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:00,905 INFO L87 Difference]: Start difference. First operand 933 states and 1384 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:00,919 INFO L93 Difference]: Finished difference Result 933 states and 1383 transitions. [2024-10-13 17:46:00,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1383 transitions. [2024-10-13 17:46:00,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,925 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1383 transitions. [2024-10-13 17:46:00,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:00,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:00,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1383 transitions. [2024-10-13 17:46:00,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:00,926 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-10-13 17:46:00,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1383 transitions. [2024-10-13 17:46:00,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:00,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.482315112540193) internal successors, (1383), 932 states have internal predecessors, (1383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:00,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1383 transitions. [2024-10-13 17:46:00,936 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-10-13 17:46:00,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:00,937 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-10-13 17:46:00,937 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-13 17:46:00,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1383 transitions. [2024-10-13 17:46:00,940 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:00,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:00,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:00,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:00,943 INFO L745 eck$LassoCheckResult]: Stem: 11504#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11505#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12133#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 11623#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11624#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12129#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12125#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11695#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11696#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11930#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11931#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11779#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11780#L838 assume !(0 == ~M_E~0); 11938#L838-2 assume !(0 == ~T1_E~0); 11303#L843-1 assume !(0 == ~T2_E~0); 11304#L848-1 assume !(0 == ~T3_E~0); 11424#L853-1 assume !(0 == ~T4_E~0); 11766#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11254#L863-1 assume !(0 == ~T6_E~0); 11255#L868-1 assume !(0 == ~T7_E~0); 12161#L873-1 assume !(0 == ~T8_E~0); 12159#L878-1 assume !(0 == ~E_1~0); 12150#L883-1 assume !(0 == ~E_2~0); 12151#L888-1 assume !(0 == ~E_3~0); 11899#L893-1 assume !(0 == ~E_4~0); 11900#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12171#L903-1 assume !(0 == ~E_6~0); 12148#L908-1 assume !(0 == ~E_7~0); 12029#L913-1 assume !(0 == ~E_8~0); 11315#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11316#L402 assume !(1 == ~m_pc~0); 11527#L402-2 is_master_triggered_~__retres1~0#1 := 0; 11448#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11449#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11701#L1035 assume !(0 != activate_threads_~tmp~1#1); 11702#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11754#L421 assume 1 == ~t1_pc~0; 12144#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12162#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11318#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11319#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12169#L440 assume 1 == ~t2_pc~0; 11287#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11288#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11458#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11649#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 12044#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11652#L459 assume !(1 == ~t3_pc~0); 11653#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12142#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11276#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11277#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11443#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11452#L478 assume 1 == ~t4_pc~0; 11453#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11904#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11397#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 11357#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11358#L497 assume !(1 == ~t5_pc~0); 11407#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11408#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11975#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12081#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 12138#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12139#L516 assume 1 == ~t6_pc~0; 12185#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11929#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11632#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11498#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 11499#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11918#L535 assume !(1 == ~t7_pc~0); 11919#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11989#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11990#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12021#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 12011#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12012#L554 assume 1 == ~t8_pc~0; 11954#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11279#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12037#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11586#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 11587#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11265#L931 assume !(1 == ~M_E~0); 11266#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12157#L936-1 assume !(1 == ~T2_E~0); 12176#L941-1 assume !(1 == ~T3_E~0); 11755#L946-1 assume !(1 == ~T4_E~0); 11756#L951-1 assume !(1 == ~T5_E~0); 11513#L956-1 assume !(1 == ~T6_E~0); 11514#L961-1 assume !(1 == ~T7_E~0); 11901#L966-1 assume !(1 == ~T8_E~0); 11902#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12014#L976-1 assume !(1 == ~E_2~0); 11979#L981-1 assume !(1 == ~E_3~0); 11759#L986-1 assume !(1 == ~E_4~0); 11540#L991-1 assume !(1 == ~E_5~0); 11541#L996-1 assume !(1 == ~E_6~0); 12166#L1001-1 assume !(1 == ~E_7~0); 11949#L1006-1 assume !(1 == ~E_8~0); 11950#L1011-1 assume { :end_inline_reset_delta_events } true; 11326#L1272-2 [2024-10-13 17:46:00,944 INFO L747 eck$LassoCheckResult]: Loop: 11326#L1272-2 assume !false; 11327#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11563#L813-1 assume !false; 12099#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12100#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11329#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11668#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11669#L696 assume !(0 != eval_~tmp~0#1); 12042#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11810#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11998#L838-5 assume !(0 == ~T1_E~0); 11999#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11852#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11853#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11903#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11968#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11958#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11959#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11567#L878-3 assume !(0 == ~E_1~0); 11290#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11291#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11292#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11293#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11785#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12101#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11793#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11331#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11332#L402-27 assume 1 == ~m_pc~0; 11280#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11281#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11991#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11992#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12118#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12119#L421-27 assume !(1 == ~t1_pc~0); 11557#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 11558#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11877#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11878#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12167#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11921#L440-27 assume !(1 == ~t2_pc~0); 11922#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 12096#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11963#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11828#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 11829#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11543#L459-27 assume 1 == ~t3_pc~0; 11544#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11984#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11805#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11806#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11917#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12160#L478-27 assume 1 == ~t4_pc~0; 12179#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11533#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11716#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11717#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12066#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12102#L497-27 assume 1 == ~t5_pc~0; 12103#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11576#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11519#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11520#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11787#L516-27 assume !(1 == ~t6_pc~0); 11788#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 11640#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11641#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11940#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11941#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11720#L535-27 assume 1 == ~t7_pc~0; 11721#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12050#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11600#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11601#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11671#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11672#L554-27 assume 1 == ~t8_pc~0; 11874#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11306#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11457#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11837#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11564#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11565#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11439#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11440#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11670#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11804#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11580#L951-3 assume !(1 == ~T5_E~0); 11581#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11875#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11680#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11681#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11928#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11324#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11325#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11313#L991-3 assume !(1 == ~E_5~0); 11314#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12004#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11657#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11658#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11352#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11353#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11606#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11607#L1291 assume !(0 == start_simulation_~tmp~3#1); 11872#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11775#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11258#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11259#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11317#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11741#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11742#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11827#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 11326#L1272-2 [2024-10-13 17:46:00,944 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,944 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2024-10-13 17:46:00,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,944 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480652145] [2024-10-13 17:46:00,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:00,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:00,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:00,970 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480652145] [2024-10-13 17:46:00,971 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1480652145] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:00,971 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:00,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:00,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1149277338] [2024-10-13 17:46:00,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:00,971 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:00,971 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:00,971 INFO L85 PathProgramCache]: Analyzing trace with hash -567599280, now seen corresponding path program 1 times [2024-10-13 17:46:00,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:00,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290462237] [2024-10-13 17:46:00,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:00,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:00,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,002 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290462237] [2024-10-13 17:46:01,002 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290462237] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,002 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,002 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337221449] [2024-10-13 17:46:01,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,002 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,002 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,002 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,003 INFO L87 Difference]: Start difference. First operand 933 states and 1383 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,014 INFO L93 Difference]: Finished difference Result 933 states and 1382 transitions. [2024-10-13 17:46:01,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1382 transitions. [2024-10-13 17:46:01,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:01,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1382 transitions. [2024-10-13 17:46:01,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:01,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:01,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1382 transitions. [2024-10-13 17:46:01,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,022 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-10-13 17:46:01,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1382 transitions. [2024-10-13 17:46:01,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:01,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4812433011789925) internal successors, (1382), 932 states have internal predecessors, (1382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1382 transitions. [2024-10-13 17:46:01,032 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-10-13 17:46:01,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,034 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-10-13 17:46:01,034 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-13 17:46:01,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1382 transitions. [2024-10-13 17:46:01,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:01,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,038 INFO L745 eck$LassoCheckResult]: Stem: 13377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14004#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14005#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14006#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13496#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13497#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14002#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13998#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13568#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13569#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13803#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13804#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13652#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13653#L838 assume !(0 == ~M_E~0); 13812#L838-2 assume !(0 == ~T1_E~0); 13176#L843-1 assume !(0 == ~T2_E~0); 13177#L848-1 assume !(0 == ~T3_E~0); 13297#L853-1 assume !(0 == ~T4_E~0); 13641#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13129#L863-1 assume !(0 == ~T6_E~0); 13130#L868-1 assume !(0 == ~T7_E~0); 14034#L873-1 assume !(0 == ~T8_E~0); 14032#L878-1 assume !(0 == ~E_1~0); 14023#L883-1 assume !(0 == ~E_2~0); 14024#L888-1 assume !(0 == ~E_3~0); 13775#L893-1 assume !(0 == ~E_4~0); 13776#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 14044#L903-1 assume !(0 == ~E_6~0); 14021#L908-1 assume !(0 == ~E_7~0); 13903#L913-1 assume !(0 == ~E_8~0); 13189#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13190#L402 assume !(1 == ~m_pc~0); 13404#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13321#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13322#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13574#L1035 assume !(0 != activate_threads_~tmp~1#1); 13575#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13629#L421 assume 1 == ~t1_pc~0; 14017#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14038#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13191#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13192#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13683#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14042#L440 assume 1 == ~t2_pc~0; 13160#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13161#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13522#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13917#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13529#L459 assume !(1 == ~t3_pc~0); 13530#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14015#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13150#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13316#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13325#L478 assume 1 == ~t4_pc~0; 13326#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13777#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13270#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13232#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13233#L497 assume !(1 == ~t5_pc~0); 13280#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13281#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13954#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 14011#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14012#L516 assume 1 == ~t6_pc~0; 14058#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13802#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13505#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13371#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13372#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13791#L535 assume !(1 == ~t7_pc~0); 13792#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13862#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13863#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13894#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13885#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13886#L554 assume 1 == ~t8_pc~0; 13827#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13152#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13911#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13462#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13463#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13138#L931 assume !(1 == ~M_E~0); 13139#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14030#L936-1 assume !(1 == ~T2_E~0); 14049#L941-1 assume !(1 == ~T3_E~0); 13627#L946-1 assume !(1 == ~T4_E~0); 13628#L951-1 assume !(1 == ~T5_E~0); 13386#L956-1 assume !(1 == ~T6_E~0); 13387#L961-1 assume !(1 == ~T7_E~0); 13772#L966-1 assume !(1 == ~T8_E~0); 13773#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13887#L976-1 assume !(1 == ~E_2~0); 13852#L981-1 assume !(1 == ~E_3~0); 13632#L986-1 assume !(1 == ~E_4~0); 13413#L991-1 assume !(1 == ~E_5~0); 13414#L996-1 assume !(1 == ~E_6~0); 14039#L1001-1 assume !(1 == ~E_7~0); 13822#L1006-1 assume !(1 == ~E_8~0); 13823#L1011-1 assume { :end_inline_reset_delta_events } true; 13199#L1272-2 [2024-10-13 17:46:01,038 INFO L747 eck$LassoCheckResult]: Loop: 13199#L1272-2 assume !false; 13200#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13436#L813-1 assume !false; 13972#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13973#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13202#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13541#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13542#L696 assume !(0 != eval_~tmp~0#1); 13915#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13682#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13871#L838-5 assume !(0 == ~T1_E~0); 13872#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13725#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13726#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13774#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13841#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13440#L878-3 assume !(0 == ~E_1~0); 13163#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13164#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13165#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13166#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13658#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13974#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13666#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13204#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13205#L402-27 assume 1 == ~m_pc~0; 13153#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13154#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13864#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13865#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13991#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13992#L421-27 assume !(1 == ~t1_pc~0); 13430#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 13431#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13750#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13751#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14040#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13794#L440-27 assume !(1 == ~t2_pc~0); 13795#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 13968#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13836#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13701#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 13702#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13416#L459-27 assume 1 == ~t3_pc~0; 13417#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13857#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13678#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13679#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13790#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14033#L478-27 assume 1 == ~t4_pc~0; 14052#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13406#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13589#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13590#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13939#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13975#L497-27 assume 1 == ~t5_pc~0; 13976#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13449#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13450#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13392#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13393#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13660#L516-27 assume !(1 == ~t6_pc~0); 13661#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 13513#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13514#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13813#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13814#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13593#L535-27 assume 1 == ~t7_pc~0; 13594#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13923#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13473#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13474#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13544#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13545#L554-27 assume 1 == ~t8_pc~0; 13747#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13179#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13330#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13710#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13437#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13438#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13312#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13313#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13543#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13677#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13453#L951-3 assume !(1 == ~T5_E~0); 13454#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13748#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13553#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13554#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13801#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13197#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13198#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13186#L991-3 assume !(1 == ~E_5~0); 13187#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13877#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13527#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13528#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13225#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13226#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13480#L1291 assume !(0 == start_simulation_~tmp~3#1); 13745#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13648#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13131#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13188#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13614#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13615#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13700#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13199#L1272-2 [2024-10-13 17:46:01,039 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,039 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2024-10-13 17:46:01,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926252571] [2024-10-13 17:46:01,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926252571] [2024-10-13 17:46:01,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926252571] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627658801] [2024-10-13 17:46:01,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,073 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,073 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,073 INFO L85 PathProgramCache]: Analyzing trace with hash -567599280, now seen corresponding path program 2 times [2024-10-13 17:46:01,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915707332] [2024-10-13 17:46:01,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,117 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915707332] [2024-10-13 17:46:01,117 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915707332] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,117 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,117 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063565767] [2024-10-13 17:46:01,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,118 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,118 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,118 INFO L87 Difference]: Start difference. First operand 933 states and 1382 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,133 INFO L93 Difference]: Finished difference Result 933 states and 1381 transitions. [2024-10-13 17:46:01,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1381 transitions. [2024-10-13 17:46:01,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:01,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1381 transitions. [2024-10-13 17:46:01,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:01,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:01,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1381 transitions. [2024-10-13 17:46:01,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-10-13 17:46:01,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1381 transitions. [2024-10-13 17:46:01,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:01,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.480171489817792) internal successors, (1381), 932 states have internal predecessors, (1381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1381 transitions. [2024-10-13 17:46:01,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-10-13 17:46:01,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,155 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-10-13 17:46:01,155 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-13 17:46:01,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1381 transitions. [2024-10-13 17:46:01,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:01,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,159 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,159 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,159 INFO L745 eck$LassoCheckResult]: Stem: 15250#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 15251#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15879#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 15369#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15370#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15875#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15871#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15441#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15442#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15676#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15677#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15525#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15526#L838 assume !(0 == ~M_E~0); 15685#L838-2 assume !(0 == ~T1_E~0); 15049#L843-1 assume !(0 == ~T2_E~0); 15050#L848-1 assume !(0 == ~T3_E~0); 15170#L853-1 assume !(0 == ~T4_E~0); 15514#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15002#L863-1 assume !(0 == ~T6_E~0); 15003#L868-1 assume !(0 == ~T7_E~0); 15907#L873-1 assume !(0 == ~T8_E~0); 15905#L878-1 assume !(0 == ~E_1~0); 15896#L883-1 assume !(0 == ~E_2~0); 15897#L888-1 assume !(0 == ~E_3~0); 15645#L893-1 assume !(0 == ~E_4~0); 15646#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15917#L903-1 assume !(0 == ~E_6~0); 15894#L908-1 assume !(0 == ~E_7~0); 15776#L913-1 assume !(0 == ~E_8~0); 15062#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15063#L402 assume !(1 == ~m_pc~0); 15277#L402-2 is_master_triggered_~__retres1~0#1 := 0; 15194#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15195#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15447#L1035 assume !(0 != activate_threads_~tmp~1#1); 15448#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15500#L421 assume 1 == ~t1_pc~0; 15890#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15911#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15064#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15065#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 15554#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15915#L440 assume 1 == ~t2_pc~0; 15033#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15034#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15204#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15395#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 15790#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15402#L459 assume !(1 == ~t3_pc~0); 15403#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15888#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15023#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15189#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15198#L478 assume 1 == ~t4_pc~0; 15199#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15650#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15143#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 15105#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15106#L497 assume !(1 == ~t5_pc~0); 15153#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15154#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15827#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 15884#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15885#L516 assume 1 == ~t6_pc~0; 15931#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15675#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15378#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15244#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 15245#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15664#L535 assume !(1 == ~t7_pc~0); 15665#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15735#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15736#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15767#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 15758#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15759#L554 assume 1 == ~t8_pc~0; 15700#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15025#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15783#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15335#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 15336#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15011#L931 assume !(1 == ~M_E~0); 15012#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15903#L936-1 assume !(1 == ~T2_E~0); 15922#L941-1 assume !(1 == ~T3_E~0); 15501#L946-1 assume !(1 == ~T4_E~0); 15502#L951-1 assume !(1 == ~T5_E~0); 15259#L956-1 assume !(1 == ~T6_E~0); 15260#L961-1 assume !(1 == ~T7_E~0); 15647#L966-1 assume !(1 == ~T8_E~0); 15648#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15761#L976-1 assume !(1 == ~E_2~0); 15725#L981-1 assume !(1 == ~E_3~0); 15505#L986-1 assume !(1 == ~E_4~0); 15286#L991-1 assume !(1 == ~E_5~0); 15287#L996-1 assume !(1 == ~E_6~0); 15912#L1001-1 assume !(1 == ~E_7~0); 15695#L1006-1 assume !(1 == ~E_8~0); 15696#L1011-1 assume { :end_inline_reset_delta_events } true; 15072#L1272-2 [2024-10-13 17:46:01,159 INFO L747 eck$LassoCheckResult]: Loop: 15072#L1272-2 assume !false; 15073#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15311#L813-1 assume !false; 15845#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15846#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15075#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15414#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15415#L696 assume !(0 != eval_~tmp~0#1); 15788#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15556#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15744#L838-5 assume !(0 == ~T1_E~0); 15745#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15599#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15600#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15649#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15714#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15705#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15706#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15315#L878-3 assume !(0 == ~E_1~0); 15038#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15039#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15036#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15037#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15531#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15847#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15539#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15077#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15078#L402-27 assume 1 == ~m_pc~0; 15026#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15027#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15737#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15738#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15864#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15865#L421-27 assume !(1 == ~t1_pc~0); 15303#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 15304#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15623#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15624#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15913#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15667#L440-27 assume !(1 == ~t2_pc~0); 15668#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15841#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15709#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 15575#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15289#L459-27 assume 1 == ~t3_pc~0; 15290#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15730#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15552#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15663#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15906#L478-27 assume 1 == ~t4_pc~0; 15925#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15279#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15462#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15463#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15812#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15848#L497-27 assume !(1 == ~t5_pc~0); 15456#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15322#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15323#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15265#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15266#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15532#L516-27 assume !(1 == ~t6_pc~0); 15533#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 15383#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15384#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15686#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15687#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15466#L535-27 assume 1 == ~t7_pc~0; 15467#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15796#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15346#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15347#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15417#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15418#L554-27 assume 1 == ~t8_pc~0; 15620#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15052#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15203#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15580#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15308#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15309#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15185#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15186#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15416#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15550#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15326#L951-3 assume !(1 == ~T5_E~0); 15327#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15621#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15426#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15427#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15674#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15070#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15071#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15059#L991-3 assume !(1 == ~E_5~0); 15060#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15750#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15400#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15401#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15098#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15099#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15349#L1291 assume !(0 == start_simulation_~tmp~3#1); 15618#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15521#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15004#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15005#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15061#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15487#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15488#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15573#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 15072#L1272-2 [2024-10-13 17:46:01,160 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,160 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2024-10-13 17:46:01,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469999818] [2024-10-13 17:46:01,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469999818] [2024-10-13 17:46:01,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469999818] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,224 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,224 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:01,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651720834] [2024-10-13 17:46:01,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,225 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,225 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,225 INFO L85 PathProgramCache]: Analyzing trace with hash -464798033, now seen corresponding path program 1 times [2024-10-13 17:46:01,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785806402] [2024-10-13 17:46:01,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,259 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,259 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785806402] [2024-10-13 17:46:01,259 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785806402] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,259 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,259 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570940716] [2024-10-13 17:46:01,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,260 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,260 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,260 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,260 INFO L87 Difference]: Start difference. First operand 933 states and 1381 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,290 INFO L93 Difference]: Finished difference Result 933 states and 1376 transitions. [2024-10-13 17:46:01,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1376 transitions. [2024-10-13 17:46:01,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:01,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1376 transitions. [2024-10-13 17:46:01,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-13 17:46:01,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-13 17:46:01,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1376 transitions. [2024-10-13 17:46:01,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,299 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-10-13 17:46:01,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1376 transitions. [2024-10-13 17:46:01,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-13 17:46:01,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.47481243301179) internal successors, (1376), 932 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1376 transitions. [2024-10-13 17:46:01,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-10-13 17:46:01,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,311 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-10-13 17:46:01,311 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-13 17:46:01,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1376 transitions. [2024-10-13 17:46:01,314 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-13 17:46:01,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,315 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,315 INFO L745 eck$LassoCheckResult]: Stem: 17123#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 17124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17750#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17751#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17752#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17242#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17243#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17748#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17744#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17314#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17315#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17549#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17550#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17398#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17399#L838 assume !(0 == ~M_E~0); 17558#L838-2 assume !(0 == ~T1_E~0); 16922#L843-1 assume !(0 == ~T2_E~0); 16923#L848-1 assume !(0 == ~T3_E~0); 17043#L853-1 assume !(0 == ~T4_E~0); 17387#L858-1 assume !(0 == ~T5_E~0); 16873#L863-1 assume !(0 == ~T6_E~0); 16874#L868-1 assume !(0 == ~T7_E~0); 17780#L873-1 assume !(0 == ~T8_E~0); 17778#L878-1 assume !(0 == ~E_1~0); 17769#L883-1 assume !(0 == ~E_2~0); 17770#L888-1 assume !(0 == ~E_3~0); 17518#L893-1 assume !(0 == ~E_4~0); 17519#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17790#L903-1 assume !(0 == ~E_6~0); 17767#L908-1 assume !(0 == ~E_7~0); 17648#L913-1 assume !(0 == ~E_8~0); 16935#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16936#L402 assume !(1 == ~m_pc~0); 17148#L402-2 is_master_triggered_~__retres1~0#1 := 0; 17067#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17068#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17320#L1035 assume !(0 != activate_threads_~tmp~1#1); 17321#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17373#L421 assume 1 == ~t1_pc~0; 17763#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17784#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16937#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16938#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 17427#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17788#L440 assume 1 == ~t2_pc~0; 16906#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16907#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17268#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 17663#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17275#L459 assume !(1 == ~t3_pc~0); 17276#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17761#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16895#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16896#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17062#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17071#L478 assume 1 == ~t4_pc~0; 17072#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17523#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17015#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17016#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 16978#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16979#L497 assume !(1 == ~t5_pc~0); 17026#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17027#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17594#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17700#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 17757#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17758#L516 assume 1 == ~t6_pc~0; 17804#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17548#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17251#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17117#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 17118#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17537#L535 assume !(1 == ~t7_pc~0); 17538#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17608#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17609#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17640#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 17630#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17631#L554 assume 1 == ~t8_pc~0; 17573#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16898#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17656#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17208#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17209#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16884#L931 assume !(1 == ~M_E~0); 16885#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17776#L936-1 assume !(1 == ~T2_E~0); 17795#L941-1 assume !(1 == ~T3_E~0); 17374#L946-1 assume !(1 == ~T4_E~0); 17375#L951-1 assume !(1 == ~T5_E~0); 17132#L956-1 assume !(1 == ~T6_E~0); 17133#L961-1 assume !(1 == ~T7_E~0); 17520#L966-1 assume !(1 == ~T8_E~0); 17521#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17633#L976-1 assume !(1 == ~E_2~0); 17598#L981-1 assume !(1 == ~E_3~0); 17378#L986-1 assume !(1 == ~E_4~0); 17159#L991-1 assume !(1 == ~E_5~0); 17160#L996-1 assume !(1 == ~E_6~0); 17785#L1001-1 assume !(1 == ~E_7~0); 17568#L1006-1 assume !(1 == ~E_8~0); 17569#L1011-1 assume { :end_inline_reset_delta_events } true; 16945#L1272-2 [2024-10-13 17:46:01,315 INFO L747 eck$LassoCheckResult]: Loop: 16945#L1272-2 assume !false; 16946#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17184#L813-1 assume !false; 17718#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17719#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16948#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17287#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17288#L696 assume !(0 != eval_~tmp~0#1); 17661#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17429#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17617#L838-5 assume !(0 == ~T1_E~0); 17618#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17471#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17472#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17522#L858-3 assume !(0 == ~T5_E~0); 17587#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17578#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17579#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17188#L878-3 assume !(0 == ~E_1~0); 16909#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16910#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16911#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16912#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17404#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17722#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17412#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16950#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16951#L402-27 assume 1 == ~m_pc~0; 16899#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16900#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17610#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17611#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17737#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17738#L421-27 assume !(1 == ~t1_pc~0); 17176#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 17177#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17496#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17497#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17786#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17540#L440-27 assume !(1 == ~t2_pc~0); 17541#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 17714#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17582#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17447#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 17448#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17162#L459-27 assume 1 == ~t3_pc~0; 17163#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17603#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17424#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17425#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17536#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17779#L478-27 assume 1 == ~t4_pc~0; 17798#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17335#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17336#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17685#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17720#L497-27 assume 1 == ~t5_pc~0; 17721#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17195#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17196#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17138#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17139#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17405#L516-27 assume !(1 == ~t6_pc~0); 17406#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 17252#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17253#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17559#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17560#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17339#L535-27 assume 1 == ~t7_pc~0; 17340#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17667#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17219#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17220#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17290#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17291#L554-27 assume 1 == ~t8_pc~0; 17493#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16925#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17076#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17453#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17181#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17182#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17058#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17059#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17289#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17423#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17199#L951-3 assume !(1 == ~T5_E~0); 17200#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17494#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17299#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17300#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17547#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16943#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16944#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16932#L991-3 assume !(1 == ~E_5~0); 16933#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17623#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17273#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17274#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16971#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16972#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17221#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 17222#L1291 assume !(0 == start_simulation_~tmp~3#1); 17491#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17392#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16877#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 16934#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17359#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17360#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 17446#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 16945#L1272-2 [2024-10-13 17:46:01,316 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,316 INFO L85 PathProgramCache]: Analyzing trace with hash 623392352, now seen corresponding path program 1 times [2024-10-13 17:46:01,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319259171] [2024-10-13 17:46:01,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,376 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319259171] [2024-10-13 17:46:01,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319259171] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,376 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,376 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858013419] [2024-10-13 17:46:01,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,376 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,377 INFO L85 PathProgramCache]: Analyzing trace with hash 1033471826, now seen corresponding path program 1 times [2024-10-13 17:46:01,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182908506] [2024-10-13 17:46:01,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182908506] [2024-10-13 17:46:01,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [182908506] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,418 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,418 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286475316] [2024-10-13 17:46:01,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,419 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,419 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:46:01,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:46:01,419 INFO L87 Difference]: Start difference. First operand 933 states and 1376 transitions. cyclomatic complexity: 444 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,553 INFO L93 Difference]: Finished difference Result 1704 states and 2511 transitions. [2024-10-13 17:46:01,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1704 states and 2511 transitions. [2024-10-13 17:46:01,559 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2024-10-13 17:46:01,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1704 states to 1704 states and 2511 transitions. [2024-10-13 17:46:01,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1704 [2024-10-13 17:46:01,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1704 [2024-10-13 17:46:01,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1704 states and 2511 transitions. [2024-10-13 17:46:01,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1704 states and 2511 transitions. [2024-10-13 17:46:01,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1704 states and 2511 transitions. [2024-10-13 17:46:01,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1704 to 1703. [2024-10-13 17:46:01,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1703 states, 1703 states have (on average 1.473869641808573) internal successors, (2510), 1702 states have internal predecessors, (2510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1703 states to 1703 states and 2510 transitions. [2024-10-13 17:46:01,590 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2024-10-13 17:46:01,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:46:01,592 INFO L425 stractBuchiCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2024-10-13 17:46:01,592 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-13 17:46:01,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1703 states and 2510 transitions. [2024-10-13 17:46:01,597 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2024-10-13 17:46:01,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,598 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,598 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,598 INFO L745 eck$LassoCheckResult]: Stem: 19770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 19771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20418#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20419#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 19889#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19890#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20415#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20409#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19963#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19964#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20207#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20208#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 20048#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20049#L838 assume !(0 == ~M_E~0); 20215#L838-2 assume !(0 == ~T1_E~0); 19569#L843-1 assume !(0 == ~T2_E~0); 19570#L848-1 assume !(0 == ~T3_E~0); 19690#L853-1 assume !(0 == ~T4_E~0); 20035#L858-1 assume !(0 == ~T5_E~0); 19520#L863-1 assume !(0 == ~T6_E~0); 19521#L868-1 assume !(0 == ~T7_E~0); 20452#L873-1 assume !(0 == ~T8_E~0); 20450#L878-1 assume !(0 == ~E_1~0); 20438#L883-1 assume !(0 == ~E_2~0); 20439#L888-1 assume !(0 == ~E_3~0); 20175#L893-1 assume !(0 == ~E_4~0); 20176#L898-1 assume !(0 == ~E_5~0); 20464#L903-1 assume !(0 == ~E_6~0); 20436#L908-1 assume !(0 == ~E_7~0); 20306#L913-1 assume !(0 == ~E_8~0); 19581#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19582#L402 assume !(1 == ~m_pc~0); 19793#L402-2 is_master_triggered_~__retres1~0#1 := 0; 19714#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19715#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19969#L1035 assume !(0 != activate_threads_~tmp~1#1); 19970#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20023#L421 assume 1 == ~t1_pc~0; 20432#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20453#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19584#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19585#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 20079#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20462#L440 assume 1 == ~t2_pc~0; 19553#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19554#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19915#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 20325#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19918#L459 assume !(1 == ~t3_pc~0); 19919#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20428#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19542#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19543#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19709#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19718#L478 assume 1 == ~t4_pc~0; 19719#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20180#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19662#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19663#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 19623#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19624#L497 assume !(1 == ~t5_pc~0); 19673#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19674#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20252#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20363#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 20424#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20425#L516 assume 1 == ~t6_pc~0; 20486#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20206#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19898#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19764#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 19765#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20195#L535 assume !(1 == ~t7_pc~0); 20196#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20266#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20298#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 20288#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20289#L554 assume 1 == ~t8_pc~0; 20231#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19545#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19852#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 19853#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19531#L931 assume !(1 == ~M_E~0); 19532#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20447#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20473#L941-1 assume !(1 == ~T3_E~0); 20024#L946-1 assume !(1 == ~T4_E~0); 20025#L951-1 assume !(1 == ~T5_E~0); 19779#L956-1 assume !(1 == ~T6_E~0); 19780#L961-1 assume !(1 == ~T7_E~0); 20177#L966-1 assume !(1 == ~T8_E~0); 20178#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20291#L976-1 assume !(1 == ~E_2~0); 20256#L981-1 assume !(1 == ~E_3~0); 20028#L986-1 assume !(1 == ~E_4~0); 19806#L991-1 assume !(1 == ~E_5~0); 19807#L996-1 assume !(1 == ~E_6~0); 20457#L1001-1 assume !(1 == ~E_7~0); 20226#L1006-1 assume !(1 == ~E_8~0); 20227#L1011-1 assume { :end_inline_reset_delta_events } true; 20505#L1272-2 [2024-10-13 17:46:01,599 INFO L747 eck$LassoCheckResult]: Loop: 20505#L1272-2 assume !false; 20501#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20476#L813-1 assume !false; 20477#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20499#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20172#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19934#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19935#L696 assume !(0 != eval_~tmp~0#1); 20322#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20323#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20412#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20413#L838-5 assume !(0 == ~T1_E~0); 20489#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20123#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20124#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20179#L858-3 assume !(0 == ~T5_E~0); 20245#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20235#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20236#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19833#L878-3 assume !(0 == ~E_1~0); 19556#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19557#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19558#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19559#L898-3 assume !(0 == ~E_5~0); 20054#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20383#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20063#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19597#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19598#L402-27 assume 1 == ~m_pc~0; 19546#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19547#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20268#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20269#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20402#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20403#L421-27 assume 1 == ~t1_pc~0; 20304#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19824#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20151#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20152#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20458#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20198#L440-27 assume !(1 == ~t2_pc~0); 20199#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 20378#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20240#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20099#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 20100#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19809#L459-27 assume 1 == ~t3_pc~0; 19810#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20261#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20075#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20076#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20194#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20451#L478-27 assume !(1 == ~t4_pc~0); 19798#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 19799#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19984#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19985#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20347#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20384#L497-27 assume 1 == ~t5_pc~0; 20385#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19842#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19843#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19785#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19786#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20056#L516-27 assume !(1 == ~t6_pc~0); 20057#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 19906#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19907#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20217#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20218#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19988#L535-27 assume 1 == ~t7_pc~0; 19989#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20331#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19866#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19867#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19938#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19939#L554-27 assume !(1 == ~t8_pc~0); 19571#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 19572#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19723#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20108#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19830#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19831#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19705#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19706#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19937#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20074#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19846#L951-3 assume !(1 == ~T5_E~0); 19847#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20149#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19948#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19949#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20205#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19590#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19591#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19579#L991-3 assume !(1 == ~E_5~0); 19580#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20281#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19923#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19924#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19618#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19619#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20078#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 20537#L1291 assume !(0 == start_simulation_~tmp~3#1); 20535#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20534#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20524#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20523#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 20442#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20009#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20010#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20098#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 20505#L1272-2 [2024-10-13 17:46:01,599 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1671526308, now seen corresponding path program 1 times [2024-10-13 17:46:01,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913888183] [2024-10-13 17:46:01,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913888183] [2024-10-13 17:46:01,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913888183] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:01,656 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993538461] [2024-10-13 17:46:01,656 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,657 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,657 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,657 INFO L85 PathProgramCache]: Analyzing trace with hash -2131409869, now seen corresponding path program 1 times [2024-10-13 17:46:01,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163224129] [2024-10-13 17:46:01,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,689 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163224129] [2024-10-13 17:46:01,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163224129] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995374344] [2024-10-13 17:46:01,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,690 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,691 INFO L87 Difference]: Start difference. First operand 1703 states and 2510 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:01,771 INFO L93 Difference]: Finished difference Result 3128 states and 4579 transitions. [2024-10-13 17:46:01,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3128 states and 4579 transitions. [2024-10-13 17:46:01,781 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2997 [2024-10-13 17:46:01,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3128 states to 3128 states and 4579 transitions. [2024-10-13 17:46:01,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3128 [2024-10-13 17:46:01,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3128 [2024-10-13 17:46:01,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3128 states and 4579 transitions. [2024-10-13 17:46:01,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:01,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3128 states and 4579 transitions. [2024-10-13 17:46:01,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3128 states and 4579 transitions. [2024-10-13 17:46:01,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3128 to 3124. [2024-10-13 17:46:01,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3124 states, 3124 states have (on average 1.4644686299615877) internal successors, (4575), 3123 states have internal predecessors, (4575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:01,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3124 states to 3124 states and 4575 transitions. [2024-10-13 17:46:01,846 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3124 states and 4575 transitions. [2024-10-13 17:46:01,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:01,847 INFO L425 stractBuchiCegarLoop]: Abstraction has 3124 states and 4575 transitions. [2024-10-13 17:46:01,847 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-13 17:46:01,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3124 states and 4575 transitions. [2024-10-13 17:46:01,858 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2993 [2024-10-13 17:46:01,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:01,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:01,860 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,860 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:01,861 INFO L745 eck$LassoCheckResult]: Stem: 24613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 24614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25349#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25350#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25351#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 24735#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24736#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25341#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25335#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24819#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24820#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25079#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25080#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24911#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24912#L838 assume !(0 == ~M_E~0); 25087#L838-2 assume !(0 == ~T1_E~0); 24407#L843-1 assume !(0 == ~T2_E~0); 24408#L848-1 assume !(0 == ~T3_E~0); 24530#L853-1 assume !(0 == ~T4_E~0); 24898#L858-1 assume !(0 == ~T5_E~0); 24358#L863-1 assume !(0 == ~T6_E~0); 24359#L868-1 assume !(0 == ~T7_E~0); 25407#L873-1 assume !(0 == ~T8_E~0); 25404#L878-1 assume !(0 == ~E_1~0); 25379#L883-1 assume !(0 == ~E_2~0); 25380#L888-1 assume !(0 == ~E_3~0); 25047#L893-1 assume !(0 == ~E_4~0); 25048#L898-1 assume !(0 == ~E_5~0); 25422#L903-1 assume !(0 == ~E_6~0); 25375#L908-1 assume !(0 == ~E_7~0); 25197#L913-1 assume !(0 == ~E_8~0); 24420#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24421#L402 assume !(1 == ~m_pc~0); 24636#L402-2 is_master_triggered_~__retres1~0#1 := 0; 24554#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24555#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24826#L1035 assume !(0 != activate_threads_~tmp~1#1); 24827#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24885#L421 assume !(1 == ~t1_pc~0); 25371#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25408#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24424#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24425#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 24941#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25419#L440 assume 1 == ~t2_pc~0; 24391#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24392#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24564#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24762#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 25215#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24765#L459 assume !(1 == ~t3_pc~0); 24766#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25362#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24380#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24381#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24549#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24558#L478 assume 1 == ~t4_pc~0; 24559#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25052#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24502#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24503#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 24462#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24463#L497 assume !(1 == ~t5_pc~0); 24513#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24514#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25131#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25265#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 25357#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25358#L516 assume 1 == ~t6_pc~0; 25454#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25078#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24745#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24607#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 24608#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25067#L535 assume !(1 == ~t7_pc~0); 25068#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25146#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25147#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25186#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 25174#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25175#L554 assume 1 == ~t8_pc~0; 25105#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24383#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25207#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24695#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 24696#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24369#L931 assume !(1 == ~M_E~0); 24370#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25397#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25430#L941-1 assume !(1 == ~T3_E~0); 24886#L946-1 assume !(1 == ~T4_E~0); 24887#L951-1 assume !(1 == ~T5_E~0); 24622#L956-1 assume !(1 == ~T6_E~0); 24623#L961-1 assume !(1 == ~T7_E~0); 25049#L966-1 assume !(1 == ~T8_E~0); 25050#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 25178#L976-1 assume !(1 == ~E_2~0); 25135#L981-1 assume !(1 == ~E_3~0); 25136#L986-1 assume !(1 == ~E_4~0); 24649#L991-1 assume !(1 == ~E_5~0); 24650#L996-1 assume !(1 == ~E_6~0); 25412#L1001-1 assume !(1 == ~E_7~0); 25413#L1006-1 assume !(1 == ~E_8~0); 25369#L1011-1 assume { :end_inline_reset_delta_events } true; 25243#L1272-2 [2024-10-13 17:46:01,861 INFO L747 eck$LassoCheckResult]: Loop: 25243#L1272-2 assume !false; 25093#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24670#L813-1 assume !false; 25433#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26690#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25044#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24783#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24784#L696 assume !(0 != eval_~tmp~0#1); 26680#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26679#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26678#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26677#L838-5 assume !(0 == ~T1_E~0); 26674#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26675#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27404#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27403#L858-3 assume !(0 == ~T5_E~0); 27402#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27401#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27400#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27399#L878-3 assume !(0 == ~E_1~0); 27398#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27397#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27396#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27395#L898-3 assume !(0 == ~E_5~0); 27394#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27393#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27392#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27391#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27390#L402-27 assume 1 == ~m_pc~0; 27388#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27387#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27386#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27385#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27384#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27383#L421-27 assume !(1 == ~t1_pc~0); 27382#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 27381#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27380#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27379#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27378#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27377#L440-27 assume !(1 == ~t2_pc~0); 27376#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 27374#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27373#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27372#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 27371#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27370#L459-27 assume 1 == ~t3_pc~0; 27368#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27367#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27366#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27365#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27364#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27363#L478-27 assume 1 == ~t4_pc~0; 27361#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27360#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27359#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27358#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27357#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27356#L497-27 assume 1 == ~t5_pc~0; 27354#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27353#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27352#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27351#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27350#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27349#L516-27 assume !(1 == ~t6_pc~0); 27347#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 27346#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27345#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27344#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27343#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27342#L535-27 assume 1 == ~t7_pc~0; 27340#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27339#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27338#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27337#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27336#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27335#L554-27 assume !(1 == ~t8_pc~0); 27333#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 27332#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27331#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27330#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27329#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27328#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27327#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27326#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24787#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27325#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27324#L951-3 assume !(1 == ~T5_E~0); 27323#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27322#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27321#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27320#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27319#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27318#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27317#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27316#L991-3 assume !(1 == ~E_5~0); 26009#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27315#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27314#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27313#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 27311#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 27303#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 27302#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 27300#L1291 assume !(0 == start_simulation_~tmp~3#1); 27298#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24907#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24482#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24422#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 24423#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24867#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24868#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25242#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 25243#L1272-2 [2024-10-13 17:46:01,861 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,861 INFO L85 PathProgramCache]: Analyzing trace with hash 493551747, now seen corresponding path program 1 times [2024-10-13 17:46:01,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842963669] [2024-10-13 17:46:01,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842963669] [2024-10-13 17:46:01,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842963669] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:01,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973573847] [2024-10-13 17:46:01,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,901 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:01,901 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:01,901 INFO L85 PathProgramCache]: Analyzing trace with hash -1502078349, now seen corresponding path program 1 times [2024-10-13 17:46:01,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:01,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753141104] [2024-10-13 17:46:01,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:01,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:01,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:01,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:01,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:01,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753141104] [2024-10-13 17:46:01,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [753141104] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:01,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:01,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:01,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917689174] [2024-10-13 17:46:01,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:01,936 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:01,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:01,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:01,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:01,937 INFO L87 Difference]: Start difference. First operand 3124 states and 4575 transitions. cyclomatic complexity: 1455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,015 INFO L93 Difference]: Finished difference Result 5826 states and 8485 transitions. [2024-10-13 17:46:02,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5826 states and 8485 transitions. [2024-10-13 17:46:02,086 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5684 [2024-10-13 17:46:02,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5826 states to 5826 states and 8485 transitions. [2024-10-13 17:46:02,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5826 [2024-10-13 17:46:02,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5826 [2024-10-13 17:46:02,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5826 states and 8485 transitions. [2024-10-13 17:46:02,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:02,116 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5826 states and 8485 transitions. [2024-10-13 17:46:02,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5826 states and 8485 transitions. [2024-10-13 17:46:02,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5826 to 5818. [2024-10-13 17:46:02,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5818 states, 5818 states have (on average 1.4570299071845996) internal successors, (8477), 5817 states have internal predecessors, (8477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5818 states to 5818 states and 8477 transitions. [2024-10-13 17:46:02,191 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5818 states and 8477 transitions. [2024-10-13 17:46:02,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:02,192 INFO L425 stractBuchiCegarLoop]: Abstraction has 5818 states and 8477 transitions. [2024-10-13 17:46:02,192 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-13 17:46:02,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5818 states and 8477 transitions. [2024-10-13 17:46:02,205 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5676 [2024-10-13 17:46:02,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:02,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:02,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,207 INFO L745 eck$LassoCheckResult]: Stem: 33564#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 33565#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 34233#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34234#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34235#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 33682#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33683#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34231#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34225#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33758#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33759#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33999#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34000#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33843#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33844#L838 assume !(0 == ~M_E~0); 34007#L838-2 assume !(0 == ~T1_E~0); 33363#L843-1 assume !(0 == ~T2_E~0); 33364#L848-1 assume !(0 == ~T3_E~0); 33482#L853-1 assume !(0 == ~T4_E~0); 33830#L858-1 assume !(0 == ~T5_E~0); 33315#L863-1 assume !(0 == ~T6_E~0); 33316#L868-1 assume !(0 == ~T7_E~0); 34277#L873-1 assume !(0 == ~T8_E~0); 34274#L878-1 assume !(0 == ~E_1~0); 34256#L883-1 assume !(0 == ~E_2~0); 34257#L888-1 assume !(0 == ~E_3~0); 33968#L893-1 assume !(0 == ~E_4~0); 33969#L898-1 assume !(0 == ~E_5~0); 34293#L903-1 assume !(0 == ~E_6~0); 34254#L908-1 assume !(0 == ~E_7~0); 34109#L913-1 assume !(0 == ~E_8~0); 33375#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33376#L402 assume !(1 == ~m_pc~0); 33589#L402-2 is_master_triggered_~__retres1~0#1 := 0; 33507#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33508#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33764#L1035 assume !(0 != activate_threads_~tmp~1#1); 33765#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33818#L421 assume !(1 == ~t1_pc~0); 34251#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34278#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33378#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33379#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 33872#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34290#L440 assume !(1 == ~t2_pc~0); 34326#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33517#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33708#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 34126#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33711#L459 assume !(1 == ~t3_pc~0); 33712#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34246#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33337#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33338#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33501#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33511#L478 assume 1 == ~t4_pc~0; 33512#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33973#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33454#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33455#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 33416#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33417#L497 assume !(1 == ~t5_pc~0); 33465#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33466#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34049#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34170#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 34241#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34242#L516 assume 1 == ~t6_pc~0; 34320#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33998#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33692#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33558#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 33559#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33988#L535 assume !(1 == ~t7_pc~0); 33989#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34063#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34064#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34100#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 34090#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34091#L554 assume 1 == ~t8_pc~0; 34024#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33340#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34118#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33644#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 33645#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33326#L931 assume !(1 == ~M_E~0); 33327#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34268#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34301#L941-1 assume !(1 == ~T3_E~0); 33819#L946-1 assume !(1 == ~T4_E~0); 33820#L951-1 assume !(1 == ~T5_E~0); 33573#L956-1 assume !(1 == ~T6_E~0); 33574#L961-1 assume !(1 == ~T7_E~0); 33970#L966-1 assume !(1 == ~T8_E~0); 33971#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 34093#L976-1 assume !(1 == ~E_2~0); 34053#L981-1 assume !(1 == ~E_3~0); 33823#L986-1 assume !(1 == ~E_4~0); 33600#L991-1 assume !(1 == ~E_5~0); 33601#L996-1 assume !(1 == ~E_6~0); 34285#L1001-1 assume !(1 == ~E_7~0); 34018#L1006-1 assume !(1 == ~E_8~0); 34019#L1011-1 assume { :end_inline_reset_delta_events } true; 34249#L1272-2 [2024-10-13 17:46:02,207 INFO L747 eck$LassoCheckResult]: Loop: 34249#L1272-2 assume !false; 38515#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38514#L813-1 assume !false; 34192#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 34193#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 33389#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 33727#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33728#L696 assume !(0 != eval_~tmp~0#1); 34203#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36825#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36826#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37071#L838-5 assume !(0 == ~T1_E~0); 34296#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33918#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33919#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33972#L858-3 assume !(0 == ~T5_E~0); 34041#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34029#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34030#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33625#L878-3 assume !(0 == ~E_1~0); 33350#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33351#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33352#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33353#L898-3 assume !(0 == ~E_5~0); 33849#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34194#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33857#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33391#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33392#L402-27 assume 1 == ~m_pc~0; 33341#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33342#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34065#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34066#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34217#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34218#L421-27 assume !(1 == ~t1_pc~0); 33615#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 33616#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33945#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33946#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34286#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33991#L440-27 assume !(1 == ~t2_pc~0); 33992#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 34189#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34036#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33894#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 33895#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33603#L459-27 assume 1 == ~t3_pc~0; 33604#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34058#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33869#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33870#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33987#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34276#L478-27 assume 1 == ~t4_pc~0; 34306#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33593#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33779#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33780#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34154#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34195#L497-27 assume 1 == ~t5_pc~0; 34196#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33635#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33636#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33579#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33580#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33851#L516-27 assume !(1 == ~t6_pc~0); 33852#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 33699#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33700#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34009#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34010#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33783#L535-27 assume 1 == ~t7_pc~0; 33784#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34132#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33660#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33661#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33731#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33732#L554-27 assume !(1 == ~t8_pc~0); 33365#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 33366#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33516#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33903#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33622#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33623#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33497#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33498#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33729#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33868#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33638#L951-3 assume !(1 == ~T5_E~0); 33639#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33942#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33743#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33744#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33997#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33384#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33385#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33373#L991-3 assume !(1 == ~E_5~0); 33374#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34079#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33716#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33717#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 33411#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 33412#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 33666#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 33667#L1291 assume !(0 == start_simulation_~tmp~3#1); 34291#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38631#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38621#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38620#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 38619#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38616#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38614#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 38612#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 34249#L1272-2 [2024-10-13 17:46:02,207 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1412932446, now seen corresponding path program 1 times [2024-10-13 17:46:02,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391968692] [2024-10-13 17:46:02,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391968692] [2024-10-13 17:46:02,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [391968692] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:02,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963405670] [2024-10-13 17:46:02,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,249 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:02,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1502078349, now seen corresponding path program 2 times [2024-10-13 17:46:02,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425176928] [2024-10-13 17:46:02,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425176928] [2024-10-13 17:46:02,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425176928] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685381894] [2024-10-13 17:46:02,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,276 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:02,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:02,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:02,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:02,276 INFO L87 Difference]: Start difference. First operand 5818 states and 8477 transitions. cyclomatic complexity: 2667 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,451 INFO L93 Difference]: Finished difference Result 6025 states and 8684 transitions. [2024-10-13 17:46:02,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6025 states and 8684 transitions. [2024-10-13 17:46:02,475 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5880 [2024-10-13 17:46:02,499 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6025 states to 6025 states and 8684 transitions. [2024-10-13 17:46:02,500 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6025 [2024-10-13 17:46:02,503 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6025 [2024-10-13 17:46:02,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6025 states and 8684 transitions. [2024-10-13 17:46:02,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:02,510 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-10-13 17:46:02,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6025 states and 8684 transitions. [2024-10-13 17:46:02,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6025 to 6025. [2024-10-13 17:46:02,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6025 states, 6025 states have (on average 1.4413278008298755) internal successors, (8684), 6024 states have internal predecessors, (8684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6025 states to 6025 states and 8684 transitions. [2024-10-13 17:46:02,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-10-13 17:46:02,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:02,662 INFO L425 stractBuchiCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-10-13 17:46:02,663 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-13 17:46:02,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6025 states and 8684 transitions. [2024-10-13 17:46:02,679 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5880 [2024-10-13 17:46:02,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:02,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:02,680 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:02,681 INFO L745 eck$LassoCheckResult]: Stem: 45414#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 45415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 46114#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46115#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46117#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 45532#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45533#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46109#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46096#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45614#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45615#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45861#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45862#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45700#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45701#L838 assume !(0 == ~M_E~0); 45871#L838-2 assume !(0 == ~T1_E~0); 45213#L843-1 assume !(0 == ~T2_E~0); 45214#L848-1 assume !(0 == ~T3_E~0); 45333#L853-1 assume !(0 == ~T4_E~0); 45689#L858-1 assume !(0 == ~T5_E~0); 45169#L863-1 assume !(0 == ~T6_E~0); 45170#L868-1 assume !(0 == ~T7_E~0); 46164#L873-1 assume !(0 == ~T8_E~0); 46157#L878-1 assume !(0 == ~E_1~0); 46142#L883-1 assume !(0 == ~E_2~0); 46143#L888-1 assume !(0 == ~E_3~0); 45830#L893-1 assume !(0 == ~E_4~0); 45831#L898-1 assume !(0 == ~E_5~0); 46183#L903-1 assume !(0 == ~E_6~0); 46139#L908-1 assume !(0 == ~E_7~0); 45971#L913-1 assume !(0 == ~E_8~0); 45227#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45228#L402 assume !(1 == ~m_pc~0); 45441#L402-2 is_master_triggered_~__retres1~0#1 := 0; 45358#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45359#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45621#L1035 assume !(0 != activate_threads_~tmp~1#1); 45622#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45674#L421 assume !(1 == ~t1_pc~0); 46135#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46168#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45229#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45230#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 45731#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46178#L440 assume !(1 == ~t2_pc~0); 46226#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45368#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45369#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45560#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 45994#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45567#L459 assume !(1 == ~t3_pc~0); 45568#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46131#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45189#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45190#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 45352#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45362#L478 assume 1 == ~t4_pc~0; 45363#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45834#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45305#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45306#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 45269#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45270#L497 assume !(1 == ~t5_pc~0); 45316#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45317#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45910#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46041#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 46126#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46127#L516 assume 1 == ~t6_pc~0; 46216#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45860#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45542#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45408#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 45409#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45849#L535 assume !(1 == ~t7_pc~0); 45850#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45924#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45925#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45963#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 45954#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45955#L554 assume 1 == ~t8_pc~0; 45887#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45192#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45982#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45499#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 45500#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45178#L931 assume !(1 == ~M_E~0); 45179#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46151#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46192#L941-1 assume !(1 == ~T3_E~0); 45675#L946-1 assume !(1 == ~T4_E~0); 45676#L951-1 assume !(1 == ~T5_E~0); 45423#L956-1 assume !(1 == ~T6_E~0); 45424#L961-1 assume !(1 == ~T7_E~0); 45832#L966-1 assume !(1 == ~T8_E~0); 45833#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45956#L976-1 assume !(1 == ~E_2~0); 45914#L981-1 assume !(1 == ~E_3~0); 45679#L986-1 assume !(1 == ~E_4~0); 45680#L991-1 assume !(1 == ~E_5~0); 45451#L996-1 assume !(1 == ~E_6~0); 46172#L1001-1 assume !(1 == ~E_7~0); 46173#L1006-1 assume !(1 == ~E_8~0); 48306#L1011-1 assume { :end_inline_reset_delta_events } true; 48302#L1272-2 [2024-10-13 17:46:02,681 INFO L747 eck$LassoCheckResult]: Loop: 48302#L1272-2 assume !false; 48300#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47962#L813-1 assume !false; 47963#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 47949#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 47942#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 45580#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45581#L696 assume !(0 != eval_~tmp~0#1); 46073#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50316#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50314#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50312#L838-5 assume !(0 == ~T1_E~0); 50295#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50294#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50292#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50290#L858-3 assume !(0 == ~T5_E~0); 50288#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50279#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50277#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50276#L878-3 assume !(0 == ~E_1~0); 50274#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50273#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50255#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50254#L898-3 assume !(0 == ~E_5~0); 50253#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50252#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50251#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50250#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50248#L402-27 assume 1 == ~m_pc~0; 50245#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50244#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45926#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45927#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46091#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46092#L421-27 assume !(1 == ~t1_pc~0); 46108#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 50054#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50053#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49755#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49746#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45852#L440-27 assume !(1 == ~t2_pc~0); 45853#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 50249#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50247#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49823#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 49820#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49819#L459-27 assume !(1 == ~t3_pc~0); 49817#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 49815#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49813#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49812#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 49810#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49809#L478-27 assume !(1 == ~t4_pc~0); 49808#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 49806#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49798#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49797#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49796#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49794#L497-27 assume 1 == ~t5_pc~0; 49792#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49791#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49790#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49789#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49788#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49787#L516-27 assume !(1 == ~t6_pc~0); 49785#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 49784#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49783#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49782#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49781#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49779#L535-27 assume 1 == ~t7_pc~0; 49776#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49775#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49774#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49773#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49771#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49769#L554-27 assume !(1 == ~t8_pc~0); 49766#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 49764#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49762#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49760#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49758#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49756#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49607#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49593#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48670#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48666#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48662#L951-3 assume !(1 == ~T5_E~0); 48656#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48650#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48646#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48642#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48638#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48634#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48630#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48624#L991-3 assume !(1 == ~E_5~0); 48621#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48618#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48378#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48377#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48340#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 48331#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 48329#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 48327#L1291 assume !(0 == start_simulation_~tmp~3#1); 48325#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48324#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 48315#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 48314#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 48313#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48312#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48311#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 48305#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 48302#L1272-2 [2024-10-13 17:46:02,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,682 INFO L85 PathProgramCache]: Analyzing trace with hash -1894012704, now seen corresponding path program 1 times [2024-10-13 17:46:02,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229756385] [2024-10-13 17:46:02,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229756385] [2024-10-13 17:46:02,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [229756385] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,715 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:02,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281179337] [2024-10-13 17:46:02,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,716 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:02,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:02,716 INFO L85 PathProgramCache]: Analyzing trace with hash 387702447, now seen corresponding path program 1 times [2024-10-13 17:46:02,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:02,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147450894] [2024-10-13 17:46:02,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:02,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:02,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:02,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:02,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:02,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147450894] [2024-10-13 17:46:02,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147450894] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:02,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:02,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:02,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382923490] [2024-10-13 17:46:02,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:02,754 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:02,755 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:02,755 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:02,755 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:02,755 INFO L87 Difference]: Start difference. First operand 6025 states and 8684 transitions. cyclomatic complexity: 2667 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:02,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:02,842 INFO L93 Difference]: Finished difference Result 11580 states and 16593 transitions. [2024-10-13 17:46:02,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11580 states and 16593 transitions. [2024-10-13 17:46:02,886 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11404 [2024-10-13 17:46:03,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11580 states to 11580 states and 16593 transitions. [2024-10-13 17:46:03,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11580 [2024-10-13 17:46:03,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11580 [2024-10-13 17:46:03,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11580 states and 16593 transitions. [2024-10-13 17:46:03,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:03,025 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11580 states and 16593 transitions. [2024-10-13 17:46:03,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11580 states and 16593 transitions. [2024-10-13 17:46:03,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11580 to 11564. [2024-10-13 17:46:03,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11564 states, 11564 states have (on average 1.4335005188516083) internal successors, (16577), 11563 states have internal predecessors, (16577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:03,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11564 states to 11564 states and 16577 transitions. [2024-10-13 17:46:03,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11564 states and 16577 transitions. [2024-10-13 17:46:03,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:03,186 INFO L425 stractBuchiCegarLoop]: Abstraction has 11564 states and 16577 transitions. [2024-10-13 17:46:03,186 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-13 17:46:03,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11564 states and 16577 transitions. [2024-10-13 17:46:03,270 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11388 [2024-10-13 17:46:03,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:03,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:03,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:03,273 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:03,273 INFO L745 eck$LassoCheckResult]: Stem: 63027#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 63028#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 63721#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63722#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63724#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 63147#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63148#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63715#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63706#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63223#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63224#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63469#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63470#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63310#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63311#L838 assume !(0 == ~M_E~0); 63479#L838-2 assume !(0 == ~T1_E~0); 62827#L843-1 assume !(0 == ~T2_E~0); 62828#L848-1 assume !(0 == ~T3_E~0); 62946#L853-1 assume !(0 == ~T4_E~0); 63297#L858-1 assume !(0 == ~T5_E~0); 62779#L863-1 assume !(0 == ~T6_E~0); 62780#L868-1 assume !(0 == ~T7_E~0); 63778#L873-1 assume !(0 == ~T8_E~0); 63773#L878-1 assume !(0 == ~E_1~0); 63751#L883-1 assume !(0 == ~E_2~0); 63752#L888-1 assume !(0 == ~E_3~0); 63438#L893-1 assume !(0 == ~E_4~0); 63439#L898-1 assume !(0 == ~E_5~0); 63797#L903-1 assume !(0 == ~E_6~0); 63749#L908-1 assume !(0 == ~E_7~0); 63576#L913-1 assume !(0 == ~E_8~0); 62839#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62840#L402 assume !(1 == ~m_pc~0); 63051#L402-2 is_master_triggered_~__retres1~0#1 := 0; 62972#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62973#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63230#L1035 assume !(0 != activate_threads_~tmp~1#1); 63231#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63285#L421 assume !(1 == ~t1_pc~0); 63742#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63779#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62842#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62843#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 63341#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63791#L440 assume !(1 == ~t2_pc~0); 63833#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62981#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63174#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 63599#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63177#L459 assume !(1 == ~t3_pc~0); 63178#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63739#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62801#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62802#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 62967#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62976#L478 assume !(1 == ~t4_pc~0); 62977#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63655#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62918#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62919#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 62880#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62881#L497 assume !(1 == ~t5_pc~0); 62929#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62930#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63518#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63650#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 63732#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63733#L516 assume 1 == ~t6_pc~0; 63826#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63468#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63157#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63021#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 63022#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63457#L535 assume !(1 == ~t7_pc~0); 63458#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 63532#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63533#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63567#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 63557#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63558#L554 assume 1 == ~t8_pc~0; 63495#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62804#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63587#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63109#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 63110#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62790#L931 assume !(1 == ~M_E~0); 62791#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63764#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63807#L941-1 assume !(1 == ~T3_E~0); 69830#L946-1 assume !(1 == ~T4_E~0); 69829#L951-1 assume !(1 == ~T5_E~0); 69828#L956-1 assume !(1 == ~T6_E~0); 69827#L961-1 assume !(1 == ~T7_E~0); 69826#L966-1 assume !(1 == ~T8_E~0); 69825#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 69824#L976-1 assume !(1 == ~E_2~0); 69823#L981-1 assume !(1 == ~E_3~0); 69822#L986-1 assume !(1 == ~E_4~0); 69821#L991-1 assume !(1 == ~E_5~0); 63065#L996-1 assume !(1 == ~E_6~0); 69820#L1001-1 assume !(1 == ~E_7~0); 69819#L1006-1 assume !(1 == ~E_8~0); 69818#L1011-1 assume { :end_inline_reset_delta_events } true; 69816#L1272-2 [2024-10-13 17:46:03,273 INFO L747 eck$LassoCheckResult]: Loop: 69816#L1272-2 assume !false; 69511#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69510#L813-1 assume !false; 69509#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 69470#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 69461#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 69460#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69458#L696 assume !(0 != eval_~tmp~0#1); 69459#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70229#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70228#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 70227#L838-5 assume !(0 == ~T1_E~0); 70226#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70225#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70224#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70223#L858-3 assume !(0 == ~T5_E~0); 70222#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70221#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70219#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70218#L878-3 assume !(0 == ~E_1~0); 70217#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70216#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70215#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70214#L898-3 assume !(0 == ~E_5~0); 70212#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70211#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70210#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70209#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70208#L402-27 assume !(1 == ~m_pc~0); 70207#L402-29 is_master_triggered_~__retres1~0#1 := 0; 70204#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70202#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 70200#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70198#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70196#L421-27 assume !(1 == ~t1_pc~0); 70194#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 70192#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70190#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70188#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70186#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70184#L440-27 assume !(1 == ~t2_pc~0); 70182#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 70180#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70178#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 70176#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 70174#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70172#L459-27 assume !(1 == ~t3_pc~0); 70168#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 70166#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70164#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70161#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 70158#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70156#L478-27 assume !(1 == ~t4_pc~0); 70154#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 70152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70150#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 70148#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70146#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70144#L497-27 assume 1 == ~t5_pc~0; 70141#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 70139#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70137#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70135#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70133#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70131#L516-27 assume 1 == ~t6_pc~0; 70129#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 70126#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70122#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70120#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70118#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70116#L535-27 assume !(1 == ~t7_pc~0); 70113#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 70110#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70108#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70106#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70104#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70102#L554-27 assume !(1 == ~t8_pc~0); 70099#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 70097#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70095#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70092#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70090#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70088#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70086#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70084#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70047#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70080#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70078#L951-3 assume !(1 == ~T5_E~0); 70076#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70074#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70072#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70070#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70067#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70065#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70063#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70061#L991-3 assume !(1 == ~E_5~0); 70033#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70058#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70055#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70053#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 69860#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 69851#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 69849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 69847#L1291 assume !(0 == start_simulation_~tmp~3#1); 69845#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 69844#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 69835#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 69834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 69833#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69832#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69831#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 69817#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 69816#L1272-2 [2024-10-13 17:46:03,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,274 INFO L85 PathProgramCache]: Analyzing trace with hash -461177985, now seen corresponding path program 1 times [2024-10-13 17:46:03,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940935134] [2024-10-13 17:46:03,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:03,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:03,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940935134] [2024-10-13 17:46:03,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1940935134] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,321 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:03,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074980493] [2024-10-13 17:46:03,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,322 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:03,322 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:03,322 INFO L85 PathProgramCache]: Analyzing trace with hash 639414542, now seen corresponding path program 1 times [2024-10-13 17:46:03,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:03,322 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942112664] [2024-10-13 17:46:03,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:03,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:03,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:03,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:03,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:03,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942112664] [2024-10-13 17:46:03,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942112664] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:03,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:03,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:03,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261012745] [2024-10-13 17:46:03,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:03,355 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:03,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:03,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:03,355 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:03,356 INFO L87 Difference]: Start difference. First operand 11564 states and 16577 transitions. cyclomatic complexity: 5029 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:03,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:03,475 INFO L93 Difference]: Finished difference Result 21803 states and 31130 transitions. [2024-10-13 17:46:03,475 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21803 states and 31130 transitions. [2024-10-13 17:46:03,575 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21548 [2024-10-13 17:46:03,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21803 states to 21803 states and 31130 transitions. [2024-10-13 17:46:03,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21803 [2024-10-13 17:46:03,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21803 [2024-10-13 17:46:03,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21803 states and 31130 transitions. [2024-10-13 17:46:03,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:03,686 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21803 states and 31130 transitions. [2024-10-13 17:46:03,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21803 states and 31130 transitions. [2024-10-13 17:46:03,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21803 to 21771. [2024-10-13 17:46:03,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21771 states, 21771 states have (on average 1.4284139451564006) internal successors, (31098), 21770 states have internal predecessors, (31098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:04,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21771 states to 21771 states and 31098 transitions. [2024-10-13 17:46:04,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21771 states and 31098 transitions. [2024-10-13 17:46:04,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:04,039 INFO L425 stractBuchiCegarLoop]: Abstraction has 21771 states and 31098 transitions. [2024-10-13 17:46:04,039 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-13 17:46:04,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21771 states and 31098 transitions. [2024-10-13 17:46:04,095 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21516 [2024-10-13 17:46:04,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:04,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:04,096 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:04,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:04,097 INFO L745 eck$LassoCheckResult]: Stem: 96402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 96403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 97108#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97109#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 97111#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 96523#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96524#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97100#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97092#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96599#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96600#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96851#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96852#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96686#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96687#L838 assume !(0 == ~M_E~0); 96861#L838-2 assume !(0 == ~T1_E~0); 96199#L843-1 assume !(0 == ~T2_E~0); 96200#L848-1 assume !(0 == ~T3_E~0); 96320#L853-1 assume !(0 == ~T4_E~0); 96673#L858-1 assume !(0 == ~T5_E~0); 96153#L863-1 assume !(0 == ~T6_E~0); 96154#L868-1 assume !(0 == ~T7_E~0); 97164#L873-1 assume !(0 == ~T8_E~0); 97157#L878-1 assume !(0 == ~E_1~0); 97140#L883-1 assume !(0 == ~E_2~0); 97141#L888-1 assume !(0 == ~E_3~0); 96817#L893-1 assume !(0 == ~E_4~0); 96818#L898-1 assume !(0 == ~E_5~0); 97180#L903-1 assume !(0 == ~E_6~0); 97137#L908-1 assume !(0 == ~E_7~0); 96960#L913-1 assume !(0 == ~E_8~0); 96211#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96212#L402 assume !(1 == ~m_pc~0); 96426#L402-2 is_master_triggered_~__retres1~0#1 := 0; 96347#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96348#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96606#L1035 assume !(0 != activate_threads_~tmp~1#1); 96607#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96661#L421 assume !(1 == ~t1_pc~0); 97132#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97165#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96214#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96215#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 96718#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97175#L440 assume !(1 == ~t2_pc~0); 97227#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96356#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96357#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96551#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 96979#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96554#L459 assume !(1 == ~t3_pc~0); 96555#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97127#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 96176#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 96341#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96351#L478 assume !(1 == ~t4_pc~0); 96352#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 97040#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96291#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96292#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 96252#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96253#L497 assume !(1 == ~t5_pc~0); 96302#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96303#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96901#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 97034#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 97121#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97122#L516 assume !(1 == ~t6_pc~0); 97053#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 96850#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96533#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96396#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 96397#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96837#L535 assume !(1 == ~t7_pc~0); 96838#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96916#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96917#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96952#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 96942#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96943#L554 assume 1 == ~t8_pc~0; 96878#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 96178#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96970#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96485#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 96486#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96164#L931 assume !(1 == ~M_E~0); 96165#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97151#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97188#L941-1 assume !(1 == ~T3_E~0); 96662#L946-1 assume !(1 == ~T4_E~0); 96663#L951-1 assume !(1 == ~T5_E~0); 96412#L956-1 assume !(1 == ~T6_E~0); 96413#L961-1 assume !(1 == ~T7_E~0); 96819#L966-1 assume !(1 == ~T8_E~0); 96820#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 96945#L976-1 assume !(1 == ~E_2~0); 97197#L981-1 assume !(1 == ~E_3~0); 96666#L986-1 assume !(1 == ~E_4~0); 96440#L991-1 assume !(1 == ~E_5~0); 96441#L996-1 assume !(1 == ~E_6~0); 97170#L1001-1 assume !(1 == ~E_7~0); 96873#L1006-1 assume !(1 == ~E_8~0); 96874#L1011-1 assume { :end_inline_reset_delta_events } true; 99819#L1272-2 [2024-10-13 17:46:04,097 INFO L747 eck$LassoCheckResult]: Loop: 99819#L1272-2 assume !false; 99813#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99810#L813-1 assume !false; 99808#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 99692#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 99679#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 99675#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 99670#L696 assume !(0 != eval_~tmp~0#1); 99671#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100209#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100207#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 100205#L838-5 assume !(0 == ~T1_E~0); 100202#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 100200#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100198#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100196#L858-3 assume !(0 == ~T5_E~0); 100194#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100192#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 100190#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 100188#L878-3 assume !(0 == ~E_1~0); 100186#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100183#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100181#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100179#L898-3 assume !(0 == ~E_5~0); 100177#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100175#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 100173#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 100171#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100169#L402-27 assume !(1 == ~m_pc~0); 100167#L402-29 is_master_triggered_~__retres1~0#1 := 0; 100164#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100162#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100160#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100157#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100155#L421-27 assume !(1 == ~t1_pc~0); 100153#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 100151#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100149#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100147#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100144#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100142#L440-27 assume !(1 == ~t2_pc~0); 100140#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 100138#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100136#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100134#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 100132#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100128#L459-27 assume !(1 == ~t3_pc~0); 100124#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 100122#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100120#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100118#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 100115#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100113#L478-27 assume !(1 == ~t4_pc~0); 100111#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 100109#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100107#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 100105#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100101#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100099#L497-27 assume !(1 == ~t5_pc~0); 100097#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 100094#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100093#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100092#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100091#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100090#L516-27 assume !(1 == ~t6_pc~0); 100089#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 100088#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100087#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100086#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100085#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100084#L535-27 assume 1 == ~t7_pc~0; 100081#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 100079#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100077#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100075#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 100072#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100070#L554-27 assume !(1 == ~t8_pc~0); 100067#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 100065#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100063#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100061#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 100059#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100057#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 100055#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100053#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100025#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100050#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100047#L951-3 assume !(1 == ~T5_E~0); 100045#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100043#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100041#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 100039#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100037#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100034#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 100032#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99997#L991-3 assume !(1 == ~E_5~0); 99995#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 99993#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 99990#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 99988#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 99982#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 99973#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 99971#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 99968#L1291 assume !(0 == start_simulation_~tmp~3#1); 99965#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 99858#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 99848#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 99846#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 99843#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99841#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99839#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 99827#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 99819#L1272-2 [2024-10-13 17:46:04,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:04,097 INFO L85 PathProgramCache]: Analyzing trace with hash 2068972702, now seen corresponding path program 1 times [2024-10-13 17:46:04,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:04,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640888472] [2024-10-13 17:46:04,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:04,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:04,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:04,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:04,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:04,145 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1640888472] [2024-10-13 17:46:04,145 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1640888472] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:04,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:04,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:04,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960429133] [2024-10-13 17:46:04,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:04,146 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:04,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:04,146 INFO L85 PathProgramCache]: Analyzing trace with hash 35597613, now seen corresponding path program 1 times [2024-10-13 17:46:04,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:04,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336784320] [2024-10-13 17:46:04,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:04,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:04,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:04,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:04,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:04,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336784320] [2024-10-13 17:46:04,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336784320] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:04,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:04,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:04,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548224954] [2024-10-13 17:46:04,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:04,196 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:04,197 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:04,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:04,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:04,197 INFO L87 Difference]: Start difference. First operand 21771 states and 31098 transitions. cyclomatic complexity: 9359 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:04,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:04,456 INFO L93 Difference]: Finished difference Result 43134 states and 61227 transitions. [2024-10-13 17:46:04,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43134 states and 61227 transitions. [2024-10-13 17:46:04,624 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42688 [2024-10-13 17:46:04,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43134 states to 43134 states and 61227 transitions. [2024-10-13 17:46:04,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43134 [2024-10-13 17:46:04,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43134 [2024-10-13 17:46:04,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43134 states and 61227 transitions. [2024-10-13 17:46:04,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:04,953 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43134 states and 61227 transitions. [2024-10-13 17:46:04,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43134 states and 61227 transitions. [2024-10-13 17:46:05,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43134 to 43006. [2024-10-13 17:46:05,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43006 states, 43006 states have (on average 1.4199646560944985) internal successors, (61067), 43005 states have internal predecessors, (61067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:05,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43006 states to 43006 states and 61067 transitions. [2024-10-13 17:46:05,515 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43006 states and 61067 transitions. [2024-10-13 17:46:05,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:05,516 INFO L425 stractBuchiCegarLoop]: Abstraction has 43006 states and 61067 transitions. [2024-10-13 17:46:05,516 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-13 17:46:05,517 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43006 states and 61067 transitions. [2024-10-13 17:46:05,764 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-10-13 17:46:05,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:05,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:05,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:05,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:05,773 INFO L745 eck$LassoCheckResult]: Stem: 161312#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 161313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 162045#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 162046#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 162048#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 161431#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 161432#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 162037#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 162030#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 161510#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 161511#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 161768#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 161769#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 161598#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 161599#L838 assume !(0 == ~M_E~0); 161778#L838-2 assume !(0 == ~T1_E~0); 161113#L843-1 assume !(0 == ~T2_E~0); 161114#L848-1 assume !(0 == ~T3_E~0); 161232#L853-1 assume !(0 == ~T4_E~0); 161586#L858-1 assume !(0 == ~T5_E~0); 161069#L863-1 assume !(0 == ~T6_E~0); 161070#L868-1 assume !(0 == ~T7_E~0); 162115#L873-1 assume !(0 == ~T8_E~0); 162109#L878-1 assume !(0 == ~E_1~0); 162087#L883-1 assume !(0 == ~E_2~0); 162088#L888-1 assume !(0 == ~E_3~0); 161736#L893-1 assume !(0 == ~E_4~0); 161737#L898-1 assume !(0 == ~E_5~0); 162127#L903-1 assume !(0 == ~E_6~0); 162084#L908-1 assume !(0 == ~E_7~0); 161884#L913-1 assume !(0 == ~E_8~0); 161126#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 161127#L402 assume !(1 == ~m_pc~0); 161340#L402-2 is_master_triggered_~__retres1~0#1 := 0; 161256#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161257#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 161517#L1035 assume !(0 != activate_threads_~tmp~1#1); 161518#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161572#L421 assume !(1 == ~t1_pc~0); 162072#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 162118#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 161128#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 161129#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 161629#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162124#L440 assume !(1 == ~t2_pc~0); 162181#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 161265#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 161266#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 161458#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 161907#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161467#L459 assume !(1 == ~t3_pc~0); 161468#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 162068#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161089#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 161090#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 161251#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161260#L478 assume !(1 == ~t4_pc~0); 161261#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 161959#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 161204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 161205#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 161168#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 161169#L497 assume !(1 == ~t5_pc~0); 161215#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 161216#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 161819#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 161954#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 162059#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 162060#L516 assume !(1 == ~t6_pc~0); 161974#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 161767#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 161441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 161306#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 161307#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 161755#L535 assume !(1 == ~t7_pc~0); 161756#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 161834#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 161835#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 161874#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 161864#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 161865#L554 assume !(1 == ~t8_pc~0); 161091#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 161092#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 161899#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 161395#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 161396#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 161078#L931 assume !(1 == ~M_E~0); 161079#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 162102#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 162142#L941-1 assume !(1 == ~T3_E~0); 161573#L946-1 assume !(1 == ~T4_E~0); 161574#L951-1 assume !(1 == ~T5_E~0); 161322#L956-1 assume !(1 == ~T6_E~0); 161323#L961-1 assume !(1 == ~T7_E~0); 161738#L966-1 assume !(1 == ~T8_E~0); 161739#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 161867#L976-1 assume !(1 == ~E_2~0); 161824#L981-1 assume !(1 == ~E_3~0); 161577#L986-1 assume !(1 == ~E_4~0); 161349#L991-1 assume !(1 == ~E_5~0); 161350#L996-1 assume !(1 == ~E_6~0); 162120#L1001-1 assume !(1 == ~E_7~0); 161787#L1006-1 assume !(1 == ~E_8~0); 161788#L1011-1 assume { :end_inline_reset_delta_events } true; 162070#L1272-2 [2024-10-13 17:46:05,773 INFO L747 eck$LassoCheckResult]: Loop: 162070#L1272-2 assume !false; 180999#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 180995#L813-1 assume !false; 180992#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 180840#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 180823#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 180816#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 180809#L696 assume !(0 != eval_~tmp~0#1); 180810#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 181483#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 181481#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 181479#L838-5 assume !(0 == ~T1_E~0); 181477#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 181475#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 181473#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 181470#L858-3 assume !(0 == ~T5_E~0); 181468#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 181466#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 181464#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 181462#L878-3 assume !(0 == ~E_1~0); 181460#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 181458#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 181456#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 181454#L898-3 assume !(0 == ~E_5~0); 181452#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 181450#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 181446#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 181444#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 181442#L402-27 assume 1 == ~m_pc~0; 181438#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 181437#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 181436#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 181434#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 181431#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 181429#L421-27 assume !(1 == ~t1_pc~0); 181427#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 181425#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 181423#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 181421#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 181419#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 181417#L440-27 assume !(1 == ~t2_pc~0); 181415#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 181413#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 181411#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 181409#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 181407#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 181405#L459-27 assume 1 == ~t3_pc~0; 181402#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 181399#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 181396#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 181393#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 181390#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 181387#L478-27 assume !(1 == ~t4_pc~0); 181384#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 181381#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 181379#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 181377#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 181375#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 181372#L497-27 assume 1 == ~t5_pc~0; 181368#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 181365#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181362#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 181359#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 181355#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 181352#L516-27 assume !(1 == ~t6_pc~0); 181349#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 181346#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 181343#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 181340#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 181337#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 181334#L535-27 assume 1 == ~t7_pc~0; 181330#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 181327#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 181324#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 181321#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 181317#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 181314#L554-27 assume !(1 == ~t8_pc~0); 181311#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 181307#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 181304#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 181301#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 181298#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 181294#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 181289#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 181285#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 172318#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 181278#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 181274#L951-3 assume !(1 == ~T5_E~0); 181270#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 181267#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 181263#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 181259#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 181255#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 181251#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 181247#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 181243#L991-3 assume !(1 == ~E_5~0); 172294#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 181234#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 181229#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 181225#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 181159#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 181147#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 181140#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 181133#L1291 assume !(0 == start_simulation_~tmp~3#1); 181129#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 181060#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 181045#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 181040#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 181034#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 181028#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 181020#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 181011#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 162070#L1272-2 [2024-10-13 17:46:05,773 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:05,774 INFO L85 PathProgramCache]: Analyzing trace with hash 478577725, now seen corresponding path program 1 times [2024-10-13 17:46:05,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:05,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71130380] [2024-10-13 17:46:05,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:05,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:05,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:05,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:05,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:05,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [71130380] [2024-10-13 17:46:05,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [71130380] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:05,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:05,825 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:05,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103097146] [2024-10-13 17:46:05,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:05,826 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:05,826 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:05,826 INFO L85 PathProgramCache]: Analyzing trace with hash 886404754, now seen corresponding path program 1 times [2024-10-13 17:46:05,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:05,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240220609] [2024-10-13 17:46:05,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:05,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:05,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:05,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:05,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:05,851 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240220609] [2024-10-13 17:46:05,851 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1240220609] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:05,851 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:05,851 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:05,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316630336] [2024-10-13 17:46:05,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:05,852 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:05,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:05,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:05,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:05,853 INFO L87 Difference]: Start difference. First operand 43006 states and 61067 transitions. cyclomatic complexity: 18125 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:05,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:05,949 INFO L93 Difference]: Finished difference Result 43006 states and 60873 transitions. [2024-10-13 17:46:05,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43006 states and 60873 transitions. [2024-10-13 17:46:06,252 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-10-13 17:46:06,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43006 states to 43006 states and 60873 transitions. [2024-10-13 17:46:06,362 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43006 [2024-10-13 17:46:06,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43006 [2024-10-13 17:46:06,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43006 states and 60873 transitions. [2024-10-13 17:46:06,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:06,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-10-13 17:46:06,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43006 states and 60873 transitions. [2024-10-13 17:46:06,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43006 to 43006. [2024-10-13 17:46:06,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43006 states, 43006 states have (on average 1.415453657629168) internal successors, (60873), 43005 states have internal predecessors, (60873), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:06,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43006 states to 43006 states and 60873 transitions. [2024-10-13 17:46:06,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-10-13 17:46:06,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:06,860 INFO L425 stractBuchiCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-10-13 17:46:06,860 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-13 17:46:06,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43006 states and 60873 transitions. [2024-10-13 17:46:07,129 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-10-13 17:46:07,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:07,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:07,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:07,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:07,131 INFO L745 eck$LassoCheckResult]: Stem: 247332#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 247333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 248050#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 248051#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 248053#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 247450#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 247451#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 248044#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 248030#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247526#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247527#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 247776#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 247777#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 247613#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247614#L838 assume !(0 == ~M_E~0); 247785#L838-2 assume !(0 == ~T1_E~0); 247132#L843-1 assume !(0 == ~T2_E~0); 247133#L848-1 assume !(0 == ~T3_E~0); 247252#L853-1 assume !(0 == ~T4_E~0); 247600#L858-1 assume !(0 == ~T5_E~0); 247086#L863-1 assume !(0 == ~T6_E~0); 247087#L868-1 assume !(0 == ~T7_E~0); 248101#L873-1 assume !(0 == ~T8_E~0); 248099#L878-1 assume !(0 == ~E_1~0); 248080#L883-1 assume !(0 == ~E_2~0); 248081#L888-1 assume !(0 == ~E_3~0); 247745#L893-1 assume !(0 == ~E_4~0); 247746#L898-1 assume !(0 == ~E_5~0); 248117#L903-1 assume !(0 == ~E_6~0); 248078#L908-1 assume !(0 == ~E_7~0); 247890#L913-1 assume !(0 == ~E_8~0); 247144#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247145#L402 assume !(1 == ~m_pc~0); 247357#L402-2 is_master_triggered_~__retres1~0#1 := 0; 247276#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247277#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 247533#L1035 assume !(0 != activate_threads_~tmp~1#1); 247534#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247588#L421 assume !(1 == ~t1_pc~0); 248072#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 248102#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247148#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 247149#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 247641#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 248114#L440 assume !(1 == ~t2_pc~0); 248161#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 247286#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 247476#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 247907#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247479#L459 assume !(1 == ~t3_pc~0); 247480#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 248069#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247108#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247109#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 247271#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247280#L478 assume !(1 == ~t4_pc~0); 247281#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 247966#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247224#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247225#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 247186#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247187#L497 assume !(1 == ~t5_pc~0); 247235#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 247236#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247830#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 247962#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 248063#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 248064#L516 assume !(1 == ~t6_pc~0); 247981#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 247775#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247460#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247326#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 247327#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 247764#L535 assume !(1 == ~t7_pc~0); 247765#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 247845#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 247846#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247881#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 247871#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247872#L554 assume !(1 == ~t8_pc~0); 247110#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 247111#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 247898#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247413#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 247414#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247097#L931 assume !(1 == ~M_E~0); 247098#L931-2 assume !(1 == ~T1_E~0); 248092#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 248126#L941-1 assume !(1 == ~T3_E~0); 247589#L946-1 assume !(1 == ~T4_E~0); 247590#L951-1 assume !(1 == ~T5_E~0); 247342#L956-1 assume !(1 == ~T6_E~0); 247343#L961-1 assume !(1 == ~T7_E~0); 247747#L966-1 assume !(1 == ~T8_E~0); 247748#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 247874#L976-1 assume !(1 == ~E_2~0); 247835#L981-1 assume !(1 == ~E_3~0); 247593#L986-1 assume !(1 == ~E_4~0); 247371#L991-1 assume !(1 == ~E_5~0); 247372#L996-1 assume !(1 == ~E_6~0); 248108#L1001-1 assume !(1 == ~E_7~0); 247797#L1006-1 assume !(1 == ~E_8~0); 247798#L1011-1 assume { :end_inline_reset_delta_events } true; 248070#L1272-2 [2024-10-13 17:46:07,131 INFO L747 eck$LassoCheckResult]: Loop: 248070#L1272-2 assume !false; 262501#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 262499#L813-1 assume !false; 262497#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262491#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262481#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262479#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 262476#L696 assume !(0 != eval_~tmp~0#1); 262477#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 262975#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 262974#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 262973#L838-5 assume !(0 == ~T1_E~0); 262972#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 262971#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 262970#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 262969#L858-3 assume !(0 == ~T5_E~0); 262968#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 262967#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 262966#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 262965#L878-3 assume !(0 == ~E_1~0); 262964#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 262963#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 262962#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 262961#L898-3 assume !(0 == ~E_5~0); 262960#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 262958#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 262957#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 262956#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 262955#L402-27 assume 1 == ~m_pc~0; 262953#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 262951#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 262950#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 262949#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 262948#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 262947#L421-27 assume !(1 == ~t1_pc~0); 262945#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 262942#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 262940#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 262938#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 262936#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 262934#L440-27 assume !(1 == ~t2_pc~0); 262932#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 262930#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 262928#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 262926#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 262924#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 262922#L459-27 assume !(1 == ~t3_pc~0); 262918#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 262916#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 262914#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 262912#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 262909#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 262907#L478-27 assume !(1 == ~t4_pc~0); 262903#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 262901#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 262899#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 262897#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 262894#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 262892#L497-27 assume 1 == ~t5_pc~0; 262889#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 262887#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 262885#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 262883#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 262881#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 262879#L516-27 assume !(1 == ~t6_pc~0); 262877#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 262874#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 262872#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 262870#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 262868#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 262866#L535-27 assume !(1 == ~t7_pc~0); 262864#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 262861#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 262859#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 262857#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 262855#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 262853#L554-27 assume !(1 == ~t8_pc~0); 262851#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 262848#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 262846#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 262844#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 262842#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 262840#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 262838#L931-5 assume !(1 == ~T1_E~0); 262836#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 257553#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 262833#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 262831#L951-3 assume !(1 == ~T5_E~0); 262829#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 262827#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 262825#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 262823#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 262822#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 262820#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 262818#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 262816#L991-3 assume !(1 == ~E_5~0); 257529#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 262813#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 262811#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 262809#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262804#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262795#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262793#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 262791#L1291 assume !(0 == start_simulation_~tmp~3#1); 262789#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262784#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262774#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262772#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 262770#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 262768#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 262766#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 262764#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 248070#L1272-2 [2024-10-13 17:46:07,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:07,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1109770177, now seen corresponding path program 1 times [2024-10-13 17:46:07,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:07,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253964202] [2024-10-13 17:46:07,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:07,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:07,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:07,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:07,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:07,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [253964202] [2024-10-13 17:46:07,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [253964202] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:07,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:07,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-13 17:46:07,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134425273] [2024-10-13 17:46:07,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:07,178 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:07,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:07,178 INFO L85 PathProgramCache]: Analyzing trace with hash -381608560, now seen corresponding path program 1 times [2024-10-13 17:46:07,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:07,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110974286] [2024-10-13 17:46:07,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:07,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:07,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:07,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:07,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:07,207 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110974286] [2024-10-13 17:46:07,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110974286] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:07,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:07,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:07,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74528926] [2024-10-13 17:46:07,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:07,207 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:07,207 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:07,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:07,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:07,208 INFO L87 Difference]: Start difference. First operand 43006 states and 60873 transitions. cyclomatic complexity: 17931 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:07,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:07,325 INFO L93 Difference]: Finished difference Result 42995 states and 60691 transitions. [2024-10-13 17:46:07,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42995 states and 60691 transitions. [2024-10-13 17:46:07,612 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-10-13 17:46:07,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42995 states to 42995 states and 60691 transitions. [2024-10-13 17:46:07,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42995 [2024-10-13 17:46:07,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42995 [2024-10-13 17:46:07,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42995 states and 60691 transitions. [2024-10-13 17:46:07,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:07,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42995 states and 60691 transitions. [2024-10-13 17:46:07,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42995 states and 60691 transitions. [2024-10-13 17:46:08,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42995 to 22079. [2024-10-13 17:46:08,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.4100276280628652) internal successors, (31132), 22078 states have internal predecessors, (31132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:08,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 31132 transitions. [2024-10-13 17:46:08,060 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 31132 transitions. [2024-10-13 17:46:08,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:08,061 INFO L425 stractBuchiCegarLoop]: Abstraction has 22079 states and 31132 transitions. [2024-10-13 17:46:08,061 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-13 17:46:08,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 31132 transitions. [2024-10-13 17:46:08,109 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-10-13 17:46:08,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:08,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:08,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:08,113 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:08,114 INFO L745 eck$LassoCheckResult]: Stem: 333343#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 333344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 334049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 334050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 334052#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 333460#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 333461#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 334042#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 334034#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 333537#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 333538#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 333788#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 333789#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 333623#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 333624#L838 assume !(0 == ~M_E~0); 333798#L838-2 assume !(0 == ~T1_E~0); 333142#L843-1 assume !(0 == ~T2_E~0); 333143#L848-1 assume !(0 == ~T3_E~0); 333261#L853-1 assume !(0 == ~T4_E~0); 333610#L858-1 assume !(0 == ~T5_E~0); 333094#L863-1 assume !(0 == ~T6_E~0); 333095#L868-1 assume !(0 == ~T7_E~0); 334097#L873-1 assume !(0 == ~T8_E~0); 334094#L878-1 assume !(0 == ~E_1~0); 334075#L883-1 assume !(0 == ~E_2~0); 334076#L888-1 assume !(0 == ~E_3~0); 333755#L893-1 assume !(0 == ~E_4~0); 333756#L898-1 assume !(0 == ~E_5~0); 334116#L903-1 assume !(0 == ~E_6~0); 334073#L908-1 assume !(0 == ~E_7~0); 333902#L913-1 assume !(0 == ~E_8~0); 333155#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 333156#L402 assume !(1 == ~m_pc~0); 333369#L402-2 is_master_triggered_~__retres1~0#1 := 0; 333288#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 333289#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 333544#L1035 assume !(0 != activate_threads_~tmp~1#1); 333545#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 333597#L421 assume !(1 == ~t1_pc~0); 334068#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 334098#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 333157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 333158#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 333656#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 334111#L440 assume !(1 == ~t2_pc~0); 334159#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 333298#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 333299#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 333487#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 333921#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 333493#L459 assume !(1 == ~t3_pc~0); 333494#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 334065#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 333116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 333117#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 333282#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 333292#L478 assume !(1 == ~t4_pc~0); 333293#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 333974#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 333233#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 333234#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 333195#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 333196#L497 assume !(1 == ~t5_pc~0); 333244#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 333245#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 333839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 333970#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 334060#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 334061#L516 assume !(1 == ~t6_pc~0); 333987#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 333787#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 333470#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 333337#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 333338#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 333775#L535 assume !(1 == ~t7_pc~0); 333776#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 333854#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 333855#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 333891#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 333880#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 333881#L554 assume !(1 == ~t8_pc~0); 333118#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 333119#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 333912#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 333423#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 333424#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 333105#L931 assume !(1 == ~M_E~0); 333106#L931-2 assume !(1 == ~T1_E~0); 334087#L936-1 assume !(1 == ~T2_E~0); 334128#L941-1 assume !(1 == ~T3_E~0); 333598#L946-1 assume !(1 == ~T4_E~0); 333599#L951-1 assume !(1 == ~T5_E~0); 333353#L956-1 assume !(1 == ~T6_E~0); 333354#L961-1 assume !(1 == ~T7_E~0); 333757#L966-1 assume !(1 == ~T8_E~0); 333758#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 333883#L976-1 assume !(1 == ~E_2~0); 333844#L981-1 assume !(1 == ~E_3~0); 333603#L986-1 assume !(1 == ~E_4~0); 333380#L991-1 assume !(1 == ~E_5~0); 333381#L996-1 assume !(1 == ~E_6~0); 334102#L1001-1 assume !(1 == ~E_7~0); 333809#L1006-1 assume !(1 == ~E_8~0); 333810#L1011-1 assume { :end_inline_reset_delta_events } true; 334066#L1272-2 [2024-10-13 17:46:08,114 INFO L747 eck$LassoCheckResult]: Loop: 334066#L1272-2 assume !false; 338009#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 337988#L813-1 assume !false; 337974#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 337935#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 337911#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 337903#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 337895#L696 assume !(0 != eval_~tmp~0#1); 337896#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 353895#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 353891#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 353887#L838-5 assume !(0 == ~T1_E~0); 353883#L843-3 assume !(0 == ~T2_E~0); 353555#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 353554#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 353553#L858-3 assume !(0 == ~T5_E~0); 353551#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 353550#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 353549#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 353548#L878-3 assume !(0 == ~E_1~0); 353547#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 353545#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 353543#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 353541#L898-3 assume !(0 == ~E_5~0); 353539#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 353536#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 353534#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 353211#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 353210#L402-27 assume !(1 == ~m_pc~0); 353209#L402-29 is_master_triggered_~__retres1~0#1 := 0; 353207#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 353206#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 353205#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 353204#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 353202#L421-27 assume !(1 == ~t1_pc~0); 353200#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 353199#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 353198#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 353197#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 353195#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 353194#L440-27 assume !(1 == ~t2_pc~0); 353193#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 353192#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 353191#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 353189#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 353187#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 353184#L459-27 assume !(1 == ~t3_pc~0); 353180#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 353178#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353176#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 353174#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 353171#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 353169#L478-27 assume !(1 == ~t4_pc~0); 353167#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 353165#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 353163#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 353161#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 353159#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 353157#L497-27 assume !(1 == ~t5_pc~0); 353155#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 353152#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 353150#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 353148#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 353146#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 353143#L516-27 assume !(1 == ~t6_pc~0); 353141#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 353139#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 353136#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 353134#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 353132#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 353129#L535-27 assume !(1 == ~t7_pc~0); 353127#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 353124#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 353122#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 353120#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 353118#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 353115#L554-27 assume !(1 == ~t8_pc~0); 353113#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 353111#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 353109#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 353107#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 353105#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 353103#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 353101#L931-5 assume !(1 == ~T1_E~0); 353099#L936-3 assume !(1 == ~T2_E~0); 353097#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 338828#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 338403#L951-3 assume !(1 == ~T5_E~0); 338402#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 338401#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 338399#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 338398#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 338397#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 338396#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 338391#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 338387#L991-3 assume !(1 == ~E_5~0); 338383#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 338377#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 338372#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 338370#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 338159#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 338146#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 338133#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 338125#L1291 assume !(0 == start_simulation_~tmp~3#1); 338117#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 338040#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 338030#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 338028#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 338025#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 338023#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 338021#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 338019#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 334066#L1272-2 [2024-10-13 17:46:08,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:08,115 INFO L85 PathProgramCache]: Analyzing trace with hash -2130838531, now seen corresponding path program 1 times [2024-10-13 17:46:08,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:08,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001759681] [2024-10-13 17:46:08,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:08,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:08,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:08,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:08,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:08,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001759681] [2024-10-13 17:46:08,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001759681] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:08,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:08,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:08,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [546203749] [2024-10-13 17:46:08,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:08,158 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:08,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:08,159 INFO L85 PathProgramCache]: Analyzing trace with hash 654310282, now seen corresponding path program 1 times [2024-10-13 17:46:08,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:08,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868659439] [2024-10-13 17:46:08,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:08,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:08,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:08,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:08,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:08,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868659439] [2024-10-13 17:46:08,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868659439] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:08,200 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:08,200 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:08,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517344776] [2024-10-13 17:46:08,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:08,201 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:08,201 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:08,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:46:08,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:46:08,202 INFO L87 Difference]: Start difference. First operand 22079 states and 31132 transitions. cyclomatic complexity: 9085 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:08,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:08,497 INFO L93 Difference]: Finished difference Result 45574 states and 64007 transitions. [2024-10-13 17:46:08,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45574 states and 64007 transitions. [2024-10-13 17:46:08,648 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 45056 [2024-10-13 17:46:08,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45574 states to 45574 states and 64007 transitions. [2024-10-13 17:46:08,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45574 [2024-10-13 17:46:08,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45574 [2024-10-13 17:46:08,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45574 states and 64007 transitions. [2024-10-13 17:46:08,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:08,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45574 states and 64007 transitions. [2024-10-13 17:46:08,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45574 states and 64007 transitions. [2024-10-13 17:46:09,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45574 to 24766. [2024-10-13 17:46:09,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24766 states, 24766 states have (on average 1.4045061778244368) internal successors, (34784), 24765 states have internal predecessors, (34784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:09,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24766 states to 24766 states and 34784 transitions. [2024-10-13 17:46:09,319 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24766 states and 34784 transitions. [2024-10-13 17:46:09,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:46:09,320 INFO L425 stractBuchiCegarLoop]: Abstraction has 24766 states and 34784 transitions. [2024-10-13 17:46:09,320 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-13 17:46:09,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24766 states and 34784 transitions. [2024-10-13 17:46:09,392 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24448 [2024-10-13 17:46:09,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:09,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:09,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:09,394 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:09,394 INFO L745 eck$LassoCheckResult]: Stem: 401011#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 401012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 401718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 401719#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 401721#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 401131#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 401132#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 401714#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 401703#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 401209#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 401210#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 401463#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 401464#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 401296#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 401297#L838 assume !(0 == ~M_E~0); 401472#L838-2 assume !(0 == ~T1_E~0); 400804#L843-1 assume !(0 == ~T2_E~0); 400805#L848-1 assume !(0 == ~T3_E~0); 400926#L853-1 assume !(0 == ~T4_E~0); 401283#L858-1 assume !(0 == ~T5_E~0); 400759#L863-1 assume !(0 == ~T6_E~0); 400760#L868-1 assume !(0 == ~T7_E~0); 401772#L873-1 assume !(0 == ~T8_E~0); 401768#L878-1 assume 0 == ~E_1~0;~E_1~0 := 1; 401769#L883-1 assume !(0 == ~E_2~0); 401791#L888-1 assume !(0 == ~E_3~0); 401792#L893-1 assume !(0 == ~E_4~0); 401793#L898-1 assume !(0 == ~E_5~0); 401794#L903-1 assume !(0 == ~E_6~0); 401845#L908-1 assume !(0 == ~E_7~0); 401872#L913-1 assume !(0 == ~E_8~0); 401871#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 401589#L402 assume !(1 == ~m_pc~0); 401590#L402-2 is_master_triggered_~__retres1~0#1 := 0; 400954#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 400955#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 401870#L1035 assume !(0 != activate_threads_~tmp~1#1); 401270#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 401271#L421 assume !(1 == ~t1_pc~0); 401773#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 401774#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 401869#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 401325#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 401326#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 401841#L440 assume !(1 == ~t2_pc~0); 401842#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 400964#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 400965#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 401808#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 401809#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 401167#L459 assume !(1 == ~t3_pc~0); 401168#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 401867#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 401865#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 401863#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 401862#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 400958#L478 assume !(1 == ~t4_pc~0); 400959#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 401712#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 401713#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 401141#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 401142#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 401484#L497 assume !(1 == ~t5_pc~0); 401485#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 401512#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 401513#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 401786#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 401787#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 401831#L516 assume !(1 == ~t6_pc~0); 401832#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 401461#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 401462#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 401861#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 401860#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 401449#L535 assume !(1 == ~t7_pc~0); 401450#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 401859#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 401825#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 401565#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 401555#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 401556#L554 assume !(1 == ~t8_pc~0); 400781#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 400782#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 401856#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 401095#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 401096#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 400769#L931 assume !(1 == ~M_E~0); 400770#L931-2 assume !(1 == ~T1_E~0); 401803#L936-1 assume !(1 == ~T2_E~0); 401804#L941-1 assume !(1 == ~T3_E~0); 401838#L946-1 assume !(1 == ~T4_E~0); 401737#L951-1 assume !(1 == ~T5_E~0); 401020#L956-1 assume !(1 == ~T6_E~0); 401021#L961-1 assume !(1 == ~T7_E~0); 401833#L966-1 assume !(1 == ~T8_E~0); 401850#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 401558#L976-1 assume !(1 == ~E_2~0); 401517#L981-1 assume !(1 == ~E_3~0); 401276#L986-1 assume !(1 == ~E_4~0); 401048#L991-1 assume !(1 == ~E_5~0); 401049#L996-1 assume !(1 == ~E_6~0); 401779#L1001-1 assume !(1 == ~E_7~0); 401482#L1006-1 assume !(1 == ~E_8~0); 401483#L1011-1 assume { :end_inline_reset_delta_events } true; 401738#L1272-2 [2024-10-13 17:46:09,395 INFO L747 eck$LassoCheckResult]: Loop: 401738#L1272-2 assume !false; 408848#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 408845#L813-1 assume !false; 408841#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 407866#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 407857#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 407855#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 407852#L696 assume !(0 != eval_~tmp~0#1); 407853#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 409280#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 409194#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 409190#L838-5 assume !(0 == ~T1_E~0); 409186#L843-3 assume !(0 == ~T2_E~0); 409182#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 409178#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 409174#L858-3 assume !(0 == ~T5_E~0); 409170#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 409166#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 409162#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 409160#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 409159#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 409158#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 409157#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 409156#L898-3 assume !(0 == ~E_5~0); 409155#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 409154#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 409153#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 409152#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 409151#L402-27 assume !(1 == ~m_pc~0); 409150#L402-29 is_master_triggered_~__retres1~0#1 := 0; 409148#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 409147#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 409146#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 409145#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 409144#L421-27 assume !(1 == ~t1_pc~0); 409143#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 409142#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 409141#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 409140#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 409139#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 409138#L440-27 assume !(1 == ~t2_pc~0); 409137#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 409136#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 409135#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 409134#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 409133#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 409132#L459-27 assume 1 == ~t3_pc~0; 409130#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 409128#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 409126#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 409124#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 409123#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 409122#L478-27 assume !(1 == ~t4_pc~0); 409121#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 409120#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 409119#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 409118#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 409117#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 409116#L497-27 assume 1 == ~t5_pc~0; 409114#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 409113#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 409112#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 409111#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 409110#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 409109#L516-27 assume !(1 == ~t6_pc~0); 409108#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 409107#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 409106#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 409105#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 409104#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 409103#L535-27 assume !(1 == ~t7_pc~0); 409102#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 409100#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 409099#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 409098#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 409097#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 409096#L554-27 assume !(1 == ~t8_pc~0); 409095#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 409094#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 409093#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 409092#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 409091#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 409090#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 409089#L931-5 assume !(1 == ~T1_E~0); 409088#L936-3 assume !(1 == ~T2_E~0); 409087#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 409086#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 409085#L951-3 assume !(1 == ~T5_E~0); 409084#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 409083#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 409082#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 409080#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 409077#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 409075#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 409062#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 409058#L991-3 assume !(1 == ~E_5~0); 409054#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 409049#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 409046#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 409044#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 408965#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 408954#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 408951#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 408946#L1291 assume !(0 == start_simulation_~tmp~3#1); 408943#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 408899#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 408886#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 408882#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 408876#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 408872#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 408867#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 408861#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 401738#L1272-2 [2024-10-13 17:46:09,395 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:09,395 INFO L85 PathProgramCache]: Analyzing trace with hash -1073000453, now seen corresponding path program 1 times [2024-10-13 17:46:09,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:09,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051155323] [2024-10-13 17:46:09,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:09,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:09,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:09,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:09,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:09,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051155323] [2024-10-13 17:46:09,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1051155323] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:09,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:09,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:09,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906686013] [2024-10-13 17:46:09,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:09,436 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-13 17:46:09,437 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:09,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1933720332, now seen corresponding path program 1 times [2024-10-13 17:46:09,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:09,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256048819] [2024-10-13 17:46:09,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:09,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:09,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:09,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:09,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:09,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256048819] [2024-10-13 17:46:09,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256048819] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:09,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:09,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:09,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069333651] [2024-10-13 17:46:09,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:09,465 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:09,466 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:09,466 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-13 17:46:09,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-13 17:46:09,466 INFO L87 Difference]: Start difference. First operand 24766 states and 34784 transitions. cyclomatic complexity: 10050 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:09,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:09,627 INFO L93 Difference]: Finished difference Result 41983 states and 58906 transitions. [2024-10-13 17:46:09,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41983 states and 58906 transitions. [2024-10-13 17:46:09,791 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41552 [2024-10-13 17:46:09,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41983 states to 41983 states and 58906 transitions. [2024-10-13 17:46:09,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41983 [2024-10-13 17:46:09,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41983 [2024-10-13 17:46:09,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41983 states and 58906 transitions. [2024-10-13 17:46:09,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:09,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41983 states and 58906 transitions. [2024-10-13 17:46:09,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41983 states and 58906 transitions. [2024-10-13 17:46:10,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41983 to 22079. [2024-10-13 17:46:10,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.4001539924815436) internal successors, (30914), 22078 states have internal predecessors, (30914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:10,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 30914 transitions. [2024-10-13 17:46:10,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 30914 transitions. [2024-10-13 17:46:10,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-13 17:46:10,478 INFO L425 stractBuchiCegarLoop]: Abstraction has 22079 states and 30914 transitions. [2024-10-13 17:46:10,478 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-13 17:46:10,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 30914 transitions. [2024-10-13 17:46:10,520 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-10-13 17:46:10,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:10,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:10,521 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:10,521 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:10,521 INFO L745 eck$LassoCheckResult]: Stem: 467765#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 467766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 468492#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 468493#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 468495#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 467883#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 467884#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 468490#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 468479#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 467969#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 467970#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 468227#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 468228#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 468059#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 468060#L838 assume !(0 == ~M_E~0); 468240#L838-2 assume !(0 == ~T1_E~0); 467563#L843-1 assume !(0 == ~T2_E~0); 467564#L848-1 assume !(0 == ~T3_E~0); 467682#L853-1 assume !(0 == ~T4_E~0); 468048#L858-1 assume !(0 == ~T5_E~0); 467518#L863-1 assume !(0 == ~T6_E~0); 467519#L868-1 assume !(0 == ~T7_E~0); 468544#L873-1 assume !(0 == ~T8_E~0); 468542#L878-1 assume !(0 == ~E_1~0); 468524#L883-1 assume !(0 == ~E_2~0); 468525#L888-1 assume !(0 == ~E_3~0); 468195#L893-1 assume !(0 == ~E_4~0); 468196#L898-1 assume !(0 == ~E_5~0); 468570#L903-1 assume !(0 == ~E_6~0); 468522#L908-1 assume !(0 == ~E_7~0); 468345#L913-1 assume !(0 == ~E_8~0); 467576#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 467577#L402 assume !(1 == ~m_pc~0); 467790#L402-2 is_master_triggered_~__retres1~0#1 := 0; 467709#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467710#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 467977#L1035 assume !(0 != activate_threads_~tmp~1#1); 467978#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 468034#L421 assume !(1 == ~t1_pc~0); 468516#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 468547#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 467578#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 467579#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 468089#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 468563#L440 assume !(1 == ~t2_pc~0); 468617#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 467719#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 467720#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 467910#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 468363#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 467921#L459 assume !(1 == ~t3_pc~0); 467922#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 468510#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 467538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 467539#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 467703#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 467713#L478 assume !(1 == ~t4_pc~0); 467714#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 468415#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 467654#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 467655#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 467619#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 467620#L497 assume !(1 == ~t5_pc~0); 467665#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 467666#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 468284#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 468411#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 468504#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 468505#L516 assume !(1 == ~t6_pc~0); 468428#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 468226#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 467893#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 467759#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 467760#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 468215#L535 assume !(1 == ~t7_pc~0); 468216#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 468299#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 468300#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 468337#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 468327#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 468328#L554 assume !(1 == ~t8_pc~0); 467540#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 467541#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 468355#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 467849#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 467850#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 467528#L931 assume !(1 == ~M_E~0); 467529#L931-2 assume !(1 == ~T1_E~0); 468537#L936-1 assume !(1 == ~T2_E~0); 468583#L941-1 assume !(1 == ~T3_E~0); 468035#L946-1 assume !(1 == ~T4_E~0); 468036#L951-1 assume !(1 == ~T5_E~0); 467774#L956-1 assume !(1 == ~T6_E~0); 467775#L961-1 assume !(1 == ~T7_E~0); 468197#L966-1 assume !(1 == ~T8_E~0); 468198#L971-1 assume !(1 == ~E_1~0); 468330#L976-1 assume !(1 == ~E_2~0); 468289#L981-1 assume !(1 == ~E_3~0); 468039#L986-1 assume !(1 == ~E_4~0); 467802#L991-1 assume !(1 == ~E_5~0); 467803#L996-1 assume !(1 == ~E_6~0); 468554#L1001-1 assume !(1 == ~E_7~0); 468252#L1006-1 assume !(1 == ~E_8~0); 468253#L1011-1 assume { :end_inline_reset_delta_events } true; 468514#L1272-2 [2024-10-13 17:46:10,522 INFO L747 eck$LassoCheckResult]: Loop: 468514#L1272-2 assume !false; 475412#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 475411#L813-1 assume !false; 475410#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 475405#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 475396#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 475379#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 475374#L696 assume !(0 != eval_~tmp~0#1); 475375#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 476511#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 476504#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 476500#L838-5 assume !(0 == ~T1_E~0); 476495#L843-3 assume !(0 == ~T2_E~0); 476489#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 476484#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 476478#L858-3 assume !(0 == ~T5_E~0); 476473#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 476468#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 476463#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 476457#L878-3 assume !(0 == ~E_1~0); 476451#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 476446#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 476441#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 476436#L898-3 assume !(0 == ~E_5~0); 476431#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 476425#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 476420#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 476414#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475781#L402-27 assume !(1 == ~m_pc~0); 475778#L402-29 is_master_triggered_~__retres1~0#1 := 0; 475775#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475773#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 475771#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 475769#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475765#L421-27 assume !(1 == ~t1_pc~0); 475763#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 475761#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475759#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 475756#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 475754#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 475752#L440-27 assume !(1 == ~t2_pc~0); 475750#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 475748#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475746#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 475744#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 475742#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475740#L459-27 assume !(1 == ~t3_pc~0); 475735#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 475733#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 475731#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 475729#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 475726#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475724#L478-27 assume !(1 == ~t4_pc~0); 475722#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 475720#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475718#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 475716#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 475714#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475712#L497-27 assume !(1 == ~t5_pc~0); 475709#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 475706#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 475704#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 475702#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 475700#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 475698#L516-27 assume !(1 == ~t6_pc~0); 475695#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 475693#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 475691#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475689#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 475687#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 475686#L535-27 assume !(1 == ~t7_pc~0); 475685#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 475680#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 475678#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 475676#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 475675#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 475672#L554-27 assume !(1 == ~t8_pc~0); 475671#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 475670#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 475667#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 475663#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 475659#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475654#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 475652#L931-5 assume !(1 == ~T1_E~0); 475650#L936-3 assume !(1 == ~T2_E~0); 475649#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 475648#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 475647#L951-3 assume !(1 == ~T5_E~0); 475637#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 475635#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 475633#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 475630#L971-3 assume !(1 == ~E_1~0); 475626#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 475622#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 475618#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 475614#L991-3 assume !(1 == ~E_5~0); 475611#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 475608#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 475607#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 475606#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 475493#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 475484#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 475482#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 475479#L1291 assume !(0 == start_simulation_~tmp~3#1); 475476#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 475448#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 475438#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 475436#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 475434#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 475433#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 475432#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 475428#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 468514#L1272-2 [2024-10-13 17:46:10,522 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:10,522 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2024-10-13 17:46:10,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:10,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899452362] [2024-10-13 17:46:10,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:10,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:10,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:10,534 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:10,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:10,573 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:10,574 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:10,574 INFO L85 PathProgramCache]: Analyzing trace with hash 1077012108, now seen corresponding path program 1 times [2024-10-13 17:46:10,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:10,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318206299] [2024-10-13 17:46:10,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:10,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:10,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:10,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:10,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:10,609 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318206299] [2024-10-13 17:46:10,609 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1318206299] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:10,609 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:10,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:10,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172864199] [2024-10-13 17:46:10,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:10,610 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:10,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:10,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:10,610 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:10,610 INFO L87 Difference]: Start difference. First operand 22079 states and 30914 transitions. cyclomatic complexity: 8867 Second operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:10,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:10,698 INFO L93 Difference]: Finished difference Result 22303 states and 31138 transitions. [2024-10-13 17:46:10,698 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22303 states and 31138 transitions. [2024-10-13 17:46:10,761 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22064 [2024-10-13 17:46:10,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22303 states to 22303 states and 31138 transitions. [2024-10-13 17:46:10,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22303 [2024-10-13 17:46:10,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22303 [2024-10-13 17:46:10,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22303 states and 31138 transitions. [2024-10-13 17:46:10,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:10,820 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22303 states and 31138 transitions. [2024-10-13 17:46:10,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22303 states and 31138 transitions. [2024-10-13 17:46:11,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22303 to 22175. [2024-10-13 17:46:11,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22175 states, 22175 states have (on average 1.3984216459977452) internal successors, (31010), 22174 states have internal predecessors, (31010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:11,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22175 states to 22175 states and 31010 transitions. [2024-10-13 17:46:11,234 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22175 states and 31010 transitions. [2024-10-13 17:46:11,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:11,235 INFO L425 stractBuchiCegarLoop]: Abstraction has 22175 states and 31010 transitions. [2024-10-13 17:46:11,235 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-13 17:46:11,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22175 states and 31010 transitions. [2024-10-13 17:46:11,277 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21936 [2024-10-13 17:46:11,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:11,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:11,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:11,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:11,278 INFO L745 eck$LassoCheckResult]: Stem: 512158#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 512159#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 512871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512872#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 512874#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 512274#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 512275#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 512869#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 512859#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 512351#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 512352#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 512608#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 512609#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 512439#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 512440#L838 assume !(0 == ~M_E~0); 512619#L838-2 assume !(0 == ~T1_E~0); 511954#L843-1 assume !(0 == ~T2_E~0); 511955#L848-1 assume !(0 == ~T3_E~0); 512075#L853-1 assume !(0 == ~T4_E~0); 512428#L858-1 assume !(0 == ~T5_E~0); 511910#L863-1 assume !(0 == ~T6_E~0); 511911#L868-1 assume !(0 == ~T7_E~0); 512924#L873-1 assume !(0 == ~T8_E~0); 512921#L878-1 assume !(0 == ~E_1~0); 512903#L883-1 assume !(0 == ~E_2~0); 512904#L888-1 assume !(0 == ~E_3~0); 512577#L893-1 assume !(0 == ~E_4~0); 512578#L898-1 assume !(0 == ~E_5~0); 512943#L903-1 assume !(0 == ~E_6~0); 512900#L908-1 assume !(0 == ~E_7~0); 512724#L913-1 assume !(0 == ~E_8~0); 511968#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 511969#L402 assume !(1 == ~m_pc~0); 512185#L402-2 is_master_triggered_~__retres1~0#1 := 0; 512100#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 512101#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 512357#L1035 assume !(0 != activate_threads_~tmp~1#1); 512358#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 512413#L421 assume !(1 == ~t1_pc~0); 512892#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 512928#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 511970#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 511971#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 512472#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 512939#L440 assume !(1 == ~t2_pc~0); 512993#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 512111#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 512112#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 512300#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 512747#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 512307#L459 assume !(1 == ~t3_pc~0); 512308#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 512889#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 511928#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 511929#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 512094#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 512104#L478 assume !(1 == ~t4_pc~0); 512105#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 512799#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 512046#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 512047#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 512010#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 512011#L497 assume !(1 == ~t5_pc~0); 512057#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 512058#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 512657#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 512793#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 512881#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 512882#L516 assume !(1 == ~t6_pc~0); 512818#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 512607#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 512284#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 512152#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 512153#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 512595#L535 assume !(1 == ~t7_pc~0); 512596#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 512672#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 512673#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 512714#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 512705#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 512706#L554 assume !(1 == ~t8_pc~0); 511930#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 511931#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 512738#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 512240#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 512241#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511918#L931 assume !(1 == ~M_E~0); 511919#L931-2 assume !(1 == ~T1_E~0); 512914#L936-1 assume !(1 == ~T2_E~0); 512957#L941-1 assume !(1 == ~T3_E~0); 512414#L946-1 assume !(1 == ~T4_E~0); 512415#L951-1 assume !(1 == ~T5_E~0); 512167#L956-1 assume !(1 == ~T6_E~0); 512168#L961-1 assume !(1 == ~T7_E~0); 512579#L966-1 assume !(1 == ~T8_E~0); 512580#L971-1 assume !(1 == ~E_1~0); 512708#L976-1 assume !(1 == ~E_2~0); 512662#L981-1 assume !(1 == ~E_3~0); 512418#L986-1 assume !(1 == ~E_4~0); 512194#L991-1 assume !(1 == ~E_5~0); 512195#L996-1 assume !(1 == ~E_6~0); 512932#L1001-1 assume !(1 == ~E_7~0); 512630#L1006-1 assume !(1 == ~E_8~0); 512631#L1011-1 assume { :end_inline_reset_delta_events } true; 512890#L1272-2 [2024-10-13 17:46:11,279 INFO L747 eck$LassoCheckResult]: Loop: 512890#L1272-2 assume !false; 515692#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 515690#L813-1 assume !false; 515688#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 515682#L634 assume !(0 == ~m_st~0); 515683#L638 assume !(0 == ~t1_st~0); 515678#L642 assume !(0 == ~t2_st~0); 515679#L646 assume !(0 == ~t3_st~0); 515681#L650 assume !(0 == ~t4_st~0); 515674#L654 assume !(0 == ~t5_st~0); 515675#L658 assume !(0 == ~t6_st~0); 515680#L662 assume !(0 == ~t7_st~0); 515676#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 515677#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 517166#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 517164#L696 assume !(0 != eval_~tmp~0#1); 517162#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 517160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 517158#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 517156#L838-5 assume !(0 == ~T1_E~0); 517154#L843-3 assume !(0 == ~T2_E~0); 517152#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 517150#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 517147#L858-3 assume !(0 == ~T5_E~0); 517145#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 517143#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 517141#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 517139#L878-3 assume !(0 == ~E_1~0); 517136#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 517134#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 517132#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 517130#L898-3 assume !(0 == ~E_5~0); 517128#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 517126#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 517124#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 517122#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517120#L402-27 assume !(1 == ~m_pc~0); 517118#L402-29 is_master_triggered_~__retres1~0#1 := 0; 517115#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 517113#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 517109#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 517107#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 517105#L421-27 assume !(1 == ~t1_pc~0); 517103#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 517100#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 517098#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 517096#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 517093#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 517091#L440-27 assume !(1 == ~t2_pc~0); 517089#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 517087#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 517085#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 517083#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 517080#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 517078#L459-27 assume 1 == ~t3_pc~0; 517076#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 517077#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 517183#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 517067#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 517065#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 517063#L478-27 assume !(1 == ~t4_pc~0); 517061#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 517059#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 517057#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 517055#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 517052#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 517050#L497-27 assume 1 == ~t5_pc~0; 517047#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 517045#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 517043#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 517041#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 517038#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 517036#L516-27 assume !(1 == ~t6_pc~0); 517034#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 517032#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 517030#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 517028#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 517026#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 517024#L535-27 assume !(1 == ~t7_pc~0); 517022#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 517019#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 517017#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 517015#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 517013#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 517011#L554-27 assume !(1 == ~t8_pc~0); 517009#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 517007#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 517005#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 517003#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 517001#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516999#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 516997#L931-5 assume !(1 == ~T1_E~0); 516995#L936-3 assume !(1 == ~T2_E~0); 516993#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 516992#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 516991#L951-3 assume !(1 == ~T5_E~0); 516990#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 516980#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 516978#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 516976#L971-3 assume !(1 == ~E_1~0); 516972#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 516970#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 516969#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 516968#L991-3 assume !(1 == ~E_5~0); 516967#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 516966#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 516965#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 516964#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 516962#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 516840#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 516056#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 516053#L1291 assume !(0 == start_simulation_~tmp~3#1); 516051#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 516050#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 515986#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 515981#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 515979#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 515977#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 515975#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 515974#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 512890#L1272-2 [2024-10-13 17:46:11,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:11,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 2 times [2024-10-13 17:46:11,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:11,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679146296] [2024-10-13 17:46:11,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:11,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:11,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:11,287 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:11,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:11,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:11,311 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:11,311 INFO L85 PathProgramCache]: Analyzing trace with hash 1342151226, now seen corresponding path program 1 times [2024-10-13 17:46:11,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:11,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057745473] [2024-10-13 17:46:11,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:11,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:11,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:11,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:11,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:11,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2057745473] [2024-10-13 17:46:11,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2057745473] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:11,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:11,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:11,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2120196948] [2024-10-13 17:46:11,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:11,337 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:11,337 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:11,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:11,337 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:11,337 INFO L87 Difference]: Start difference. First operand 22175 states and 31010 transitions. cyclomatic complexity: 8867 Second operand has 3 states, 3 states have (on average 40.0) internal successors, (120), 3 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:11,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:11,465 INFO L93 Difference]: Finished difference Result 40724 states and 56454 transitions. [2024-10-13 17:46:11,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40724 states and 56454 transitions. [2024-10-13 17:46:11,589 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40320 [2024-10-13 17:46:11,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40724 states to 40724 states and 56454 transitions. [2024-10-13 17:46:11,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40724 [2024-10-13 17:46:11,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40724 [2024-10-13 17:46:11,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40724 states and 56454 transitions. [2024-10-13 17:46:11,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:11,712 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40724 states and 56454 transitions. [2024-10-13 17:46:11,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40724 states and 56454 transitions. [2024-10-13 17:46:12,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40724 to 40708. [2024-10-13 17:46:12,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40708 states, 40708 states have (on average 1.3864105335560577) internal successors, (56438), 40707 states have internal predecessors, (56438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:12,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40708 states to 40708 states and 56438 transitions. [2024-10-13 17:46:12,204 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40708 states and 56438 transitions. [2024-10-13 17:46:12,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:12,205 INFO L425 stractBuchiCegarLoop]: Abstraction has 40708 states and 56438 transitions. [2024-10-13 17:46:12,205 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-13 17:46:12,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40708 states and 56438 transitions. [2024-10-13 17:46:12,296 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40304 [2024-10-13 17:46:12,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:12,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:12,297 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:12,298 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:12,298 INFO L745 eck$LassoCheckResult]: Stem: 575061#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 575062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 575802#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 575803#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 575805#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 575180#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 575181#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 575798#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 575788#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 575266#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 575267#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 575525#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 575526#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 575356#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 575357#L838 assume !(0 == ~M_E~0); 575534#L838-2 assume !(0 == ~T1_E~0); 574858#L843-1 assume !(0 == ~T2_E~0); 574859#L848-1 assume !(0 == ~T3_E~0); 574977#L853-1 assume !(0 == ~T4_E~0); 575343#L858-1 assume !(0 == ~T5_E~0); 574813#L863-1 assume !(0 == ~T6_E~0); 574814#L868-1 assume !(0 == ~T7_E~0); 575863#L873-1 assume !(0 == ~T8_E~0); 575860#L878-1 assume !(0 == ~E_1~0); 575834#L883-1 assume !(0 == ~E_2~0); 575835#L888-1 assume !(0 == ~E_3~0); 575489#L893-1 assume !(0 == ~E_4~0); 575490#L898-1 assume !(0 == ~E_5~0); 575880#L903-1 assume !(0 == ~E_6~0); 575832#L908-1 assume !(0 == ~E_7~0); 575644#L913-1 assume !(0 == ~E_8~0); 574870#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 574871#L402 assume !(1 == ~m_pc~0); 575084#L402-2 is_master_triggered_~__retres1~0#1 := 0; 575005#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 575006#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 575273#L1035 assume !(0 != activate_threads_~tmp~1#1); 575274#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 575329#L421 assume !(1 == ~t1_pc~0); 575827#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 575865#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 574873#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 574874#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 575385#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 575875#L440 assume !(1 == ~t2_pc~0); 575942#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 575015#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 575016#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 575208#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 575665#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 575214#L459 assume !(1 == ~t3_pc~0); 575215#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 575822#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 575873#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 574998#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 574999#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 575009#L478 assume !(1 == ~t4_pc~0); 575010#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 575724#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 574949#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 574950#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 574911#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 574912#L497 assume !(1 == ~t5_pc~0); 574960#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 575448#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 575719#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 575720#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 575814#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 575815#L516 assume !(1 == ~t6_pc~0); 575737#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 575738#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 575190#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 575191#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 575597#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 575598#L535 assume !(1 == ~t7_pc~0); 575769#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 575768#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 575923#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 575635#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 575624#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 575625#L554 assume !(1 == ~t8_pc~0); 574835#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 574836#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 575963#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 575141#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 575142#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 574823#L931 assume !(1 == ~M_E~0); 574824#L931-2 assume !(1 == ~T1_E~0); 575892#L936-1 assume !(1 == ~T2_E~0); 575893#L941-1 assume !(1 == ~T3_E~0); 575330#L946-1 assume !(1 == ~T4_E~0); 575331#L951-1 assume !(1 == ~T5_E~0); 575960#L956-1 assume !(1 == ~T6_E~0); 575932#L961-1 assume !(1 == ~T7_E~0); 575933#L966-1 assume !(1 == ~T8_E~0); 575959#L971-1 assume !(1 == ~E_1~0); 575908#L976-1 assume !(1 == ~E_2~0); 575583#L981-1 assume !(1 == ~E_3~0); 575334#L986-1 assume !(1 == ~E_4~0); 575335#L991-1 assume !(1 == ~E_5~0); 575098#L996-1 assume !(1 == ~E_6~0); 575869#L1001-1 assume !(1 == ~E_7~0); 575547#L1006-1 assume !(1 == ~E_8~0); 575548#L1011-1 assume { :end_inline_reset_delta_events } true; 575825#L1272-2 [2024-10-13 17:46:12,298 INFO L747 eck$LassoCheckResult]: Loop: 575825#L1272-2 assume !false; 602177#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 598148#L813-1 assume !false; 602176#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 602174#L634 assume !(0 == ~m_st~0); 602175#L638 assume !(0 == ~t1_st~0); 602170#L642 assume !(0 == ~t2_st~0); 602171#L646 assume !(0 == ~t3_st~0); 602173#L650 assume !(0 == ~t4_st~0); 602166#L654 assume !(0 == ~t5_st~0); 602167#L658 assume !(0 == ~t6_st~0); 602172#L662 assume !(0 == ~t7_st~0); 602168#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 602169#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 602113#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 602114#L696 assume !(0 != eval_~tmp~0#1); 602516#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 602514#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 602512#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 602510#L838-5 assume !(0 == ~T1_E~0); 602508#L843-3 assume !(0 == ~T2_E~0); 602506#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 602504#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 602502#L858-3 assume !(0 == ~T5_E~0); 602500#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 602498#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 602496#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 602494#L878-3 assume !(0 == ~E_1~0); 602492#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 602490#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 602488#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 602486#L898-3 assume !(0 == ~E_5~0); 602484#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 602482#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 602480#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 602478#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602476#L402-27 assume !(1 == ~m_pc~0); 602473#L402-29 is_master_triggered_~__retres1~0#1 := 0; 602470#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 602468#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 602466#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 602463#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 602459#L421-27 assume !(1 == ~t1_pc~0); 602456#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 602453#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 602450#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 602447#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 602444#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 602441#L440-27 assume !(1 == ~t2_pc~0); 602438#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 602435#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 602432#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 602429#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 602426#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 602423#L459-27 assume !(1 == ~t3_pc~0); 602419#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 602414#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 602409#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 602404#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 602400#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 602396#L478-27 assume !(1 == ~t4_pc~0); 602392#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 602388#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 602384#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 602381#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 602378#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 602374#L497-27 assume !(1 == ~t5_pc~0); 602369#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 602366#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602363#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 602360#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 602357#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 602353#L516-27 assume !(1 == ~t6_pc~0); 602349#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 602345#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 602341#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 602337#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 602333#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 602329#L535-27 assume 1 == ~t7_pc~0; 602323#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 602319#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 602315#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 602311#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 602307#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 602301#L554-27 assume !(1 == ~t8_pc~0); 602297#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 602293#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 602289#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 602285#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 602281#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 602277#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 602273#L931-5 assume !(1 == ~T1_E~0); 602269#L936-3 assume !(1 == ~T2_E~0); 602265#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 602261#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 602257#L951-3 assume !(1 == ~T5_E~0); 602253#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 602249#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 602245#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 602241#L971-3 assume !(1 == ~E_1~0); 602237#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 602233#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 602229#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 602225#L991-3 assume !(1 == ~E_5~0); 602222#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 602219#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 602216#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 602213#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 602209#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 602200#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 602198#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 602195#L1291 assume !(0 == start_simulation_~tmp~3#1); 602193#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 602192#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 602183#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 602182#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 602181#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 602180#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 602179#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 602178#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 575825#L1272-2 [2024-10-13 17:46:12,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:12,299 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 3 times [2024-10-13 17:46:12,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:12,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642071464] [2024-10-13 17:46:12,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:12,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:12,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,306 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:12,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:12,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:12,323 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:12,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1193202729, now seen corresponding path program 1 times [2024-10-13 17:46:12,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:12,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252916183] [2024-10-13 17:46:12,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:12,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:12,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:12,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:12,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:12,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252916183] [2024-10-13 17:46:12,368 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252916183] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:12,368 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:12,368 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:12,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103964009] [2024-10-13 17:46:12,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:12,368 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:12,368 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:12,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:12,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:12,369 INFO L87 Difference]: Start difference. First operand 40708 states and 56438 transitions. cyclomatic complexity: 15762 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:12,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:12,590 INFO L93 Difference]: Finished difference Result 42103 states and 57833 transitions. [2024-10-13 17:46:12,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42103 states and 57833 transitions. [2024-10-13 17:46:12,723 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41696 [2024-10-13 17:46:13,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42103 states to 42103 states and 57833 transitions. [2024-10-13 17:46:13,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42103 [2024-10-13 17:46:13,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42103 [2024-10-13 17:46:13,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42103 states and 57833 transitions. [2024-10-13 17:46:13,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:13,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42103 states and 57833 transitions. [2024-10-13 17:46:13,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42103 states and 57833 transitions. [2024-10-13 17:46:13,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42103 to 42103. [2024-10-13 17:46:13,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42103 states, 42103 states have (on average 1.3736075814075006) internal successors, (57833), 42102 states have internal predecessors, (57833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:13,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42103 states to 42103 states and 57833 transitions. [2024-10-13 17:46:13,527 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42103 states and 57833 transitions. [2024-10-13 17:46:13,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:13,528 INFO L425 stractBuchiCegarLoop]: Abstraction has 42103 states and 57833 transitions. [2024-10-13 17:46:13,528 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-13 17:46:13,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42103 states and 57833 transitions. [2024-10-13 17:46:13,639 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41696 [2024-10-13 17:46:13,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:13,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:13,640 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:13,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:13,641 INFO L745 eck$LassoCheckResult]: Stem: 657881#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 657882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 658616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 658617#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 658618#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 658002#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 658003#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 658608#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 658602#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 658078#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 658079#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 658337#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 658338#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 658166#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 658167#L838 assume !(0 == ~M_E~0); 658347#L838-2 assume !(0 == ~T1_E~0); 657677#L843-1 assume !(0 == ~T2_E~0); 657678#L848-1 assume !(0 == ~T3_E~0); 657797#L853-1 assume !(0 == ~T4_E~0); 658153#L858-1 assume !(0 == ~T5_E~0); 657632#L863-1 assume !(0 == ~T6_E~0); 657633#L868-1 assume !(0 == ~T7_E~0); 658675#L873-1 assume !(0 == ~T8_E~0); 658668#L878-1 assume !(0 == ~E_1~0); 658646#L883-1 assume !(0 == ~E_2~0); 658647#L888-1 assume !(0 == ~E_3~0); 658302#L893-1 assume !(0 == ~E_4~0); 658303#L898-1 assume !(0 == ~E_5~0); 658700#L903-1 assume !(0 == ~E_6~0); 658644#L908-1 assume !(0 == ~E_7~0); 658452#L913-1 assume !(0 == ~E_8~0); 657689#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 657690#L402 assume !(1 == ~m_pc~0); 657907#L402-2 is_master_triggered_~__retres1~0#1 := 0; 657824#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 657825#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 658084#L1035 assume !(0 != activate_threads_~tmp~1#1); 658085#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 658140#L421 assume !(1 == ~t1_pc~0); 658637#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 658677#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 657692#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 657693#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 658198#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 658689#L440 assume !(1 == ~t2_pc~0); 658761#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 657834#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 657835#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 658029#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 658471#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 658033#L459 assume !(1 == ~t3_pc~0); 658034#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 658632#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 657652#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 657653#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 657818#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 657828#L478 assume !(1 == ~t4_pc~0); 657829#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 658528#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 657769#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 657770#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 657730#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 657731#L497 assume !(1 == ~t5_pc~0); 657780#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 658262#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 658523#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 658524#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 658627#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 658628#L516 assume !(1 == ~t6_pc~0); 658546#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 658547#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 658012#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 657875#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 657876#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 658411#L535 assume !(1 == ~t7_pc~0); 658581#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 658407#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 658408#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 658794#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 658793#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 658619#L554 assume !(1 == ~t8_pc~0); 658620#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 658714#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 658463#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 658464#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 658791#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 658790#L931 assume !(1 == ~M_E~0); 658659#L931-2 assume !(1 == ~T1_E~0); 658660#L936-1 assume !(1 == ~T2_E~0); 658789#L941-1 assume !(1 == ~T3_E~0); 658141#L946-1 assume !(1 == ~T4_E~0); 658142#L951-1 assume !(1 == ~T5_E~0); 658788#L956-1 assume !(1 == ~T6_E~0); 658787#L961-1 assume !(1 == ~T7_E~0); 658304#L966-1 assume !(1 == ~T8_E~0); 658305#L971-1 assume !(1 == ~E_1~0); 658435#L976-1 assume !(1 == ~E_2~0); 658396#L981-1 assume !(1 == ~E_3~0); 658145#L986-1 assume !(1 == ~E_4~0); 658146#L991-1 assume !(1 == ~E_5~0); 657921#L996-1 assume !(1 == ~E_6~0); 658682#L1001-1 assume !(1 == ~E_7~0); 658360#L1006-1 assume !(1 == ~E_8~0); 658361#L1011-1 assume { :end_inline_reset_delta_events } true; 658635#L1272-2 [2024-10-13 17:46:13,641 INFO L747 eck$LassoCheckResult]: Loop: 658635#L1272-2 assume !false; 666129#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 666120#L813-1 assume !false; 666112#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 666109#L634 assume !(0 == ~m_st~0); 666110#L638 assume !(0 == ~t1_st~0); 666105#L642 assume !(0 == ~t2_st~0); 666106#L646 assume !(0 == ~t3_st~0); 666108#L650 assume !(0 == ~t4_st~0); 666101#L654 assume !(0 == ~t5_st~0); 666102#L658 assume !(0 == ~t6_st~0); 666107#L662 assume !(0 == ~t7_st~0); 666103#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 666104#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 666097#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 666098#L696 assume !(0 != eval_~tmp~0#1); 668247#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 668242#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 668236#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 668230#L838-5 assume !(0 == ~T1_E~0); 668222#L843-3 assume !(0 == ~T2_E~0); 668218#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 668213#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 668208#L858-3 assume !(0 == ~T5_E~0); 668203#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 668198#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 668193#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 668187#L878-3 assume !(0 == ~E_1~0); 668182#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 668177#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 668171#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 668167#L898-3 assume !(0 == ~E_5~0); 667321#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 667317#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 667315#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 667313#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 667311#L402-27 assume !(1 == ~m_pc~0); 667307#L402-29 is_master_triggered_~__retres1~0#1 := 0; 667305#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 667303#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 667301#L1035-27 assume !(0 != activate_threads_~tmp~1#1); 667298#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 667296#L421-27 assume !(1 == ~t1_pc~0); 667294#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 667291#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 667289#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 667287#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 667285#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 667283#L440-27 assume !(1 == ~t2_pc~0); 667281#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 667279#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 667277#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 667275#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 667273#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 667271#L459-27 assume 1 == ~t3_pc~0; 667268#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 667266#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 667264#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 667260#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 667258#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 667256#L478-27 assume !(1 == ~t4_pc~0); 667254#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 667252#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 667250#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 667248#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 667246#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 667244#L497-27 assume 1 == ~t5_pc~0; 667243#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 667170#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 667168#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 667166#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 667164#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 667162#L516-27 assume !(1 == ~t6_pc~0); 667161#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 667160#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 667159#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 667158#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 667156#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 667155#L535-27 assume 1 == ~t7_pc~0; 667152#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 667150#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 667148#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 667144#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 667142#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 667140#L554-27 assume !(1 == ~t8_pc~0); 667138#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 667135#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 667133#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 667131#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 667129#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 667127#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 667125#L931-5 assume !(1 == ~T1_E~0); 667123#L936-3 assume !(1 == ~T2_E~0); 667121#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 667117#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 667115#L951-3 assume !(1 == ~T5_E~0); 667113#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 667111#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 667109#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 667107#L971-3 assume !(1 == ~E_1~0); 667105#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 667102#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 667100#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 667098#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 667095#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 667093#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 667091#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 667088#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 666740#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 666723#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 666717#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 666710#L1291 assume !(0 == start_simulation_~tmp~3#1); 666705#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 666419#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 666409#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 666408#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 666404#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 666402#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 666400#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 666399#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 658635#L1272-2 [2024-10-13 17:46:13,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:13,642 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 4 times [2024-10-13 17:46:13,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:13,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801674720] [2024-10-13 17:46:13,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:13,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:13,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:13,656 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:13,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:13,681 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:13,681 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:13,681 INFO L85 PathProgramCache]: Analyzing trace with hash -351456233, now seen corresponding path program 1 times [2024-10-13 17:46:13,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:13,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320908918] [2024-10-13 17:46:13,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:13,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:13,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:13,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:13,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:13,719 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320908918] [2024-10-13 17:46:13,719 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320908918] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:13,719 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:13,719 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:13,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215518421] [2024-10-13 17:46:13,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:13,720 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:13,720 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:13,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:13,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:13,720 INFO L87 Difference]: Start difference. First operand 42103 states and 57833 transitions. cyclomatic complexity: 15762 Second operand has 3 states, 3 states have (on average 40.0) internal successors, (120), 3 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:13,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:13,933 INFO L93 Difference]: Finished difference Result 80023 states and 108801 transitions. [2024-10-13 17:46:13,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80023 states and 108801 transitions. [2024-10-13 17:46:14,509 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79360 [2024-10-13 17:46:14,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80023 states to 80023 states and 108801 transitions. [2024-10-13 17:46:14,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80023 [2024-10-13 17:46:14,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80023 [2024-10-13 17:46:14,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80023 states and 108801 transitions. [2024-10-13 17:46:14,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:14,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80023 states and 108801 transitions. [2024-10-13 17:46:14,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80023 states and 108801 transitions. [2024-10-13 17:46:15,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80023 to 76151. [2024-10-13 17:46:15,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76151 states, 76151 states have (on average 1.362358997255453) internal successors, (103745), 76150 states have internal predecessors, (103745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:15,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76151 states to 76151 states and 103745 transitions. [2024-10-13 17:46:15,710 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76151 states and 103745 transitions. [2024-10-13 17:46:15,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-13 17:46:15,711 INFO L425 stractBuchiCegarLoop]: Abstraction has 76151 states and 103745 transitions. [2024-10-13 17:46:15,711 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-10-13 17:46:15,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76151 states and 103745 transitions. [2024-10-13 17:46:15,870 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75488 [2024-10-13 17:46:15,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:15,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:15,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:15,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:15,871 INFO L745 eck$LassoCheckResult]: Stem: 780013#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 780014#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 780791#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 780792#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 780794#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 780135#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 780136#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 780785#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 780772#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 780220#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 780221#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 780488#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 780489#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 780310#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 780311#L838 assume !(0 == ~M_E~0); 780498#L838-2 assume !(0 == ~T1_E~0); 779810#L843-1 assume !(0 == ~T2_E~0); 779811#L848-1 assume !(0 == ~T3_E~0); 779929#L853-1 assume !(0 == ~T4_E~0); 780296#L858-1 assume !(0 == ~T5_E~0); 779764#L863-1 assume !(0 == ~T6_E~0); 779765#L868-1 assume !(0 == ~T7_E~0); 780856#L873-1 assume !(0 == ~T8_E~0); 780852#L878-1 assume !(0 == ~E_1~0); 780826#L883-1 assume !(0 == ~E_2~0); 780827#L888-1 assume !(0 == ~E_3~0); 780453#L893-1 assume !(0 == ~E_4~0); 780454#L898-1 assume !(0 == ~E_5~0); 780883#L903-1 assume !(0 == ~E_6~0); 780824#L908-1 assume !(0 == ~E_7~0); 780620#L913-1 assume !(0 == ~E_8~0); 779822#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 779823#L402 assume !(1 == ~m_pc~0); 780038#L402-2 is_master_triggered_~__retres1~0#1 := 0; 779954#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 779955#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 780227#L1035 assume !(0 != activate_threads_~tmp~1#1); 780228#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 780283#L421 assume !(1 == ~t1_pc~0); 780820#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 780858#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 779825#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 779826#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 780344#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 780872#L440 assume !(1 == ~t2_pc~0); 780960#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 779964#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 779965#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 780163#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 780637#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 780168#L459 assume !(1 == ~t3_pc~0); 780169#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 780813#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 779784#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 779785#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 779948#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 779958#L478 assume !(1 == ~t4_pc~0); 779959#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 780697#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 779900#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 779901#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 779862#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 779863#L497 assume !(1 == ~t5_pc~0); 779911#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 780412#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 780551#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 780873#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 780874#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 780945#L516 assume !(1 == ~t6_pc~0); 780946#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 780486#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 780487#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 780007#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 780008#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 780572#L535 assume !(1 == ~t7_pc~0); 780753#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 780752#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 780932#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 780610#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 780598#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 780599#L554 assume !(1 == ~t8_pc~0); 779786#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 779787#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 780981#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 780096#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 780097#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 779774#L931 assume !(1 == ~M_E~0); 779775#L931-2 assume !(1 == ~T1_E~0); 780897#L936-1 assume !(1 == ~T2_E~0); 780898#L941-1 assume !(1 == ~T3_E~0); 780284#L946-1 assume !(1 == ~T4_E~0); 780285#L951-1 assume !(1 == ~T5_E~0); 780978#L956-1 assume !(1 == ~T6_E~0); 780977#L961-1 assume !(1 == ~T7_E~0); 780455#L966-1 assume !(1 == ~T8_E~0); 780456#L971-1 assume !(1 == ~E_1~0); 780601#L976-1 assume !(1 == ~E_2~0); 780558#L981-1 assume !(1 == ~E_3~0); 780288#L986-1 assume !(1 == ~E_4~0); 780289#L991-1 assume !(1 == ~E_5~0); 780052#L996-1 assume !(1 == ~E_6~0); 780864#L1001-1 assume !(1 == ~E_7~0); 780514#L1006-1 assume !(1 == ~E_8~0); 780515#L1011-1 assume { :end_inline_reset_delta_events } true; 780818#L1272-2 [2024-10-13 17:46:15,872 INFO L747 eck$LassoCheckResult]: Loop: 780818#L1272-2 assume !false; 791445#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 791443#L813-1 assume !false; 791441#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 791438#L634 assume !(0 == ~m_st~0); 791439#L638 assume !(0 == ~t1_st~0); 800805#L642 assume !(0 == ~t2_st~0); 800802#L646 assume !(0 == ~t3_st~0); 800800#L650 assume !(0 == ~t4_st~0); 800798#L654 assume !(0 == ~t5_st~0); 800796#L658 assume !(0 == ~t6_st~0); 800794#L662 assume !(0 == ~t7_st~0); 800791#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 800788#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 800786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 800784#L696 assume !(0 != eval_~tmp~0#1); 800782#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 800780#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 800778#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 800776#L838-5 assume !(0 == ~T1_E~0); 800774#L843-3 assume !(0 == ~T2_E~0); 800772#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 800770#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 800768#L858-3 assume !(0 == ~T5_E~0); 800767#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 800766#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 800764#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 800763#L878-3 assume !(0 == ~E_1~0); 800762#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 800760#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 800758#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 800756#L898-3 assume !(0 == ~E_5~0); 800755#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 800753#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 800751#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 800749#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 800747#L402-27 assume 1 == ~m_pc~0; 800744#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 800742#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 800740#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 800738#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 800736#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 800734#L421-27 assume !(1 == ~t1_pc~0); 800732#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 800730#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 800729#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 800725#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 800723#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 800721#L440-27 assume !(1 == ~t2_pc~0); 800719#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 800716#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 799538#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 799535#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 799533#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 799531#L459-27 assume 1 == ~t3_pc~0; 799529#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 799530#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 800671#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 799520#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 799518#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 799516#L478-27 assume !(1 == ~t4_pc~0); 799513#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 799511#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 799509#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 799507#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 799505#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 799503#L497-27 assume !(1 == ~t5_pc~0); 799500#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 799498#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 799496#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 799494#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 799492#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 799490#L516-27 assume !(1 == ~t6_pc~0); 799487#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 799485#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 799483#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 799481#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 799479#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 799477#L535-27 assume 1 == ~t7_pc~0; 799474#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 799472#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 799470#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 799468#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 799466#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 799464#L554-27 assume !(1 == ~t8_pc~0); 799462#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 799460#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 799458#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 799456#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 799454#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 799452#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 799450#L931-5 assume !(1 == ~T1_E~0); 799448#L936-3 assume !(1 == ~T2_E~0); 799446#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 799444#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 799442#L951-3 assume !(1 == ~T5_E~0); 799440#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 799437#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 799435#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 799433#L971-3 assume !(1 == ~E_1~0); 799006#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 795729#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 793684#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 792721#L991-3 assume !(1 == ~E_5~0); 792719#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 792717#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 792715#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 792713#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 792710#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 792707#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 792705#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 792702#L1291 assume !(0 == start_simulation_~tmp~3#1); 792699#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 792696#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 792694#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 792692#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 792690#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 792688#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 792686#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 792684#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 780818#L1272-2 [2024-10-13 17:46:15,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:15,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 5 times [2024-10-13 17:46:15,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:15,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374433309] [2024-10-13 17:46:15,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:15,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:15,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:15,881 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:15,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:15,897 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:15,898 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:15,898 INFO L85 PathProgramCache]: Analyzing trace with hash -239594341, now seen corresponding path program 1 times [2024-10-13 17:46:15,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:15,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174038055] [2024-10-13 17:46:15,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:15,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:15,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:15,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:15,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:15,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [174038055] [2024-10-13 17:46:15,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [174038055] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:15,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:15,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:15,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140152267] [2024-10-13 17:46:15,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:15,943 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:15,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:15,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:15,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:15,944 INFO L87 Difference]: Start difference. First operand 76151 states and 103745 transitions. cyclomatic complexity: 27626 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:16,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:16,215 INFO L93 Difference]: Finished difference Result 76247 states and 103008 transitions. [2024-10-13 17:46:16,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76247 states and 103008 transitions. [2024-10-13 17:46:16,468 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75584 [2024-10-13 17:46:16,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76247 states to 76247 states and 103008 transitions. [2024-10-13 17:46:16,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76247 [2024-10-13 17:46:16,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76247 [2024-10-13 17:46:16,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76247 states and 103008 transitions. [2024-10-13 17:46:17,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:17,083 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76247 states and 103008 transitions. [2024-10-13 17:46:17,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76247 states and 103008 transitions. [2024-10-13 17:46:17,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76247 to 76247. [2024-10-13 17:46:17,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76247 states, 76247 states have (on average 1.350977743386625) internal successors, (103008), 76246 states have internal predecessors, (103008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:17,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76247 states to 76247 states and 103008 transitions. [2024-10-13 17:46:17,701 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76247 states and 103008 transitions. [2024-10-13 17:46:17,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:17,701 INFO L425 stractBuchiCegarLoop]: Abstraction has 76247 states and 103008 transitions. [2024-10-13 17:46:17,701 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-10-13 17:46:17,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76247 states and 103008 transitions. [2024-10-13 17:46:17,884 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75584 [2024-10-13 17:46:17,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:17,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:17,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:17,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:17,885 INFO L745 eck$LassoCheckResult]: Stem: 932418#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 932419#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 933170#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 933171#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 933172#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 932540#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 932541#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 933161#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 933152#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 932621#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 932622#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 932888#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 932889#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 932708#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 932709#L838 assume !(0 == ~M_E~0); 932898#L838-2 assume !(0 == ~T1_E~0); 932215#L843-1 assume !(0 == ~T2_E~0); 932216#L848-1 assume !(0 == ~T3_E~0); 932334#L853-1 assume !(0 == ~T4_E~0); 932695#L858-1 assume !(0 == ~T5_E~0); 932170#L863-1 assume !(0 == ~T6_E~0); 932171#L868-1 assume !(0 == ~T7_E~0); 933233#L873-1 assume !(0 == ~T8_E~0); 933231#L878-1 assume !(0 == ~E_1~0); 933203#L883-1 assume !(0 == ~E_2~0); 933204#L888-1 assume !(0 == ~E_3~0); 932852#L893-1 assume !(0 == ~E_4~0); 932853#L898-1 assume !(0 == ~E_5~0); 933256#L903-1 assume !(0 == ~E_6~0); 933201#L908-1 assume !(0 == ~E_7~0); 933010#L913-1 assume !(0 == ~E_8~0); 932228#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 932229#L402 assume !(1 == ~m_pc~0); 932447#L402-2 is_master_triggered_~__retres1~0#1 := 0; 932360#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 932361#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 932628#L1035 assume !(0 != activate_threads_~tmp~1#1); 932629#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 932683#L421 assume !(1 == ~t1_pc~0); 933192#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 933236#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 932230#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 932231#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 932740#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 933245#L440 assume !(1 == ~t2_pc~0); 933327#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 932369#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 932370#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 932568#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 933031#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 932575#L459 assume !(1 == ~t3_pc~0); 932576#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 933187#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 933244#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 932353#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 932354#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 932364#L478 assume !(1 == ~t4_pc~0); 932365#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 933090#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 932306#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 932307#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 932267#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 932268#L497 assume !(1 == ~t5_pc~0); 932317#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 932806#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 932946#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 933246#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 933247#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 933314#L516 assume !(1 == ~t6_pc~0); 933315#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 932886#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 932887#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 932412#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 932413#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 932874#L535 assume !(1 == ~t7_pc~0); 932875#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 932961#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 932962#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 933348#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 933347#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 933173#L554 assume !(1 == ~t8_pc~0); 933174#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 933272#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 933019#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 933020#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 933345#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 933344#L931 assume !(1 == ~M_E~0); 933218#L931-2 assume !(1 == ~T1_E~0); 933219#L936-1 assume !(1 == ~T2_E~0); 933325#L941-1 assume !(1 == ~T3_E~0); 933326#L946-1 assume !(1 == ~T4_E~0); 933189#L951-1 assume !(1 == ~T5_E~0); 932428#L956-1 assume !(1 == ~T6_E~0); 932429#L961-1 assume !(1 == ~T7_E~0); 932854#L966-1 assume !(1 == ~T8_E~0); 932855#L971-1 assume !(1 == ~E_1~0); 932992#L976-1 assume !(1 == ~E_2~0); 933340#L981-1 assume !(1 == ~E_3~0); 933339#L986-1 assume !(1 == ~E_4~0); 933338#L991-1 assume !(1 == ~E_5~0); 932459#L996-1 assume !(1 == ~E_6~0); 933239#L1001-1 assume !(1 == ~E_7~0); 932913#L1006-1 assume !(1 == ~E_8~0); 932914#L1011-1 assume { :end_inline_reset_delta_events } true; 933190#L1272-2 [2024-10-13 17:46:17,886 INFO L747 eck$LassoCheckResult]: Loop: 933190#L1272-2 assume !false; 938403#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 938401#L813-1 assume !false; 938398#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 938395#L634 assume !(0 == ~m_st~0); 938396#L638 assume !(0 == ~t1_st~0); 947377#L642 assume !(0 == ~t2_st~0); 947378#L646 assume !(0 == ~t3_st~0); 947380#L650 assume !(0 == ~t4_st~0); 947375#L654 assume !(0 == ~t5_st~0); 947376#L658 assume !(0 == ~t6_st~0); 947379#L662 assume !(0 == ~t7_st~0); 947381#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 947371#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 947366#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 947360#L696 assume !(0 != eval_~tmp~0#1); 947354#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 947348#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 947342#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 947338#L838-5 assume !(0 == ~T1_E~0); 947335#L843-3 assume !(0 == ~T2_E~0); 947331#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 946390#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 946358#L858-3 assume !(0 == ~T5_E~0); 946351#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 946344#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 946335#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 946327#L878-3 assume !(0 == ~E_1~0); 946319#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 946306#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 946299#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 945058#L898-3 assume !(0 == ~E_5~0); 938766#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 938761#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 938759#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 938757#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 938755#L402-27 assume 1 == ~m_pc~0; 938752#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 938750#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 938748#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 938745#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 938743#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 938741#L421-27 assume !(1 == ~t1_pc~0); 938739#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 938737#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 938735#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 938733#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 938729#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 938727#L440-27 assume !(1 == ~t2_pc~0); 938725#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 938723#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 938720#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 938718#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 938716#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 938714#L459-27 assume 1 == ~t3_pc~0; 938712#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 938713#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 938820#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 938703#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 938699#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 938697#L478-27 assume !(1 == ~t4_pc~0); 938695#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 938693#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 938691#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 938689#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 938687#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 938685#L497-27 assume 1 == ~t5_pc~0; 938684#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 938529#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 938527#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 938525#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 938523#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 938521#L516-27 assume !(1 == ~t6_pc~0); 938519#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 938517#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 938515#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 938513#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 938511#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 938509#L535-27 assume 1 == ~t7_pc~0; 938506#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 938504#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 938502#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 938501#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 938497#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 938495#L554-27 assume !(1 == ~t8_pc~0); 938493#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 938491#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 938488#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 938486#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 938484#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 938482#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 938480#L931-5 assume !(1 == ~T1_E~0); 938478#L936-3 assume !(1 == ~T2_E~0); 938476#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 938474#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 938470#L951-3 assume !(1 == ~T5_E~0); 938468#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 938466#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 938464#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 938462#L971-3 assume !(1 == ~E_1~0); 938460#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 938458#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 938456#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 938454#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 938451#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 938449#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 938447#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 938445#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 938441#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 938439#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 938437#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 938434#L1291 assume !(0 == start_simulation_~tmp~3#1); 938431#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 938428#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 938426#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 938424#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 938422#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 938420#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 938418#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 938417#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 933190#L1272-2 [2024-10-13 17:46:17,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:17,886 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 6 times [2024-10-13 17:46:17,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:17,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663905320] [2024-10-13 17:46:17,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:17,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:17,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:17,895 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:17,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:17,910 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:17,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:17,911 INFO L85 PathProgramCache]: Analyzing trace with hash 2133175160, now seen corresponding path program 1 times [2024-10-13 17:46:17,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:17,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317368101] [2024-10-13 17:46:17,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:17,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:17,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:18,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:18,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:18,339 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317368101] [2024-10-13 17:46:18,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317368101] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:18,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:18,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:18,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923853262] [2024-10-13 17:46:18,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:18,340 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:18,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:18,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:18,340 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:18,341 INFO L87 Difference]: Start difference. First operand 76247 states and 103008 transitions. cyclomatic complexity: 26793 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:18,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:18,704 INFO L93 Difference]: Finished difference Result 77591 states and 103935 transitions. [2024-10-13 17:46:18,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77591 states and 103935 transitions. [2024-10-13 17:46:19,005 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76928 [2024-10-13 17:46:19,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77591 states to 77591 states and 103935 transitions. [2024-10-13 17:46:19,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77591 [2024-10-13 17:46:19,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77591 [2024-10-13 17:46:19,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77591 states and 103935 transitions. [2024-10-13 17:46:19,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:19,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77591 states and 103935 transitions. [2024-10-13 17:46:19,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77591 states and 103935 transitions. [2024-10-13 17:46:20,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77591 to 77591. [2024-10-13 17:46:20,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77591 states, 77591 states have (on average 1.3395239138559885) internal successors, (103935), 77590 states have internal predecessors, (103935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:20,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77591 states to 77591 states and 103935 transitions. [2024-10-13 17:46:20,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77591 states and 103935 transitions. [2024-10-13 17:46:20,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:20,379 INFO L425 stractBuchiCegarLoop]: Abstraction has 77591 states and 103935 transitions. [2024-10-13 17:46:20,379 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-10-13 17:46:20,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77591 states and 103935 transitions. [2024-10-13 17:46:20,553 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76928 [2024-10-13 17:46:20,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:20,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:20,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:20,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:20,554 INFO L745 eck$LassoCheckResult]: Stem: 1086266#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1086267#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1087039#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1087040#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1087042#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1086392#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1086393#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1087035#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1087025#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1086473#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1086474#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1086742#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1086743#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1086563#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1086564#L838 assume !(0 == ~M_E~0); 1086753#L838-2 assume !(0 == ~T1_E~0); 1086062#L843-1 assume !(0 == ~T2_E~0); 1086063#L848-1 assume !(0 == ~T3_E~0); 1086181#L853-1 assume !(0 == ~T4_E~0); 1086552#L858-1 assume !(0 == ~T5_E~0); 1086018#L863-1 assume !(0 == ~T6_E~0); 1086019#L868-1 assume !(0 == ~T7_E~0); 1087102#L873-1 assume !(0 == ~T8_E~0); 1087099#L878-1 assume !(0 == ~E_1~0); 1087076#L883-1 assume !(0 == ~E_2~0); 1087077#L888-1 assume !(0 == ~E_3~0); 1086705#L893-1 assume !(0 == ~E_4~0); 1086706#L898-1 assume !(0 == ~E_5~0); 1087124#L903-1 assume !(0 == ~E_6~0); 1087073#L908-1 assume !(0 == ~E_7~0); 1086869#L913-1 assume !(0 == ~E_8~0); 1086075#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1086076#L402 assume !(1 == ~m_pc~0); 1086295#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1086208#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1086209#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1086480#L1035 assume !(0 != activate_threads_~tmp~1#1); 1086481#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1086537#L421 assume !(1 == ~t1_pc~0); 1087065#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1087104#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1086077#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1086078#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1086597#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1087114#L440 assume !(1 == ~t2_pc~0); 1087187#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1086218#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1086219#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1086420#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1086889#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1086430#L459 assume !(1 == ~t3_pc~0); 1086431#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1087059#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1087113#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1086201#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1086202#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1086212#L478 assume !(1 == ~t4_pc~0); 1086213#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1086951#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1086153#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1086154#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1086116#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1086117#L497 assume !(1 == ~t5_pc~0); 1086164#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1086658#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1086945#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1086946#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1087053#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1087054#L516 assume !(1 == ~t6_pc~0); 1086971#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1086972#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1086402#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1086403#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1086816#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1086817#L535 assume !(1 == ~t7_pc~0); 1087002#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1087001#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1087164#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1086858#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1086846#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1086847#L554 assume !(1 == ~t8_pc~0); 1086038#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1086039#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1086880#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1086881#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1087206#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1087205#L931 assume !(1 == ~M_E~0); 1087088#L931-2 assume !(1 == ~T1_E~0); 1087089#L936-1 assume !(1 == ~T2_E~0); 1087185#L941-1 assume !(1 == ~T3_E~0); 1087186#L946-1 assume !(1 == ~T4_E~0); 1087062#L951-1 assume !(1 == ~T5_E~0); 1086276#L956-1 assume !(1 == ~T6_E~0); 1086277#L961-1 assume !(1 == ~T7_E~0); 1086707#L966-1 assume !(1 == ~T8_E~0); 1086708#L971-1 assume !(1 == ~E_1~0); 1086851#L976-1 assume !(1 == ~E_2~0); 1087201#L981-1 assume !(1 == ~E_3~0); 1087200#L986-1 assume !(1 == ~E_4~0); 1087199#L991-1 assume !(1 == ~E_5~0); 1086306#L996-1 assume !(1 == ~E_6~0); 1087107#L1001-1 assume !(1 == ~E_7~0); 1086764#L1006-1 assume !(1 == ~E_8~0); 1086765#L1011-1 assume { :end_inline_reset_delta_events } true; 1087063#L1272-2 [2024-10-13 17:46:20,555 INFO L747 eck$LassoCheckResult]: Loop: 1087063#L1272-2 assume !false; 1098114#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1098112#L813-1 assume !false; 1098110#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1098107#L634 assume !(0 == ~m_st~0); 1098108#L638 assume !(0 == ~t1_st~0); 1100151#L642 assume !(0 == ~t2_st~0); 1100150#L646 assume !(0 == ~t3_st~0); 1100148#L650 assume !(0 == ~t4_st~0); 1100147#L654 assume !(0 == ~t5_st~0); 1100146#L658 assume !(0 == ~t6_st~0); 1100145#L662 assume !(0 == ~t7_st~0); 1100143#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1100142#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1100141#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1100139#L696 assume !(0 != eval_~tmp~0#1); 1100137#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1100135#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1100133#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1100131#L838-5 assume !(0 == ~T1_E~0); 1100129#L843-3 assume !(0 == ~T2_E~0); 1100127#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1100125#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1100123#L858-3 assume !(0 == ~T5_E~0); 1100121#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1100119#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1100117#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1100115#L878-3 assume !(0 == ~E_1~0); 1100113#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1100111#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1100109#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1100107#L898-3 assume !(0 == ~E_5~0); 1100105#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1100103#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1100101#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1100099#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1100097#L402-27 assume 1 == ~m_pc~0; 1100094#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1100092#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1100089#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1100086#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1100084#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1100081#L421-27 assume !(1 == ~t1_pc~0); 1100079#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1100077#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1100075#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1100073#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1100071#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1100069#L440-27 assume !(1 == ~t2_pc~0); 1100067#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1100065#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1100063#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1100061#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1100059#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1100057#L459-27 assume !(1 == ~t3_pc~0); 1100053#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1100049#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1100047#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1100045#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1100042#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1100039#L478-27 assume !(1 == ~t4_pc~0); 1100037#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1100035#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1100033#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1100031#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1100029#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1100025#L497-27 assume 1 == ~t5_pc~0; 1100026#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1100019#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1100018#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1100017#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1100016#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1100015#L516-27 assume !(1 == ~t6_pc~0); 1100013#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1100009#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1100007#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1100005#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1100003#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1100001#L535-27 assume 1 == ~t7_pc~0; 1099998#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1099996#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1099994#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1099992#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1099990#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1099988#L554-27 assume !(1 == ~t8_pc~0); 1099986#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1099984#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1099982#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1099980#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1099978#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1099976#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1099975#L931-5 assume !(1 == ~T1_E~0); 1099971#L936-3 assume !(1 == ~T2_E~0); 1099969#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1099967#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1099965#L951-3 assume !(1 == ~T5_E~0); 1099962#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1099960#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1099958#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1099956#L971-3 assume !(1 == ~E_1~0); 1099954#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1099952#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1099950#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1099948#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1099943#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1099941#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1099939#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1099937#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1099934#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1099932#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1099930#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1099927#L1291 assume !(0 == start_simulation_~tmp~3#1); 1099924#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1099921#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1099919#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1099917#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1099915#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1099914#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1099913#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1099911#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1087063#L1272-2 [2024-10-13 17:46:20,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:20,555 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 7 times [2024-10-13 17:46:20,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:20,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167750707] [2024-10-13 17:46:20,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:20,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:20,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:20,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:20,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:20,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:20,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:20,579 INFO L85 PathProgramCache]: Analyzing trace with hash 1675147603, now seen corresponding path program 1 times [2024-10-13 17:46:20,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:20,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626562398] [2024-10-13 17:46:20,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:20,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:20,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:20,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:20,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:20,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626562398] [2024-10-13 17:46:20,618 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [626562398] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:20,618 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:20,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:20,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207110484] [2024-10-13 17:46:20,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:20,618 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:20,619 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:20,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:20,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:20,619 INFO L87 Difference]: Start difference. First operand 77591 states and 103935 transitions. cyclomatic complexity: 26376 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:20,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:20,907 INFO L93 Difference]: Finished difference Result 79079 states and 104989 transitions. [2024-10-13 17:46:20,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79079 states and 104989 transitions. [2024-10-13 17:46:21,179 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78416 [2024-10-13 17:46:21,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79079 states to 79079 states and 104989 transitions. [2024-10-13 17:46:21,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79079 [2024-10-13 17:46:21,910 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79079 [2024-10-13 17:46:21,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79079 states and 104989 transitions. [2024-10-13 17:46:21,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:21,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79079 states and 104989 transitions. [2024-10-13 17:46:21,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79079 states and 104989 transitions. [2024-10-13 17:46:22,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79079 to 79079. [2024-10-13 17:46:22,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79079 states, 79079 states have (on average 1.327647036507796) internal successors, (104989), 79078 states have internal predecessors, (104989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:22,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79079 states to 79079 states and 104989 transitions. [2024-10-13 17:46:22,515 INFO L240 hiAutomatonCegarLoop]: Abstraction has 79079 states and 104989 transitions. [2024-10-13 17:46:22,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:22,515 INFO L425 stractBuchiCegarLoop]: Abstraction has 79079 states and 104989 transitions. [2024-10-13 17:46:22,516 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-10-13 17:46:22,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79079 states and 104989 transitions. [2024-10-13 17:46:22,701 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78416 [2024-10-13 17:46:22,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:22,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:22,702 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:22,702 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:22,703 INFO L745 eck$LassoCheckResult]: Stem: 1242946#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1242947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1243707#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1243708#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1243710#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1243066#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1243067#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1243703#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1243690#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1243148#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1243149#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1243418#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1243419#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1243237#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1243238#L838 assume !(0 == ~M_E~0); 1243430#L838-2 assume !(0 == ~T1_E~0); 1242739#L843-1 assume !(0 == ~T2_E~0); 1242740#L848-1 assume !(0 == ~T3_E~0); 1242857#L853-1 assume !(0 == ~T4_E~0); 1243226#L858-1 assume !(0 == ~T5_E~0); 1242696#L863-1 assume !(0 == ~T6_E~0); 1242697#L868-1 assume !(0 == ~T7_E~0); 1243768#L873-1 assume !(0 == ~T8_E~0); 1243766#L878-1 assume !(0 == ~E_1~0); 1243745#L883-1 assume !(0 == ~E_2~0); 1243746#L888-1 assume !(0 == ~E_3~0); 1243385#L893-1 assume !(0 == ~E_4~0); 1243386#L898-1 assume !(0 == ~E_5~0); 1243792#L903-1 assume !(0 == ~E_6~0); 1243741#L908-1 assume !(0 == ~E_7~0); 1243544#L913-1 assume !(0 == ~E_8~0); 1242752#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1242753#L402 assume !(1 == ~m_pc~0); 1242974#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1242884#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1242885#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1243155#L1035 assume !(0 != activate_threads_~tmp~1#1); 1243156#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1243211#L421 assume !(1 == ~t1_pc~0); 1243733#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1243773#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1242754#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1242755#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1243272#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1243783#L440 assume !(1 == ~t2_pc~0); 1243854#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1242894#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1242895#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1243094#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1243562#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1243103#L459 assume !(1 == ~t3_pc~0); 1243104#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1243729#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1243781#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1242877#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1242878#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1242888#L478 assume !(1 == ~t4_pc~0); 1242889#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1243626#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1242829#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1242830#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1242793#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1242794#L497 assume !(1 == ~t5_pc~0); 1242840#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1243337#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1243619#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1243620#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1243723#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1243724#L516 assume !(1 == ~t6_pc~0); 1243643#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1243644#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1243076#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1243077#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1243494#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1243495#L535 assume !(1 == ~t7_pc~0); 1243675#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1243674#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1243830#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1243534#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1243525#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1243526#L554 assume !(1 == ~t8_pc~0); 1242716#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1242717#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1243555#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1243556#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1243876#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1243875#L931 assume !(1 == ~M_E~0); 1243755#L931-2 assume !(1 == ~T1_E~0); 1243756#L936-1 assume !(1 == ~T2_E~0); 1243852#L941-1 assume !(1 == ~T3_E~0); 1243853#L946-1 assume !(1 == ~T4_E~0); 1243730#L951-1 assume !(1 == ~T5_E~0); 1242955#L956-1 assume !(1 == ~T6_E~0); 1242956#L961-1 assume !(1 == ~T7_E~0); 1243387#L966-1 assume !(1 == ~T8_E~0); 1243388#L971-1 assume !(1 == ~E_1~0); 1243528#L976-1 assume !(1 == ~E_2~0); 1243871#L981-1 assume !(1 == ~E_3~0); 1243870#L986-1 assume !(1 == ~E_4~0); 1243869#L991-1 assume !(1 == ~E_5~0); 1242984#L996-1 assume !(1 == ~E_6~0); 1243777#L1001-1 assume !(1 == ~E_7~0); 1243443#L1006-1 assume !(1 == ~E_8~0); 1243444#L1011-1 assume { :end_inline_reset_delta_events } true; 1243731#L1272-2 [2024-10-13 17:46:22,703 INFO L747 eck$LassoCheckResult]: Loop: 1243731#L1272-2 assume !false; 1249762#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1249718#L813-1 assume !false; 1249759#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1249757#L634 assume !(0 == ~m_st~0); 1249758#L638 assume !(0 == ~t1_st~0); 1255945#L642 assume !(0 == ~t2_st~0); 1255943#L646 assume !(0 == ~t3_st~0); 1255941#L650 assume !(0 == ~t4_st~0); 1255937#L654 assume !(0 == ~t5_st~0); 1255935#L658 assume !(0 == ~t6_st~0); 1255341#L662 assume !(0 == ~t7_st~0); 1255339#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1255338#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1255337#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1255336#L696 assume !(0 != eval_~tmp~0#1); 1255334#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1255332#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1255331#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1255330#L838-5 assume !(0 == ~T1_E~0); 1255328#L843-3 assume !(0 == ~T2_E~0); 1255326#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1255324#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1255321#L858-3 assume !(0 == ~T5_E~0); 1255319#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1255317#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1255316#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1255315#L878-3 assume !(0 == ~E_1~0); 1255313#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1255311#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1255309#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1255306#L898-3 assume !(0 == ~E_5~0); 1255304#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1255302#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1255298#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1255296#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1255294#L402-27 assume 1 == ~m_pc~0; 1255291#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1255289#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1255287#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1255284#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1255282#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1255280#L421-27 assume !(1 == ~t1_pc~0); 1255277#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1255275#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1255273#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1255271#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1255270#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1255265#L440-27 assume !(1 == ~t2_pc~0); 1255264#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1255263#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1255262#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1255261#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1255259#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1255258#L459-27 assume 1 == ~t3_pc~0; 1255257#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1255255#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1255253#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1255250#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1255249#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1255247#L478-27 assume !(1 == ~t4_pc~0); 1255246#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1255242#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1255240#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1255238#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1255236#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1255233#L497-27 assume 1 == ~t5_pc~0; 1255232#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1249883#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1249878#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1249876#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1249874#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1249872#L516-27 assume !(1 == ~t6_pc~0); 1249870#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1249868#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1249866#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1249864#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1249862#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1249860#L535-27 assume !(1 == ~t7_pc~0); 1249858#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1249855#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1249853#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1249851#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1249849#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1249846#L554-27 assume !(1 == ~t8_pc~0); 1249844#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1249842#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1249839#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1249837#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1249835#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1249833#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1249831#L931-5 assume !(1 == ~T1_E~0); 1249829#L936-3 assume !(1 == ~T2_E~0); 1249827#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1249825#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1249821#L951-3 assume !(1 == ~T5_E~0); 1249819#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1249817#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1249815#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1249813#L971-3 assume !(1 == ~E_1~0); 1249811#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1249809#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1249807#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1249805#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1249802#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1249800#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1249798#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1249796#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1249792#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1249790#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1249788#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1249785#L1291 assume !(0 == start_simulation_~tmp~3#1); 1249782#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1249779#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1249777#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1249775#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1249773#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1249771#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1249769#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1249768#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1243731#L1272-2 [2024-10-13 17:46:22,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:22,703 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 8 times [2024-10-13 17:46:22,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:22,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679828939] [2024-10-13 17:46:22,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:22,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:22,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:22,710 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:22,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:22,729 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:22,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:22,730 INFO L85 PathProgramCache]: Analyzing trace with hash -2031052333, now seen corresponding path program 1 times [2024-10-13 17:46:22,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:22,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229949095] [2024-10-13 17:46:22,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:22,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:22,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:22,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:22,768 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:22,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229949095] [2024-10-13 17:46:22,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229949095] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:22,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:22,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:22,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272859953] [2024-10-13 17:46:22,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:22,769 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:22,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:22,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:22,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:22,770 INFO L87 Difference]: Start difference. First operand 79079 states and 104989 transitions. cyclomatic complexity: 25942 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:23,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:23,456 INFO L93 Difference]: Finished difference Result 81869 states and 107779 transitions. [2024-10-13 17:46:23,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81869 states and 107779 transitions. [2024-10-13 17:46:23,755 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 81200 [2024-10-13 17:46:23,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81869 states to 81869 states and 107779 transitions. [2024-10-13 17:46:23,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81869 [2024-10-13 17:46:24,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81869 [2024-10-13 17:46:24,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81869 states and 107779 transitions. [2024-10-13 17:46:24,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:24,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81869 states and 107779 transitions. [2024-10-13 17:46:24,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81869 states and 107779 transitions. [2024-10-13 17:46:24,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81869 to 81869. [2024-10-13 17:46:24,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81869 states, 81869 states have (on average 1.3164812077831658) internal successors, (107779), 81868 states have internal predecessors, (107779), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:25,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81869 states to 81869 states and 107779 transitions. [2024-10-13 17:46:25,134 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81869 states and 107779 transitions. [2024-10-13 17:46:25,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:25,135 INFO L425 stractBuchiCegarLoop]: Abstraction has 81869 states and 107779 transitions. [2024-10-13 17:46:25,135 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-10-13 17:46:25,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81869 states and 107779 transitions. [2024-10-13 17:46:25,368 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 81200 [2024-10-13 17:46:25,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:25,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:25,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:25,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:25,370 INFO L745 eck$LassoCheckResult]: Stem: 1403899#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1403900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1404664#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1404665#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1404667#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1404018#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1404019#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1404659#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1404647#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1404098#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1404099#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1404370#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1404371#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1404189#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1404190#L838 assume !(0 == ~M_E~0); 1404382#L838-2 assume !(0 == ~T1_E~0); 1403695#L843-1 assume !(0 == ~T2_E~0); 1403696#L848-1 assume !(0 == ~T3_E~0); 1403815#L853-1 assume !(0 == ~T4_E~0); 1404176#L858-1 assume !(0 == ~T5_E~0); 1403650#L863-1 assume !(0 == ~T6_E~0); 1403651#L868-1 assume !(0 == ~T7_E~0); 1404736#L873-1 assume !(0 == ~T8_E~0); 1404734#L878-1 assume !(0 == ~E_1~0); 1404704#L883-1 assume !(0 == ~E_2~0); 1404705#L888-1 assume !(0 == ~E_3~0); 1404334#L893-1 assume !(0 == ~E_4~0); 1404335#L898-1 assume !(0 == ~E_5~0); 1404761#L903-1 assume !(0 == ~E_6~0); 1404702#L908-1 assume !(0 == ~E_7~0); 1404489#L913-1 assume !(0 == ~E_8~0); 1403707#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1403708#L402 assume !(1 == ~m_pc~0); 1403924#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1403842#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1403843#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1404106#L1035 assume !(0 != activate_threads_~tmp~1#1); 1404107#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1404162#L421 assume !(1 == ~t1_pc~0); 1404693#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1404737#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1403710#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1403711#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1404222#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1404749#L440 assume !(1 == ~t2_pc~0); 1404816#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1403851#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1403852#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1404047#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1404509#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1404051#L459 assume !(1 == ~t3_pc~0); 1404052#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1404684#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1403670#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1403671#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1403836#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1403846#L478 assume !(1 == ~t4_pc~0); 1403847#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1404575#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1403787#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1403788#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1403747#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1403748#L497 assume !(1 == ~t5_pc~0); 1403798#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1404286#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1404567#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1404568#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1404678#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1404679#L516 assume !(1 == ~t6_pc~0); 1404593#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1404594#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1404028#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1404029#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1404446#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1404447#L535 assume !(1 == ~t7_pc~0); 1404626#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1404763#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1404796#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1404482#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1404470#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1404471#L554 assume !(1 == ~t8_pc~0); 1403672#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1403673#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1404834#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1403981#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1403982#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1403660#L931 assume !(1 == ~M_E~0); 1403661#L931-2 assume !(1 == ~T1_E~0); 1404772#L936-1 assume !(1 == ~T2_E~0); 1404773#L941-1 assume !(1 == ~T3_E~0); 1404163#L946-1 assume !(1 == ~T4_E~0); 1404164#L951-1 assume !(1 == ~T5_E~0); 1404831#L956-1 assume !(1 == ~T6_E~0); 1404830#L961-1 assume !(1 == ~T7_E~0); 1404336#L966-1 assume !(1 == ~T8_E~0); 1404337#L971-1 assume !(1 == ~E_1~0); 1404473#L976-1 assume !(1 == ~E_2~0); 1404432#L981-1 assume !(1 == ~E_3~0); 1404167#L986-1 assume !(1 == ~E_4~0); 1404168#L991-1 assume !(1 == ~E_5~0); 1403939#L996-1 assume !(1 == ~E_6~0); 1404742#L1001-1 assume !(1 == ~E_7~0); 1404397#L1006-1 assume !(1 == ~E_8~0); 1404398#L1011-1 assume { :end_inline_reset_delta_events } true; 1404691#L1272-2 [2024-10-13 17:46:25,371 INFO L747 eck$LassoCheckResult]: Loop: 1404691#L1272-2 assume !false; 1417894#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1417893#L813-1 assume !false; 1417891#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1417888#L634 assume !(0 == ~m_st~0); 1417889#L638 assume !(0 == ~t1_st~0); 1418930#L642 assume !(0 == ~t2_st~0); 1418928#L646 assume !(0 == ~t3_st~0); 1418926#L650 assume !(0 == ~t4_st~0); 1418924#L654 assume !(0 == ~t5_st~0); 1418922#L658 assume !(0 == ~t6_st~0); 1418918#L662 assume !(0 == ~t7_st~0); 1418915#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1418913#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1418911#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1418908#L696 assume !(0 != eval_~tmp~0#1); 1418906#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1418904#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1418902#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1418900#L838-5 assume !(0 == ~T1_E~0); 1418898#L843-3 assume !(0 == ~T2_E~0); 1418896#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1418894#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1418892#L858-3 assume !(0 == ~T5_E~0); 1418891#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1418889#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1418887#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1418886#L878-3 assume !(0 == ~E_1~0); 1418883#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1418880#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1418877#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1418875#L898-3 assume !(0 == ~E_5~0); 1418872#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1418870#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1418868#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1418865#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1418863#L402-27 assume 1 == ~m_pc~0; 1418860#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1418859#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1418858#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1418856#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1418855#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1418854#L421-27 assume !(1 == ~t1_pc~0); 1418853#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1418852#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1418850#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1418849#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1418848#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1418847#L440-27 assume !(1 == ~t2_pc~0); 1418845#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1418844#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1418843#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1418842#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1418840#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1418838#L459-27 assume 1 == ~t3_pc~0; 1418836#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1418837#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1418846#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1418827#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1418825#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1418823#L478-27 assume !(1 == ~t4_pc~0); 1418821#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1418817#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1418815#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1418813#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1418811#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1418808#L497-27 assume !(1 == ~t5_pc~0); 1418805#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1418803#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1418801#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1418799#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1418797#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1418795#L516-27 assume !(1 == ~t6_pc~0); 1418793#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1418791#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1418789#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1418787#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1418785#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1418783#L535-27 assume 1 == ~t7_pc~0; 1418781#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1418782#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1418857#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1418772#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1418770#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1418768#L554-27 assume !(1 == ~t8_pc~0); 1418766#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1418764#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1418763#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1418762#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1418760#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1418758#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1418756#L931-5 assume !(1 == ~T1_E~0); 1418754#L936-3 assume !(1 == ~T2_E~0); 1418752#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1418750#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1418748#L951-3 assume !(1 == ~T5_E~0); 1418746#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1418744#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1418742#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1418740#L971-3 assume !(1 == ~E_1~0); 1418738#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1418736#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1418734#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1418418#L991-3 assume !(1 == ~E_5~0); 1418416#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1418413#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1418411#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1418409#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1418406#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1418405#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1418404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1418401#L1291 assume !(0 == start_simulation_~tmp~3#1); 1418399#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1418397#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1418396#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1418392#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1418390#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1418388#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1418386#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1418381#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1404691#L1272-2 [2024-10-13 17:46:25,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:25,371 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 9 times [2024-10-13 17:46:25,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:25,371 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126409917] [2024-10-13 17:46:25,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:25,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:25,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:25,385 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:25,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:25,405 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:25,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:25,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1361084587, now seen corresponding path program 1 times [2024-10-13 17:46:25,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:25,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135484627] [2024-10-13 17:46:25,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:25,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:25,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:25,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:25,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:25,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135484627] [2024-10-13 17:46:25,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135484627] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:25,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:25,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:25,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948797338] [2024-10-13 17:46:25,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:25,462 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:25,462 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:25,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:25,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:25,462 INFO L87 Difference]: Start difference. First operand 81869 states and 107779 transitions. cyclomatic complexity: 25942 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:25,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:25,827 INFO L93 Difference]: Finished difference Result 83117 states and 108578 transitions. [2024-10-13 17:46:25,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83117 states and 108578 transitions. [2024-10-13 17:46:26,147 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 82448 [2024-10-13 17:46:26,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83117 states to 83117 states and 108578 transitions. [2024-10-13 17:46:26,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83117 [2024-10-13 17:46:26,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83117 [2024-10-13 17:46:26,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83117 states and 108578 transitions. [2024-10-13 17:46:26,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:26,973 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83117 states and 108578 transitions. [2024-10-13 17:46:27,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83117 states and 108578 transitions. [2024-10-13 17:46:27,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83117 to 83117. [2024-10-13 17:46:27,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83117 states, 83117 states have (on average 1.3063272254773393) internal successors, (108578), 83116 states have internal predecessors, (108578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:27,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83117 states to 83117 states and 108578 transitions. [2024-10-13 17:46:27,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 83117 states and 108578 transitions. [2024-10-13 17:46:27,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:27,582 INFO L425 stractBuchiCegarLoop]: Abstraction has 83117 states and 108578 transitions. [2024-10-13 17:46:27,582 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-10-13 17:46:27,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83117 states and 108578 transitions. [2024-10-13 17:46:27,779 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 82448 [2024-10-13 17:46:27,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:27,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:27,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:27,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:27,780 INFO L745 eck$LassoCheckResult]: Stem: 1568890#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1568891#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1569637#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1569638#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1569640#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1569011#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1569012#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1569632#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1569621#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1569092#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1569093#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1569357#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1569358#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1569181#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1569182#L838 assume !(0 == ~M_E~0); 1569367#L838-2 assume !(0 == ~T1_E~0); 1568689#L843-1 assume !(0 == ~T2_E~0); 1568690#L848-1 assume !(0 == ~T3_E~0); 1568806#L853-1 assume !(0 == ~T4_E~0); 1569167#L858-1 assume !(0 == ~T5_E~0); 1568644#L863-1 assume !(0 == ~T6_E~0); 1568645#L868-1 assume !(0 == ~T7_E~0); 1569700#L873-1 assume !(0 == ~T8_E~0); 1569698#L878-1 assume !(0 == ~E_1~0); 1569669#L883-1 assume !(0 == ~E_2~0); 1569670#L888-1 assume !(0 == ~E_3~0); 1569323#L893-1 assume !(0 == ~E_4~0); 1569324#L898-1 assume !(0 == ~E_5~0); 1569724#L903-1 assume !(0 == ~E_6~0); 1569667#L908-1 assume !(0 == ~E_7~0); 1569479#L913-1 assume !(0 == ~E_8~0); 1568701#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1568702#L402 assume !(1 == ~m_pc~0); 1568914#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1568832#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1568833#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1569098#L1035 assume !(0 != activate_threads_~tmp~1#1); 1569099#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1569154#L421 assume !(1 == ~t1_pc~0); 1569661#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1569701#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1568704#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1568705#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1569213#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1569713#L440 assume !(1 == ~t2_pc~0); 1569780#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1568841#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1568842#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1569039#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1569496#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1569043#L459 assume !(1 == ~t3_pc~0); 1569044#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1569655#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1568664#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1568665#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1568826#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1568836#L478 assume !(1 == ~t4_pc~0); 1568837#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1569557#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1568778#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1568779#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1568741#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1568742#L497 assume !(1 == ~t5_pc~0); 1568789#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1569279#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1569551#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1569552#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1569650#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1569651#L516 assume !(1 == ~t6_pc~0); 1569570#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1569571#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1569021#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1569022#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1569430#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1569431#L535 assume !(1 == ~t7_pc~0); 1569603#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1569726#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1569757#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1569471#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1569460#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1569461#L554 assume !(1 == ~t8_pc~0); 1568666#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1568667#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1569804#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1568972#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1568973#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1568654#L931 assume !(1 == ~M_E~0); 1568655#L931-2 assume !(1 == ~T1_E~0); 1569737#L936-1 assume !(1 == ~T2_E~0); 1569738#L941-1 assume !(1 == ~T3_E~0); 1569155#L946-1 assume !(1 == ~T4_E~0); 1569156#L951-1 assume !(1 == ~T5_E~0); 1569801#L956-1 assume !(1 == ~T6_E~0); 1569800#L961-1 assume !(1 == ~T7_E~0); 1569325#L966-1 assume !(1 == ~T8_E~0); 1569326#L971-1 assume !(1 == ~E_1~0); 1569463#L976-1 assume !(1 == ~E_2~0); 1569416#L981-1 assume !(1 == ~E_3~0); 1569159#L986-1 assume !(1 == ~E_4~0); 1569160#L991-1 assume !(1 == ~E_5~0); 1568928#L996-1 assume !(1 == ~E_6~0); 1569707#L1001-1 assume !(1 == ~E_7~0); 1569381#L1006-1 assume !(1 == ~E_8~0); 1569382#L1011-1 assume { :end_inline_reset_delta_events } true; 1569659#L1272-2 [2024-10-13 17:46:27,781 INFO L747 eck$LassoCheckResult]: Loop: 1569659#L1272-2 assume !false; 1600621#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1600568#L813-1 assume !false; 1600616#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1600613#L634 assume !(0 == ~m_st~0); 1600614#L638 assume !(0 == ~t1_st~0); 1600930#L642 assume !(0 == ~t2_st~0); 1600928#L646 assume !(0 == ~t3_st~0); 1600926#L650 assume !(0 == ~t4_st~0); 1600924#L654 assume !(0 == ~t5_st~0); 1600922#L658 assume !(0 == ~t6_st~0); 1600918#L662 assume !(0 == ~t7_st~0); 1600915#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1600913#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1600911#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1600907#L696 assume !(0 != eval_~tmp~0#1); 1600905#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1600903#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1600901#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1600899#L838-5 assume !(0 == ~T1_E~0); 1600897#L843-3 assume !(0 == ~T2_E~0); 1600895#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1600893#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1600891#L858-3 assume !(0 == ~T5_E~0); 1600890#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1600888#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1600886#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1600885#L878-3 assume !(0 == ~E_1~0); 1600882#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1600880#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1600878#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1600876#L898-3 assume !(0 == ~E_5~0); 1600875#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1600873#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1600871#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1600869#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1600867#L402-27 assume 1 == ~m_pc~0; 1600864#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1600862#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1600859#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1600856#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1600854#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1600852#L421-27 assume !(1 == ~t1_pc~0); 1600850#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1600848#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1600846#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1600844#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1600842#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1600840#L440-27 assume !(1 == ~t2_pc~0); 1600838#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1600836#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1600834#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1600832#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1600830#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1600828#L459-27 assume !(1 == ~t3_pc~0); 1600824#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1600822#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1600820#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1600818#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1600815#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1600813#L478-27 assume !(1 == ~t4_pc~0); 1600811#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1600809#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1600807#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1600804#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1600802#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1600800#L497-27 assume !(1 == ~t5_pc~0); 1600795#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1600793#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1600791#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1600789#L1075-27 assume !(0 != activate_threads_~tmp___4~0#1); 1600787#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1600785#L516-27 assume !(1 == ~t6_pc~0); 1600783#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1600781#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1600779#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1600777#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1600775#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1600773#L535-27 assume !(1 == ~t7_pc~0); 1600769#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1600767#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1600763#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1600761#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 1600758#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1600756#L554-27 assume !(1 == ~t8_pc~0); 1600753#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1600751#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1600749#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1600747#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1600745#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1600743#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1600741#L931-5 assume !(1 == ~T1_E~0); 1600739#L936-3 assume !(1 == ~T2_E~0); 1600736#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1600734#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1600732#L951-3 assume !(1 == ~T5_E~0); 1600730#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1600727#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1600725#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1600723#L971-3 assume !(1 == ~E_1~0); 1600721#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1600719#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1600717#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1600663#L991-3 assume !(1 == ~E_5~0); 1600660#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1600658#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1600656#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1600654#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1600651#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1600649#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1600647#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1600644#L1291 assume !(0 == start_simulation_~tmp~3#1); 1600640#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1600637#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1600635#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1600633#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1600631#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1600629#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1600627#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1600625#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1569659#L1272-2 [2024-10-13 17:46:27,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:27,781 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 10 times [2024-10-13 17:46:27,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:27,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389336569] [2024-10-13 17:46:27,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:27,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:27,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:27,787 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:27,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:27,803 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:27,803 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:27,803 INFO L85 PathProgramCache]: Analyzing trace with hash -1230773555, now seen corresponding path program 1 times [2024-10-13 17:46:27,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:27,804 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290913121] [2024-10-13 17:46:27,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:27,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:27,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:27,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:27,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:27,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290913121] [2024-10-13 17:46:27,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290913121] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:27,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:27,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-13 17:46:27,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605086701] [2024-10-13 17:46:27,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:27,848 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-13 17:46:27,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:27,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-13 17:46:27,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-13 17:46:27,849 INFO L87 Difference]: Start difference. First operand 83117 states and 108578 transitions. cyclomatic complexity: 25493 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:28,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:28,585 INFO L93 Difference]: Finished difference Result 84509 states and 109504 transitions. [2024-10-13 17:46:28,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84509 states and 109504 transitions. [2024-10-13 17:46:28,851 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83840 [2024-10-13 17:46:29,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84509 states to 84509 states and 109504 transitions. [2024-10-13 17:46:29,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84509 [2024-10-13 17:46:29,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84509 [2024-10-13 17:46:29,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84509 states and 109504 transitions. [2024-10-13 17:46:29,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-13 17:46:29,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84509 states and 109504 transitions. [2024-10-13 17:46:29,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84509 states and 109504 transitions. [2024-10-13 17:46:29,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84509 to 84509. [2024-10-13 17:46:29,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84509 states, 84509 states have (on average 1.2957673147238755) internal successors, (109504), 84508 states have internal predecessors, (109504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:30,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84509 states to 84509 states and 109504 transitions. [2024-10-13 17:46:30,331 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84509 states and 109504 transitions. [2024-10-13 17:46:30,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-13 17:46:30,332 INFO L425 stractBuchiCegarLoop]: Abstraction has 84509 states and 109504 transitions. [2024-10-13 17:46:30,332 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-10-13 17:46:30,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84509 states and 109504 transitions. [2024-10-13 17:46:30,518 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83840 [2024-10-13 17:46:30,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-13 17:46:30,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-13 17:46:30,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:30,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-13 17:46:30,519 INFO L745 eck$LassoCheckResult]: Stem: 1736528#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1736529#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1737311#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1737312#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1737314#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1736648#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1736649#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1737305#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1737294#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1736732#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1736733#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1737007#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1737008#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1736823#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1736824#L838 assume !(0 == ~M_E~0); 1737017#L838-2 assume !(0 == ~T1_E~0); 1736324#L843-1 assume !(0 == ~T2_E~0); 1736325#L848-1 assume !(0 == ~T3_E~0); 1736443#L853-1 assume !(0 == ~T4_E~0); 1736808#L858-1 assume !(0 == ~T5_E~0); 1736280#L863-1 assume !(0 == ~T6_E~0); 1736281#L868-1 assume !(0 == ~T7_E~0); 1737386#L873-1 assume !(0 == ~T8_E~0); 1737381#L878-1 assume !(0 == ~E_1~0); 1737349#L883-1 assume !(0 == ~E_2~0); 1737350#L888-1 assume !(0 == ~E_3~0); 1736971#L893-1 assume !(0 == ~E_4~0); 1736972#L898-1 assume !(0 == ~E_5~0); 1737410#L903-1 assume !(0 == ~E_6~0); 1737346#L908-1 assume !(0 == ~E_7~0); 1737131#L913-1 assume !(0 == ~E_8~0); 1736337#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1736338#L402 assume !(1 == ~m_pc~0); 1736557#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1736470#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1736471#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1736739#L1035 assume !(0 != activate_threads_~tmp~1#1); 1736740#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1736795#L421 assume !(1 == ~t1_pc~0); 1737337#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1737388#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1736339#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1736340#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1736857#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1737400#L440 assume !(1 == ~t2_pc~0); 1737482#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1736481#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1736482#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1736678#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1737155#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1736687#L459 assume !(1 == ~t3_pc~0); 1736688#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1737331#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1737398#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1736463#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1736464#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1736474#L478 assume !(1 == ~t4_pc~0); 1736475#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1737222#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1736414#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1736415#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1736378#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1736379#L497 assume !(1 == ~t5_pc~0); 1736425#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1736928#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1737066#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1737401#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1737326#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1737327#L516 assume !(1 == ~t6_pc~0); 1737239#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1737240#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1736658#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1736659#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1737084#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1737085#L535 assume !(1 == ~t7_pc~0); 1737277#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1737412#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1737454#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1737123#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1737112#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1737113#L554 assume !(1 == ~t8_pc~0); 1736300#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1736301#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1737145#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1737146#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1737507#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1737506#L931 assume !(1 == ~M_E~0); 1737367#L931-2 assume !(1 == ~T1_E~0); 1737368#L936-1 assume !(1 == ~T2_E~0); 1737480#L941-1 assume !(1 == ~T3_E~0); 1737481#L946-1 assume !(1 == ~T4_E~0); 1737334#L951-1 assume !(1 == ~T5_E~0); 1736538#L956-1 assume !(1 == ~T6_E~0); 1736539#L961-1 assume !(1 == ~T7_E~0); 1736973#L966-1 assume !(1 == ~T8_E~0); 1736974#L971-1 assume !(1 == ~E_1~0); 1737116#L976-1 assume !(1 == ~E_2~0); 1737501#L981-1 assume !(1 == ~E_3~0); 1737500#L986-1 assume !(1 == ~E_4~0); 1737499#L991-1 assume !(1 == ~E_5~0); 1736567#L996-1 assume !(1 == ~E_6~0); 1737391#L1001-1 assume !(1 == ~E_7~0); 1737031#L1006-1 assume !(1 == ~E_8~0); 1737032#L1011-1 assume { :end_inline_reset_delta_events } true; 1737335#L1272-2 [2024-10-13 17:46:30,520 INFO L747 eck$LassoCheckResult]: Loop: 1737335#L1272-2 assume !false; 1770189#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1770187#L813-1 assume !false; 1770184#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1770181#L634 assume !(0 == ~m_st~0); 1770182#L638 assume !(0 == ~t1_st~0); 1772605#L642 assume !(0 == ~t2_st~0); 1772603#L646 assume !(0 == ~t3_st~0); 1772601#L650 assume !(0 == ~t4_st~0); 1772599#L654 assume !(0 == ~t5_st~0); 1772597#L658 assume !(0 == ~t6_st~0); 1772595#L662 assume !(0 == ~t7_st~0); 1772592#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1772590#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1772587#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1772585#L696 assume !(0 != eval_~tmp~0#1); 1772583#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1772581#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1772580#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1772579#L838-5 assume !(0 == ~T1_E~0); 1772578#L843-3 assume !(0 == ~T2_E~0); 1772577#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1772576#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1772574#L858-3 assume !(0 == ~T5_E~0); 1772573#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1772572#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1772570#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1772569#L878-3 assume !(0 == ~E_1~0); 1772568#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1772567#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1772566#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1772565#L898-3 assume !(0 == ~E_5~0); 1772564#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1772562#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1772561#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1772560#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1772558#L402-27 assume 1 == ~m_pc~0; 1772556#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1772555#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1772554#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1772552#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1772550#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1772548#L421-27 assume !(1 == ~t1_pc~0); 1772546#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1772545#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1772543#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1772541#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1772539#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1772537#L440-27 assume !(1 == ~t2_pc~0); 1772535#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1772533#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1772531#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1772529#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1772527#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1772525#L459-27 assume 1 == ~t3_pc~0; 1772523#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1772524#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1772559#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1772512#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1772510#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1772508#L478-27 assume !(1 == ~t4_pc~0); 1772505#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1772503#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1772501#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1772499#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1772497#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1772495#L497-27 assume 1 == ~t5_pc~0; 1772494#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1770601#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1770599#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1770595#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1770593#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1770592#L516-27 assume !(1 == ~t6_pc~0); 1770591#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1770589#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1770588#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1770587#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1770586#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1770585#L535-27 assume !(1 == ~t7_pc~0); 1770579#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1770577#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1770575#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1770573#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 1770567#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1770565#L554-27 assume !(1 == ~t8_pc~0); 1770563#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1770561#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1770559#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1770557#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1770555#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1770553#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1770551#L931-5 assume !(1 == ~T1_E~0); 1770549#L936-3 assume !(1 == ~T2_E~0); 1770547#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1770545#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1770543#L951-3 assume !(1 == ~T5_E~0); 1770541#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1770540#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1770536#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1770534#L971-3 assume !(1 == ~E_1~0); 1770532#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1770530#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1770527#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1770525#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1770522#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1770520#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1770518#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1770516#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1770513#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1770511#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1770508#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1770505#L1291 assume !(0 == start_simulation_~tmp~3#1); 1770502#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1770499#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1770497#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1770495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1770493#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1770491#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1770489#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1770487#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1737335#L1272-2 [2024-10-13 17:46:30,520 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:30,520 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 11 times [2024-10-13 17:46:30,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:30,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251058002] [2024-10-13 17:46:30,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:30,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:30,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:30,526 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:30,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:30,542 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:30,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:30,542 INFO L85 PathProgramCache]: Analyzing trace with hash 1509315279, now seen corresponding path program 1 times [2024-10-13 17:46:30,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:30,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866404527] [2024-10-13 17:46:30,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:30,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:30,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:30,550 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-13 17:46:30,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-13 17:46:30,560 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-13 17:46:30,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:30,561 INFO L85 PathProgramCache]: Analyzing trace with hash 943729357, now seen corresponding path program 1 times [2024-10-13 17:46:30,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-13 17:46:30,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357550765] [2024-10-13 17:46:30,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-13 17:46:30,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-13 17:46:30,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:30,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:30,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-13 17:46:30,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357550765] [2024-10-13 17:46:30,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1357550765] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-13 17:46:30,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-13 17:46:30,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-13 17:46:30,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328791284] [2024-10-13 17:46:30,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-13 17:46:31,845 INFO L204 LassoAnalysis]: Preferences: [2024-10-13 17:46:31,845 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-13 17:46:31,845 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-13 17:46:31,845 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-13 17:46:31,845 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-13 17:46:31,845 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:31,845 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-13 17:46:31,846 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-13 17:46:31,846 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.08.cil.c_Iteration31_Loop [2024-10-13 17:46:31,846 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-13 17:46:31,846 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-13 17:46:31,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,871 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,874 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,898 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,899 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,901 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,906 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,911 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,914 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,917 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,919 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,920 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,922 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,927 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,932 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,938 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,941 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,952 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,954 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,960 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,961 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,963 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,966 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,967 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,971 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,976 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,980 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,985 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,992 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:31,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,002 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,011 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,014 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,018 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,020 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,021 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,023 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,027 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,028 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,029 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,033 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,034 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,036 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,038 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,039 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,040 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,042 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,044 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,048 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,049 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,052 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,055 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,057 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,060 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,063 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,066 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,072 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,074 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:32,514 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-13 17:46:32,515 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-13 17:46:32,517 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,517 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,518 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,519 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-13 17:46:32,521 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,521 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:32,536 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:46:32,536 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:46:32,546 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-10-13 17:46:32,546 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,546 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,547 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,548 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-13 17:46:32,549 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,549 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:32,559 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:46:32,560 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:46:32,570 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-10-13 17:46:32,570 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,570 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,572 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,572 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-13 17:46:32,573 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,573 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:32,584 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:46:32,585 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:46:32,595 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-10-13 17:46:32,596 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,596 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,598 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,599 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-13 17:46:32,600 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,600 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:32,618 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:46:32,619 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:46:32,629 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-10-13 17:46:32,629 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,630 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,631 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,632 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-10-13 17:46:32,633 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,633 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:32,644 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:46:32,645 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:46:32,658 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-10-13 17:46:32,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,659 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,660 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,661 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-10-13 17:46:32,662 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,662 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:32,679 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:46:32,680 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t8_st~0=4} Honda state: {~t8_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:46:32,691 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-10-13 17:46:32,691 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,691 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,693 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,940 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-10-13 17:46:32,941 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,941 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:32,955 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:46:32,955 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:46:32,965 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-10-13 17:46:32,965 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,965 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,966 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,967 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-10-13 17:46:32,968 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,968 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:32,979 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-13 17:46:32,979 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-13 17:46:32,989 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-10-13 17:46:32,989 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:32,989 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:32,990 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:32,991 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-10-13 17:46:32,992 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-13 17:46:32,992 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:33,013 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-10-13 17:46:33,014 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,014 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,015 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,017 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-10-13 17:46:33,017 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-13 17:46:33,018 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-13 17:46:33,034 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-13 17:46:33,050 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-10-13 17:46:33,052 INFO L204 LassoAnalysis]: Preferences: [2024-10-13 17:46:33,052 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-13 17:46:33,052 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-13 17:46:33,052 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-13 17:46:33,052 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-13 17:46:33,053 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,053 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-13 17:46:33,053 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-13 17:46:33,053 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.08.cil.c_Iteration31_Loop [2024-10-13 17:46:33,053 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-13 17:46:33,053 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-13 17:46:33,059 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,061 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,063 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,064 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,067 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,071 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,072 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,080 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,081 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,083 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,085 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,088 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,090 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,092 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,094 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,097 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,103 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,105 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,109 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,110 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,112 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,113 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,115 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,116 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,120 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,124 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,126 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,129 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,131 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,135 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,136 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,138 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,139 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,141 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,144 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,146 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,148 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,152 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,154 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,156 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,157 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,159 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,163 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,164 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,166 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,168 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,170 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,173 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,178 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,180 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,182 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,184 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,186 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,190 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,192 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,193 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,197 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,198 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,200 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,206 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,208 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,209 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,210 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,211 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,212 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,214 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,215 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,217 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,218 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,219 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,223 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,225 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,233 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,234 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,236 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,237 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,238 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,240 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,241 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,245 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,247 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,248 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,252 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,255 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,259 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,262 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,265 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-13 17:46:33,727 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-13 17:46:33,730 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-13 17:46:33,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,731 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,733 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,734 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-10-13 17:46:33,737 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:46:33,747 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:46:33,747 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:46:33,747 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:46:33,747 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:46:33,747 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:46:33,749 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:46:33,749 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:46:33,750 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:46:33,760 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-10-13 17:46:33,761 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,761 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,762 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,763 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-10-13 17:46:33,764 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:46:33,773 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:46:33,774 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:46:33,774 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:46:33,774 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:46:33,774 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:46:33,774 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:46:33,774 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:46:33,775 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:46:33,786 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-10-13 17:46:33,786 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,786 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,787 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,788 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-10-13 17:46:33,789 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:46:33,798 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:46:33,799 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:46:33,799 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:46:33,799 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:46:33,799 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:46:33,799 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:46:33,799 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:46:33,800 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:46:33,811 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-10-13 17:46:33,811 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,811 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,813 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,814 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-10-13 17:46:33,814 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:46:33,824 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:46:33,824 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:46:33,824 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:46:33,824 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-13 17:46:33,824 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:46:33,825 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-13 17:46:33,825 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:46:33,826 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:46:33,836 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-10-13 17:46:33,837 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,837 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,838 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,839 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-10-13 17:46:33,839 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:46:33,849 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:46:33,849 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:46:33,849 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:46:33,849 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:46:33,849 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:46:33,850 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:46:33,850 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:46:33,851 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:46:33,860 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2024-10-13 17:46:33,861 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,861 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,862 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,863 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-10-13 17:46:33,867 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:46:33,876 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:46:33,876 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:46:33,876 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:46:33,877 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-13 17:46:33,877 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:46:33,879 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-13 17:46:33,879 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:46:33,880 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:46:33,890 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-10-13 17:46:33,890 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,891 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,892 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,893 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-10-13 17:46:33,894 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:46:33,904 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:46:33,904 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:46:33,904 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:46:33,904 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:46:33,904 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:46:33,904 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:46:33,904 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:46:33,905 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-13 17:46:33,915 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2024-10-13 17:46:33,916 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,916 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,917 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,917 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-10-13 17:46:33,918 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-13 17:46:33,928 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-13 17:46:33,928 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-13 17:46:33,928 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-13 17:46:33,928 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-13 17:46:33,928 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-13 17:46:33,929 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-13 17:46:33,929 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-13 17:46:33,930 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-13 17:46:33,932 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-13 17:46:33,932 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-13 17:46:33,934 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-13 17:46:33,934 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-13 17:46:33,957 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-13 17:46:33,959 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-10-13 17:46:33,959 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-13 17:46:33,960 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-13 17:46:33,960 INFO L474 LassoAnalysis]: Proved termination. [2024-10-13 17:46:33,960 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2024-10-13 17:46:33,970 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2024-10-13 17:46:33,972 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-13 17:46:33,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-13 17:46:34,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:34,039 INFO L255 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-13 17:46:34,041 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-13 17:46:34,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-13 17:46:34,201 INFO L255 TraceCheckSpWp]: Trace formula consists of 268 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-13 17:46:34,203 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-13 17:46:34,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-13 17:46:34,413 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-10-13 17:46:34,414 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 84509 states and 109504 transitions. cyclomatic complexity: 25027 Second operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:35,301 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 84509 states and 109504 transitions. cyclomatic complexity: 25027. Second operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 236063 states and 304867 transitions. Complement of second has 5 states. [2024-10-13 17:46:35,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-13 17:46:35,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:35,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1203 transitions. [2024-10-13 17:46:35,308 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1203 transitions. Stem has 104 letters. Loop has 120 letters. [2024-10-13 17:46:35,311 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:46:35,311 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1203 transitions. Stem has 224 letters. Loop has 120 letters. [2024-10-13 17:46:35,313 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:46:35,313 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1203 transitions. Stem has 104 letters. Loop has 240 letters. [2024-10-13 17:46:35,317 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-13 17:46:35,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236063 states and 304867 transitions. [2024-10-13 17:46:36,177 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-10-13 17:46:36,621 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 158912 [2024-10-13 17:46:37,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236063 states to 236063 states and 304867 transitions. [2024-10-13 17:46:37,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 160094 [2024-10-13 17:46:37,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 160287 [2024-10-13 17:46:37,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236063 states and 304867 transitions. [2024-10-13 17:46:37,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-13 17:46:37,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 236063 states and 304867 transitions. [2024-10-13 17:46:37,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236063 states and 304867 transitions. [2024-10-13 17:46:38,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236063 to 235870. [2024-10-13 17:46:39,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 235870 states, 235870 states have (on average 1.291703056768559) internal successors, (304674), 235869 states have internal predecessors, (304674), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:40,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235870 states to 235870 states and 304674 transitions. [2024-10-13 17:46:40,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 235870 states and 304674 transitions. [2024-10-13 17:46:40,138 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-13 17:46:40,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-13 17:46:40,139 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-13 17:46:40,139 INFO L87 Difference]: Start difference. First operand 235870 states and 304674 transitions. Second operand has 3 states, 3 states have (on average 74.66666666666667) internal successors, (224), 3 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-13 17:46:40,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-13 17:46:40,816 INFO L93 Difference]: Finished difference Result 249502 states and 320802 transitions. [2024-10-13 17:46:40,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 249502 states and 320802 transitions.