./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 61a67961 Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb --- Real Ultimate output --- This is Ultimate 0.2.5-wip.fs.cvc5-61a6796-m [2024-10-15 00:58:12,664 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-15 00:58:12,751 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-15 00:58:12,755 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-15 00:58:12,758 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-15 00:58:12,785 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-15 00:58:12,788 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-15 00:58:12,788 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-15 00:58:12,789 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-15 00:58:12,789 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-15 00:58:12,790 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-15 00:58:12,790 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-15 00:58:12,790 INFO L153 SettingsManager]: * Use SBE=true [2024-10-15 00:58:12,790 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-15 00:58:12,791 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-15 00:58:12,791 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-15 00:58:12,791 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-15 00:58:12,792 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-15 00:58:12,792 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-15 00:58:12,793 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-15 00:58:12,793 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-15 00:58:12,793 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-15 00:58:12,794 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-15 00:58:12,794 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-15 00:58:12,794 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-15 00:58:12,795 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-15 00:58:12,795 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-15 00:58:12,795 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-15 00:58:12,796 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-15 00:58:12,796 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-15 00:58:12,796 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-15 00:58:12,797 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-15 00:58:12,797 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-15 00:58:12,797 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-15 00:58:12,797 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-15 00:58:12,798 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-15 00:58:12,798 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-15 00:58:12,798 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-15 00:58:12,799 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-15 00:58:12,799 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb [2024-10-15 00:58:13,071 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-15 00:58:13,096 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-15 00:58:13,099 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-15 00:58:13,100 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-15 00:58:13,100 INFO L274 PluginConnector]: CDTParser initialized [2024-10-15 00:58:13,101 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu.cil.c [2024-10-15 00:58:14,453 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-15 00:58:14,653 INFO L384 CDTParser]: Found 1 translation units. [2024-10-15 00:58:14,654 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu.cil.c [2024-10-15 00:58:14,669 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5767b745c/4b211d038b274846a9da41bc92af8f7f/FLAGb8c1d53c0 [2024-10-15 00:58:14,681 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5767b745c/4b211d038b274846a9da41bc92af8f7f [2024-10-15 00:58:14,683 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-15 00:58:14,684 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-15 00:58:14,686 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-15 00:58:14,686 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-15 00:58:14,690 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-15 00:58:14,691 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 12:58:14" (1/1) ... [2024-10-15 00:58:14,692 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b1f2d6a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:14, skipping insertion in model container [2024-10-15 00:58:14,692 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 12:58:14" (1/1) ... [2024-10-15 00:58:14,730 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-15 00:58:14,922 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-15 00:58:14,938 INFO L200 MainTranslator]: Completed pre-run [2024-10-15 00:58:14,996 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-15 00:58:15,030 INFO L204 MainTranslator]: Completed translation [2024-10-15 00:58:15,031 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15 WrapperNode [2024-10-15 00:58:15,031 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-15 00:58:15,032 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-15 00:58:15,032 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-15 00:58:15,032 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-15 00:58:15,039 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,051 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,089 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 540 [2024-10-15 00:58:15,094 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-15 00:58:15,094 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-15 00:58:15,095 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-15 00:58:15,095 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-15 00:58:15,110 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,114 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,117 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,149 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-15 00:58:15,149 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,149 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,161 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,185 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,191 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,194 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,198 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-15 00:58:15,199 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-15 00:58:15,199 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-15 00:58:15,199 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-15 00:58:15,204 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (1/1) ... [2024-10-15 00:58:15,224 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:58:15,255 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:58:15,289 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:58:15,294 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-15 00:58:15,344 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-15 00:58:15,345 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-15 00:58:15,345 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-15 00:58:15,345 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-15 00:58:15,437 INFO L238 CfgBuilder]: Building ICFG [2024-10-15 00:58:15,439 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-15 00:58:15,992 INFO L? ?]: Removed 101 outVars from TransFormulas that were not future-live. [2024-10-15 00:58:15,993 INFO L287 CfgBuilder]: Performing block encoding [2024-10-15 00:58:16,011 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-15 00:58:16,011 INFO L314 CfgBuilder]: Removed 5 assume(true) statements. [2024-10-15 00:58:16,012 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 12:58:16 BoogieIcfgContainer [2024-10-15 00:58:16,012 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-15 00:58:16,013 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-15 00:58:16,014 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-15 00:58:16,018 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-15 00:58:16,018 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 00:58:16,020 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.10 12:58:14" (1/3) ... [2024-10-15 00:58:16,021 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bc643c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 12:58:16, skipping insertion in model container [2024-10-15 00:58:16,021 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 00:58:16,021 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:58:15" (2/3) ... [2024-10-15 00:58:16,022 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bc643c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 12:58:16, skipping insertion in model container [2024-10-15 00:58:16,022 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 00:58:16,022 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 12:58:16" (3/3) ... [2024-10-15 00:58:16,024 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu.cil.c [2024-10-15 00:58:16,098 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-15 00:58:16,099 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-15 00:58:16,099 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-15 00:58:16,099 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-15 00:58:16,099 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-15 00:58:16,099 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-15 00:58:16,100 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-15 00:58:16,100 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-15 00:58:16,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:16,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158 [2024-10-15 00:58:16,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:16,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:16,155 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:16,155 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:16,156 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-15 00:58:16,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:16,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158 [2024-10-15 00:58:16,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:16,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:16,173 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:16,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:16,182 INFO L745 eck$LassoCheckResult]: Stem: 128#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 136#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 190#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 146#L305true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 184#L305-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 152#L310-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 186#L315-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 165#L118true assume !(1 == ~P_1_pc~0); 54#L118-2true is_P_1_triggered_~__retres1~0#1 := 0; 181#L129true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 47#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4#L491true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 185#L491-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 58#L186true assume 1 == ~P_2_pc~0; 95#L187true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 60#L197true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 89#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 45#L499true assume !(0 != activate_threads_~tmp___0~1#1); 143#L499-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 120#L268true assume 1 == ~C_1_pc~0; 56#L269true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 132#L289true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 189#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 121#L507true assume !(0 != activate_threads_~tmp___1~1#1); 30#L507-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 179#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 39#L561-2true [2024-10-15 00:58:16,184 INFO L747 eck$LassoCheckResult]: Loop: 39#L561-2true assume !false; 157#L562true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 97#L397true assume false; 67#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 182#L118-6true assume !(1 == ~P_1_pc~0); 5#L118-8true is_P_1_triggered_~__retres1~0#1 := 0; 16#L129-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 42#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 83#L491-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 28#L491-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 57#L186-6true assume !(1 == ~P_2_pc~0); 29#L186-8true is_P_2_triggered_~__retres1~1#1 := 0; 178#L197-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 193#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 129#L499-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 127#L499-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 11#L268-6true assume 1 == ~C_1_pc~0; 102#L269-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 117#L289-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 99#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22#L507-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 161#L507-8true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 62#L328-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 66#L345-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 167#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2#L580true assume !(0 == start_simulation_~tmp~3#1); 13#L580-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 59#L328-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 183#L345-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 160#L535true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 111#L542true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 63#L593true assume !(0 != start_simulation_~tmp___0~2#1); 39#L561-2true [2024-10-15 00:58:16,189 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:16,190 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2024-10-15 00:58:16,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:16,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775017376] [2024-10-15 00:58:16,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:16,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:16,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:16,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:16,430 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:16,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775017376] [2024-10-15 00:58:16,431 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775017376] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:16,431 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:16,431 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 00:58:16,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2648456] [2024-10-15 00:58:16,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:16,437 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 00:58:16,437 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:16,439 INFO L85 PathProgramCache]: Analyzing trace with hash -1388386939, now seen corresponding path program 1 times [2024-10-15 00:58:16,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:16,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487273255] [2024-10-15 00:58:16,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:16,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:16,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:16,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:16,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:16,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487273255] [2024-10-15 00:58:16,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487273255] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:16,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:16,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 00:58:16,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991138897] [2024-10-15 00:58:16,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:16,483 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 00:58:16,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:16,518 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 00:58:16,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 00:58:16,522 INFO L87 Difference]: Start difference. First operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:16,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:16,556 INFO L93 Difference]: Finished difference Result 187 states and 270 transitions. [2024-10-15 00:58:16,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187 states and 270 transitions. [2024-10-15 00:58:16,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2024-10-15 00:58:16,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187 states to 179 states and 262 transitions. [2024-10-15 00:58:16,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2024-10-15 00:58:16,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2024-10-15 00:58:16,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 262 transitions. [2024-10-15 00:58:16,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:16,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2024-10-15 00:58:16,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 262 transitions. [2024-10-15 00:58:16,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2024-10-15 00:58:16,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.4636871508379887) internal successors, (262), 178 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:16,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 262 transitions. [2024-10-15 00:58:16,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2024-10-15 00:58:16,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 00:58:16,609 INFO L425 stractBuchiCegarLoop]: Abstraction has 179 states and 262 transitions. [2024-10-15 00:58:16,610 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-15 00:58:16,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 262 transitions. [2024-10-15 00:58:16,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2024-10-15 00:58:16,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:16,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:16,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:16,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:16,614 INFO L745 eck$LassoCheckResult]: Stem: 490#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 516#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 508#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 536#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 549#L310-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 550#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 561#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 559#L118 assume !(1 == ~P_1_pc~0); 530#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 531#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 526#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 400#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 401#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 538#L186 assume 1 == ~P_2_pc~0; 539#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 423#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 543#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 522#L499 assume !(0 != activate_threads_~tmp___0~1#1); 523#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 465#L268 assume 1 == ~C_1_pc~0; 467#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 500#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 501#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 468#L507 assume !(0 != activate_threads_~tmp___1~1#1); 469#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 482#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 511#L561-2 [2024-10-15 00:58:16,615 INFO L747 eck$LassoCheckResult]: Loop: 511#L561-2 assume !false; 512#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 418#L397 assume !false; 441#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 442#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 484#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 437#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 438#L362 assume !(0 != eval_~tmp___2~0#1); 554#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 513#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 514#L118-6 assume !(1 == ~P_1_pc~0); 402#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 403#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 436#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 518#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 476#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 477#L186-6 assume 1 == ~P_2_pc~0; 537#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 479#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 569#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 492#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 489#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 426#L268-6 assume 1 == ~C_1_pc~0; 427#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 443#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 444#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 458#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 459#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 556#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 547#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 405#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 552#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 391#L580 assume !(0 == start_simulation_~tmp~3#1); 392#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 433#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 541#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 502#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 503#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 411#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 412#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 548#L593 assume !(0 != start_simulation_~tmp___0~2#1); 511#L561-2 [2024-10-15 00:58:16,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:16,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2024-10-15 00:58:16,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:16,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578748425] [2024-10-15 00:58:16,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:16,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:16,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:16,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:16,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:16,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578748425] [2024-10-15 00:58:16,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578748425] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:16,706 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:16,706 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 00:58:16,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [650119454] [2024-10-15 00:58:16,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:16,707 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 00:58:16,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:16,708 INFO L85 PathProgramCache]: Analyzing trace with hash 169210142, now seen corresponding path program 1 times [2024-10-15 00:58:16,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:16,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762066610] [2024-10-15 00:58:16,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:16,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:16,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:16,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:16,839 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:16,839 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762066610] [2024-10-15 00:58:16,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762066610] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:16,840 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:16,840 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 00:58:16,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449984771] [2024-10-15 00:58:16,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:16,841 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 00:58:16,841 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:16,843 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 00:58:16,843 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 00:58:16,843 INFO L87 Difference]: Start difference. First operand 179 states and 262 transitions. cyclomatic complexity: 84 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:16,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:16,866 INFO L93 Difference]: Finished difference Result 179 states and 261 transitions. [2024-10-15 00:58:16,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179 states and 261 transitions. [2024-10-15 00:58:16,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2024-10-15 00:58:16,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179 states to 179 states and 261 transitions. [2024-10-15 00:58:16,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2024-10-15 00:58:16,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2024-10-15 00:58:16,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 261 transitions. [2024-10-15 00:58:16,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:16,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2024-10-15 00:58:16,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 261 transitions. [2024-10-15 00:58:16,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2024-10-15 00:58:16,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.458100558659218) internal successors, (261), 178 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:16,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 261 transitions. [2024-10-15 00:58:16,886 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2024-10-15 00:58:16,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 00:58:16,887 INFO L425 stractBuchiCegarLoop]: Abstraction has 179 states and 261 transitions. [2024-10-15 00:58:16,888 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-15 00:58:16,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 261 transitions. [2024-10-15 00:58:16,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2024-10-15 00:58:16,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:16,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:16,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:16,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:16,891 INFO L745 eck$LassoCheckResult]: Stem: 857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 882#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 874#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 875#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 903#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 916#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 917#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 928#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 926#L118 assume !(1 == ~P_1_pc~0); 897#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 898#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 893#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 765#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 766#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 905#L186 assume 1 == ~P_2_pc~0; 906#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 785#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 910#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 888#L499 assume !(0 != activate_threads_~tmp___0~1#1); 889#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 831#L268 assume 1 == ~C_1_pc~0; 833#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 867#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 868#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 834#L507 assume !(0 != activate_threads_~tmp___1~1#1); 835#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 847#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 877#L561-2 [2024-10-15 00:58:16,895 INFO L747 eck$LassoCheckResult]: Loop: 877#L561-2 assume !false; 878#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 787#L397 assume !false; 806#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 807#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 803#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 804#L362 assume !(0 != eval_~tmp___2~0#1); 921#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 922#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 880#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 881#L118-6 assume !(1 == ~P_1_pc~0); 769#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 770#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 805#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 885#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 843#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 844#L186-6 assume 1 == ~P_2_pc~0; 904#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 846#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 936#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 859#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 856#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 793#L268-6 assume 1 == ~C_1_pc~0; 794#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 810#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 811#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 825#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 826#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 923#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 914#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 772#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 919#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 758#L580 assume !(0 == start_simulation_~tmp~3#1); 759#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 800#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 908#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 869#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 870#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 778#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 779#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 915#L593 assume !(0 != start_simulation_~tmp___0~2#1); 877#L561-2 [2024-10-15 00:58:16,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:16,896 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2024-10-15 00:58:16,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:16,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136223148] [2024-10-15 00:58:16,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:16,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:16,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:17,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:17,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:17,047 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1136223148] [2024-10-15 00:58:17,047 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1136223148] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:17,047 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:17,047 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 00:58:17,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361419322] [2024-10-15 00:58:17,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:17,048 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 00:58:17,048 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:17,048 INFO L85 PathProgramCache]: Analyzing trace with hash 169210142, now seen corresponding path program 2 times [2024-10-15 00:58:17,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:17,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218360940] [2024-10-15 00:58:17,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:17,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:17,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:17,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:17,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:17,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [218360940] [2024-10-15 00:58:17,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [218360940] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:17,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:17,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 00:58:17,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633774582] [2024-10-15 00:58:17,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:17,123 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 00:58:17,123 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:17,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 00:58:17,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-15 00:58:17,124 INFO L87 Difference]: Start difference. First operand 179 states and 261 transitions. cyclomatic complexity: 83 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:17,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:17,240 INFO L93 Difference]: Finished difference Result 191 states and 273 transitions. [2024-10-15 00:58:17,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191 states and 273 transitions. [2024-10-15 00:58:17,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2024-10-15 00:58:17,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191 states to 191 states and 273 transitions. [2024-10-15 00:58:17,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191 [2024-10-15 00:58:17,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191 [2024-10-15 00:58:17,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191 states and 273 transitions. [2024-10-15 00:58:17,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:17,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 191 states and 273 transitions. [2024-10-15 00:58:17,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states and 273 transitions. [2024-10-15 00:58:17,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 191. [2024-10-15 00:58:17,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191 states, 191 states have (on average 1.4293193717277486) internal successors, (273), 190 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:17,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 273 transitions. [2024-10-15 00:58:17,259 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191 states and 273 transitions. [2024-10-15 00:58:17,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 00:58:17,263 INFO L425 stractBuchiCegarLoop]: Abstraction has 191 states and 273 transitions. [2024-10-15 00:58:17,263 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-15 00:58:17,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states and 273 transitions. [2024-10-15 00:58:17,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2024-10-15 00:58:17,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:17,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:17,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:17,266 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:17,268 INFO L745 eck$LassoCheckResult]: Stem: 1238#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1265#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1257#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1258#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1286#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1299#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1300#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1311#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1309#L118 assume !(1 == ~P_1_pc~0); 1280#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1281#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1276#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1148#L491 assume !(0 != activate_threads_~tmp~1#1); 1149#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1288#L186 assume 1 == ~P_2_pc~0; 1289#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1166#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1293#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1270#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1271#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1213#L268 assume 1 == ~C_1_pc~0; 1215#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1249#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1250#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1216#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1217#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1230#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1260#L561-2 [2024-10-15 00:58:17,270 INFO L747 eck$LassoCheckResult]: Loop: 1260#L561-2 assume !false; 1261#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1168#L397 assume !false; 1189#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1190#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1232#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1184#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1185#L362 assume !(0 != eval_~tmp___2~0#1); 1304#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1305#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1262#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1263#L118-6 assume 1 == ~P_1_pc~0; 1272#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 1273#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1329#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1328#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1224#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1225#L186-6 assume 1 == ~P_2_pc~0; 1287#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1227#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1320#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1240#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1237#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1174#L268-6 assume 1 == ~C_1_pc~0; 1175#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1191#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1192#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1206#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1207#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1306#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1297#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1153#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1302#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1139#L580 assume !(0 == start_simulation_~tmp~3#1); 1140#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1180#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1291#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1251#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1252#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1159#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1160#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1298#L593 assume !(0 != start_simulation_~tmp___0~2#1); 1260#L561-2 [2024-10-15 00:58:17,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:17,271 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2024-10-15 00:58:17,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:17,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824211350] [2024-10-15 00:58:17,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:17,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:17,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:17,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:17,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:17,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824211350] [2024-10-15 00:58:17,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824211350] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:17,350 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:17,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-15 00:58:17,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685535174] [2024-10-15 00:58:17,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:17,351 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 00:58:17,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:17,351 INFO L85 PathProgramCache]: Analyzing trace with hash 1940681117, now seen corresponding path program 1 times [2024-10-15 00:58:17,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:17,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971840515] [2024-10-15 00:58:17,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:17,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:17,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:17,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:17,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:17,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971840515] [2024-10-15 00:58:17,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971840515] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:17,408 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:17,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 00:58:17,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652648558] [2024-10-15 00:58:17,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:17,409 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 00:58:17,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:17,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-15 00:58:17,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-15 00:58:17,411 INFO L87 Difference]: Start difference. First operand 191 states and 273 transitions. cyclomatic complexity: 83 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:17,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:17,517 INFO L93 Difference]: Finished difference Result 478 states and 671 transitions. [2024-10-15 00:58:17,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 671 transitions. [2024-10-15 00:58:17,521 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 415 [2024-10-15 00:58:17,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 671 transitions. [2024-10-15 00:58:17,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2024-10-15 00:58:17,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2024-10-15 00:58:17,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 671 transitions. [2024-10-15 00:58:17,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:17,527 INFO L218 hiAutomatonCegarLoop]: Abstraction has 478 states and 671 transitions. [2024-10-15 00:58:17,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 671 transitions. [2024-10-15 00:58:17,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 436. [2024-10-15 00:58:17,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 436 states have (on average 1.4128440366972477) internal successors, (616), 435 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:17,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 616 transitions. [2024-10-15 00:58:17,552 INFO L240 hiAutomatonCegarLoop]: Abstraction has 436 states and 616 transitions. [2024-10-15 00:58:17,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-15 00:58:17,555 INFO L425 stractBuchiCegarLoop]: Abstraction has 436 states and 616 transitions. [2024-10-15 00:58:17,555 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-15 00:58:17,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 436 states and 616 transitions. [2024-10-15 00:58:17,558 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 399 [2024-10-15 00:58:17,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:17,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:17,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:17,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:17,560 INFO L745 eck$LassoCheckResult]: Stem: 1922#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1947#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1939#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1940#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1972#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1984#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1985#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1999#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1998#L118 assume !(1 == ~P_1_pc~0); 1966#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1967#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1960#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1828#L491 assume !(0 != activate_threads_~tmp~1#1); 1829#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1973#L186 assume !(1 == ~P_2_pc~0); 1847#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 1848#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1977#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1953#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1954#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1896#L268 assume 1 == ~C_1_pc~0; 1898#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1932#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1933#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1899#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1900#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1912#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1942#L561-2 [2024-10-15 00:58:17,560 INFO L747 eck$LassoCheckResult]: Loop: 1942#L561-2 assume !false; 1943#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1850#L397 assume !false; 1871#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1872#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1914#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1868#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1869#L362 assume !(0 != eval_~tmp___2~0#1); 1992#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1993#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1945#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1946#L118-6 assume !(1 == ~P_1_pc~0); 1832#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 1833#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1870#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1950#L491-6 assume !(0 != activate_threads_~tmp~1#1); 1908#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1909#L186-6 assume !(1 == ~P_2_pc~0); 1910#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 1911#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2011#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1924#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1921#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1857#L268-6 assume 1 == ~C_1_pc~0; 1858#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1875#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1876#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1890#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1891#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1994#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1981#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1835#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1821#L580 assume !(0 == start_simulation_~tmp~3#1); 1822#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2239#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2235#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1935#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1841#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1842#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1982#L593 assume !(0 != start_simulation_~tmp___0~2#1); 1942#L561-2 [2024-10-15 00:58:17,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:17,561 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2024-10-15 00:58:17,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:17,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809396629] [2024-10-15 00:58:17,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:17,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:17,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:17,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:17,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:17,623 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809396629] [2024-10-15 00:58:17,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809396629] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:17,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:17,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-15 00:58:17,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [727991599] [2024-10-15 00:58:17,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:17,624 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 00:58:17,625 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:17,625 INFO L85 PathProgramCache]: Analyzing trace with hash 34834145, now seen corresponding path program 1 times [2024-10-15 00:58:17,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:17,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791539976] [2024-10-15 00:58:17,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:17,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:17,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:17,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:17,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:17,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791539976] [2024-10-15 00:58:17,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791539976] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:17,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:17,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 00:58:17,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [565363814] [2024-10-15 00:58:17,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:17,691 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 00:58:17,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:17,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-15 00:58:17,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-15 00:58:17,692 INFO L87 Difference]: Start difference. First operand 436 states and 616 transitions. cyclomatic complexity: 182 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:17,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:17,825 INFO L93 Difference]: Finished difference Result 1188 states and 1642 transitions. [2024-10-15 00:58:17,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1188 states and 1642 transitions. [2024-10-15 00:58:17,832 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1108 [2024-10-15 00:58:17,838 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1188 states to 1188 states and 1642 transitions. [2024-10-15 00:58:17,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1188 [2024-10-15 00:58:17,839 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1188 [2024-10-15 00:58:17,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1188 states and 1642 transitions. [2024-10-15 00:58:17,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:17,841 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1642 transitions. [2024-10-15 00:58:17,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1188 states and 1642 transitions. [2024-10-15 00:58:17,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1188 to 1129. [2024-10-15 00:58:17,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1129 states, 1129 states have (on average 1.3906111603188662) internal successors, (1570), 1128 states have internal predecessors, (1570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:17,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 1570 transitions. [2024-10-15 00:58:17,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2024-10-15 00:58:17,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-15 00:58:17,868 INFO L425 stractBuchiCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2024-10-15 00:58:17,868 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-15 00:58:17,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1129 states and 1570 transitions. [2024-10-15 00:58:17,875 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1087 [2024-10-15 00:58:17,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:17,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:17,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:17,877 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:17,878 INFO L745 eck$LassoCheckResult]: Stem: 3559#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3585#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3577#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3578#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3613#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3626#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3627#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3641#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3640#L118 assume !(1 == ~P_1_pc~0); 3607#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 3608#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3600#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3465#L491 assume !(0 != activate_threads_~tmp~1#1); 3466#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3614#L186 assume !(1 == ~P_2_pc~0); 3484#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 3485#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3618#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3593#L499 assume !(0 != activate_threads_~tmp___0~1#1); 3594#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3533#L268 assume !(1 == ~C_1_pc~0); 3534#L268-2 assume 2 == ~C_1_pc~0; 3604#L279 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3570#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3571#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3535#L507 assume !(0 != activate_threads_~tmp___1~1#1); 3536#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3548#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3580#L561-2 [2024-10-15 00:58:17,878 INFO L747 eck$LassoCheckResult]: Loop: 3580#L561-2 assume !false; 3581#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3487#L397 assume !false; 3507#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3508#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3550#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3503#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3504#L362 assume !(0 != eval_~tmp___2~0#1); 3633#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3634#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4555#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4553#L118-6 assume !(1 == ~P_1_pc~0); 4551#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 3505#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3506#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3588#L491-6 assume !(0 != activate_threads_~tmp~1#1); 3544#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3545#L186-6 assume !(1 == ~P_2_pc~0); 3546#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 3547#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3658#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3561#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 3557#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3558#L268-6 assume !(1 == ~C_1_pc~0); 4513#L268-8 assume !(2 == ~C_1_pc~0); 4505#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 4503#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 4501#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4499#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4497#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4490#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4483#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4476#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4469#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4456#L580 assume !(0 == start_simulation_~tmp~3#1); 4453#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4451#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4443#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4431#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4427#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4425#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3670#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3624#L593 assume !(0 != start_simulation_~tmp___0~2#1); 3580#L561-2 [2024-10-15 00:58:17,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:17,880 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2024-10-15 00:58:17,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:17,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295087624] [2024-10-15 00:58:17,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:17,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:17,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:17,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:17,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:17,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295087624] [2024-10-15 00:58:17,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295087624] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:17,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:17,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 00:58:17,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987989886] [2024-10-15 00:58:17,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:17,949 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 00:58:17,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:17,949 INFO L85 PathProgramCache]: Analyzing trace with hash -597585727, now seen corresponding path program 1 times [2024-10-15 00:58:17,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:17,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096757329] [2024-10-15 00:58:17,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:17,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:17,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:17,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:17,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:17,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096757329] [2024-10-15 00:58:17,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096757329] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:17,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:17,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 00:58:17,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045594495] [2024-10-15 00:58:17,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:17,998 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 00:58:17,998 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:17,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 00:58:17,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 00:58:17,999 INFO L87 Difference]: Start difference. First operand 1129 states and 1570 transitions. cyclomatic complexity: 445 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:18,053 INFO L93 Difference]: Finished difference Result 1500 states and 2055 transitions. [2024-10-15 00:58:18,053 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1500 states and 2055 transitions. [2024-10-15 00:58:18,062 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2024-10-15 00:58:18,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1500 states to 1500 states and 2055 transitions. [2024-10-15 00:58:18,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1500 [2024-10-15 00:58:18,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1500 [2024-10-15 00:58:18,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1500 states and 2055 transitions. [2024-10-15 00:58:18,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:18,075 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2055 transitions. [2024-10-15 00:58:18,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1500 states and 2055 transitions. [2024-10-15 00:58:18,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1500 to 1476. [2024-10-15 00:58:18,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.3719512195121952) internal successors, (2025), 1475 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2025 transitions. [2024-10-15 00:58:18,095 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2024-10-15 00:58:18,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 00:58:18,098 INFO L425 stractBuchiCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2024-10-15 00:58:18,098 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-15 00:58:18,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2025 transitions. [2024-10-15 00:58:18,105 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1429 [2024-10-15 00:58:18,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:18,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:18,107 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:18,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:18,108 INFO L745 eck$LassoCheckResult]: Stem: 6194#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6221#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6213#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6214#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6249#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6261#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6262#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6277#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6276#L118 assume !(1 == ~P_1_pc~0); 6244#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 6245#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6236#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6103#L491 assume !(0 != activate_threads_~tmp~1#1); 6104#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6250#L186 assume !(1 == ~P_2_pc~0); 6121#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 6122#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6254#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6229#L499 assume !(0 != activate_threads_~tmp___0~1#1); 6230#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6169#L268 assume !(1 == ~C_1_pc~0); 6170#L268-2 assume !(2 == ~C_1_pc~0); 6284#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 6206#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6207#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6171#L507 assume !(0 != activate_threads_~tmp___1~1#1); 6172#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6184#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6216#L561-2 [2024-10-15 00:58:18,108 INFO L747 eck$LassoCheckResult]: Loop: 6216#L561-2 assume !false; 6217#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 6124#L397 assume !false; 6143#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6144#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6186#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6140#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6141#L362 assume !(0 != eval_~tmp___2~0#1); 6268#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6269#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6219#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6220#L118-6 assume !(1 == ~P_1_pc~0); 6107#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 6108#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6142#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6225#L491-6 assume !(0 != activate_threads_~tmp~1#1); 6180#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6181#L186-6 assume !(1 == ~P_2_pc~0); 6182#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 6183#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6292#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6196#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 6193#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6129#L268-6 assume !(1 == ~C_1_pc~0); 6130#L268-8 assume !(2 == ~C_1_pc~0); 6239#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 6240#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 7538#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7537#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 7531#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7530#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7527#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7524#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7522#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7519#L580 assume !(0 == start_simulation_~tmp~3#1); 7517#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7516#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7513#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7512#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7511#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6115#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6116#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6259#L593 assume !(0 != start_simulation_~tmp___0~2#1); 6216#L561-2 [2024-10-15 00:58:18,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2024-10-15 00:58:18,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799742187] [2024-10-15 00:58:18,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,121 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:18,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,155 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:18,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,156 INFO L85 PathProgramCache]: Analyzing trace with hash -597585727, now seen corresponding path program 2 times [2024-10-15 00:58:18,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301806597] [2024-10-15 00:58:18,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:18,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:18,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:18,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301806597] [2024-10-15 00:58:18,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301806597] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:18,199 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:18,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 00:58:18,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955885521] [2024-10-15 00:58:18,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:18,200 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 00:58:18,200 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:18,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 00:58:18,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-15 00:58:18,200 INFO L87 Difference]: Start difference. First operand 1476 states and 2025 transitions. cyclomatic complexity: 553 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:18,253 INFO L93 Difference]: Finished difference Result 1560 states and 2109 transitions. [2024-10-15 00:58:18,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1560 states and 2109 transitions. [2024-10-15 00:58:18,262 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1513 [2024-10-15 00:58:18,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1560 states to 1560 states and 2109 transitions. [2024-10-15 00:58:18,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1560 [2024-10-15 00:58:18,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1560 [2024-10-15 00:58:18,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1560 states and 2109 transitions. [2024-10-15 00:58:18,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:18,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1560 states and 2109 transitions. [2024-10-15 00:58:18,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1560 states and 2109 transitions. [2024-10-15 00:58:18,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1560 to 1512. [2024-10-15 00:58:18,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1512 states, 1512 states have (on average 1.3630952380952381) internal successors, (2061), 1511 states have internal predecessors, (2061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1512 states to 1512 states and 2061 transitions. [2024-10-15 00:58:18,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2024-10-15 00:58:18,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 00:58:18,294 INFO L425 stractBuchiCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2024-10-15 00:58:18,294 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-15 00:58:18,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1512 states and 2061 transitions. [2024-10-15 00:58:18,300 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1465 [2024-10-15 00:58:18,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:18,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:18,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:18,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:18,301 INFO L745 eck$LassoCheckResult]: Stem: 9240#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 9241#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 9271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9261#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9262#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 9300#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 9313#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 9314#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9333#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 9332#L118 assume !(1 == ~P_1_pc~0); 9295#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 9296#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 9285#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9149#L491 assume !(0 != activate_threads_~tmp~1#1); 9150#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 9301#L186 assume !(1 == ~P_2_pc~0); 9170#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 9171#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 9305#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9280#L499 assume !(0 != activate_threads_~tmp___0~1#1); 9281#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 9215#L268 assume !(1 == ~C_1_pc~0); 9216#L268-2 assume !(2 == ~C_1_pc~0); 9342#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 9252#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 9253#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9217#L507 assume !(0 != activate_threads_~tmp___1~1#1); 9218#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9230#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 9310#L561-2 [2024-10-15 00:58:18,301 INFO L747 eck$LassoCheckResult]: Loop: 9310#L561-2 assume !false; 9319#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 9166#L397 assume !false; 9187#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9188#L328 assume !(0 == ~P_1_st~0); 9231#L332 assume !(0 == ~P_2_st~0); 9233#L336 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 9315#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10199#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10200#L362 assume !(0 != eval_~tmp___2~0#1); 10600#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10651#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10650#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10649#L118-6 assume !(1 == ~P_1_pc~0); 10648#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 10647#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10646#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10645#L491-6 assume !(0 != activate_threads_~tmp~1#1); 10644#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10643#L186-6 assume !(1 == ~P_2_pc~0); 10642#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 10641#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10640#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10639#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10638#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10637#L268-6 assume !(1 == ~C_1_pc~0); 10636#L268-8 assume !(2 == ~C_1_pc~0); 10635#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 10634#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10633#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10632#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10631#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10630#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10628#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10626#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10609#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9140#L580 assume !(0 == start_simulation_~tmp~3#1); 9141#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10620#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10617#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9254#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9255#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9326#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9377#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 9309#L593 assume !(0 != start_simulation_~tmp___0~2#1); 9310#L561-2 [2024-10-15 00:58:18,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2024-10-15 00:58:18,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751251520] [2024-10-15 00:58:18,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,309 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:18,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,318 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:18,318 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,318 INFO L85 PathProgramCache]: Analyzing trace with hash 162746408, now seen corresponding path program 1 times [2024-10-15 00:58:18,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184812980] [2024-10-15 00:58:18,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:18,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:18,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:18,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184812980] [2024-10-15 00:58:18,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184812980] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:18,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:18,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 00:58:18,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065576637] [2024-10-15 00:58:18,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:18,348 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 00:58:18,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:18,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 00:58:18,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 00:58:18,348 INFO L87 Difference]: Start difference. First operand 1512 states and 2061 transitions. cyclomatic complexity: 553 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:18,395 INFO L93 Difference]: Finished difference Result 2343 states and 3154 transitions. [2024-10-15 00:58:18,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2343 states and 3154 transitions. [2024-10-15 00:58:18,411 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2024-10-15 00:58:18,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2343 states to 2343 states and 3154 transitions. [2024-10-15 00:58:18,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2343 [2024-10-15 00:58:18,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2343 [2024-10-15 00:58:18,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2343 states and 3154 transitions. [2024-10-15 00:58:18,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:18,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2024-10-15 00:58:18,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states and 3154 transitions. [2024-10-15 00:58:18,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 2343. [2024-10-15 00:58:18,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2343 states, 2343 states have (on average 1.3461374306444729) internal successors, (3154), 2342 states have internal predecessors, (3154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2343 states to 2343 states and 3154 transitions. [2024-10-15 00:58:18,462 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2024-10-15 00:58:18,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 00:58:18,464 INFO L425 stractBuchiCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2024-10-15 00:58:18,465 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-15 00:58:18,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2343 states and 3154 transitions. [2024-10-15 00:58:18,475 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2024-10-15 00:58:18,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:18,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:18,477 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:18,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:18,478 INFO L745 eck$LassoCheckResult]: Stem: 13099#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 13100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 13127#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13120#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 13153#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 13167#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 13168#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13185#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 13184#L118 assume !(1 == ~P_1_pc~0); 13148#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 13149#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 13140#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13008#L491 assume !(0 != activate_threads_~tmp~1#1); 13009#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 13157#L186 assume !(1 == ~P_2_pc~0); 13026#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 13027#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 13160#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13133#L499 assume !(0 != activate_threads_~tmp___0~1#1); 13134#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 13075#L268 assume !(1 == ~C_1_pc~0); 13076#L268-2 assume !(2 == ~C_1_pc~0); 13192#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 13111#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 13112#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13077#L507 assume !(0 != activate_threads_~tmp___1~1#1); 13078#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13089#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 13204#L561-2 assume !false; 14431#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 14432#L397 [2024-10-15 00:58:18,478 INFO L747 eck$LassoCheckResult]: Loop: 14432#L397 assume !false; 14902#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14900#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14899#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14898#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14897#L362 assume 0 != eval_~tmp___2~0#1; 14896#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 14895#L371 assume !(0 != eval_~tmp~0#1); 14894#L367 assume !(0 == ~P_2_st~0); 14227#L382 assume !(0 == ~C_1_st~0); 14432#L397 [2024-10-15 00:58:18,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,479 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2024-10-15 00:58:18,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1243521644] [2024-10-15 00:58:18,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,487 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:18,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,496 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:18,497 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,497 INFO L85 PathProgramCache]: Analyzing trace with hash -658298241, now seen corresponding path program 1 times [2024-10-15 00:58:18,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,497 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899181081] [2024-10-15 00:58:18,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,502 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:18,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,505 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:18,506 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,506 INFO L85 PathProgramCache]: Analyzing trace with hash -1216568596, now seen corresponding path program 1 times [2024-10-15 00:58:18,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161536587] [2024-10-15 00:58:18,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:18,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:18,561 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:18,561 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161536587] [2024-10-15 00:58:18,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161536587] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:18,562 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:18,562 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 00:58:18,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746472086] [2024-10-15 00:58:18,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:18,627 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:18,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 00:58:18,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 00:58:18,628 INFO L87 Difference]: Start difference. First operand 2343 states and 3154 transitions. cyclomatic complexity: 818 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:18,694 INFO L93 Difference]: Finished difference Result 3913 states and 5192 transitions. [2024-10-15 00:58:18,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3913 states and 5192 transitions. [2024-10-15 00:58:18,714 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3761 [2024-10-15 00:58:18,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3913 states to 3913 states and 5192 transitions. [2024-10-15 00:58:18,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3913 [2024-10-15 00:58:18,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3913 [2024-10-15 00:58:18,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3913 states and 5192 transitions. [2024-10-15 00:58:18,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:18,740 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3913 states and 5192 transitions. [2024-10-15 00:58:18,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3913 states and 5192 transitions. [2024-10-15 00:58:18,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3913 to 3829. [2024-10-15 00:58:18,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3829 states, 3829 states have (on average 1.329328806476887) internal successors, (5090), 3828 states have internal predecessors, (5090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 3829 states and 5090 transitions. [2024-10-15 00:58:18,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2024-10-15 00:58:18,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 00:58:18,802 INFO L425 stractBuchiCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2024-10-15 00:58:18,802 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-15 00:58:18,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3829 states and 5090 transitions. [2024-10-15 00:58:18,814 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2024-10-15 00:58:18,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:18,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:18,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:18,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:18,815 INFO L745 eck$LassoCheckResult]: Stem: 19362#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 19363#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 19392#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19384#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19385#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 19423#L305-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 19495#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 19499#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19500#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 19460#L118 assume !(1 == ~P_1_pc~0); 19461#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 19491#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 19492#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19274#L491 assume !(0 != activate_threads_~tmp~1#1); 19275#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 19426#L186 assume !(1 == ~P_2_pc~0); 19427#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 19431#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 19432#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19402#L499 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 19403#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 19412#L268 assume !(1 == ~C_1_pc~0); 19475#L268-2 assume !(2 == ~C_1_pc~0); 19476#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 19374#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 19375#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19339#L507 assume !(0 != activate_threads_~tmp___1~1#1); 19340#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19488#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 19489#L561-2 assume !false; 22196#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 22197#L397 [2024-10-15 00:58:18,815 INFO L747 eck$LassoCheckResult]: Loop: 22197#L397 assume !false; 22532#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22531#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22530#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22529#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22528#L362 assume 0 != eval_~tmp___2~0#1; 22525#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 22522#L371 assume !(0 != eval_~tmp~0#1); 22492#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 22489#L386 assume !(0 != eval_~tmp___0~0#1); 22490#L382 assume !(0 == ~C_1_st~0); 22197#L397 [2024-10-15 00:58:18,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,816 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2024-10-15 00:58:18,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420856373] [2024-10-15 00:58:18,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:18,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:18,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:18,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420856373] [2024-10-15 00:58:18,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420856373] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:18,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:18,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 00:58:18,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581407671] [2024-10-15 00:58:18,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:18,837 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 00:58:18,837 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:18,837 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 1 times [2024-10-15 00:58:18,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:18,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85124592] [2024-10-15 00:58:18,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:18,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:18,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,841 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:18,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:18,845 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:18,890 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:18,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 00:58:18,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 00:58:18,891 INFO L87 Difference]: Start difference. First operand 3829 states and 5090 transitions. cyclomatic complexity: 1268 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:18,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:18,911 INFO L93 Difference]: Finished difference Result 3804 states and 5062 transitions. [2024-10-15 00:58:18,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3804 states and 5062 transitions. [2024-10-15 00:58:18,926 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2024-10-15 00:58:18,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3804 states to 3804 states and 5062 transitions. [2024-10-15 00:58:18,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3804 [2024-10-15 00:58:18,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3804 [2024-10-15 00:58:18,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3804 states and 5062 transitions. [2024-10-15 00:58:18,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:18,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2024-10-15 00:58:18,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3804 states and 5062 transitions. [2024-10-15 00:58:18,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3804 to 3804. [2024-10-15 00:58:19,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3804 states, 3804 states have (on average 1.3307045215562565) internal successors, (5062), 3803 states have internal predecessors, (5062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:19,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3804 states to 3804 states and 5062 transitions. [2024-10-15 00:58:19,013 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2024-10-15 00:58:19,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 00:58:19,017 INFO L425 stractBuchiCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2024-10-15 00:58:19,017 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-15 00:58:19,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3804 states and 5062 transitions. [2024-10-15 00:58:19,044 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2024-10-15 00:58:19,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:19,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:19,045 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:19,045 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:19,045 INFO L745 eck$LassoCheckResult]: Stem: 26999#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 27000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 27029#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27020#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27021#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 27054#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 27070#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 27071#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27092#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 27091#L118 assume !(1 == ~P_1_pc~0); 27049#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 27050#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 27042#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26913#L491 assume !(0 != activate_threads_~tmp~1#1); 26914#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 27060#L186 assume !(1 == ~P_2_pc~0); 26934#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 26935#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 27063#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27035#L499 assume !(0 != activate_threads_~tmp___0~1#1); 27036#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 26976#L268 assume !(1 == ~C_1_pc~0); 26977#L268-2 assume !(2 == ~C_1_pc~0); 27101#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 27011#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 27012#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26978#L507 assume !(0 != activate_threads_~tmp___1~1#1); 26979#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26994#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 27117#L561-2 assume !false; 29911#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 29903#L397 [2024-10-15 00:58:19,045 INFO L747 eck$LassoCheckResult]: Loop: 29903#L397 assume !false; 29897#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 29890#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 29886#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 29881#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29866#L362 assume 0 != eval_~tmp___2~0#1; 29865#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 27055#L371 assume !(0 != eval_~tmp~0#1); 27057#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 29728#L386 assume !(0 != eval_~tmp___0~0#1); 29815#L382 assume !(0 == ~C_1_st~0); 29903#L397 [2024-10-15 00:58:19,046 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:19,046 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2024-10-15 00:58:19,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:19,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338909715] [2024-10-15 00:58:19,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:19,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:19,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,056 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:19,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,071 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:19,073 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:19,074 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 2 times [2024-10-15 00:58:19,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:19,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776441183] [2024-10-15 00:58:19,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:19,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:19,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,081 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:19,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:19,088 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:19,089 INFO L85 PathProgramCache]: Analyzing trace with hash 940936576, now seen corresponding path program 1 times [2024-10-15 00:58:19,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:19,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642315652] [2024-10-15 00:58:19,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:19,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:19,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:58:19,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:58:19,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:58:19,123 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642315652] [2024-10-15 00:58:19,123 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642315652] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:58:19,123 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:58:19,123 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 00:58:19,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107382767] [2024-10-15 00:58:19,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:58:19,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:58:19,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 00:58:19,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 00:58:19,171 INFO L87 Difference]: Start difference. First operand 3804 states and 5062 transitions. cyclomatic complexity: 1265 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:19,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:58:19,243 INFO L93 Difference]: Finished difference Result 6650 states and 8776 transitions. [2024-10-15 00:58:19,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6650 states and 8776 transitions. [2024-10-15 00:58:19,273 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2024-10-15 00:58:19,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6650 states to 6650 states and 8776 transitions. [2024-10-15 00:58:19,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6650 [2024-10-15 00:58:19,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6650 [2024-10-15 00:58:19,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6650 states and 8776 transitions. [2024-10-15 00:58:19,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:58:19,317 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2024-10-15 00:58:19,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6650 states and 8776 transitions. [2024-10-15 00:58:19,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6650 to 6650. [2024-10-15 00:58:19,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6650 states, 6650 states have (on average 1.3196992481203007) internal successors, (8776), 6649 states have internal predecessors, (8776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:58:19,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6650 states to 6650 states and 8776 transitions. [2024-10-15 00:58:19,425 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2024-10-15 00:58:19,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 00:58:19,426 INFO L425 stractBuchiCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2024-10-15 00:58:19,426 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-15 00:58:19,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6650 states and 8776 transitions. [2024-10-15 00:58:19,447 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2024-10-15 00:58:19,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:58:19,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:58:19,448 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:19,448 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:58:19,449 INFO L745 eck$LassoCheckResult]: Stem: 37465#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 37466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 37498#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37489#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37490#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 37526#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 37542#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 37543#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37565#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 37564#L118 assume !(1 == ~P_1_pc~0); 37520#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 37521#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 37511#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 37375#L491 assume !(0 != activate_threads_~tmp~1#1); 37376#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 37530#L186 assume !(1 == ~P_2_pc~0); 37396#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 37397#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 37534#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37504#L499 assume !(0 != activate_threads_~tmp___0~1#1); 37505#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 37441#L268 assume !(1 == ~C_1_pc~0); 37442#L268-2 assume !(2 == ~C_1_pc~0); 37577#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 37478#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 37479#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37443#L507 assume !(0 != activate_threads_~tmp___1~1#1); 37444#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37460#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 37590#L561-2 assume !false; 43899#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 38939#L397 [2024-10-15 00:58:19,449 INFO L747 eck$LassoCheckResult]: Loop: 38939#L397 assume !false; 43898#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 43897#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 37598#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37599#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38272#L362 assume 0 != eval_~tmp___2~0#1; 38269#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 38265#L371 assume !(0 != eval_~tmp~0#1); 38245#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 38246#L386 assume !(0 != eval_~tmp___0~0#1); 38940#L382 assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 38906#L401 assume !(0 != eval_~tmp___1~0#1); 38939#L397 [2024-10-15 00:58:19,449 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:19,449 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2024-10-15 00:58:19,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:19,450 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721729594] [2024-10-15 00:58:19,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:19,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:19,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,457 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:19,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,468 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:19,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:19,469 INFO L85 PathProgramCache]: Analyzing trace with hash -1268840153, now seen corresponding path program 1 times [2024-10-15 00:58:19,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:19,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660280474] [2024-10-15 00:58:19,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:19,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:19,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,473 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:19,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,475 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:19,475 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:58:19,476 INFO L85 PathProgramCache]: Analyzing trace with hash -895739308, now seen corresponding path program 1 times [2024-10-15 00:58:19,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:58:19,476 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151308491] [2024-10-15 00:58:19,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:58:19,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:58:19,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,483 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:19,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:19,518 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:58:20,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:20,365 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:58:20,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:58:20,491 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 15.10 12:58:20 BoogieIcfgContainer [2024-10-15 00:58:20,494 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-10-15 00:58:20,495 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-10-15 00:58:20,495 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-10-15 00:58:20,496 INFO L274 PluginConnector]: Witness Printer initialized [2024-10-15 00:58:20,496 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 12:58:16" (3/4) ... [2024-10-15 00:58:20,498 INFO L136 WitnessPrinter]: Generating witness for non-termination counterexample [2024-10-15 00:58:20,567 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-10-15 00:58:20,567 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-10-15 00:58:20,568 INFO L158 Benchmark]: Toolchain (without parser) took 5883.47ms. Allocated memory was 163.6MB in the beginning and 237.0MB in the end (delta: 73.4MB). Free memory was 111.8MB in the beginning and 65.0MB in the end (delta: 46.9MB). Peak memory consumption was 120.3MB. Max. memory is 16.1GB. [2024-10-15 00:58:20,568 INFO L158 Benchmark]: CDTParser took 0.09ms. Allocated memory is still 98.6MB. Free memory was 61.0MB in the beginning and 61.0MB in the end (delta: 76.9kB). There was no memory consumed. Max. memory is 16.1GB. [2024-10-15 00:58:20,568 INFO L158 Benchmark]: CACSL2BoogieTranslator took 345.73ms. Allocated memory is still 163.6MB. Free memory was 111.3MB in the beginning and 96.4MB in the end (delta: 14.8MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-10-15 00:58:20,568 INFO L158 Benchmark]: Boogie Procedure Inliner took 61.56ms. Allocated memory is still 163.6MB. Free memory was 96.4MB in the beginning and 93.4MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-10-15 00:58:20,569 INFO L158 Benchmark]: Boogie Preprocessor took 103.50ms. Allocated memory is still 163.6MB. Free memory was 93.4MB in the beginning and 132.8MB in the end (delta: -39.4MB). Peak memory consumption was 6.8MB. Max. memory is 16.1GB. [2024-10-15 00:58:20,569 INFO L158 Benchmark]: RCFGBuilder took 813.82ms. Allocated memory is still 163.6MB. Free memory was 132.8MB in the beginning and 100.8MB in the end (delta: 31.9MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. [2024-10-15 00:58:20,569 INFO L158 Benchmark]: BuchiAutomizer took 4481.08ms. Allocated memory was 163.6MB in the beginning and 237.0MB in the end (delta: 73.4MB). Free memory was 100.8MB in the beginning and 70.2MB in the end (delta: 30.6MB). Peak memory consumption was 107.1MB. Max. memory is 16.1GB. [2024-10-15 00:58:20,569 INFO L158 Benchmark]: Witness Printer took 72.02ms. Allocated memory is still 237.0MB. Free memory was 70.2MB in the beginning and 65.0MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-10-15 00:58:20,571 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09ms. Allocated memory is still 98.6MB. Free memory was 61.0MB in the beginning and 61.0MB in the end (delta: 76.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 345.73ms. Allocated memory is still 163.6MB. Free memory was 111.3MB in the beginning and 96.4MB in the end (delta: 14.8MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 61.56ms. Allocated memory is still 163.6MB. Free memory was 96.4MB in the beginning and 93.4MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 103.50ms. Allocated memory is still 163.6MB. Free memory was 93.4MB in the beginning and 132.8MB in the end (delta: -39.4MB). Peak memory consumption was 6.8MB. Max. memory is 16.1GB. * RCFGBuilder took 813.82ms. Allocated memory is still 163.6MB. Free memory was 132.8MB in the beginning and 100.8MB in the end (delta: 31.9MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 4481.08ms. Allocated memory was 163.6MB in the beginning and 237.0MB in the end (delta: 73.4MB). Free memory was 100.8MB in the beginning and 70.2MB in the end (delta: 30.6MB). Peak memory consumption was 107.1MB. Max. memory is 16.1GB. * Witness Printer took 72.02ms. Allocated memory is still 237.0MB. Free memory was 70.2MB in the beginning and 65.0MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6650 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.3s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 2.6s. Construction of modules took 0.3s. Büchi inclusion checks took 1.1s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 11 MinimizatonAttempts, 257 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2703 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2703 mSDsluCounter, 5893 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3124 mSDsCounter, 111 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 306 IncrementalHoareTripleChecker+Invalid, 417 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 111 mSolverCounterUnsat, 2769 mSDtfsCounter, 306 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 357]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L128] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L130] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L196] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L198] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L288] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L290] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 357]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L128] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L130] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L196] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L198] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L288] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L290] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-10-15 00:58:20,601 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)