./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 61a67961 Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.2.5-wip.fs.cvc5-61a6796-m [2024-10-15 00:19:21,221 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-15 00:19:21,307 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-15 00:19:21,311 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-15 00:19:21,311 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-15 00:19:21,334 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-15 00:19:21,334 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-15 00:19:21,335 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-15 00:19:21,335 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-15 00:19:21,336 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-15 00:19:21,336 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-15 00:19:21,337 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-15 00:19:21,337 INFO L153 SettingsManager]: * Use SBE=true [2024-10-15 00:19:21,338 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-15 00:19:21,338 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-15 00:19:21,338 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-15 00:19:21,339 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-15 00:19:21,341 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-15 00:19:21,342 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-15 00:19:21,342 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-15 00:19:21,342 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-15 00:19:21,347 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-15 00:19:21,347 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-15 00:19:21,347 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-15 00:19:21,348 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-15 00:19:21,348 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-15 00:19:21,348 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-15 00:19:21,349 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-15 00:19:21,349 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-15 00:19:21,349 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-15 00:19:21,350 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-15 00:19:21,350 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-15 00:19:21,350 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-15 00:19:21,350 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-15 00:19:21,351 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-15 00:19:21,351 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-15 00:19:21,352 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-15 00:19:21,352 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-15 00:19:21,352 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-15 00:19:21,353 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2024-10-15 00:19:21,607 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-15 00:19:21,636 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-15 00:19:21,641 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-15 00:19:21,642 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-15 00:19:21,643 INFO L274 PluginConnector]: CDTParser initialized [2024-10-15 00:19:21,644 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2024-10-15 00:19:23,195 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-15 00:19:23,378 INFO L384 CDTParser]: Found 1 translation units. [2024-10-15 00:19:23,379 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2024-10-15 00:19:23,386 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b585d7685/cac439be9abb4489b9f843eb6214768e/FLAG473cb5958 [2024-10-15 00:19:23,400 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b585d7685/cac439be9abb4489b9f843eb6214768e [2024-10-15 00:19:23,403 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-15 00:19:23,404 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-15 00:19:23,405 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-15 00:19:23,405 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-15 00:19:23,411 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-15 00:19:23,411 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,414 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b8a7705 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23, skipping insertion in model container [2024-10-15 00:19:23,414 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,434 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-15 00:19:23,597 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-15 00:19:23,609 INFO L200 MainTranslator]: Completed pre-run [2024-10-15 00:19:23,627 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-15 00:19:23,643 INFO L204 MainTranslator]: Completed translation [2024-10-15 00:19:23,644 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23 WrapperNode [2024-10-15 00:19:23,644 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-15 00:19:23,645 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-15 00:19:23,645 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-15 00:19:23,646 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-15 00:19:23,651 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,658 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,680 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 78 [2024-10-15 00:19:23,680 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-15 00:19:23,681 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-15 00:19:23,681 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-15 00:19:23,682 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-15 00:19:23,695 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,695 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,698 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,713 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [2, 5]. 71 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2024-10-15 00:19:23,714 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,714 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,721 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,727 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,729 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,730 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,732 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-15 00:19:23,733 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-15 00:19:23,733 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-15 00:19:23,733 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-15 00:19:23,734 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (1/1) ... [2024-10-15 00:19:23,740 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:23,754 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:23,771 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:23,775 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-15 00:19:23,825 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-15 00:19:23,825 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-15 00:19:23,825 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2024-10-15 00:19:23,825 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-10-15 00:19:23,826 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-10-15 00:19:23,826 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-10-15 00:19:23,826 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-15 00:19:23,826 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-15 00:19:23,826 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-10-15 00:19:23,826 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-10-15 00:19:23,826 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-10-15 00:19:23,910 INFO L238 CfgBuilder]: Building ICFG [2024-10-15 00:19:23,913 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-15 00:19:24,123 INFO L? ?]: Removed 18 outVars from TransFormulas that were not future-live. [2024-10-15 00:19:24,124 INFO L287 CfgBuilder]: Performing block encoding [2024-10-15 00:19:24,141 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-15 00:19:24,141 INFO L314 CfgBuilder]: Removed 3 assume(true) statements. [2024-10-15 00:19:24,142 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 12:19:24 BoogieIcfgContainer [2024-10-15 00:19:24,142 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-15 00:19:24,143 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-15 00:19:24,143 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-15 00:19:24,147 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-15 00:19:24,148 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 00:19:24,149 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.10 12:19:23" (1/3) ... [2024-10-15 00:19:24,150 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5d647edb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 12:19:24, skipping insertion in model container [2024-10-15 00:19:24,150 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 00:19:24,150 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 12:19:23" (2/3) ... [2024-10-15 00:19:24,151 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5d647edb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 12:19:24, skipping insertion in model container [2024-10-15 00:19:24,151 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 00:19:24,151 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 12:19:24" (3/3) ... [2024-10-15 00:19:24,153 INFO L332 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2024-10-15 00:19:24,261 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-15 00:19:24,261 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-15 00:19:24,261 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-15 00:19:24,261 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-15 00:19:24,261 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-15 00:19:24,261 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-15 00:19:24,262 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-15 00:19:24,262 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-15 00:19:24,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:24,279 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2024-10-15 00:19:24,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:24,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:24,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-15 00:19:24,284 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-15 00:19:24,284 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-15 00:19:24,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:24,286 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2024-10-15 00:19:24,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:24,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:24,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-15 00:19:24,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-15 00:19:24,292 INFO L745 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28#L27-3true [2024-10-15 00:19:24,293 INFO L747 eck$LassoCheckResult]: Loop: 28#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5#L27-2true main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 28#L27-3true [2024-10-15 00:19:24,297 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:24,297 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-10-15 00:19:24,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:24,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151923961] [2024-10-15 00:19:24,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:24,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:24,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:24,414 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:24,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:24,453 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:24,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:24,457 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2024-10-15 00:19:24,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:24,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465128937] [2024-10-15 00:19:24,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:24,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:24,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:24,480 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:24,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:24,493 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:24,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:24,500 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2024-10-15 00:19:24,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:24,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616407195] [2024-10-15 00:19:24,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:24,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:24,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:24,537 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:24,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:24,558 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:24,945 INFO L204 LassoAnalysis]: Preferences: [2024-10-15 00:19:24,946 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-15 00:19:24,946 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-15 00:19:24,946 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-15 00:19:24,946 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-15 00:19:24,946 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:24,946 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-15 00:19:24,947 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-15 00:19:24,947 INFO L132 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2024-10-15 00:19:24,947 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-15 00:19:24,947 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-15 00:19:24,963 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:24,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:24,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:24,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:24,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:24,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:24,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:25,179 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:25,186 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:25,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:25,192 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:25,195 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 00:19:25,406 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-15 00:19:25,410 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-15 00:19:25,412 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,412 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,414 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,415 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-15 00:19:25,416 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,430 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,430 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 00:19:25,431 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,431 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,431 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,433 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 00:19:25,434 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 00:19:25,436 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 00:19:25,453 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-10-15 00:19:25,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,455 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,457 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,459 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-15 00:19:25,460 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,471 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,472 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,472 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,472 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,475 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-15 00:19:25,475 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-15 00:19:25,481 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 00:19:25,492 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-10-15 00:19:25,493 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,493 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,496 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,497 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-15 00:19:25,498 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,509 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,510 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,510 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,510 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,513 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-15 00:19:25,513 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-15 00:19:25,518 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 00:19:25,534 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-10-15 00:19:25,534 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,535 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,538 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,539 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-15 00:19:25,542 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,555 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,556 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 00:19:25,556 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,556 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,557 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,557 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 00:19:25,558 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 00:19:25,562 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 00:19:25,577 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-10-15 00:19:25,578 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,578 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,579 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,580 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-10-15 00:19:25,581 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,591 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,591 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 00:19:25,591 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,591 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,591 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,592 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 00:19:25,592 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 00:19:25,593 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 00:19:25,604 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-10-15 00:19:25,605 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,605 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,607 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,608 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-10-15 00:19:25,609 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,623 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,623 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 00:19:25,623 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,623 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,623 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,624 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 00:19:25,624 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 00:19:25,629 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 00:19:25,645 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-10-15 00:19:25,647 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,647 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,649 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,650 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-10-15 00:19:25,652 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,664 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,665 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 00:19:25,665 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,665 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,665 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,666 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 00:19:25,668 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 00:19:25,671 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 00:19:25,688 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-10-15 00:19:25,688 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,688 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,690 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,693 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-10-15 00:19:25,694 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,708 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,708 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,709 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,709 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,712 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-15 00:19:25,713 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-15 00:19:25,718 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 00:19:25,734 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-10-15 00:19:25,735 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,735 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,738 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,740 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-10-15 00:19:25,741 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 00:19:25,755 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 00:19:25,755 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 00:19:25,755 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 00:19:25,755 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 00:19:25,767 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-15 00:19:25,771 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-15 00:19:25,783 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-15 00:19:25,804 INFO L443 ModelExtractionUtils]: Simplification made 7 calls to the SMT solver. [2024-10-15 00:19:25,805 INFO L444 ModelExtractionUtils]: 5 out of 16 variables were initially zero. Simplification set additionally 7 variables to zero. [2024-10-15 00:19:25,807 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 00:19:25,807 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:25,872 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 00:19:25,874 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-10-15 00:19:25,874 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-15 00:19:25,887 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2024-10-15 00:19:25,888 INFO L474 LassoAnalysis]: Proved termination. [2024-10-15 00:19:25,888 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~#array~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~#array~0#1.offset Supporting invariants [] [2024-10-15 00:19:25,904 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-10-15 00:19:25,922 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2024-10-15 00:19:25,929 WARN L953 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2024-10-15 00:19:25,930 WARN L953 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2024-10-15 00:19:25,932 WARN L953 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~#array~0!offset [2024-10-15 00:19:25,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:25,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:25,976 INFO L255 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-15 00:19:25,977 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:25,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:25,996 INFO L255 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-15 00:19:25,996 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:26,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:26,063 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-10-15 00:19:26,066 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:26,122 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 54 states and 77 transitions. Complement of second has 6 states. [2024-10-15 00:19:26,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-15 00:19:26,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:26,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 38 transitions. [2024-10-15 00:19:26,134 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 2 letters. Loop has 2 letters. [2024-10-15 00:19:26,134 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 00:19:26,134 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 4 letters. Loop has 2 letters. [2024-10-15 00:19:26,134 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 00:19:26,134 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 2 letters. Loop has 4 letters. [2024-10-15 00:19:26,135 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 00:19:26,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 77 transitions. [2024-10-15 00:19:26,139 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2024-10-15 00:19:26,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 25 states and 35 transitions. [2024-10-15 00:19:26,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2024-10-15 00:19:26,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2024-10-15 00:19:26,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 35 transitions. [2024-10-15 00:19:26,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:26,146 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-10-15 00:19:26,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 35 transitions. [2024-10-15 00:19:26,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2024-10-15 00:19:26,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.4) internal successors, (35), 24 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:26,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2024-10-15 00:19:26,176 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-10-15 00:19:26,176 INFO L425 stractBuchiCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-10-15 00:19:26,176 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-15 00:19:26,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 35 transitions. [2024-10-15 00:19:26,179 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2024-10-15 00:19:26,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:26,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:26,183 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2024-10-15 00:19:26,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:26,183 INFO L745 eck$LassoCheckResult]: Stem: 157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 146#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 149#L27-4 main_~i~0#1 := 0; 150#L32-3 [2024-10-15 00:19:26,184 INFO L747 eck$LassoCheckResult]: Loop: 150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 155#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 144#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 150#L32-3 [2024-10-15 00:19:26,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:26,184 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2024-10-15 00:19:26,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:26,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399873003] [2024-10-15 00:19:26,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:26,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:26,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:26,199 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:26,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:26,217 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:26,217 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:26,217 INFO L85 PathProgramCache]: Analyzing trace with hash 54361, now seen corresponding path program 1 times [2024-10-15 00:19:26,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:26,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626680680] [2024-10-15 00:19:26,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:26,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:26,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:26,235 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:26,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:26,248 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:26,249 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:26,249 INFO L85 PathProgramCache]: Analyzing trace with hash 1807958031, now seen corresponding path program 1 times [2024-10-15 00:19:26,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:26,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272720438] [2024-10-15 00:19:26,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:26,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:26,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:26,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:26,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:26,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272720438] [2024-10-15 00:19:26,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [272720438] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 00:19:26,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 00:19:26,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 00:19:26,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539691734] [2024-10-15 00:19:26,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 00:19:26,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:26,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 00:19:26,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-10-15 00:19:26,488 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. cyclomatic complexity: 13 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:26,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:26,542 INFO L93 Difference]: Finished difference Result 44 states and 51 transitions. [2024-10-15 00:19:26,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 51 transitions. [2024-10-15 00:19:26,544 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:26,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 32 states and 38 transitions. [2024-10-15 00:19:26,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2024-10-15 00:19:26,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2024-10-15 00:19:26,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2024-10-15 00:19:26,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:26,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2024-10-15 00:19:26,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2024-10-15 00:19:26,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2024-10-15 00:19:26,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:26,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2024-10-15 00:19:26,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2024-10-15 00:19:26,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 00:19:26,549 INFO L425 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2024-10-15 00:19:26,549 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-15 00:19:26,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2024-10-15 00:19:26,550 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:26,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:26,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:26,561 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-10-15 00:19:26,561 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:26,561 INFO L745 eck$LassoCheckResult]: Stem: 231#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 220#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 223#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 224#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 225#L27-4 main_~i~0#1 := 0; 226#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 230#L34 [2024-10-15 00:19:26,561 INFO L747 eck$LassoCheckResult]: Loop: 230#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 218#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 227#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 230#L34 [2024-10-15 00:19:26,562 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:26,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2024-10-15 00:19:26,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:26,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41658806] [2024-10-15 00:19:26,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:26,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:26,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:26,575 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:26,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:26,584 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:26,584 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:26,585 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 2 times [2024-10-15 00:19:26,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:26,585 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3094562] [2024-10-15 00:19:26,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:26,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:26,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:26,590 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:26,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:26,605 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:26,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:26,606 INFO L85 PathProgramCache]: Analyzing trace with hash 1436021995, now seen corresponding path program 1 times [2024-10-15 00:19:26,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:26,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281187684] [2024-10-15 00:19:26,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:26,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:26,616 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-10-15 00:19:26,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:26,721 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:26,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:26,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281187684] [2024-10-15 00:19:26,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281187684] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:26,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [391045993] [2024-10-15 00:19:26,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:26,722 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:26,722 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:26,724 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:26,725 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-10-15 00:19:26,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:26,779 INFO L255 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-10-15 00:19:26,780 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:26,841 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:26,841 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:26,882 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:26,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [391045993] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:26,882 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:26,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2024-10-15 00:19:26,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726320483] [2024-10-15 00:19:26,883 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:26,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:26,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-10-15 00:19:26,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2024-10-15 00:19:26,931 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:27,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:27,035 INFO L93 Difference]: Finished difference Result 62 states and 73 transitions. [2024-10-15 00:19:27,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 73 transitions. [2024-10-15 00:19:27,037 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:27,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 46 states and 54 transitions. [2024-10-15 00:19:27,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2024-10-15 00:19:27,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2024-10-15 00:19:27,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2024-10-15 00:19:27,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:27,041 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2024-10-15 00:19:27,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2024-10-15 00:19:27,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2024-10-15 00:19:27,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:27,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2024-10-15 00:19:27,044 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-10-15 00:19:27,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-10-15 00:19:27,049 INFO L425 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-10-15 00:19:27,049 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-15 00:19:27,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2024-10-15 00:19:27,050 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:27,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:27,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:27,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-10-15 00:19:27,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:27,051 INFO L745 eck$LassoCheckResult]: Stem: 386#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 373#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 374#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 387#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 388#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 377#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 378#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 379#L27-4 main_~i~0#1 := 0; 380#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 392#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 381#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 382#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 385#L34 [2024-10-15 00:19:27,051 INFO L747 eck$LassoCheckResult]: Loop: 385#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 372#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 390#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 385#L34 [2024-10-15 00:19:27,051 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:27,051 INFO L85 PathProgramCache]: Analyzing trace with hash 780824429, now seen corresponding path program 2 times [2024-10-15 00:19:27,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:27,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488866114] [2024-10-15 00:19:27,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:27,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:27,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:27,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:27,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:27,113 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:27,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:27,114 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 3 times [2024-10-15 00:19:27,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:27,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372939301] [2024-10-15 00:19:27,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:27,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:27,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:27,120 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:27,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:27,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:27,130 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:27,130 INFO L85 PathProgramCache]: Analyzing trace with hash -2264087, now seen corresponding path program 3 times [2024-10-15 00:19:27,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:27,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605029416] [2024-10-15 00:19:27,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:27,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:27,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:27,280 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:27,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:27,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605029416] [2024-10-15 00:19:27,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1605029416] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:27,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2001183247] [2024-10-15 00:19:27,281 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-15 00:19:27,281 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:27,282 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:27,284 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:27,285 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-10-15 00:19:27,337 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2024-10-15 00:19:27,338 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:27,338 INFO L255 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-10-15 00:19:27,340 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:27,411 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:27,412 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:27,471 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:27,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2001183247] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:27,471 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:27,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2024-10-15 00:19:27,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988753316] [2024-10-15 00:19:27,472 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:27,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:27,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2024-10-15 00:19:27,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2024-10-15 00:19:27,522 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:27,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:27,673 INFO L93 Difference]: Finished difference Result 88 states and 103 transitions. [2024-10-15 00:19:27,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 103 transitions. [2024-10-15 00:19:27,674 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:27,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 60 states and 70 transitions. [2024-10-15 00:19:27,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2024-10-15 00:19:27,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2024-10-15 00:19:27,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2024-10-15 00:19:27,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:27,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2024-10-15 00:19:27,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2024-10-15 00:19:27,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2024-10-15 00:19:27,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:27,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2024-10-15 00:19:27,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2024-10-15 00:19:27,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-10-15 00:19:27,684 INFO L425 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2024-10-15 00:19:27,685 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-15 00:19:27,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2024-10-15 00:19:27,686 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:27,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:27,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:27,690 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-10-15 00:19:27,690 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:27,690 INFO L745 eck$LassoCheckResult]: Stem: 610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 596#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 597#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 611#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 612#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 600#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 601#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 616#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 615#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 602#L27-4 main_~i~0#1 := 0; 603#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 624#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 604#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 605#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 609#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 618#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 623#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 608#L34 [2024-10-15 00:19:27,690 INFO L747 eck$LassoCheckResult]: Loop: 608#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 595#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 614#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 608#L34 [2024-10-15 00:19:27,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:27,691 INFO L85 PathProgramCache]: Analyzing trace with hash -79873369, now seen corresponding path program 4 times [2024-10-15 00:19:27,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:27,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181580249] [2024-10-15 00:19:27,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:27,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:27,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:27,721 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:27,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:27,742 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:27,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:27,745 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 4 times [2024-10-15 00:19:27,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:27,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706828773] [2024-10-15 00:19:27,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:27,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:27,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:27,753 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:27,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:27,759 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:27,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:27,760 INFO L85 PathProgramCache]: Analyzing trace with hash -95607185, now seen corresponding path program 5 times [2024-10-15 00:19:27,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:27,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614135764] [2024-10-15 00:19:27,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:27,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:27,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:27,940 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 5 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:27,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:27,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614135764] [2024-10-15 00:19:27,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614135764] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:27,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1546810589] [2024-10-15 00:19:27,941 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-15 00:19:27,941 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:27,941 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:27,943 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:27,944 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-10-15 00:19:28,010 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2024-10-15 00:19:28,011 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:28,012 INFO L255 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-10-15 00:19:28,013 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:28,142 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:28,143 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:28,234 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:28,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1546810589] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:28,234 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:28,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2024-10-15 00:19:28,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004680813] [2024-10-15 00:19:28,235 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:28,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:28,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2024-10-15 00:19:28,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=197, Unknown=0, NotChecked=0, Total=272 [2024-10-15 00:19:28,286 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.375) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:28,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:28,481 INFO L93 Difference]: Finished difference Result 114 states and 133 transitions. [2024-10-15 00:19:28,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 133 transitions. [2024-10-15 00:19:28,482 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:28,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 74 states and 86 transitions. [2024-10-15 00:19:28,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2024-10-15 00:19:28,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2024-10-15 00:19:28,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2024-10-15 00:19:28,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:28,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2024-10-15 00:19:28,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2024-10-15 00:19:28,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2024-10-15 00:19:28,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:28,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2024-10-15 00:19:28,490 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2024-10-15 00:19:28,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-10-15 00:19:28,492 INFO L425 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2024-10-15 00:19:28,492 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-15 00:19:28,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2024-10-15 00:19:28,493 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:28,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:28,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:28,493 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2024-10-15 00:19:28,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:28,494 INFO L745 eck$LassoCheckResult]: Stem: 904#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 889#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 902#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 903#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 892#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 893#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 913#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 912#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 909#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 908#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 894#L27-4 main_~i~0#1 := 0; 895#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 900#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 887#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 897#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 923#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 921#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 917#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 915#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 907#L34 [2024-10-15 00:19:28,494 INFO L747 eck$LassoCheckResult]: Loop: 907#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 910#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 906#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 907#L34 [2024-10-15 00:19:28,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:28,494 INFO L85 PathProgramCache]: Analyzing trace with hash 1712449137, now seen corresponding path program 6 times [2024-10-15 00:19:28,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:28,494 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1206871484] [2024-10-15 00:19:28,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:28,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:28,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:28,521 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:28,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:28,556 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:28,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:28,557 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 5 times [2024-10-15 00:19:28,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:28,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751107260] [2024-10-15 00:19:28,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:28,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:28,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:28,563 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:28,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:28,568 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:28,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:28,569 INFO L85 PathProgramCache]: Analyzing trace with hash -49254811, now seen corresponding path program 7 times [2024-10-15 00:19:28,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:28,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760927235] [2024-10-15 00:19:28,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:28,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:28,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:28,777 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:28,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:28,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760927235] [2024-10-15 00:19:28,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760927235] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:28,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1862699396] [2024-10-15 00:19:28,777 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-15 00:19:28,778 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:28,778 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:28,780 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:28,781 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-10-15 00:19:28,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:28,839 INFO L255 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-10-15 00:19:28,841 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:28,978 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:28,979 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:29,099 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:29,099 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1862699396] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:29,099 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:29,099 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2024-10-15 00:19:29,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892088350] [2024-10-15 00:19:29,100 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:29,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:29,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2024-10-15 00:19:29,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2024-10-15 00:19:29,147 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:29,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:29,379 INFO L93 Difference]: Finished difference Result 140 states and 163 transitions. [2024-10-15 00:19:29,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 163 transitions. [2024-10-15 00:19:29,380 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:29,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 88 states and 102 transitions. [2024-10-15 00:19:29,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2024-10-15 00:19:29,381 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2024-10-15 00:19:29,381 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2024-10-15 00:19:29,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:29,382 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2024-10-15 00:19:29,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2024-10-15 00:19:29,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2024-10-15 00:19:29,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:29,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2024-10-15 00:19:29,388 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2024-10-15 00:19:29,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-10-15 00:19:29,391 INFO L425 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2024-10-15 00:19:29,391 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-15 00:19:29,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2024-10-15 00:19:29,392 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:29,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:29,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:29,393 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2024-10-15 00:19:29,393 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:29,393 INFO L745 eck$LassoCheckResult]: Stem: 1264#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1250#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1265#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1253#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1254#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1277#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1276#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1275#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1274#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1271#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1270#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1255#L27-4 main_~i~0#1 := 0; 1256#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1261#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1248#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1258#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1263#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1291#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1290#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1287#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1285#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1284#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1281#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1279#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1278#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1269#L34 [2024-10-15 00:19:29,394 INFO L747 eck$LassoCheckResult]: Loop: 1269#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1272#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1268#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1269#L34 [2024-10-15 00:19:29,395 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:29,395 INFO L85 PathProgramCache]: Analyzing trace with hash -240296029, now seen corresponding path program 8 times [2024-10-15 00:19:29,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:29,395 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848339684] [2024-10-15 00:19:29,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:29,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:29,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:29,431 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:29,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:29,449 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:29,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:29,450 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 6 times [2024-10-15 00:19:29,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:29,450 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351778783] [2024-10-15 00:19:29,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:29,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:29,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:29,454 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:29,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:29,457 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:29,458 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:29,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1051529203, now seen corresponding path program 9 times [2024-10-15 00:19:29,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:29,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534273717] [2024-10-15 00:19:29,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:29,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:29,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:29,681 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:29,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:29,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534273717] [2024-10-15 00:19:29,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534273717] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:29,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1892272650] [2024-10-15 00:19:29,682 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-15 00:19:29,683 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:29,683 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:29,685 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:29,687 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-10-15 00:19:29,761 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2024-10-15 00:19:29,761 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:29,762 INFO L255 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjuncts are in the unsatisfiable core [2024-10-15 00:19:29,765 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:29,927 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:29,928 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:30,061 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:30,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1892272650] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:30,061 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:30,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2024-10-15 00:19:30,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867572867] [2024-10-15 00:19:30,062 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:30,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:30,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2024-10-15 00:19:30,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2024-10-15 00:19:30,128 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:30,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:30,370 INFO L93 Difference]: Finished difference Result 166 states and 193 transitions. [2024-10-15 00:19:30,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166 states and 193 transitions. [2024-10-15 00:19:30,372 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:30,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166 states to 102 states and 118 transitions. [2024-10-15 00:19:30,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2024-10-15 00:19:30,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2024-10-15 00:19:30,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2024-10-15 00:19:30,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:30,374 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2024-10-15 00:19:30,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2024-10-15 00:19:30,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2024-10-15 00:19:30,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:30,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2024-10-15 00:19:30,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2024-10-15 00:19:30,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-10-15 00:19:30,379 INFO L425 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2024-10-15 00:19:30,379 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-15 00:19:30,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2024-10-15 00:19:30,380 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:30,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:30,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:30,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2024-10-15 00:19:30,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:30,381 INFO L745 eck$LassoCheckResult]: Stem: 1695#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1696#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1697#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1683#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1710#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1708#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1707#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1706#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1702#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1701#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1685#L27-4 main_~i~0#1 := 0; 1686#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1692#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1678#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1689#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1694#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1729#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1726#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1723#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1720#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1718#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1717#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1714#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1712#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1711#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1700#L34 [2024-10-15 00:19:30,381 INFO L747 eck$LassoCheckResult]: Loop: 1700#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1703#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1699#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1700#L34 [2024-10-15 00:19:30,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:30,382 INFO L85 PathProgramCache]: Analyzing trace with hash 1967863157, now seen corresponding path program 10 times [2024-10-15 00:19:30,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:30,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564331538] [2024-10-15 00:19:30,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:30,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:30,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:30,413 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:30,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:30,459 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:30,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:30,463 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 7 times [2024-10-15 00:19:30,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:30,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902650471] [2024-10-15 00:19:30,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:30,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:30,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:30,469 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:30,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:30,472 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:30,473 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:30,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1692233503, now seen corresponding path program 11 times [2024-10-15 00:19:30,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:30,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067387768] [2024-10-15 00:19:30,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:30,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:30,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:30,803 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 35 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:30,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:30,804 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067387768] [2024-10-15 00:19:30,804 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067387768] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:30,804 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2123856287] [2024-10-15 00:19:30,804 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-15 00:19:30,804 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:30,805 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:30,807 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:30,808 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-10-15 00:19:30,912 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2024-10-15 00:19:30,913 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:30,916 INFO L255 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-10-15 00:19:30,918 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:31,139 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:31,139 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:31,287 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:31,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2123856287] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:31,288 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:31,288 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2024-10-15 00:19:31,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163265199] [2024-10-15 00:19:31,288 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:31,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:31,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2024-10-15 00:19:31,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=485, Unknown=0, NotChecked=0, Total=650 [2024-10-15 00:19:31,361 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.48) internal successors, (62), 26 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:31,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:31,645 INFO L93 Difference]: Finished difference Result 192 states and 223 transitions. [2024-10-15 00:19:31,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192 states and 223 transitions. [2024-10-15 00:19:31,647 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:31,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192 states to 116 states and 134 transitions. [2024-10-15 00:19:31,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2024-10-15 00:19:31,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2024-10-15 00:19:31,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2024-10-15 00:19:31,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:31,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2024-10-15 00:19:31,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2024-10-15 00:19:31,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2024-10-15 00:19:31,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:31,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2024-10-15 00:19:31,653 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2024-10-15 00:19:31,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2024-10-15 00:19:31,655 INFO L425 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2024-10-15 00:19:31,656 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-15 00:19:31,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2024-10-15 00:19:31,657 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:31,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:31,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:31,658 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2024-10-15 00:19:31,658 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:31,658 INFO L745 eck$LassoCheckResult]: Stem: 2194#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2178#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2179#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2195#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2196#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2182#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2183#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2211#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2210#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2209#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2208#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2207#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2206#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2205#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2204#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2201#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2200#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2184#L27-4 main_~i~0#1 := 0; 2185#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2191#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2177#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2188#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2193#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2236#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2235#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2233#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2230#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2229#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2227#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2224#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2223#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2221#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2219#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2218#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2215#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2213#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2212#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2199#L34 [2024-10-15 00:19:31,659 INFO L747 eck$LassoCheckResult]: Loop: 2199#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2202#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2198#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2199#L34 [2024-10-15 00:19:31,659 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:31,660 INFO L85 PathProgramCache]: Analyzing trace with hash -664171361, now seen corresponding path program 12 times [2024-10-15 00:19:31,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:31,660 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859720660] [2024-10-15 00:19:31,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:31,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:31,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:31,702 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:31,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:31,742 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:31,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:31,743 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 8 times [2024-10-15 00:19:31,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:31,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708622550] [2024-10-15 00:19:31,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:31,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:31,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:31,751 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:31,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:31,756 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:31,756 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:31,757 INFO L85 PathProgramCache]: Analyzing trace with hash 585363831, now seen corresponding path program 13 times [2024-10-15 00:19:31,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:31,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164570303] [2024-10-15 00:19:31,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:31,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:31,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:32,083 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:32,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:32,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164570303] [2024-10-15 00:19:32,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164570303] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:32,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [655415913] [2024-10-15 00:19:32,084 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-15 00:19:32,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:32,084 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:32,087 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:32,089 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-10-15 00:19:32,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:32,165 INFO L255 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-10-15 00:19:32,166 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:32,442 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:32,442 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:32,632 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:32,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [655415913] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:32,633 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:32,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2024-10-15 00:19:32,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545212667] [2024-10-15 00:19:32,633 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:32,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:32,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2024-10-15 00:19:32,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2024-10-15 00:19:32,673 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:32,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:32,968 INFO L93 Difference]: Finished difference Result 218 states and 253 transitions. [2024-10-15 00:19:32,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 253 transitions. [2024-10-15 00:19:32,970 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:32,970 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 130 states and 150 transitions. [2024-10-15 00:19:32,971 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2024-10-15 00:19:32,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2024-10-15 00:19:32,971 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2024-10-15 00:19:32,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:32,975 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2024-10-15 00:19:32,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2024-10-15 00:19:32,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2024-10-15 00:19:32,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:32,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2024-10-15 00:19:32,983 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2024-10-15 00:19:32,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2024-10-15 00:19:32,989 INFO L425 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2024-10-15 00:19:32,989 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-15 00:19:32,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2024-10-15 00:19:32,989 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:32,990 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:32,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:32,990 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2024-10-15 00:19:32,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:32,991 INFO L745 eck$LassoCheckResult]: Stem: 2762#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2747#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2763#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2764#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2750#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2751#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2781#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2780#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2779#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2778#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2777#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2775#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2774#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2773#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2772#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2769#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2768#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2752#L27-4 main_~i~0#1 := 0; 2753#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2759#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2745#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2756#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2761#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2812#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2811#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2809#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2806#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2805#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2803#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2800#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2799#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2797#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2794#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2791#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2789#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2788#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2785#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2783#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2782#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2767#L34 [2024-10-15 00:19:32,991 INFO L747 eck$LassoCheckResult]: Loop: 2767#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2770#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2767#L34 [2024-10-15 00:19:32,991 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:32,991 INFO L85 PathProgramCache]: Analyzing trace with hash -704996231, now seen corresponding path program 14 times [2024-10-15 00:19:32,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:32,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113841259] [2024-10-15 00:19:32,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:32,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:33,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:33,056 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:33,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:33,103 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:33,104 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:33,104 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 9 times [2024-10-15 00:19:33,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:33,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225587522] [2024-10-15 00:19:33,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:33,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:33,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:33,108 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:33,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:33,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:33,111 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:33,111 INFO L85 PathProgramCache]: Analyzing trace with hash -152593571, now seen corresponding path program 15 times [2024-10-15 00:19:33,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:33,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988571417] [2024-10-15 00:19:33,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:33,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:33,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:33,582 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:33,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:33,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988571417] [2024-10-15 00:19:33,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988571417] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:33,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1186994045] [2024-10-15 00:19:33,582 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-15 00:19:33,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:33,583 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:33,585 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:33,586 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-10-15 00:19:33,694 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2024-10-15 00:19:33,694 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:33,695 INFO L255 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-10-15 00:19:33,697 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:33,978 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:33,978 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:34,176 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:34,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1186994045] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:34,177 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:34,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2024-10-15 00:19:34,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719466450] [2024-10-15 00:19:34,177 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:34,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:34,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2024-10-15 00:19:34,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2024-10-15 00:19:34,221 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:34,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:34,566 INFO L93 Difference]: Finished difference Result 244 states and 283 transitions. [2024-10-15 00:19:34,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244 states and 283 transitions. [2024-10-15 00:19:34,568 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:34,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244 states to 144 states and 166 transitions. [2024-10-15 00:19:34,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2024-10-15 00:19:34,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2024-10-15 00:19:34,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2024-10-15 00:19:34,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:34,570 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2024-10-15 00:19:34,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2024-10-15 00:19:34,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2024-10-15 00:19:34,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:34,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2024-10-15 00:19:34,575 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2024-10-15 00:19:34,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2024-10-15 00:19:34,576 INFO L425 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2024-10-15 00:19:34,576 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-15 00:19:34,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2024-10-15 00:19:34,577 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:34,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:34,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:34,578 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2024-10-15 00:19:34,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:34,578 INFO L745 eck$LassoCheckResult]: Stem: 3399#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3384#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3400#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3401#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3387#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3388#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3420#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3419#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3418#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3417#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3416#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3415#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3414#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3413#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3412#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3411#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3410#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3409#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3406#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3405#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3389#L27-4 main_~i~0#1 := 0; 3390#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3396#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3382#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3398#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3457#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3456#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3454#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3451#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3450#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3448#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3445#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3444#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3442#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3439#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3438#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3436#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3433#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3432#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3430#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3428#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3427#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3424#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3422#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3421#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3404#L34 [2024-10-15 00:19:34,579 INFO L747 eck$LassoCheckResult]: Loop: 3404#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3407#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3403#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3404#L34 [2024-10-15 00:19:34,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:34,579 INFO L85 PathProgramCache]: Analyzing trace with hash -1850900069, now seen corresponding path program 16 times [2024-10-15 00:19:34,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:34,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634736077] [2024-10-15 00:19:34,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:34,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:34,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:34,618 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:34,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:34,675 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:34,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:34,676 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 10 times [2024-10-15 00:19:34,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:34,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438725764] [2024-10-15 00:19:34,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:34,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:34,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:34,682 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:34,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:34,688 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:34,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:34,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1373762821, now seen corresponding path program 17 times [2024-10-15 00:19:34,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:34,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980772598] [2024-10-15 00:19:34,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:34,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:34,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:35,106 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 92 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:35,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:35,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980772598] [2024-10-15 00:19:35,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1980772598] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:35,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [490550788] [2024-10-15 00:19:35,107 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-15 00:19:35,107 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:35,107 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:35,110 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:35,111 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-10-15 00:19:35,269 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2024-10-15 00:19:35,269 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:35,271 INFO L255 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-10-15 00:19:35,273 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:35,548 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:35,549 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:35,781 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:35,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [490550788] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:35,782 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:35,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2024-10-15 00:19:35,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436095121] [2024-10-15 00:19:35,782 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:35,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:35,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2024-10-15 00:19:35,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=899, Unknown=0, NotChecked=0, Total=1190 [2024-10-15 00:19:35,823 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.5294117647058822) internal successors, (86), 35 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:36,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:36,152 INFO L93 Difference]: Finished difference Result 270 states and 313 transitions. [2024-10-15 00:19:36,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 313 transitions. [2024-10-15 00:19:36,154 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:36,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 158 states and 182 transitions. [2024-10-15 00:19:36,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2024-10-15 00:19:36,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2024-10-15 00:19:36,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2024-10-15 00:19:36,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:36,156 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2024-10-15 00:19:36,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2024-10-15 00:19:36,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2024-10-15 00:19:36,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:36,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2024-10-15 00:19:36,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2024-10-15 00:19:36,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2024-10-15 00:19:36,161 INFO L425 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2024-10-15 00:19:36,161 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-15 00:19:36,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2024-10-15 00:19:36,162 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:36,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:36,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:36,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2024-10-15 00:19:36,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:36,163 INFO L745 eck$LassoCheckResult]: Stem: 4105#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4090#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4106#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4107#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4093#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4094#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4128#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4127#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4126#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4125#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4124#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4123#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4122#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4121#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4120#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4119#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4118#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4117#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4116#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4115#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4112#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4111#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4095#L27-4 main_~i~0#1 := 0; 4096#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4102#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4088#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4099#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4104#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4171#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4168#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4165#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4164#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4162#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4159#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4158#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4156#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4153#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4152#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4150#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4147#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4144#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4141#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4138#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4136#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4135#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4132#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4130#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4129#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4110#L34 [2024-10-15 00:19:36,163 INFO L747 eck$LassoCheckResult]: Loop: 4110#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4113#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4109#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4110#L34 [2024-10-15 00:19:36,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:36,164 INFO L85 PathProgramCache]: Analyzing trace with hash -354133123, now seen corresponding path program 18 times [2024-10-15 00:19:36,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:36,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052624074] [2024-10-15 00:19:36,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:36,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:36,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:36,204 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:36,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:36,246 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:36,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:36,247 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 11 times [2024-10-15 00:19:36,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:36,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291851102] [2024-10-15 00:19:36,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:36,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:36,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:36,252 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:36,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:36,255 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:36,255 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:36,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1540141607, now seen corresponding path program 19 times [2024-10-15 00:19:36,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:36,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914377600] [2024-10-15 00:19:36,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:36,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:36,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:36,757 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:36,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:36,757 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914377600] [2024-10-15 00:19:36,757 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [914377600] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:36,757 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [684919190] [2024-10-15 00:19:36,758 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-15 00:19:36,758 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:36,758 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:36,760 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:36,761 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-10-15 00:19:36,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:36,858 INFO L255 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-10-15 00:19:36,860 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:37,175 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:37,175 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:37,387 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:37,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [684919190] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:37,388 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:37,388 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2024-10-15 00:19:37,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1738533125] [2024-10-15 00:19:37,388 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:37,419 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:37,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2024-10-15 00:19:37,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2024-10-15 00:19:37,421 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:37,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:37,850 INFO L93 Difference]: Finished difference Result 296 states and 343 transitions. [2024-10-15 00:19:37,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 296 states and 343 transitions. [2024-10-15 00:19:37,855 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:37,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 296 states to 172 states and 198 transitions. [2024-10-15 00:19:37,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2024-10-15 00:19:37,856 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2024-10-15 00:19:37,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2024-10-15 00:19:37,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:37,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2024-10-15 00:19:37,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2024-10-15 00:19:37,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2024-10-15 00:19:37,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:37,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2024-10-15 00:19:37,864 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2024-10-15 00:19:37,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2024-10-15 00:19:37,870 INFO L425 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2024-10-15 00:19:37,870 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-15 00:19:37,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2024-10-15 00:19:37,871 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:37,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:37,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:37,874 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2024-10-15 00:19:37,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:37,874 INFO L745 eck$LassoCheckResult]: Stem: 4880#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4865#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4881#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4882#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4868#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4869#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4905#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4904#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4903#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4902#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4901#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4900#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4899#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4898#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4897#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4896#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4895#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4894#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4893#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4892#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4891#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4890#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4887#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4886#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4870#L27-4 main_~i~0#1 := 0; 4871#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4877#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4863#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4874#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4879#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4954#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4953#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4951#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4948#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4947#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4945#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4942#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4941#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4939#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4936#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4935#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4933#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4930#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4929#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4927#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4924#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4923#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4921#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4918#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4917#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4915#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4913#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4912#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4909#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4907#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4906#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4885#L34 [2024-10-15 00:19:37,876 INFO L747 eck$LassoCheckResult]: Loop: 4885#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4888#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4884#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4885#L34 [2024-10-15 00:19:37,877 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:37,877 INFO L85 PathProgramCache]: Analyzing trace with hash -726335849, now seen corresponding path program 20 times [2024-10-15 00:19:37,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:37,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572554997] [2024-10-15 00:19:37,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:37,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:37,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:37,955 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:38,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:38,010 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:38,011 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:38,011 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 12 times [2024-10-15 00:19:38,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:38,011 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378348261] [2024-10-15 00:19:38,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:38,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:38,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:38,015 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:38,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:38,019 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:38,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:38,020 INFO L85 PathProgramCache]: Analyzing trace with hash -225993601, now seen corresponding path program 21 times [2024-10-15 00:19:38,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:38,020 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213100680] [2024-10-15 00:19:38,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:38,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:38,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:38,547 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:38,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:38,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213100680] [2024-10-15 00:19:38,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213100680] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:38,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1586156239] [2024-10-15 00:19:38,548 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-15 00:19:38,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:38,548 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:38,550 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:38,552 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-10-15 00:19:38,735 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2024-10-15 00:19:38,736 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:38,737 INFO L255 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjuncts are in the unsatisfiable core [2024-10-15 00:19:38,739 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:39,121 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:39,122 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:39,395 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:39,395 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1586156239] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:39,395 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:39,395 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2024-10-15 00:19:39,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329695022] [2024-10-15 00:19:39,395 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:39,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:39,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2024-10-15 00:19:39,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2024-10-15 00:19:39,431 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:39,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:39,806 INFO L93 Difference]: Finished difference Result 322 states and 373 transitions. [2024-10-15 00:19:39,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 373 transitions. [2024-10-15 00:19:39,809 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:39,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 186 states and 214 transitions. [2024-10-15 00:19:39,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2024-10-15 00:19:39,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2024-10-15 00:19:39,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2024-10-15 00:19:39,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:39,811 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2024-10-15 00:19:39,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2024-10-15 00:19:39,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2024-10-15 00:19:39,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:39,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2024-10-15 00:19:39,815 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2024-10-15 00:19:39,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2024-10-15 00:19:39,820 INFO L425 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2024-10-15 00:19:39,820 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-15 00:19:39,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2024-10-15 00:19:39,821 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:39,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:39,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:39,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2024-10-15 00:19:39,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:39,822 INFO L745 eck$LassoCheckResult]: Stem: 5726#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5708#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5724#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5725#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5712#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5713#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5751#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5749#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5748#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5747#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5745#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5744#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5743#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5742#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5741#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5740#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5739#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5738#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5737#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5735#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5734#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5731#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5730#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5714#L27-4 main_~i~0#1 := 0; 5715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5721#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5707#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5718#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5723#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5806#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5805#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5803#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5800#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5799#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5797#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5794#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5791#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5788#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5787#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5785#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5782#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5781#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5779#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5776#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5775#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5773#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5770#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5769#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5767#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5764#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5761#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5759#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5758#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5755#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5753#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5752#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5729#L34 [2024-10-15 00:19:39,822 INFO L747 eck$LassoCheckResult]: Loop: 5729#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5732#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5729#L34 [2024-10-15 00:19:39,823 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:39,823 INFO L85 PathProgramCache]: Analyzing trace with hash -2083736959, now seen corresponding path program 22 times [2024-10-15 00:19:39,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:39,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790765967] [2024-10-15 00:19:39,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:39,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:39,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:39,894 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:39,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:39,946 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:39,946 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:39,947 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 13 times [2024-10-15 00:19:39,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:39,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702185225] [2024-10-15 00:19:39,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:39,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:39,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:39,950 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:39,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:39,953 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:39,954 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:39,954 INFO L85 PathProgramCache]: Analyzing trace with hash -1445369771, now seen corresponding path program 23 times [2024-10-15 00:19:39,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:39,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192054756] [2024-10-15 00:19:39,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:39,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:39,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:40,548 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 176 proven. 178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:40,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:40,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192054756] [2024-10-15 00:19:40,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192054756] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:40,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [699092170] [2024-10-15 00:19:40,549 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-15 00:19:40,549 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:40,550 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:40,552 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:40,553 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-10-15 00:19:40,807 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2024-10-15 00:19:40,807 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:40,809 INFO L255 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-10-15 00:19:40,811 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:41,258 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:41,259 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:41,578 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:41,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [699092170] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:41,578 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:41,579 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2024-10-15 00:19:41,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319997989] [2024-10-15 00:19:41,579 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:41,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:41,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2024-10-15 00:19:41,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2024-10-15 00:19:41,612 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.558139534883721) internal successors, (110), 44 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:42,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:42,064 INFO L93 Difference]: Finished difference Result 348 states and 403 transitions. [2024-10-15 00:19:42,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 348 states and 403 transitions. [2024-10-15 00:19:42,067 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:42,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 348 states to 200 states and 230 transitions. [2024-10-15 00:19:42,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2024-10-15 00:19:42,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2024-10-15 00:19:42,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2024-10-15 00:19:42,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:42,069 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2024-10-15 00:19:42,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2024-10-15 00:19:42,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2024-10-15 00:19:42,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:42,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2024-10-15 00:19:42,072 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2024-10-15 00:19:42,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-10-15 00:19:42,076 INFO L425 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2024-10-15 00:19:42,076 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-15 00:19:42,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2024-10-15 00:19:42,077 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:42,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:42,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:42,078 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2024-10-15 00:19:42,079 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:42,079 INFO L745 eck$LassoCheckResult]: Stem: 6637#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 6621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 6622#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6638#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6639#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6625#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6626#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6666#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6665#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6664#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6663#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6662#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6661#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6660#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6659#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6658#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6657#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6656#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6655#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6654#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6653#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6652#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6650#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6649#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6648#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6644#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6643#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 6627#L27-4 main_~i~0#1 := 0; 6628#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6634#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6620#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6631#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6636#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6727#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6726#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6724#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6721#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6720#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6718#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6715#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6714#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6712#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6709#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6708#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6706#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6703#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6702#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6700#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6697#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6696#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6694#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6691#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6690#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6688#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6685#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6684#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6682#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6679#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6678#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6676#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6674#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6673#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6670#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6668#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6667#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6642#L34 [2024-10-15 00:19:42,079 INFO L747 eck$LassoCheckResult]: Loop: 6642#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6645#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6641#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6642#L34 [2024-10-15 00:19:42,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:42,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1447312493, now seen corresponding path program 24 times [2024-10-15 00:19:42,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:42,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498758197] [2024-10-15 00:19:42,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:42,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:42,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:42,131 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:42,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:42,183 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:42,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:42,185 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 14 times [2024-10-15 00:19:42,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:42,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637501962] [2024-10-15 00:19:42,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:42,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:42,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:42,190 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:42,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:42,194 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:42,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:42,194 INFO L85 PathProgramCache]: Analyzing trace with hash 290252291, now seen corresponding path program 25 times [2024-10-15 00:19:42,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:42,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081528541] [2024-10-15 00:19:42,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:42,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:42,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:42,900 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 210 proven. 206 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:42,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:42,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081528541] [2024-10-15 00:19:42,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081528541] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:42,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1058757281] [2024-10-15 00:19:42,901 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-15 00:19:42,901 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:42,902 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:42,904 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:42,905 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-10-15 00:19:43,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:43,024 INFO L255 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjuncts are in the unsatisfiable core [2024-10-15 00:19:43,026 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:43,465 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:43,465 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:43,835 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:43,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1058757281] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:43,835 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:43,835 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 46 [2024-10-15 00:19:43,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [582958080] [2024-10-15 00:19:43,835 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:43,882 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:43,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2024-10-15 00:19:43,884 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=515, Invalid=1647, Unknown=0, NotChecked=0, Total=2162 [2024-10-15 00:19:43,884 INFO L87 Difference]: Start difference. First operand 116 states and 132 transitions. cyclomatic complexity: 19 Second operand has 47 states, 46 states have (on average 2.5652173913043477) internal successors, (118), 47 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:44,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:44,495 INFO L93 Difference]: Finished difference Result 374 states and 433 transitions. [2024-10-15 00:19:44,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 374 states and 433 transitions. [2024-10-15 00:19:44,498 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:44,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 374 states to 214 states and 246 transitions. [2024-10-15 00:19:44,500 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185 [2024-10-15 00:19:44,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185 [2024-10-15 00:19:44,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 214 states and 246 transitions. [2024-10-15 00:19:44,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:44,501 INFO L218 hiAutomatonCegarLoop]: Abstraction has 214 states and 246 transitions. [2024-10-15 00:19:44,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states and 246 transitions. [2024-10-15 00:19:44,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 124. [2024-10-15 00:19:44,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.1370967741935485) internal successors, (141), 123 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:44,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 141 transitions. [2024-10-15 00:19:44,504 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 141 transitions. [2024-10-15 00:19:44,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-10-15 00:19:44,505 INFO L425 stractBuchiCegarLoop]: Abstraction has 124 states and 141 transitions. [2024-10-15 00:19:44,505 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-15 00:19:44,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 141 transitions. [2024-10-15 00:19:44,506 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:44,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:44,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:44,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1] [2024-10-15 00:19:44,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:44,507 INFO L745 eck$LassoCheckResult]: Stem: 7619#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 7604#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7620#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7621#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7607#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7608#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7650#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7649#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7648#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7646#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7645#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7644#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7643#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7642#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7641#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7640#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7639#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7638#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7637#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7636#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7635#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7634#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7633#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7632#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7631#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7630#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7629#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 7626#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7625#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 7609#L27-4 main_~i~0#1 := 0; 7610#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7616#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7602#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7613#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7618#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7717#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7716#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7714#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7711#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7710#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7708#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7705#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7704#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7702#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7699#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7698#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7696#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7693#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7690#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7687#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7686#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7684#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7681#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7680#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7678#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7675#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7674#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7672#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7669#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7668#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7666#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7663#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7662#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7660#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7658#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7657#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7654#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7652#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7651#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7624#L34 [2024-10-15 00:19:44,508 INFO L747 eck$LassoCheckResult]: Loop: 7624#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 7627#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 7623#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7624#L34 [2024-10-15 00:19:44,508 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:44,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1635246469, now seen corresponding path program 26 times [2024-10-15 00:19:44,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:44,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408477360] [2024-10-15 00:19:44,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:44,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:44,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:44,579 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:44,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:44,634 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:44,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:44,635 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 15 times [2024-10-15 00:19:44,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:44,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234612132] [2024-10-15 00:19:44,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:44,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:44,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:44,639 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:44,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:44,642 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:44,643 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:44,643 INFO L85 PathProgramCache]: Analyzing trace with hash 2108533457, now seen corresponding path program 27 times [2024-10-15 00:19:44,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:44,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994975371] [2024-10-15 00:19:44,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:44,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:44,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:45,316 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 247 proven. 236 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:45,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:45,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994975371] [2024-10-15 00:19:45,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [994975371] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:45,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [282205469] [2024-10-15 00:19:45,317 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-15 00:19:45,317 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:45,317 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:45,321 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:45,322 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-10-15 00:19:45,655 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2024-10-15 00:19:45,655 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:45,657 INFO L255 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjuncts are in the unsatisfiable core [2024-10-15 00:19:45,659 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:46,106 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:46,107 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:46,450 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:46,451 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [282205469] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:46,451 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:46,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32] total 49 [2024-10-15 00:19:46,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747686434] [2024-10-15 00:19:46,451 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:46,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:46,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2024-10-15 00:19:46,494 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=581, Invalid=1869, Unknown=0, NotChecked=0, Total=2450 [2024-10-15 00:19:46,494 INFO L87 Difference]: Start difference. First operand 124 states and 141 transitions. cyclomatic complexity: 20 Second operand has 50 states, 49 states have (on average 2.5714285714285716) internal successors, (126), 50 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:47,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:47,029 INFO L93 Difference]: Finished difference Result 400 states and 463 transitions. [2024-10-15 00:19:47,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 400 states and 463 transitions. [2024-10-15 00:19:47,032 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:47,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 400 states to 228 states and 262 transitions. [2024-10-15 00:19:47,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2024-10-15 00:19:47,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2024-10-15 00:19:47,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 262 transitions. [2024-10-15 00:19:47,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:47,034 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228 states and 262 transitions. [2024-10-15 00:19:47,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 262 transitions. [2024-10-15 00:19:47,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 132. [2024-10-15 00:19:47,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 132 states have (on average 1.1363636363636365) internal successors, (150), 131 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:47,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 150 transitions. [2024-10-15 00:19:47,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 132 states and 150 transitions. [2024-10-15 00:19:47,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2024-10-15 00:19:47,039 INFO L425 stractBuchiCegarLoop]: Abstraction has 132 states and 150 transitions. [2024-10-15 00:19:47,039 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-15 00:19:47,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132 states and 150 transitions. [2024-10-15 00:19:47,040 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:47,040 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:47,040 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:47,041 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 15, 14, 14, 1, 1, 1, 1] [2024-10-15 00:19:47,041 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:47,041 INFO L745 eck$LassoCheckResult]: Stem: 8670#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 8654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 8655#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8671#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8672#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8658#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8659#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8703#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8702#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8701#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8700#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8699#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8698#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8697#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8696#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8695#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8694#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8693#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8692#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8691#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8690#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8689#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8687#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8686#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8685#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8683#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8682#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8681#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 8677#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 8676#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 8660#L27-4 main_~i~0#1 := 0; 8661#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8667#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8653#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8664#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8669#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8776#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8775#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8773#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8770#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8769#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8767#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8764#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8761#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8758#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8757#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8755#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8752#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8749#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8746#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8743#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8740#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8737#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8734#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8731#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8728#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8725#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8722#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8719#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8716#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8713#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8711#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8710#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8707#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8705#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8704#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8675#L34 [2024-10-15 00:19:47,041 INFO L747 eck$LassoCheckResult]: Loop: 8675#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 8678#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 8674#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8675#L34 [2024-10-15 00:19:47,042 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:47,042 INFO L85 PathProgramCache]: Analyzing trace with hash -436367217, now seen corresponding path program 28 times [2024-10-15 00:19:47,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:47,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612866051] [2024-10-15 00:19:47,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:47,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:47,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:47,127 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:47,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:47,185 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:47,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:47,186 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 16 times [2024-10-15 00:19:47,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:47,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121937106] [2024-10-15 00:19:47,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:47,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:47,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:47,192 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:47,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:47,196 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:47,196 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:47,197 INFO L85 PathProgramCache]: Analyzing trace with hash 1050290055, now seen corresponding path program 29 times [2024-10-15 00:19:47,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:47,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389467348] [2024-10-15 00:19:47,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:47,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:47,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:48,043 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 287 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:48,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:48,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389467348] [2024-10-15 00:19:48,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389467348] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:48,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [754565872] [2024-10-15 00:19:48,044 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-15 00:19:48,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:48,044 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:48,046 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:48,049 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-10-15 00:19:48,387 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2024-10-15 00:19:48,387 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:48,391 INFO L255 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjuncts are in the unsatisfiable core [2024-10-15 00:19:48,393 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:49,057 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:49,057 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:49,497 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:49,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [754565872] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:49,497 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:49,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34] total 52 [2024-10-15 00:19:49,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611402249] [2024-10-15 00:19:49,497 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:49,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:49,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2024-10-15 00:19:49,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=2105, Unknown=0, NotChecked=0, Total=2756 [2024-10-15 00:19:49,531 INFO L87 Difference]: Start difference. First operand 132 states and 150 transitions. cyclomatic complexity: 21 Second operand has 53 states, 52 states have (on average 2.576923076923077) internal successors, (134), 53 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:50,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:50,179 INFO L93 Difference]: Finished difference Result 426 states and 493 transitions. [2024-10-15 00:19:50,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 426 states and 493 transitions. [2024-10-15 00:19:50,182 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:50,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 426 states to 242 states and 278 transitions. [2024-10-15 00:19:50,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209 [2024-10-15 00:19:50,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209 [2024-10-15 00:19:50,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 278 transitions. [2024-10-15 00:19:50,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:50,184 INFO L218 hiAutomatonCegarLoop]: Abstraction has 242 states and 278 transitions. [2024-10-15 00:19:50,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 278 transitions. [2024-10-15 00:19:50,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 140. [2024-10-15 00:19:50,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.1357142857142857) internal successors, (159), 139 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:50,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 159 transitions. [2024-10-15 00:19:50,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2024-10-15 00:19:50,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2024-10-15 00:19:50,189 INFO L425 stractBuchiCegarLoop]: Abstraction has 140 states and 159 transitions. [2024-10-15 00:19:50,189 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-15 00:19:50,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 159 transitions. [2024-10-15 00:19:50,190 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:50,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:50,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:50,191 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 16, 15, 15, 1, 1, 1, 1] [2024-10-15 00:19:50,191 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:50,191 INFO L745 eck$LassoCheckResult]: Stem: 9790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 9774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 9775#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9791#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9792#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9778#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9779#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9825#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9824#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9823#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9822#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9821#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9820#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9819#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9818#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9817#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9816#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9815#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9814#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9813#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9812#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9811#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9810#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9809#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9808#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9807#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9806#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9805#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9804#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9803#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9802#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9801#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9800#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9797#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 9796#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 9780#L27-4 main_~i~0#1 := 0; 9781#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9787#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9773#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9784#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9789#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9904#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9903#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9901#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9898#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9897#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9895#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9892#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9891#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9889#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9886#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9885#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9883#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9880#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9879#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9877#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9874#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9873#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9871#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9868#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9867#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9865#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9862#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9861#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9859#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9856#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9855#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9853#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9850#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9849#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9847#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9844#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9843#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9841#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9838#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9837#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9835#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9833#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9832#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9829#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9827#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9826#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9795#L34 [2024-10-15 00:19:50,192 INFO L747 eck$LassoCheckResult]: Loop: 9795#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 9798#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 9794#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9795#L34 [2024-10-15 00:19:50,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:50,192 INFO L85 PathProgramCache]: Analyzing trace with hash -1180030839, now seen corresponding path program 30 times [2024-10-15 00:19:50,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:50,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012952391] [2024-10-15 00:19:50,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:50,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:50,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:50,272 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:50,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:50,342 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:50,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:50,343 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 17 times [2024-10-15 00:19:50,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:50,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485008715] [2024-10-15 00:19:50,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:50,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:50,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:50,347 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:50,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:50,350 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:50,350 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:50,350 INFO L85 PathProgramCache]: Analyzing trace with hash 8639821, now seen corresponding path program 31 times [2024-10-15 00:19:50,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:50,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41137769] [2024-10-15 00:19:50,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:50,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:50,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:51,270 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 330 proven. 302 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:51,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:51,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41137769] [2024-10-15 00:19:51,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [41137769] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:51,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [522111247] [2024-10-15 00:19:51,270 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-15 00:19:51,271 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:51,271 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:51,273 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:51,274 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-10-15 00:19:51,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:51,407 INFO L255 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjuncts are in the unsatisfiable core [2024-10-15 00:19:51,408 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:51,967 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:51,967 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:52,426 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:52,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [522111247] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:52,426 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:52,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 55 [2024-10-15 00:19:52,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903947100] [2024-10-15 00:19:52,427 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:52,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:52,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2024-10-15 00:19:52,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=725, Invalid=2355, Unknown=0, NotChecked=0, Total=3080 [2024-10-15 00:19:52,461 INFO L87 Difference]: Start difference. First operand 140 states and 159 transitions. cyclomatic complexity: 22 Second operand has 56 states, 55 states have (on average 2.581818181818182) internal successors, (142), 56 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:53,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:53,100 INFO L93 Difference]: Finished difference Result 452 states and 523 transitions. [2024-10-15 00:19:53,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 452 states and 523 transitions. [2024-10-15 00:19:53,103 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:53,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 452 states to 256 states and 294 transitions. [2024-10-15 00:19:53,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2024-10-15 00:19:53,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2024-10-15 00:19:53,105 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 294 transitions. [2024-10-15 00:19:53,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:53,105 INFO L218 hiAutomatonCegarLoop]: Abstraction has 256 states and 294 transitions. [2024-10-15 00:19:53,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 294 transitions. [2024-10-15 00:19:53,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 148. [2024-10-15 00:19:53,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 148 states have (on average 1.135135135135135) internal successors, (168), 147 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:53,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 168 transitions. [2024-10-15 00:19:53,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 148 states and 168 transitions. [2024-10-15 00:19:53,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-10-15 00:19:53,109 INFO L425 stractBuchiCegarLoop]: Abstraction has 148 states and 168 transitions. [2024-10-15 00:19:53,109 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-15 00:19:53,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148 states and 168 transitions. [2024-10-15 00:19:53,110 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:53,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:53,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:53,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 17, 16, 16, 1, 1, 1, 1] [2024-10-15 00:19:53,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:53,111 INFO L745 eck$LassoCheckResult]: Stem: 10979#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 10963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 10964#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10980#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10981#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10967#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10968#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11016#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11015#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11014#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11013#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11012#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11011#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11010#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11009#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11008#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11007#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11006#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11005#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11004#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11003#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11002#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11001#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11000#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10999#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10998#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10997#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10996#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10995#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10994#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10993#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10992#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10991#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10990#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10989#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 10986#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 10985#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 10969#L27-4 main_~i~0#1 := 0; 10970#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10976#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10962#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10973#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10978#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11101#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11100#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11098#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11095#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11094#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11092#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11089#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11088#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11086#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11083#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11082#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11080#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11077#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11076#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11074#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11071#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11070#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11068#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11065#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11064#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11062#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11059#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11058#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11056#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11053#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11052#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11050#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11047#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11046#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11044#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11041#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11040#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11038#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11035#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11034#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11032#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11029#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11028#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11026#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11024#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11023#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11020#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 11018#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 11017#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10984#L34 [2024-10-15 00:19:53,112 INFO L747 eck$LassoCheckResult]: Loop: 10984#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 10987#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 10983#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 10984#L34 [2024-10-15 00:19:53,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:53,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1481235061, now seen corresponding path program 32 times [2024-10-15 00:19:53,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:53,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271222314] [2024-10-15 00:19:53,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:53,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:53,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:53,188 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:53,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:53,262 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:53,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:53,264 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 18 times [2024-10-15 00:19:53,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:53,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106542562] [2024-10-15 00:19:53,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:53,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:53,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:53,268 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:53,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:53,272 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:53,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:53,272 INFO L85 PathProgramCache]: Analyzing trace with hash -979656437, now seen corresponding path program 33 times [2024-10-15 00:19:53,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:53,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858693967] [2024-10-15 00:19:53,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:53,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:53,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:54,208 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 376 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:54,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:54,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858693967] [2024-10-15 00:19:54,208 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858693967] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:54,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2076817778] [2024-10-15 00:19:54,208 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-15 00:19:54,208 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:54,209 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:54,211 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:54,213 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-10-15 00:19:54,843 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2024-10-15 00:19:54,843 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:54,847 INFO L255 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjuncts are in the unsatisfiable core [2024-10-15 00:19:54,848 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:55,471 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:55,471 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:55,950 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:55,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2076817778] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:55,951 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:55,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38] total 58 [2024-10-15 00:19:55,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141116894] [2024-10-15 00:19:55,951 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:55,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:56,000 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2024-10-15 00:19:56,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=803, Invalid=2619, Unknown=0, NotChecked=0, Total=3422 [2024-10-15 00:19:56,001 INFO L87 Difference]: Start difference. First operand 148 states and 168 transitions. cyclomatic complexity: 23 Second operand has 59 states, 58 states have (on average 2.586206896551724) internal successors, (150), 59 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:56,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:19:56,790 INFO L93 Difference]: Finished difference Result 478 states and 553 transitions. [2024-10-15 00:19:56,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 553 transitions. [2024-10-15 00:19:56,793 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:56,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 270 states and 310 transitions. [2024-10-15 00:19:56,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233 [2024-10-15 00:19:56,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233 [2024-10-15 00:19:56,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 310 transitions. [2024-10-15 00:19:56,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:19:56,796 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 310 transitions. [2024-10-15 00:19:56,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 310 transitions. [2024-10-15 00:19:56,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 156. [2024-10-15 00:19:56,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156 states, 156 states have (on average 1.1346153846153846) internal successors, (177), 155 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:19:56,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 177 transitions. [2024-10-15 00:19:56,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156 states and 177 transitions. [2024-10-15 00:19:56,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2024-10-15 00:19:56,800 INFO L425 stractBuchiCegarLoop]: Abstraction has 156 states and 177 transitions. [2024-10-15 00:19:56,800 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-15 00:19:56,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states and 177 transitions. [2024-10-15 00:19:56,801 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:19:56,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:19:56,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:19:56,802 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 18, 17, 17, 1, 1, 1, 1] [2024-10-15 00:19:56,802 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:19:56,802 INFO L745 eck$LassoCheckResult]: Stem: 12237#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 12221#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 12222#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12238#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12239#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12225#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12226#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12276#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12275#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12274#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12273#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12272#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12271#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12270#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12269#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12268#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12267#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12266#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12265#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12264#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12263#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12262#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12261#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12260#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12259#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12258#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12257#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12256#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12255#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12254#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12253#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12252#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12251#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12250#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12249#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12248#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12247#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12244#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 12243#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 12227#L27-4 main_~i~0#1 := 0; 12228#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12234#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12220#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12231#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12236#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12367#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12366#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12364#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12361#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12360#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12358#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12355#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12354#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12352#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12349#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12348#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12346#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12343#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12342#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12340#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12337#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12336#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12334#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12331#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12330#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12328#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12325#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12324#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12322#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12319#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12318#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12316#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12313#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12312#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12310#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12307#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12306#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12304#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12301#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12300#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12298#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12295#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12294#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12292#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12289#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12288#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12286#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12284#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12283#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12280#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12278#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12277#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12242#L34 [2024-10-15 00:19:56,803 INFO L747 eck$LassoCheckResult]: Loop: 12242#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 12245#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 12241#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12242#L34 [2024-10-15 00:19:56,803 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:56,803 INFO L85 PathProgramCache]: Analyzing trace with hash -1155020915, now seen corresponding path program 34 times [2024-10-15 00:19:56,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:56,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932481216] [2024-10-15 00:19:56,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:56,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:56,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:56,896 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:56,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:56,966 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:56,967 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:56,967 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 19 times [2024-10-15 00:19:56,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:56,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309431094] [2024-10-15 00:19:56,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:56,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:56,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:56,971 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:19:56,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:19:56,974 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:19:56,974 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:19:56,974 INFO L85 PathProgramCache]: Analyzing trace with hash 2049943497, now seen corresponding path program 35 times [2024-10-15 00:19:56,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:19:56,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220556099] [2024-10-15 00:19:56,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:19:56,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:19:57,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:19:58,045 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 425 proven. 376 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:58,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:19:58,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220556099] [2024-10-15 00:19:58,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220556099] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:19:58,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1005661860] [2024-10-15 00:19:58,046 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-15 00:19:58,046 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:19:58,046 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:19:58,048 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:19:58,049 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-10-15 00:19:58,607 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2024-10-15 00:19:58,607 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:19:58,611 INFO L255 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 40 conjuncts are in the unsatisfiable core [2024-10-15 00:19:58,613 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:19:59,365 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:59,365 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:19:59,877 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:19:59,877 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1005661860] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:19:59,877 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:19:59,877 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40] total 61 [2024-10-15 00:19:59,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [267554631] [2024-10-15 00:19:59,878 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:19:59,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:19:59,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2024-10-15 00:19:59,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=885, Invalid=2897, Unknown=0, NotChecked=0, Total=3782 [2024-10-15 00:19:59,915 INFO L87 Difference]: Start difference. First operand 156 states and 177 transitions. cyclomatic complexity: 24 Second operand has 62 states, 61 states have (on average 2.5901639344262297) internal successors, (158), 62 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:00,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:20:00,921 INFO L93 Difference]: Finished difference Result 504 states and 583 transitions. [2024-10-15 00:20:00,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 583 transitions. [2024-10-15 00:20:00,923 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:00,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 284 states and 326 transitions. [2024-10-15 00:20:00,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2024-10-15 00:20:00,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2024-10-15 00:20:00,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 326 transitions. [2024-10-15 00:20:00,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:20:00,926 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 326 transitions. [2024-10-15 00:20:00,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 326 transitions. [2024-10-15 00:20:00,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 164. [2024-10-15 00:20:00,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1341463414634145) internal successors, (186), 163 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:00,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 186 transitions. [2024-10-15 00:20:00,930 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 186 transitions. [2024-10-15 00:20:00,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-10-15 00:20:00,931 INFO L425 stractBuchiCegarLoop]: Abstraction has 164 states and 186 transitions. [2024-10-15 00:20:00,931 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-15 00:20:00,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 186 transitions. [2024-10-15 00:20:00,932 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:00,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:20:00,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:20:00,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 19, 18, 18, 1, 1, 1, 1] [2024-10-15 00:20:00,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:20:00,933 INFO L745 eck$LassoCheckResult]: Stem: 13564#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 13548#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 13549#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13565#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13566#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13552#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13553#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13605#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13604#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13603#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13602#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13601#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13600#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13599#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13598#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13597#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13596#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13595#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13594#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13593#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13592#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13591#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13590#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13589#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13588#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13587#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13586#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13585#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13584#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13583#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13582#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13581#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13580#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13579#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13578#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13577#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13576#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13575#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13574#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 13571#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 13570#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 13554#L27-4 main_~i~0#1 := 0; 13555#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13561#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13547#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13558#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13563#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13702#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13701#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13699#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13696#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13695#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13693#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13690#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13689#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13687#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13684#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13683#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13681#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13678#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13677#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13675#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13672#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13671#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13669#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13666#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13665#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13663#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13660#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13659#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13657#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13654#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13653#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13651#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13648#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13647#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13645#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13642#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13641#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13639#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13636#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13635#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13633#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13630#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13629#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13627#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13624#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13623#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13621#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13618#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13617#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13615#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13613#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13612#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13609#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13607#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13606#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13569#L34 [2024-10-15 00:20:00,934 INFO L747 eck$LassoCheckResult]: Loop: 13569#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 13572#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 13568#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13569#L34 [2024-10-15 00:20:00,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:00,934 INFO L85 PathProgramCache]: Analyzing trace with hash -769572217, now seen corresponding path program 36 times [2024-10-15 00:20:00,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:00,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342157330] [2024-10-15 00:20:00,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:00,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:01,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:01,007 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:01,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:01,118 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:01,119 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:01,119 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 20 times [2024-10-15 00:20:01,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:01,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331975762] [2024-10-15 00:20:01,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:01,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:01,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:01,123 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:01,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:01,126 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:01,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:01,127 INFO L85 PathProgramCache]: Analyzing trace with hash 209556111, now seen corresponding path program 37 times [2024-10-15 00:20:01,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:01,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737188410] [2024-10-15 00:20:01,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:01,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:01,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:02,295 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 477 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:02,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:20:02,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737188410] [2024-10-15 00:20:02,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1737188410] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:20:02,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1280120284] [2024-10-15 00:20:02,296 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-15 00:20:02,296 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:20:02,296 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:20:02,297 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:20:02,298 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-10-15 00:20:02,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:02,456 INFO L255 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 42 conjuncts are in the unsatisfiable core [2024-10-15 00:20:02,458 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:20:03,179 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:03,180 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:20:03,759 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:03,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1280120284] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:20:03,760 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:20:03,760 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 64 [2024-10-15 00:20:03,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728463933] [2024-10-15 00:20:03,760 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:20:03,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:20:03,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2024-10-15 00:20:03,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=971, Invalid=3189, Unknown=0, NotChecked=0, Total=4160 [2024-10-15 00:20:03,798 INFO L87 Difference]: Start difference. First operand 164 states and 186 transitions. cyclomatic complexity: 25 Second operand has 65 states, 64 states have (on average 2.59375) internal successors, (166), 65 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:04,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:20:04,704 INFO L93 Difference]: Finished difference Result 530 states and 613 transitions. [2024-10-15 00:20:04,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 530 states and 613 transitions. [2024-10-15 00:20:04,708 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:04,709 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 530 states to 298 states and 342 transitions. [2024-10-15 00:20:04,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 257 [2024-10-15 00:20:04,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 257 [2024-10-15 00:20:04,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298 states and 342 transitions. [2024-10-15 00:20:04,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:20:04,710 INFO L218 hiAutomatonCegarLoop]: Abstraction has 298 states and 342 transitions. [2024-10-15 00:20:04,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states and 342 transitions. [2024-10-15 00:20:04,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 172. [2024-10-15 00:20:04,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 172 states have (on average 1.1337209302325582) internal successors, (195), 171 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:04,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 195 transitions. [2024-10-15 00:20:04,714 INFO L240 hiAutomatonCegarLoop]: Abstraction has 172 states and 195 transitions. [2024-10-15 00:20:04,715 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2024-10-15 00:20:04,715 INFO L425 stractBuchiCegarLoop]: Abstraction has 172 states and 195 transitions. [2024-10-15 00:20:04,715 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-15 00:20:04,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 172 states and 195 transitions. [2024-10-15 00:20:04,716 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:04,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:20:04,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:20:04,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 20, 19, 19, 1, 1, 1, 1] [2024-10-15 00:20:04,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:20:04,718 INFO L745 eck$LassoCheckResult]: Stem: 14960#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 14944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 14945#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14961#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14962#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14948#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14949#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15003#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15002#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 15001#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 15000#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14999#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14998#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14997#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14996#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14995#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14994#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14993#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14992#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14991#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14990#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14989#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14988#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14987#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14986#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14985#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14984#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14983#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14982#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14981#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14980#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14979#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14978#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14977#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14976#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14975#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14974#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14973#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14972#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14971#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14970#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 14967#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 14966#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 14950#L27-4 main_~i~0#1 := 0; 14951#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14957#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14943#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14954#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14959#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15106#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15105#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15103#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15100#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15099#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15097#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15094#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15093#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15091#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15088#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15087#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15085#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15082#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15081#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15079#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15076#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15075#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15073#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15070#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15069#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15067#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15064#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15063#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15061#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15058#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15057#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15055#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15052#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15051#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15049#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15046#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15045#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15043#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15040#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15039#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15037#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15034#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15033#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15031#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15028#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15027#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15025#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15022#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15021#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15019#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15016#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15015#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15013#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15011#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15010#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15007#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 15005#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 15004#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14965#L34 [2024-10-15 00:20:04,718 INFO L747 eck$LassoCheckResult]: Loop: 14965#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 14968#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 14964#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 14965#L34 [2024-10-15 00:20:04,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:04,719 INFO L85 PathProgramCache]: Analyzing trace with hash 297074321, now seen corresponding path program 38 times [2024-10-15 00:20:04,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:04,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885027593] [2024-10-15 00:20:04,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:04,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:04,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:04,828 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:04,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:04,923 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:04,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:04,924 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 21 times [2024-10-15 00:20:04,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:04,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951252525] [2024-10-15 00:20:04,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:04,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:04,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:04,929 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:04,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:04,932 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:04,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:04,932 INFO L85 PathProgramCache]: Analyzing trace with hash -1786453435, now seen corresponding path program 39 times [2024-10-15 00:20:04,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:04,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669238165] [2024-10-15 00:20:04,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:04,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:04,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:06,091 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 532 proven. 458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:06,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:20:06,091 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669238165] [2024-10-15 00:20:06,091 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1669238165] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:20:06,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [898621336] [2024-10-15 00:20:06,092 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-15 00:20:06,092 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:20:06,092 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:20:06,094 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:20:06,097 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-10-15 00:20:07,300 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2024-10-15 00:20:07,301 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:20:07,305 INFO L255 TraceCheckSpWp]: Trace formula consists of 461 conjuncts, 44 conjuncts are in the unsatisfiable core [2024-10-15 00:20:07,308 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:20:08,077 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:08,077 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:20:08,697 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:08,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [898621336] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:20:08,697 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:20:08,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44] total 67 [2024-10-15 00:20:08,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269660881] [2024-10-15 00:20:08,697 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:20:08,728 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:20:08,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2024-10-15 00:20:08,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1061, Invalid=3495, Unknown=0, NotChecked=0, Total=4556 [2024-10-15 00:20:08,731 INFO L87 Difference]: Start difference. First operand 172 states and 195 transitions. cyclomatic complexity: 26 Second operand has 68 states, 67 states have (on average 2.5970149253731343) internal successors, (174), 68 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:09,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:20:09,634 INFO L93 Difference]: Finished difference Result 556 states and 643 transitions. [2024-10-15 00:20:09,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 556 states and 643 transitions. [2024-10-15 00:20:09,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:09,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 556 states to 312 states and 358 transitions. [2024-10-15 00:20:09,637 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 269 [2024-10-15 00:20:09,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 269 [2024-10-15 00:20:09,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 358 transitions. [2024-10-15 00:20:09,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:20:09,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312 states and 358 transitions. [2024-10-15 00:20:09,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 358 transitions. [2024-10-15 00:20:09,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 180. [2024-10-15 00:20:09,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 180 states, 180 states have (on average 1.1333333333333333) internal successors, (204), 179 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:09,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 204 transitions. [2024-10-15 00:20:09,641 INFO L240 hiAutomatonCegarLoop]: Abstraction has 180 states and 204 transitions. [2024-10-15 00:20:09,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2024-10-15 00:20:09,642 INFO L425 stractBuchiCegarLoop]: Abstraction has 180 states and 204 transitions. [2024-10-15 00:20:09,643 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-15 00:20:09,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180 states and 204 transitions. [2024-10-15 00:20:09,643 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:09,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:20:09,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:20:09,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 21, 20, 20, 1, 1, 1, 1] [2024-10-15 00:20:09,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:20:09,645 INFO L745 eck$LassoCheckResult]: Stem: 16425#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 16409#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 16410#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16426#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16427#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16413#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16414#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16470#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16469#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16468#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16467#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16466#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16465#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16464#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16463#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16462#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16461#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16460#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16459#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16458#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16457#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16456#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16455#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16454#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16453#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16452#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16451#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16450#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16449#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16448#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16447#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16446#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16445#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16444#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16443#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16442#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16441#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16440#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16439#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16438#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16437#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16436#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16435#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 16432#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 16431#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 16415#L27-4 main_~i~0#1 := 0; 16416#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16422#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16408#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16419#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16424#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16579#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16578#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16576#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16573#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16572#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16570#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16567#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16566#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16564#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16561#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16560#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16558#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16555#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16554#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16552#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16549#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16548#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16546#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16543#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16542#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16540#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16537#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16536#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16534#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16531#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16530#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16528#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16525#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16524#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16522#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16519#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16518#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16516#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16513#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16512#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16510#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16507#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16506#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16504#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16501#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16500#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16498#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16495#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16494#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16492#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16489#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16488#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16486#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16483#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16482#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16480#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16478#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16477#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16474#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16472#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16471#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16430#L34 [2024-10-15 00:20:09,645 INFO L747 eck$LassoCheckResult]: Loop: 16430#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 16433#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 16429#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16430#L34 [2024-10-15 00:20:09,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:09,645 INFO L85 PathProgramCache]: Analyzing trace with hash -1988450429, now seen corresponding path program 40 times [2024-10-15 00:20:09,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:09,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472320126] [2024-10-15 00:20:09,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:09,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:09,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:09,734 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:09,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:09,825 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:09,826 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:09,826 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 22 times [2024-10-15 00:20:09,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:09,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14131097] [2024-10-15 00:20:09,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:09,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:09,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:09,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:09,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:09,835 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:09,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:09,835 INFO L85 PathProgramCache]: Analyzing trace with hash -1737737197, now seen corresponding path program 41 times [2024-10-15 00:20:09,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:09,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631782792] [2024-10-15 00:20:09,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:09,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:09,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:11,141 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 590 proven. 502 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:11,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:20:11,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631782792] [2024-10-15 00:20:11,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [631782792] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:20:11,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1998884053] [2024-10-15 00:20:11,141 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-15 00:20:11,141 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:20:11,141 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:20:11,143 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:20:11,144 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-10-15 00:20:12,109 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2024-10-15 00:20:12,109 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:20:12,115 INFO L255 TraceCheckSpWp]: Trace formula consists of 482 conjuncts, 46 conjuncts are in the unsatisfiable core [2024-10-15 00:20:12,117 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:20:12,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:12,949 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:20:13,598 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:13,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1998884053] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:20:13,599 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:20:13,599 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46] total 70 [2024-10-15 00:20:13,599 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242210061] [2024-10-15 00:20:13,599 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:20:13,631 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:20:13,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2024-10-15 00:20:13,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1155, Invalid=3815, Unknown=0, NotChecked=0, Total=4970 [2024-10-15 00:20:13,633 INFO L87 Difference]: Start difference. First operand 180 states and 204 transitions. cyclomatic complexity: 27 Second operand has 71 states, 70 states have (on average 2.6) internal successors, (182), 71 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:14,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:20:14,573 INFO L93 Difference]: Finished difference Result 582 states and 673 transitions. [2024-10-15 00:20:14,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 582 states and 673 transitions. [2024-10-15 00:20:14,576 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:14,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 582 states to 326 states and 374 transitions. [2024-10-15 00:20:14,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2024-10-15 00:20:14,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2024-10-15 00:20:14,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 374 transitions. [2024-10-15 00:20:14,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:20:14,579 INFO L218 hiAutomatonCegarLoop]: Abstraction has 326 states and 374 transitions. [2024-10-15 00:20:14,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 374 transitions. [2024-10-15 00:20:14,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 188. [2024-10-15 00:20:14,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188 states, 188 states have (on average 1.1329787234042554) internal successors, (213), 187 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:14,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 213 transitions. [2024-10-15 00:20:14,583 INFO L240 hiAutomatonCegarLoop]: Abstraction has 188 states and 213 transitions. [2024-10-15 00:20:14,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2024-10-15 00:20:14,584 INFO L425 stractBuchiCegarLoop]: Abstraction has 188 states and 213 transitions. [2024-10-15 00:20:14,584 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-15 00:20:14,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188 states and 213 transitions. [2024-10-15 00:20:14,585 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:14,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:20:14,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:20:14,587 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 22, 21, 21, 1, 1, 1, 1] [2024-10-15 00:20:14,587 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:20:14,587 INFO L745 eck$LassoCheckResult]: Stem: 17959#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 17943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 17944#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17960#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17961#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17947#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17948#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18006#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18005#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18004#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18003#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18002#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 18001#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 18000#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17999#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17998#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17997#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17996#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17995#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17994#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17993#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17992#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17991#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17990#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17989#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17988#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17987#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17986#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17985#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17984#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17983#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17982#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17981#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17980#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17979#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17978#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17977#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17976#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17975#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17974#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17973#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17972#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17971#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17970#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17969#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 17966#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 17965#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 17949#L27-4 main_~i~0#1 := 0; 17950#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17956#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17942#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17953#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17958#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18121#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18120#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18118#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18115#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18114#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18112#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18109#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18108#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18106#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18103#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18102#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18100#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18097#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18096#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18094#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18091#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18090#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18088#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18085#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18084#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18082#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18079#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18078#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18076#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18073#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18072#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18070#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18067#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18066#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18064#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18061#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18060#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18058#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18055#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18054#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18052#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18049#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18048#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18046#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18043#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18042#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18040#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18037#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18036#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18034#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18031#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18030#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18028#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18025#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18024#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18022#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18019#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18018#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18016#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18014#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18013#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18010#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 18008#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 18007#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17964#L34 [2024-10-15 00:20:14,587 INFO L747 eck$LassoCheckResult]: Loop: 17964#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 17967#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 17963#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 17964#L34 [2024-10-15 00:20:14,588 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:14,588 INFO L85 PathProgramCache]: Analyzing trace with hash 1779830165, now seen corresponding path program 42 times [2024-10-15 00:20:14,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:14,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718890267] [2024-10-15 00:20:14,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:14,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:14,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:14,735 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:14,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:14,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:14,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:14,841 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 23 times [2024-10-15 00:20:14,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:14,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533668554] [2024-10-15 00:20:14,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:14,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:14,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:14,846 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:14,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:14,849 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:14,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:14,850 INFO L85 PathProgramCache]: Analyzing trace with hash 1549223105, now seen corresponding path program 43 times [2024-10-15 00:20:14,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:14,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970431777] [2024-10-15 00:20:14,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:14,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:14,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:16,266 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 651 proven. 548 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:16,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:20:16,267 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [970431777] [2024-10-15 00:20:16,267 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [970431777] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:20:16,267 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1359775865] [2024-10-15 00:20:16,267 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-15 00:20:16,267 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:20:16,267 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:20:16,269 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:20:16,269 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-10-15 00:20:16,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:16,458 INFO L255 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-10-15 00:20:16,460 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:20:17,370 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:17,370 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:20:18,082 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:18,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1359775865] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:20:18,082 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:20:18,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 73 [2024-10-15 00:20:18,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594456821] [2024-10-15 00:20:18,083 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:20:18,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:20:18,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2024-10-15 00:20:18,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1253, Invalid=4149, Unknown=0, NotChecked=0, Total=5402 [2024-10-15 00:20:18,117 INFO L87 Difference]: Start difference. First operand 188 states and 213 transitions. cyclomatic complexity: 28 Second operand has 74 states, 73 states have (on average 2.6027397260273974) internal successors, (190), 74 states have internal predecessors, (190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:19,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:20:19,136 INFO L93 Difference]: Finished difference Result 608 states and 703 transitions. [2024-10-15 00:20:19,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 608 states and 703 transitions. [2024-10-15 00:20:19,139 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:19,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 608 states to 340 states and 390 transitions. [2024-10-15 00:20:19,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 293 [2024-10-15 00:20:19,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 293 [2024-10-15 00:20:19,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 390 transitions. [2024-10-15 00:20:19,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:20:19,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 390 transitions. [2024-10-15 00:20:19,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 390 transitions. [2024-10-15 00:20:19,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 196. [2024-10-15 00:20:19,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.1326530612244898) internal successors, (222), 195 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:19,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 222 transitions. [2024-10-15 00:20:19,145 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 222 transitions. [2024-10-15 00:20:19,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-10-15 00:20:19,146 INFO L425 stractBuchiCegarLoop]: Abstraction has 196 states and 222 transitions. [2024-10-15 00:20:19,146 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-10-15 00:20:19,146 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 222 transitions. [2024-10-15 00:20:19,147 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:19,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:20:19,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:20:19,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 23, 22, 22, 1, 1, 1, 1] [2024-10-15 00:20:19,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:20:19,149 INFO L745 eck$LassoCheckResult]: Stem: 19562#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 19546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 19547#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19563#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19564#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19550#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19551#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19611#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19610#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19609#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19608#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19607#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19606#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19605#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19604#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19603#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19602#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19601#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19600#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19599#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19598#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19597#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19596#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19595#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19594#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19593#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19592#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19591#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19590#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19589#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19588#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19587#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19586#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19585#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19584#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19583#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19582#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19581#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19580#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19579#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19578#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19577#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19576#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19575#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19574#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19573#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19572#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 19569#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 19568#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 19552#L27-4 main_~i~0#1 := 0; 19553#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19559#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19545#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19556#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19561#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19732#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19731#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19729#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19726#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19725#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19723#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19720#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19719#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19717#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19714#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19713#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19711#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19708#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19705#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19702#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19701#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19699#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19696#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19695#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19693#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19690#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19689#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19687#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19684#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19683#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19681#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19678#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19677#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19675#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19672#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19671#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19669#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19666#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19665#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19663#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19660#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19659#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19657#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19654#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19653#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19651#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19648#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19647#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19645#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19642#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19641#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19639#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19636#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19635#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19633#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19630#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19629#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19627#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19624#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19623#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19621#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19619#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19618#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19615#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19613#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19612#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19567#L34 [2024-10-15 00:20:19,149 INFO L747 eck$LassoCheckResult]: Loop: 19567#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 19570#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 19566#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19567#L34 [2024-10-15 00:20:19,149 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:19,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1359080321, now seen corresponding path program 44 times [2024-10-15 00:20:19,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:19,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336188208] [2024-10-15 00:20:19,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:19,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:19,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:19,293 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:19,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:19,405 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:19,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:19,406 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 24 times [2024-10-15 00:20:19,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:19,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588972303] [2024-10-15 00:20:19,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:19,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:19,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:19,411 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:19,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:19,415 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:19,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:19,416 INFO L85 PathProgramCache]: Analyzing trace with hash 294903191, now seen corresponding path program 45 times [2024-10-15 00:20:19,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:19,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133296232] [2024-10-15 00:20:19,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:19,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:19,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:20,965 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 715 proven. 596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:20,965 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:20:20,965 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1133296232] [2024-10-15 00:20:20,965 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1133296232] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:20:20,965 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [442589068] [2024-10-15 00:20:20,965 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-15 00:20:20,966 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:20:20,966 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:20:20,967 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:20:20,969 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-10-15 00:20:23,288 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2024-10-15 00:20:23,288 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:20:23,295 INFO L255 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 50 conjuncts are in the unsatisfiable core [2024-10-15 00:20:23,297 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:20:24,279 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:24,279 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:20:25,043 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:25,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [442589068] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:20:25,044 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:20:25,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 76 [2024-10-15 00:20:25,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1716354190] [2024-10-15 00:20:25,044 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:20:25,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:20:25,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2024-10-15 00:20:25,085 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1355, Invalid=4497, Unknown=0, NotChecked=0, Total=5852 [2024-10-15 00:20:25,085 INFO L87 Difference]: Start difference. First operand 196 states and 222 transitions. cyclomatic complexity: 29 Second operand has 77 states, 76 states have (on average 2.6052631578947367) internal successors, (198), 77 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:26,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:20:26,256 INFO L93 Difference]: Finished difference Result 634 states and 733 transitions. [2024-10-15 00:20:26,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 634 states and 733 transitions. [2024-10-15 00:20:26,260 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:26,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 634 states to 354 states and 406 transitions. [2024-10-15 00:20:26,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 305 [2024-10-15 00:20:26,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 305 [2024-10-15 00:20:26,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354 states and 406 transitions. [2024-10-15 00:20:26,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:20:26,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 354 states and 406 transitions. [2024-10-15 00:20:26,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states and 406 transitions. [2024-10-15 00:20:26,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 204. [2024-10-15 00:20:26,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 204 states, 204 states have (on average 1.1323529411764706) internal successors, (231), 203 states have internal predecessors, (231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:26,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 231 transitions. [2024-10-15 00:20:26,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 204 states and 231 transitions. [2024-10-15 00:20:26,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2024-10-15 00:20:26,268 INFO L425 stractBuchiCegarLoop]: Abstraction has 204 states and 231 transitions. [2024-10-15 00:20:26,268 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-10-15 00:20:26,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 231 transitions. [2024-10-15 00:20:26,269 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:26,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:20:26,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:20:26,270 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 24, 23, 23, 1, 1, 1, 1] [2024-10-15 00:20:26,270 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:20:26,271 INFO L745 eck$LassoCheckResult]: Stem: 21234#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 21218#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 21219#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21235#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21236#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21222#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21223#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21285#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21284#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21283#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21282#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21281#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21280#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21279#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21278#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21277#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21276#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21275#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21274#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21273#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21272#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21271#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21270#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21269#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21268#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21267#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21265#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21264#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21263#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21262#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21261#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21260#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21259#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21258#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21257#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21256#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21255#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21254#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21253#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21252#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21251#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21250#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21249#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21248#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21247#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21246#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21245#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21244#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 21241#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 21240#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 21224#L27-4 main_~i~0#1 := 0; 21225#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21231#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21217#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21228#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21233#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21412#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21411#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21409#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21406#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21405#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21403#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21400#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21399#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21397#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21394#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21391#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21388#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21387#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21385#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21382#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21381#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21379#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21376#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21375#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21373#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21370#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21369#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21367#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21364#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21363#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21361#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21358#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21357#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21355#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21352#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21351#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21349#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21346#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21345#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21343#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21340#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21339#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21337#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21334#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21333#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21331#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21328#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21327#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21325#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21322#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21321#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21319#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21316#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21315#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21313#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21310#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21309#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21307#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21304#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21303#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21301#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21298#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21297#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21295#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21293#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21292#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21289#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21287#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21286#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21239#L34 [2024-10-15 00:20:26,271 INFO L747 eck$LassoCheckResult]: Loop: 21239#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 21242#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 21238#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21239#L34 [2024-10-15 00:20:26,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:26,272 INFO L85 PathProgramCache]: Analyzing trace with hash -166775655, now seen corresponding path program 46 times [2024-10-15 00:20:26,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:26,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109941710] [2024-10-15 00:20:26,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:26,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:26,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:26,482 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:26,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:26,638 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:26,639 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:26,639 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 25 times [2024-10-15 00:20:26,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:26,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451734790] [2024-10-15 00:20:26,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:26,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:26,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:26,644 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:26,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:26,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:26,653 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:26,654 INFO L85 PathProgramCache]: Analyzing trace with hash 863670077, now seen corresponding path program 47 times [2024-10-15 00:20:26,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:26,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55606059] [2024-10-15 00:20:26,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:26,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:26,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:28,185 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 782 proven. 646 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:28,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:20:28,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55606059] [2024-10-15 00:20:28,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55606059] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:20:28,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1224534548] [2024-10-15 00:20:28,186 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-15 00:20:28,186 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:20:28,186 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:20:28,187 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:20:28,188 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2024-10-15 00:20:29,469 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2024-10-15 00:20:29,470 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-15 00:20:29,477 INFO L255 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 52 conjuncts are in the unsatisfiable core [2024-10-15 00:20:29,480 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:20:30,536 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 852 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:30,537 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:20:31,373 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 852 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:31,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1224534548] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:20:31,374 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:20:31,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52] total 79 [2024-10-15 00:20:31,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026194885] [2024-10-15 00:20:31,374 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:20:31,406 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:20:31,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2024-10-15 00:20:31,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1461, Invalid=4859, Unknown=0, NotChecked=0, Total=6320 [2024-10-15 00:20:31,409 INFO L87 Difference]: Start difference. First operand 204 states and 231 transitions. cyclomatic complexity: 30 Second operand has 80 states, 79 states have (on average 2.607594936708861) internal successors, (206), 80 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:32,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 00:20:32,442 INFO L93 Difference]: Finished difference Result 660 states and 763 transitions. [2024-10-15 00:20:32,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 763 transitions. [2024-10-15 00:20:32,444 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:32,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 368 states and 422 transitions. [2024-10-15 00:20:32,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 317 [2024-10-15 00:20:32,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 317 [2024-10-15 00:20:32,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 422 transitions. [2024-10-15 00:20:32,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 00:20:32,447 INFO L218 hiAutomatonCegarLoop]: Abstraction has 368 states and 422 transitions. [2024-10-15 00:20:32,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 422 transitions. [2024-10-15 00:20:32,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 212. [2024-10-15 00:20:32,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 212 states have (on average 1.1320754716981132) internal successors, (240), 211 states have internal predecessors, (240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 00:20:32,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 240 transitions. [2024-10-15 00:20:32,450 INFO L240 hiAutomatonCegarLoop]: Abstraction has 212 states and 240 transitions. [2024-10-15 00:20:32,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-10-15 00:20:32,451 INFO L425 stractBuchiCegarLoop]: Abstraction has 212 states and 240 transitions. [2024-10-15 00:20:32,452 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-10-15 00:20:32,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 240 transitions. [2024-10-15 00:20:32,453 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-15 00:20:32,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 00:20:32,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 00:20:32,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 25, 24, 24, 1, 1, 1, 1] [2024-10-15 00:20:32,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-15 00:20:32,454 INFO L745 eck$LassoCheckResult]: Stem: 22975#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 22959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 22960#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22976#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22977#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22963#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22964#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23028#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23027#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23026#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23025#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23024#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23023#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23022#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23021#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23020#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23019#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23018#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23017#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23016#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23015#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23014#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23013#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23012#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23011#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23010#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23009#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23008#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23007#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23006#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23005#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23004#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23003#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23002#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 23001#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 23000#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22999#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22998#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22997#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22996#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22995#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22994#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22993#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22992#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22991#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22990#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22989#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22988#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22987#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22986#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22985#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 22982#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 22981#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 22965#L27-4 main_~i~0#1 := 0; 22966#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22972#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22958#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22969#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22974#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23161#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23160#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23158#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23155#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23154#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23152#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23149#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23148#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23146#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23143#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23142#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23140#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23137#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23136#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23134#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23131#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23130#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23128#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23125#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23124#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23122#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23119#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23118#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23116#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23113#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23112#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23110#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23107#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23106#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23104#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23101#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23100#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23098#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23095#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23094#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23092#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23089#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23088#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23086#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23083#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23082#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23080#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23077#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23076#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23074#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23071#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23070#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23068#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23065#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23064#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23062#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23059#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23058#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23056#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23053#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23052#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23050#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23047#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23046#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23044#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23041#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23040#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23038#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23036#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23035#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23032#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 23030#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 23029#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22980#L34 [2024-10-15 00:20:32,454 INFO L747 eck$LassoCheckResult]: Loop: 22980#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 22983#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 22979#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 22980#L34 [2024-10-15 00:20:32,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:32,455 INFO L85 PathProgramCache]: Analyzing trace with hash 1558661499, now seen corresponding path program 48 times [2024-10-15 00:20:32,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:32,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742487802] [2024-10-15 00:20:32,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:32,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:32,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:32,647 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:32,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:32,800 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:32,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:32,801 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 26 times [2024-10-15 00:20:32,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:32,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [231454695] [2024-10-15 00:20:32,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:32,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:32,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:32,806 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 00:20:32,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 00:20:32,809 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 00:20:32,810 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 00:20:32,810 INFO L85 PathProgramCache]: Analyzing trace with hash 1193326363, now seen corresponding path program 49 times [2024-10-15 00:20:32,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 00:20:32,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002845556] [2024-10-15 00:20:32,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 00:20:32,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 00:20:32,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:34,494 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 852 proven. 698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:34,494 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 00:20:34,494 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002845556] [2024-10-15 00:20:34,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002845556] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-15 00:20:34,494 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [237072750] [2024-10-15 00:20:34,494 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-15 00:20:34,495 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-15 00:20:34,495 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 00:20:34,497 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-15 00:20:34,498 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2024-10-15 00:20:34,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 00:20:34,719 INFO L255 TraceCheckSpWp]: Trace formula consists of 566 conjuncts, 54 conjuncts are in the unsatisfiable core [2024-10-15 00:20:34,721 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 00:20:35,853 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 925 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:35,854 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-15 00:20:36,739 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 925 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 00:20:36,739 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [237072750] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-15 00:20:36,739 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-15 00:20:36,739 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54] total 82 [2024-10-15 00:20:36,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42635757] [2024-10-15 00:20:36,739 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-15 00:20:36,770 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 00:20:36,771 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2024-10-15 00:20:36,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1571, Invalid=5235, Unknown=0, NotChecked=0, Total=6806 [2024-10-15 00:20:36,773 INFO L87 Difference]: Start difference. First operand 212 states and 240 transitions. cyclomatic complexity: 31 Second operand has 83 states, 82 states have (on average 2.6097560975609757) internal successors, (214), 83 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)