./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 61a67961 Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.2.5-wip.fs.cvc5-61a6796-m [2024-10-15 01:00:21,388 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-15 01:00:21,478 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-15 01:00:21,485 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-15 01:00:21,487 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-15 01:00:21,526 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-15 01:00:21,527 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-15 01:00:21,528 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-15 01:00:21,529 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-15 01:00:21,530 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-15 01:00:21,530 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-15 01:00:21,531 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-15 01:00:21,531 INFO L153 SettingsManager]: * Use SBE=true [2024-10-15 01:00:21,531 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-15 01:00:21,532 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-15 01:00:21,532 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-15 01:00:21,535 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-15 01:00:21,535 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-15 01:00:21,535 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-15 01:00:21,536 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-15 01:00:21,536 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-15 01:00:21,539 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-15 01:00:21,540 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-15 01:00:21,540 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-15 01:00:21,540 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-15 01:00:21,540 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-15 01:00:21,540 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-15 01:00:21,541 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-15 01:00:21,541 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-15 01:00:21,541 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-15 01:00:21,541 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-15 01:00:21,542 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-15 01:00:21,542 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-15 01:00:21,542 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-15 01:00:21,542 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-15 01:00:21,542 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-15 01:00:21,543 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-15 01:00:21,543 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-15 01:00:21,545 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-15 01:00:21,545 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2024-10-15 01:00:21,795 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-15 01:00:21,823 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-15 01:00:21,826 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-15 01:00:21,828 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-15 01:00:21,828 INFO L274 PluginConnector]: CDTParser initialized [2024-10-15 01:00:21,830 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c [2024-10-15 01:00:23,380 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-15 01:00:23,572 INFO L384 CDTParser]: Found 1 translation units. [2024-10-15 01:00:23,574 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c [2024-10-15 01:00:23,587 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3ff5f917d/d3e094c059e1466b9cedbc03ddda03d7/FLAGcd7befb84 [2024-10-15 01:00:23,957 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3ff5f917d/d3e094c059e1466b9cedbc03ddda03d7 [2024-10-15 01:00:23,959 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-15 01:00:23,961 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-15 01:00:23,963 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-15 01:00:23,963 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-15 01:00:23,967 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-15 01:00:23,968 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 01:00:23" (1/1) ... [2024-10-15 01:00:23,969 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c1e4b4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:23, skipping insertion in model container [2024-10-15 01:00:23,969 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 01:00:23" (1/1) ... [2024-10-15 01:00:24,010 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-15 01:00:24,212 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-15 01:00:24,227 INFO L200 MainTranslator]: Completed pre-run [2024-10-15 01:00:24,266 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-15 01:00:24,294 INFO L204 MainTranslator]: Completed translation [2024-10-15 01:00:24,295 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24 WrapperNode [2024-10-15 01:00:24,295 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-15 01:00:24,296 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-15 01:00:24,297 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-15 01:00:24,297 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-15 01:00:24,305 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,320 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,381 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 57, statements flattened = 741 [2024-10-15 01:00:24,382 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-15 01:00:24,382 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-15 01:00:24,382 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-15 01:00:24,383 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-15 01:00:24,406 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,410 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,421 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,453 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-15 01:00:24,457 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,458 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,473 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,491 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,493 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,500 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,510 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-15 01:00:24,511 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-15 01:00:24,512 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-15 01:00:24,512 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-15 01:00:24,513 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (1/1) ... [2024-10-15 01:00:24,519 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:24,533 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:24,552 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:24,556 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-15 01:00:24,612 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-15 01:00:24,613 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-15 01:00:24,613 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-15 01:00:24,613 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-15 01:00:24,704 INFO L238 CfgBuilder]: Building ICFG [2024-10-15 01:00:24,707 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-15 01:00:25,497 INFO L? ?]: Removed 128 outVars from TransFormulas that were not future-live. [2024-10-15 01:00:25,498 INFO L287 CfgBuilder]: Performing block encoding [2024-10-15 01:00:25,529 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-15 01:00:25,531 INFO L314 CfgBuilder]: Removed 7 assume(true) statements. [2024-10-15 01:00:25,532 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 01:00:25 BoogieIcfgContainer [2024-10-15 01:00:25,532 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-15 01:00:25,533 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-15 01:00:25,534 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-15 01:00:25,540 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-15 01:00:25,541 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 01:00:25,541 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.10 01:00:23" (1/3) ... [2024-10-15 01:00:25,542 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@73c24f1f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 01:00:25, skipping insertion in model container [2024-10-15 01:00:25,542 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 01:00:25,542 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:00:24" (2/3) ... [2024-10-15 01:00:25,543 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@73c24f1f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 01:00:25, skipping insertion in model container [2024-10-15 01:00:25,543 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-15 01:00:25,543 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 01:00:25" (3/3) ... [2024-10-15 01:00:25,546 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2024-10-15 01:00:25,624 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-15 01:00:25,625 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-15 01:00:25,670 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-15 01:00:25,671 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-15 01:00:25,671 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-15 01:00:25,671 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-15 01:00:25,671 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-15 01:00:25,671 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-15 01:00:25,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:25,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2024-10-15 01:00:25,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:25,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:25,781 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:25,782 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:25,782 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-15 01:00:25,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:25,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2024-10-15 01:00:25,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:25,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:25,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:25,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:25,809 INFO L745 eck$LassoCheckResult]: Stem: 192#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 205#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 292#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 178#L281true assume !(1 == ~m_i~0);~m_st~0 := 2; 241#L281-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 35#L286-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 219#L291-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 236#L296-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17#L418true assume !(0 == ~M_E~0); 177#L418-2true assume !(0 == ~T1_E~0); 227#L423-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 239#L428-1true assume !(0 == ~T3_E~0); 223#L433-1true assume !(0 == ~E_1~0); 209#L438-1true assume !(0 == ~E_2~0); 135#L443-1true assume !(0 == ~E_3~0); 130#L448-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96#L197true assume !(1 == ~m_pc~0); 268#L197-2true is_master_triggered_~__retres1~0#1 := 0; 271#L208true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170#is_master_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 247#L510true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7#L510-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 269#L216true assume 1 == ~t1_pc~0; 29#L217true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 125#L227true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8#L518true assume !(0 != activate_threads_~tmp___0~0#1); 143#L518-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278#L235true assume !(1 == ~t2_pc~0); 215#L235-2true is_transmit2_triggered_~__retres1~2#1 := 0; 85#L246true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 256#L526true assume !(0 != activate_threads_~tmp___1~0#1); 267#L526-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75#L254true assume 1 == ~t3_pc~0; 22#L255true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91#L265true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116#L534true assume !(0 != activate_threads_~tmp___2~0#1); 81#L534-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2#L461true assume !(1 == ~M_E~0); 36#L461-2true assume !(1 == ~T1_E~0); 237#L466-1true assume !(1 == ~T2_E~0); 274#L471-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 50#L476-1true assume !(1 == ~E_1~0); 277#L481-1true assume !(1 == ~E_2~0); 157#L486-1true assume !(1 == ~E_3~0); 59#L491-1true assume { :end_inline_reset_delta_events } true; 11#L652-2true [2024-10-15 01:00:25,811 INFO L747 eck$LassoCheckResult]: Loop: 11#L652-2true assume !false; 67#L653true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 162#L393-1true assume false; 114#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 294#L418-3true assume 0 == ~M_E~0;~M_E~0 := 1; 142#L418-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 166#L423-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 137#L428-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 95#L433-3true assume !(0 == ~E_1~0); 186#L438-3true assume 0 == ~E_2~0;~E_2~0 := 1; 193#L443-3true assume 0 == ~E_3~0;~E_3~0 := 1; 3#L448-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195#L197-12true assume 1 == ~m_pc~0; 201#L198-4true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 73#L208-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141#is_master_triggered_returnLabel#5true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10#L510-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 111#L510-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72#L216-12true assume 1 == ~t1_pc~0; 286#L217-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 108#L227-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 243#is_transmit1_triggered_returnLabel#5true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 78#L518-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34#L518-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282#L235-12true assume 1 == ~t2_pc~0; 207#L236-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 257#L246-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79#is_transmit2_triggered_returnLabel#5true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 289#L526-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131#L526-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 250#L254-12true assume 1 == ~t3_pc~0; 25#L255-4true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 134#L265-4true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51#is_transmit3_triggered_returnLabel#5true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 113#L534-12true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 158#L534-14true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74#L461-3true assume 1 == ~M_E~0;~M_E~0 := 2; 295#L461-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 148#L466-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 246#L471-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 69#L476-3true assume 1 == ~E_1~0;~E_1~0 := 2; 139#L481-3true assume !(1 == ~E_2~0); 90#L486-3true assume 1 == ~E_3~0;~E_3~0 := 2; 264#L491-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24#L309-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37#L331-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 259#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 149#L671true assume !(0 == start_simulation_~tmp~3#1); 183#L671-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 296#L309-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 155#L331-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 48#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 234#L626true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 161#L633true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 164#stop_simulation_returnLabel#1true start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 169#L684true assume !(0 != start_simulation_~tmp___0~1#1); 11#L652-2true [2024-10-15 01:00:25,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:25,818 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2024-10-15 01:00:25,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:25,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207820048] [2024-10-15 01:00:25,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:25,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:25,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:26,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:26,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:26,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207820048] [2024-10-15 01:00:26,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207820048] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:26,111 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:26,111 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:26,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749147845] [2024-10-15 01:00:26,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:26,119 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:26,121 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:26,121 INFO L85 PathProgramCache]: Analyzing trace with hash -1698573144, now seen corresponding path program 1 times [2024-10-15 01:00:26,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:26,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937399784] [2024-10-15 01:00:26,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:26,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:26,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:26,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:26,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:26,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937399784] [2024-10-15 01:00:26,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937399784] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:26,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:26,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 01:00:26,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259380540] [2024-10-15 01:00:26,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:26,170 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:26,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:26,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:26,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:26,205 INFO L87 Difference]: Start difference. First operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:26,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:26,244 INFO L93 Difference]: Finished difference Result 294 states and 434 transitions. [2024-10-15 01:00:26,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 294 states and 434 transitions. [2024-10-15 01:00:26,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-10-15 01:00:26,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 294 states to 288 states and 428 transitions. [2024-10-15 01:00:26,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-10-15 01:00:26,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-10-15 01:00:26,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 428 transitions. [2024-10-15 01:00:26,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:26,265 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 428 transitions. [2024-10-15 01:00:26,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 428 transitions. [2024-10-15 01:00:26,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-10-15 01:00:26,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4861111111111112) internal successors, (428), 287 states have internal predecessors, (428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:26,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 428 transitions. [2024-10-15 01:00:26,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 428 transitions. [2024-10-15 01:00:26,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:26,323 INFO L425 stractBuchiCegarLoop]: Abstraction has 288 states and 428 transitions. [2024-10-15 01:00:26,323 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-15 01:00:26,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 428 transitions. [2024-10-15 01:00:26,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-10-15 01:00:26,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:26,327 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:26,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:26,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:26,331 INFO L745 eck$LassoCheckResult]: Stem: 857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 867#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 841#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 842#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 668#L286-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 669#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 874#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 628#L418 assume !(0 == ~M_E~0); 629#L418-2 assume !(0 == ~T1_E~0); 840#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 877#L428-1 assume !(0 == ~T3_E~0); 875#L433-1 assume !(0 == ~E_1~0); 869#L438-1 assume !(0 == ~E_2~0); 806#L443-1 assume !(0 == ~E_3~0); 800#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 767#L197 assume !(1 == ~m_pc~0); 764#L197-2 is_master_triggered_~__retres1~0#1 := 0; 763#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 833#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 834#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 607#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608#L216 assume 1 == ~t1_pc~0; 656#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 657#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 609#L518 assume !(0 != activate_threads_~tmp___0~0#1); 610#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 814#L235 assume !(1 == ~t2_pc~0); 871#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 752#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 753#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 882#L526 assume !(0 != activate_threads_~tmp___1~0#1); 883#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 735#L254 assume 1 == ~t3_pc~0; 638#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 639#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 620#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 621#L534 assume !(0 != activate_threads_~tmp___2~0#1); 746#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 599#L461 assume !(1 == ~M_E~0); 600#L461-2 assume !(1 == ~T1_E~0); 670#L466-1 assume !(1 == ~T2_E~0); 880#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 696#L476-1 assume !(1 == ~E_1~0); 697#L481-1 assume !(1 == ~E_2~0); 828#L486-1 assume !(1 == ~E_3~0); 711#L491-1 assume { :end_inline_reset_delta_events } true; 618#L652-2 [2024-10-15 01:00:26,331 INFO L747 eck$LassoCheckResult]: Loop: 618#L652-2 assume !false; 619#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 688#L393-1 assume !false; 685#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 686#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 664#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 622#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 623#L346 assume !(0 != eval_~tmp~0#1); 716#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 818#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 811#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 812#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 809#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 765#L433-3 assume !(0 == ~E_1~0); 766#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 853#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 601#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602#L197-12 assume 1 == ~m_pc~0; 859#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 731#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 732#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 615#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728#L216-12 assume !(1 == ~t1_pc~0); 729#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 781#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 782#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 741#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 666#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 667#L235-12 assume 1 == ~t2_pc~0; 868#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 750#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 742#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 743#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 801#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 802#L254-12 assume 1 == ~t3_pc~0; 647#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 648#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 694#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 695#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 786#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 733#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 734#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 819#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 820#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 725#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 726#L481-3 assume !(1 == ~E_2~0); 757#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 758#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 641#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 642#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 671#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 821#L671 assume !(0 == start_simulation_~tmp~3#1); 625#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 846#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 723#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 691#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 692#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 829#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 830#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 831#L684 assume !(0 != start_simulation_~tmp___0~1#1); 618#L652-2 [2024-10-15 01:00:26,332 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:26,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2024-10-15 01:00:26,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:26,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273348371] [2024-10-15 01:00:26,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:26,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:26,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:26,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:26,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:26,409 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273348371] [2024-10-15 01:00:26,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [273348371] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:26,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:26,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:26,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87799564] [2024-10-15 01:00:26,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:26,412 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:26,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:26,413 INFO L85 PathProgramCache]: Analyzing trace with hash 1274205792, now seen corresponding path program 1 times [2024-10-15 01:00:26,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:26,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190364780] [2024-10-15 01:00:26,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:26,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:26,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:26,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:26,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:26,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190364780] [2024-10-15 01:00:26,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190364780] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:26,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:26,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:26,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333598998] [2024-10-15 01:00:26,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:26,573 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:26,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:26,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:26,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:26,575 INFO L87 Difference]: Start difference. First operand 288 states and 428 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:26,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:26,601 INFO L93 Difference]: Finished difference Result 288 states and 427 transitions. [2024-10-15 01:00:26,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 427 transitions. [2024-10-15 01:00:26,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-10-15 01:00:26,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 427 transitions. [2024-10-15 01:00:26,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-10-15 01:00:26,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-10-15 01:00:26,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 427 transitions. [2024-10-15 01:00:26,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:26,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 427 transitions. [2024-10-15 01:00:26,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 427 transitions. [2024-10-15 01:00:26,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-10-15 01:00:26,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4826388888888888) internal successors, (427), 287 states have internal predecessors, (427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:26,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 427 transitions. [2024-10-15 01:00:26,631 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 427 transitions. [2024-10-15 01:00:26,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:26,633 INFO L425 stractBuchiCegarLoop]: Abstraction has 288 states and 427 transitions. [2024-10-15 01:00:26,633 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-15 01:00:26,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 427 transitions. [2024-10-15 01:00:26,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-10-15 01:00:26,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:26,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:26,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:26,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:26,637 INFO L745 eck$LassoCheckResult]: Stem: 1440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1450#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1424#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1425#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1251#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1252#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1457#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1214#L418 assume !(0 == ~M_E~0); 1215#L418-2 assume !(0 == ~T1_E~0); 1423#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1460#L428-1 assume !(0 == ~T3_E~0); 1458#L433-1 assume !(0 == ~E_1~0); 1452#L438-1 assume !(0 == ~E_2~0); 1389#L443-1 assume !(0 == ~E_3~0); 1383#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1350#L197 assume !(1 == ~m_pc~0); 1347#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1346#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1416#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1417#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1190#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1191#L216 assume 1 == ~t1_pc~0; 1239#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1240#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1276#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1192#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1193#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1398#L235 assume !(1 == ~t2_pc~0); 1456#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1335#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1465#L526 assume !(0 != activate_threads_~tmp___1~0#1); 1466#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1318#L254 assume 1 == ~t3_pc~0; 1221#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1222#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1203#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1204#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1329#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182#L461 assume !(1 == ~M_E~0); 1183#L461-2 assume !(1 == ~T1_E~0); 1253#L466-1 assume !(1 == ~T2_E~0); 1463#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1279#L476-1 assume !(1 == ~E_1~0); 1280#L481-1 assume !(1 == ~E_2~0); 1411#L486-1 assume !(1 == ~E_3~0); 1298#L491-1 assume { :end_inline_reset_delta_events } true; 1201#L652-2 [2024-10-15 01:00:26,639 INFO L747 eck$LassoCheckResult]: Loop: 1201#L652-2 assume !false; 1202#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1271#L393-1 assume !false; 1268#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1269#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1247#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1205#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1206#L346 assume !(0 != eval_~tmp~0#1); 1299#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1370#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1394#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1395#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1392#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1348#L433-3 assume !(0 == ~E_1~0); 1349#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1436#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1184#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1185#L197-12 assume 1 == ~m_pc~0; 1442#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1314#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1315#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1197#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1198#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1311#L216-12 assume !(1 == ~t1_pc~0); 1312#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1364#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1365#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1322#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1249#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1250#L235-12 assume !(1 == ~t2_pc~0); 1332#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1333#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1325#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1326#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1384#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1385#L254-12 assume !(1 == ~t3_pc~0); 1232#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 1231#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1277#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1278#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1369#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1317#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1402#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1403#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1308#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1309#L481-3 assume !(1 == ~E_2~0); 1340#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1341#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1224#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1225#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1254#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1404#L671 assume !(0 == start_simulation_~tmp~3#1); 1208#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1429#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1306#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1274#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1275#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1412#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1413#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1414#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1201#L652-2 [2024-10-15 01:00:26,639 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:26,642 INFO L85 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2024-10-15 01:00:26,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:26,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412769394] [2024-10-15 01:00:26,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:26,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:26,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:26,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:26,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:26,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412769394] [2024-10-15 01:00:26,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412769394] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:26,714 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:26,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:26,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621004088] [2024-10-15 01:00:26,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:26,714 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:26,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:26,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1463002402, now seen corresponding path program 1 times [2024-10-15 01:00:26,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:26,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936266368] [2024-10-15 01:00:26,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:26,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:26,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:26,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:26,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:26,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936266368] [2024-10-15 01:00:26,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936266368] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:26,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:26,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:26,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577673699] [2024-10-15 01:00:26,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:26,798 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:26,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:26,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:26,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:26,800 INFO L87 Difference]: Start difference. First operand 288 states and 427 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:26,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:26,826 INFO L93 Difference]: Finished difference Result 288 states and 426 transitions. [2024-10-15 01:00:26,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 426 transitions. [2024-10-15 01:00:26,829 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-10-15 01:00:26,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 426 transitions. [2024-10-15 01:00:26,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-10-15 01:00:26,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-10-15 01:00:26,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 426 transitions. [2024-10-15 01:00:26,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:26,841 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 426 transitions. [2024-10-15 01:00:26,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 426 transitions. [2024-10-15 01:00:26,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-10-15 01:00:26,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4791666666666667) internal successors, (426), 287 states have internal predecessors, (426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:26,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 426 transitions. [2024-10-15 01:00:26,860 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 426 transitions. [2024-10-15 01:00:26,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:26,862 INFO L425 stractBuchiCegarLoop]: Abstraction has 288 states and 426 transitions. [2024-10-15 01:00:26,863 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-15 01:00:26,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 426 transitions. [2024-10-15 01:00:26,866 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-10-15 01:00:26,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:26,866 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:26,867 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:26,868 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:26,869 INFO L745 eck$LassoCheckResult]: Stem: 2023#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2024#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2032#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2007#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2008#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1834#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1835#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2040#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1799#L418 assume !(0 == ~M_E~0); 1800#L418-2 assume !(0 == ~T1_E~0); 2006#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2043#L428-1 assume !(0 == ~T3_E~0); 2041#L433-1 assume !(0 == ~E_1~0); 2035#L438-1 assume !(0 == ~E_2~0); 1972#L443-1 assume !(0 == ~E_3~0); 1966#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1933#L197 assume !(1 == ~m_pc~0); 1930#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1929#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1999#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2000#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1773#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1774#L216 assume 1 == ~t1_pc~0; 1822#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1823#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1859#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1778#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1779#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1981#L235 assume !(1 == ~t2_pc~0); 2039#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1918#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2048#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2049#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1904#L254 assume 1 == ~t3_pc~0; 1804#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1805#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1788#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1789#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1912#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1765#L461 assume !(1 == ~M_E~0); 1766#L461-2 assume !(1 == ~T1_E~0); 1836#L466-1 assume !(1 == ~T2_E~0); 2046#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1862#L476-1 assume !(1 == ~E_1~0); 1863#L481-1 assume !(1 == ~E_2~0); 1994#L486-1 assume !(1 == ~E_3~0); 1881#L491-1 assume { :end_inline_reset_delta_events } true; 1784#L652-2 [2024-10-15 01:00:26,870 INFO L747 eck$LassoCheckResult]: Loop: 1784#L652-2 assume !false; 1785#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1852#L393-1 assume !false; 1855#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1856#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1830#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L346 assume !(0 != eval_~tmp~0#1); 1882#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1953#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1984#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1977#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1978#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1973#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1931#L433-3 assume !(0 == ~E_1~0); 1932#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2017#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1767#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1768#L197-12 assume 1 == ~m_pc~0; 2025#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1897#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1898#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1780#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1781#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1894#L216-12 assume !(1 == ~t1_pc~0); 1895#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1947#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1948#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1907#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1832#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1833#L235-12 assume 1 == ~t2_pc~0; 2034#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1916#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1908#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1909#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1967#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1968#L254-12 assume 1 == ~t3_pc~0; 1813#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1814#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1860#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1861#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1952#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1899#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1900#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1985#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1986#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1891#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1892#L481-3 assume !(1 == ~E_2~0); 1923#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1924#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1810#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1811#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1837#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1987#L671 assume !(0 == start_simulation_~tmp~3#1); 1793#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2012#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1889#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1858#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1995#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1996#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1997#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1784#L652-2 [2024-10-15 01:00:26,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:26,873 INFO L85 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2024-10-15 01:00:26,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:26,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584563067] [2024-10-15 01:00:26,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:26,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:26,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:26,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:26,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:26,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1584563067] [2024-10-15 01:00:26,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1584563067] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:26,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:26,970 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 01:00:26,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [358701666] [2024-10-15 01:00:26,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:26,972 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:26,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:26,973 INFO L85 PathProgramCache]: Analyzing trace with hash 1274205792, now seen corresponding path program 2 times [2024-10-15 01:00:26,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:26,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823443780] [2024-10-15 01:00:26,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:26,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823443780] [2024-10-15 01:00:27,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823443780] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:27,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396746736] [2024-10-15 01:00:27,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,088 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:27,088 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:27,089 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:27,089 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:27,089 INFO L87 Difference]: Start difference. First operand 288 states and 426 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:27,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:27,109 INFO L93 Difference]: Finished difference Result 288 states and 421 transitions. [2024-10-15 01:00:27,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 421 transitions. [2024-10-15 01:00:27,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-10-15 01:00:27,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 421 transitions. [2024-10-15 01:00:27,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-10-15 01:00:27,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-10-15 01:00:27,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 421 transitions. [2024-10-15 01:00:27,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:27,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 421 transitions. [2024-10-15 01:00:27,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 421 transitions. [2024-10-15 01:00:27,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-10-15 01:00:27,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4618055555555556) internal successors, (421), 287 states have internal predecessors, (421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:27,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 421 transitions. [2024-10-15 01:00:27,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 421 transitions. [2024-10-15 01:00:27,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:27,125 INFO L425 stractBuchiCegarLoop]: Abstraction has 288 states and 421 transitions. [2024-10-15 01:00:27,126 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-15 01:00:27,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 421 transitions. [2024-10-15 01:00:27,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-10-15 01:00:27,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:27,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:27,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:27,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:27,130 INFO L745 eck$LassoCheckResult]: Stem: 2606#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2607#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2590#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2591#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2417#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2418#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2623#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2377#L418 assume !(0 == ~M_E~0); 2378#L418-2 assume !(0 == ~T1_E~0); 2589#L423-1 assume !(0 == ~T2_E~0); 2626#L428-1 assume !(0 == ~T3_E~0); 2624#L433-1 assume !(0 == ~E_1~0); 2618#L438-1 assume !(0 == ~E_2~0); 2555#L443-1 assume !(0 == ~E_3~0); 2549#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2516#L197 assume !(1 == ~m_pc~0); 2513#L197-2 is_master_triggered_~__retres1~0#1 := 0; 2512#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2582#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2583#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2356#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2357#L216 assume 1 == ~t1_pc~0; 2405#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2406#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2442#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2358#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2359#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562#L235 assume !(1 == ~t2_pc~0); 2620#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2500#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2631#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2632#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2484#L254 assume 1 == ~t3_pc~0; 2387#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2388#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2370#L534 assume !(0 != activate_threads_~tmp___2~0#1); 2495#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2348#L461 assume !(1 == ~M_E~0); 2349#L461-2 assume !(1 == ~T1_E~0); 2419#L466-1 assume !(1 == ~T2_E~0); 2629#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2443#L476-1 assume !(1 == ~E_1~0); 2444#L481-1 assume !(1 == ~E_2~0); 2577#L486-1 assume !(1 == ~E_3~0); 2460#L491-1 assume { :end_inline_reset_delta_events } true; 2365#L652-2 [2024-10-15 01:00:27,130 INFO L747 eck$LassoCheckResult]: Loop: 2365#L652-2 assume !false; 2366#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2437#L393-1 assume !false; 2434#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2435#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2413#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2371#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2372#L346 assume !(0 != eval_~tmp~0#1); 2465#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2567#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2560#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2561#L423-3 assume !(0 == ~T2_E~0); 2556#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2514#L433-3 assume !(0 == ~E_1~0); 2515#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2600#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2350#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2351#L197-12 assume 1 == ~m_pc~0; 2608#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2480#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2481#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2363#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2364#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2477#L216-12 assume !(1 == ~t1_pc~0); 2478#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 2530#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2531#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2490#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2415#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2416#L235-12 assume !(1 == ~t2_pc~0); 2498#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 2499#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2491#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2492#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2550#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2551#L254-12 assume 1 == ~t3_pc~0; 2396#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2397#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2445#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2446#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2535#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2482#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2483#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2568#L466-3 assume !(1 == ~T2_E~0); 2569#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2474#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2475#L481-3 assume !(1 == ~E_2~0); 2506#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2507#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2393#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2394#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2570#L671 assume !(0 == start_simulation_~tmp~3#1); 2376#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2595#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2472#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2440#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 2441#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2578#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2579#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2580#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2365#L652-2 [2024-10-15 01:00:27,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:27,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2024-10-15 01:00:27,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:27,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845644451] [2024-10-15 01:00:27,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:27,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845644451] [2024-10-15 01:00:27,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1845644451] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,230 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 01:00:27,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052971365] [2024-10-15 01:00:27,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,230 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:27,231 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:27,231 INFO L85 PathProgramCache]: Analyzing trace with hash -282044549, now seen corresponding path program 1 times [2024-10-15 01:00:27,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:27,232 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [289546219] [2024-10-15 01:00:27,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:27,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [289546219] [2024-10-15 01:00:27,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [289546219] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:27,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442298504] [2024-10-15 01:00:27,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,275 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:27,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:27,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 01:00:27,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-15 01:00:27,276 INFO L87 Difference]: Start difference. First operand 288 states and 421 transitions. cyclomatic complexity: 134 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:27,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:27,417 INFO L93 Difference]: Finished difference Result 306 states and 439 transitions. [2024-10-15 01:00:27,417 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 306 states and 439 transitions. [2024-10-15 01:00:27,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 250 [2024-10-15 01:00:27,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 306 states to 306 states and 439 transitions. [2024-10-15 01:00:27,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 306 [2024-10-15 01:00:27,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 306 [2024-10-15 01:00:27,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 306 states and 439 transitions. [2024-10-15 01:00:27,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:27,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 306 states and 439 transitions. [2024-10-15 01:00:27,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states and 439 transitions. [2024-10-15 01:00:27,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 306. [2024-10-15 01:00:27,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 306 states, 306 states have (on average 1.434640522875817) internal successors, (439), 305 states have internal predecessors, (439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:27,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306 states to 306 states and 439 transitions. [2024-10-15 01:00:27,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 306 states and 439 transitions. [2024-10-15 01:00:27,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 01:00:27,433 INFO L425 stractBuchiCegarLoop]: Abstraction has 306 states and 439 transitions. [2024-10-15 01:00:27,433 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-15 01:00:27,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 306 states and 439 transitions. [2024-10-15 01:00:27,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 250 [2024-10-15 01:00:27,436 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:27,436 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:27,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:27,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:27,439 INFO L745 eck$LassoCheckResult]: Stem: 3211#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3222#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3220#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 3196#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3020#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3021#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3229#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2980#L418 assume !(0 == ~M_E~0); 2981#L418-2 assume !(0 == ~T1_E~0); 3194#L423-1 assume !(0 == ~T2_E~0); 3232#L428-1 assume !(0 == ~T3_E~0); 3230#L433-1 assume !(0 == ~E_1~0); 3224#L438-1 assume !(0 == ~E_2~0); 3159#L443-1 assume !(0 == ~E_3~0); 3153#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3119#L197 assume !(1 == ~m_pc~0); 3116#L197-2 is_master_triggered_~__retres1~0#1 := 0; 3243#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3187#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3188#L510 assume !(0 != activate_threads_~tmp~1#1); 2959#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2960#L216 assume 1 == ~t1_pc~0; 3008#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3009#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3045#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2961#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2962#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3166#L235 assume !(1 == ~t2_pc~0); 3226#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3103#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3104#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3237#L526 assume !(0 != activate_threads_~tmp___1~0#1); 3238#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3087#L254 assume 1 == ~t3_pc~0; 2990#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2991#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2972#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2973#L534 assume !(0 != activate_threads_~tmp___2~0#1); 3098#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2951#L461 assume !(1 == ~M_E~0); 2952#L461-2 assume !(1 == ~T1_E~0); 3022#L466-1 assume !(1 == ~T2_E~0); 3235#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3046#L476-1 assume !(1 == ~E_1~0); 3047#L481-1 assume !(1 == ~E_2~0); 3182#L486-1 assume !(1 == ~E_3~0); 3063#L491-1 assume { :end_inline_reset_delta_events } true; 2968#L652-2 [2024-10-15 01:00:27,439 INFO L747 eck$LassoCheckResult]: Loop: 2968#L652-2 assume !false; 2969#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3040#L393-1 assume !false; 3037#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3038#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3016#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2974#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2975#L346 assume !(0 != eval_~tmp~0#1); 3068#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3139#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3171#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3164#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3165#L423-3 assume !(0 == ~T2_E~0); 3160#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3117#L433-3 assume !(0 == ~E_1~0); 3118#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3205#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2953#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2954#L197-12 assume 1 == ~m_pc~0; 3213#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3221#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3248#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3247#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2967#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3080#L216-12 assume !(1 == ~t1_pc~0); 3081#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 3133#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3134#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3093#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3018#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3019#L235-12 assume 1 == ~t2_pc~0; 3223#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3102#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3094#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3095#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3154#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3155#L254-12 assume 1 == ~t3_pc~0; 2999#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3000#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3048#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3049#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3138#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3085#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3086#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3172#L466-3 assume !(1 == ~T2_E~0); 3173#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3077#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3078#L481-3 assume !(1 == ~E_2~0); 3109#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3110#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2996#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2997#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3023#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3174#L671 assume !(0 == start_simulation_~tmp~3#1); 2979#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3200#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3075#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3043#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3044#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3183#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3184#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3185#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2968#L652-2 [2024-10-15 01:00:27,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:27,442 INFO L85 PathProgramCache]: Analyzing trace with hash 738198194, now seen corresponding path program 1 times [2024-10-15 01:00:27,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:27,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415999606] [2024-10-15 01:00:27,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:27,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415999606] [2024-10-15 01:00:27,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415999606] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 01:00:27,525 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802628118] [2024-10-15 01:00:27,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,526 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:27,526 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:27,526 INFO L85 PathProgramCache]: Analyzing trace with hash -1201019172, now seen corresponding path program 1 times [2024-10-15 01:00:27,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:27,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721407067] [2024-10-15 01:00:27,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:27,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,565 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1721407067] [2024-10-15 01:00:27,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1721407067] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,565 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,565 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:27,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250668930] [2024-10-15 01:00:27,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,566 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:27,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:27,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:27,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:27,567 INFO L87 Difference]: Start difference. First operand 306 states and 439 transitions. cyclomatic complexity: 134 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:27,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:27,611 INFO L93 Difference]: Finished difference Result 517 states and 735 transitions. [2024-10-15 01:00:27,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 517 states and 735 transitions. [2024-10-15 01:00:27,615 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 460 [2024-10-15 01:00:27,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 517 states to 517 states and 735 transitions. [2024-10-15 01:00:27,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 517 [2024-10-15 01:00:27,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 517 [2024-10-15 01:00:27,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 517 states and 735 transitions. [2024-10-15 01:00:27,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:27,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 517 states and 735 transitions. [2024-10-15 01:00:27,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states and 735 transitions. [2024-10-15 01:00:27,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 515. [2024-10-15 01:00:27,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 515 states, 515 states have (on average 1.4233009708737865) internal successors, (733), 514 states have internal predecessors, (733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:27,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 515 states to 515 states and 733 transitions. [2024-10-15 01:00:27,630 INFO L240 hiAutomatonCegarLoop]: Abstraction has 515 states and 733 transitions. [2024-10-15 01:00:27,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:27,633 INFO L425 stractBuchiCegarLoop]: Abstraction has 515 states and 733 transitions. [2024-10-15 01:00:27,633 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-15 01:00:27,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 515 states and 733 transitions. [2024-10-15 01:00:27,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2024-10-15 01:00:27,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:27,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:27,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:27,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:27,641 INFO L745 eck$LassoCheckResult]: Stem: 4049#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4061#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4059#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4033#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 4034#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3849#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3850#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4068#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3810#L418 assume !(0 == ~M_E~0); 3811#L418-2 assume !(0 == ~T1_E~0); 4032#L423-1 assume !(0 == ~T2_E~0); 4072#L428-1 assume !(0 == ~T3_E~0); 4070#L433-1 assume !(0 == ~E_1~0); 4063#L438-1 assume !(0 == ~E_2~0); 3991#L443-1 assume !(0 == ~E_3~0); 3985#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3950#L197 assume !(1 == ~m_pc~0); 3947#L197-2 is_master_triggered_~__retres1~0#1 := 0; 4088#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4023#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4024#L510 assume !(0 != activate_threads_~tmp~1#1); 3789#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3790#L216 assume !(1 == ~t1_pc~0); 3845#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3846#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3874#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3791#L518 assume !(0 != activate_threads_~tmp___0~0#1); 3792#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3998#L235 assume !(1 == ~t2_pc~0); 4065#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3934#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3935#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4082#L526 assume !(0 != activate_threads_~tmp___1~0#1); 4083#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3918#L254 assume 1 == ~t3_pc~0; 3821#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3822#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3802#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3803#L534 assume !(0 != activate_threads_~tmp___2~0#1); 3929#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3781#L461 assume !(1 == ~M_E~0); 3782#L461-2 assume !(1 == ~T1_E~0); 3851#L466-1 assume !(1 == ~T2_E~0); 4076#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3875#L476-1 assume !(1 == ~E_1~0); 3876#L481-1 assume !(1 == ~E_2~0); 4016#L486-1 assume !(1 == ~E_3~0); 3892#L491-1 assume { :end_inline_reset_delta_events } true; 3893#L652-2 [2024-10-15 01:00:27,645 INFO L747 eck$LassoCheckResult]: Loop: 3893#L652-2 assume !false; 4226#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4224#L393-1 assume !false; 4221#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4211#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4028#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3804#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3805#L346 assume !(0 != eval_~tmp~0#1); 4138#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4136#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4135#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4133#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4131#L423-3 assume !(0 == ~T2_E~0); 3992#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3948#L433-3 assume !(0 == ~E_1~0); 3949#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4043#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3783#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3784#L197-12 assume 1 == ~m_pc~0; 4051#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4060#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4158#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4156#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3797#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3912#L216-12 assume !(1 == ~t1_pc~0); 3913#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 3964#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3965#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3922#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3847#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3848#L235-12 assume !(1 == ~t2_pc~0); 3932#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 3933#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3925#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3926#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3986#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3987#L254-12 assume 1 == ~t3_pc~0; 3829#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3830#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3877#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3878#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3969#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3916#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3917#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4004#L466-3 assume !(1 == ~T2_E~0); 4005#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3909#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3910#L481-3 assume !(1 == ~E_2~0); 3940#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3941#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3826#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3827#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3852#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4006#L671 assume !(0 == start_simulation_~tmp~3#1); 4007#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4266#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4263#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4262#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 4261#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4260#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4259#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4258#L684 assume !(0 != start_simulation_~tmp___0~1#1); 3893#L652-2 [2024-10-15 01:00:27,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:27,646 INFO L85 PathProgramCache]: Analyzing trace with hash 1376982673, now seen corresponding path program 1 times [2024-10-15 01:00:27,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:27,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712762124] [2024-10-15 01:00:27,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:27,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,712 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1712762124] [2024-10-15 01:00:27,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1712762124] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,712 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 01:00:27,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470118535] [2024-10-15 01:00:27,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,713 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:27,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:27,714 INFO L85 PathProgramCache]: Analyzing trace with hash -282044549, now seen corresponding path program 2 times [2024-10-15 01:00:27,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:27,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473422451] [2024-10-15 01:00:27,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:27,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473422451] [2024-10-15 01:00:27,755 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473422451] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,755 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,755 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:27,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111285941] [2024-10-15 01:00:27,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,756 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:27,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:27,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:27,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:27,757 INFO L87 Difference]: Start difference. First operand 515 states and 733 transitions. cyclomatic complexity: 220 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:27,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:27,801 INFO L93 Difference]: Finished difference Result 961 states and 1352 transitions. [2024-10-15 01:00:27,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 961 states and 1352 transitions. [2024-10-15 01:00:27,809 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 901 [2024-10-15 01:00:27,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 961 states to 961 states and 1352 transitions. [2024-10-15 01:00:27,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 961 [2024-10-15 01:00:27,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 961 [2024-10-15 01:00:27,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 961 states and 1352 transitions. [2024-10-15 01:00:27,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:27,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 961 states and 1352 transitions. [2024-10-15 01:00:27,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 961 states and 1352 transitions. [2024-10-15 01:00:27,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 961 to 957. [2024-10-15 01:00:27,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.4085684430512018) internal successors, (1348), 956 states have internal predecessors, (1348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:27,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1348 transitions. [2024-10-15 01:00:27,842 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1348 transitions. [2024-10-15 01:00:27,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:27,844 INFO L425 stractBuchiCegarLoop]: Abstraction has 957 states and 1348 transitions. [2024-10-15 01:00:27,845 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-15 01:00:27,845 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1348 transitions. [2024-10-15 01:00:27,850 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-10-15 01:00:27,850 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:27,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:27,851 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:27,852 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:27,852 INFO L745 eck$LassoCheckResult]: Stem: 5532#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 5533#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5543#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5514#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 5515#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5328#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5329#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5556#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5293#L418 assume !(0 == ~M_E~0); 5294#L418-2 assume !(0 == ~T1_E~0); 5513#L423-1 assume !(0 == ~T2_E~0); 5560#L428-1 assume !(0 == ~T3_E~0); 5558#L433-1 assume !(0 == ~E_1~0); 5547#L438-1 assume !(0 == ~E_2~0); 5473#L443-1 assume !(0 == ~E_3~0); 5466#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5429#L197 assume !(1 == ~m_pc~0); 5426#L197-2 is_master_triggered_~__retres1~0#1 := 0; 5576#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5506#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5507#L510 assume !(0 != activate_threads_~tmp~1#1); 5272#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5273#L216 assume !(1 == ~t1_pc~0); 5324#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5325#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5355#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5274#L518 assume !(0 != activate_threads_~tmp___0~0#1); 5275#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5481#L235 assume !(1 == ~t2_pc~0); 5553#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5413#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5414#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5570#L526 assume !(0 != activate_threads_~tmp___1~0#1); 5571#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5397#L254 assume !(1 == ~t3_pc~0); 5332#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5333#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5285#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5286#L534 assume !(0 != activate_threads_~tmp___2~0#1); 5408#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5264#L461 assume !(1 == ~M_E~0); 5265#L461-2 assume !(1 == ~T1_E~0); 5330#L466-1 assume !(1 == ~T2_E~0); 5563#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5356#L476-1 assume !(1 == ~E_1~0); 5357#L481-1 assume !(1 == ~E_2~0); 5497#L486-1 assume !(1 == ~E_3~0); 5373#L491-1 assume { :end_inline_reset_delta_events } true; 5281#L652-2 [2024-10-15 01:00:27,852 INFO L747 eck$LassoCheckResult]: Loop: 5281#L652-2 assume !false; 5282#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5350#L393-1 assume !false; 5347#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5348#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5322#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5287#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5288#L346 assume !(0 != eval_~tmp~0#1); 5378#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6206#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6204#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6202#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6200#L423-3 assume !(0 == ~T2_E~0); 6197#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6195#L433-3 assume !(0 == ~E_1~0); 6194#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6193#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6192#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6191#L197-12 assume 1 == ~m_pc~0; 6189#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6187#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6184#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6181#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6180#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5391#L216-12 assume !(1 == ~t1_pc~0); 5392#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 5443#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5444#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5401#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5326#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5327#L235-12 assume !(1 == ~t2_pc~0); 5411#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 5412#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5404#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5405#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5467#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5468#L254-12 assume !(1 == ~t3_pc~0); 5565#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 5472#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5358#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5359#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5449#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5395#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5396#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5486#L466-3 assume !(1 == ~T2_E~0); 5487#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5388#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5389#L481-3 assume !(1 == ~E_2~0); 5419#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5420#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5305#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5306#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5331#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5488#L671 assume !(0 == start_simulation_~tmp~3#1); 5292#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5520#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5386#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5353#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 5354#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5502#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5503#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 5504#L684 assume !(0 != start_simulation_~tmp___0~1#1); 5281#L652-2 [2024-10-15 01:00:27,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:27,853 INFO L85 PathProgramCache]: Analyzing trace with hash 372621552, now seen corresponding path program 1 times [2024-10-15 01:00:27,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:27,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609136005] [2024-10-15 01:00:27,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:27,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609136005] [2024-10-15 01:00:27,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [609136005] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:27,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030189537] [2024-10-15 01:00:27,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,907 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:27,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:27,907 INFO L85 PathProgramCache]: Analyzing trace with hash 356739930, now seen corresponding path program 1 times [2024-10-15 01:00:27,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:27,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701507493] [2024-10-15 01:00:27,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:27,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:27,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:27,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:27,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:27,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701507493] [2024-10-15 01:00:27,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1701507493] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:27,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:27,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:27,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778886750] [2024-10-15 01:00:27,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:27,942 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:27,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:27,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-15 01:00:27,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-15 01:00:27,943 INFO L87 Difference]: Start difference. First operand 957 states and 1348 transitions. cyclomatic complexity: 395 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:28,032 INFO L93 Difference]: Finished difference Result 2053 states and 2878 transitions. [2024-10-15 01:00:28,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2053 states and 2878 transitions. [2024-10-15 01:00:28,045 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1946 [2024-10-15 01:00:28,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2053 states to 2053 states and 2878 transitions. [2024-10-15 01:00:28,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2053 [2024-10-15 01:00:28,057 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2053 [2024-10-15 01:00:28,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2053 states and 2878 transitions. [2024-10-15 01:00:28,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:28,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2053 states and 2878 transitions. [2024-10-15 01:00:28,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2053 states and 2878 transitions. [2024-10-15 01:00:28,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2053 to 1146. [2024-10-15 01:00:28,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1146 states, 1146 states have (on average 1.4013961605584642) internal successors, (1606), 1145 states have internal predecessors, (1606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1146 states to 1146 states and 1606 transitions. [2024-10-15 01:00:28,084 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1146 states and 1606 transitions. [2024-10-15 01:00:28,085 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-15 01:00:28,086 INFO L425 stractBuchiCegarLoop]: Abstraction has 1146 states and 1606 transitions. [2024-10-15 01:00:28,086 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-15 01:00:28,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1146 states and 1606 transitions. [2024-10-15 01:00:28,091 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1049 [2024-10-15 01:00:28,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:28,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:28,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,093 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,093 INFO L745 eck$LassoCheckResult]: Stem: 8565#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 8566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8580#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8577#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8548#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 8549#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8347#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8348#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8592#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8313#L418 assume !(0 == ~M_E~0); 8314#L418-2 assume !(0 == ~T1_E~0); 8547#L423-1 assume !(0 == ~T2_E~0); 8597#L428-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8602#L433-1 assume !(0 == ~E_1~0); 8582#L438-1 assume !(0 == ~E_2~0); 8583#L443-1 assume !(0 == ~E_3~0); 8495#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8496#L197 assume !(1 == ~m_pc~0); 8451#L197-2 is_master_triggered_~__retres1~0#1 := 0; 8624#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8540#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8541#L510 assume !(0 != activate_threads_~tmp~1#1); 8292#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8293#L216 assume !(1 == ~t1_pc~0); 8343#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8344#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8657#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8656#L518 assume !(0 != activate_threads_~tmp___0~0#1); 8655#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8654#L235 assume !(1 == ~t2_pc~0); 8653#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8651#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8635#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8612#L526 assume !(0 != activate_threads_~tmp___1~0#1); 8613#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8419#L254 assume !(1 == ~t3_pc~0); 8420#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8444#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8445#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8480#L534 assume !(0 != activate_threads_~tmp___2~0#1); 8481#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8648#L461 assume !(1 == ~M_E~0); 8349#L461-2 assume !(1 == ~T1_E~0); 8350#L466-1 assume !(1 == ~T2_E~0); 8601#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8376#L476-1 assume !(1 == ~E_1~0); 8377#L481-1 assume !(1 == ~E_2~0); 8530#L486-1 assume !(1 == ~E_3~0); 8394#L491-1 assume { :end_inline_reset_delta_events } true; 8395#L652-2 [2024-10-15 01:00:28,094 INFO L747 eck$LassoCheckResult]: Loop: 8395#L652-2 assume !false; 8949#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8370#L393-1 assume !false; 8947#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8945#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8940#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8938#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8934#L346 assume !(0 != eval_~tmp~0#1); 8935#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9036#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9033#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9030#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9027#L423-3 assume !(0 == ~T2_E~0); 9023#L428-3 assume !(0 == ~T3_E~0); 9024#L433-3 assume !(0 == ~E_1~0); 9092#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9091#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9090#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9089#L197-12 assume !(1 == ~m_pc~0); 9088#L197-14 is_master_triggered_~__retres1~0#1 := 0; 9086#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9084#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9081#L510-12 assume !(0 != activate_threads_~tmp~1#1); 9077#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9074#L216-12 assume !(1 == ~t1_pc~0); 9071#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 9068#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9066#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9064#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9062#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9060#L235-12 assume 1 == ~t2_pc~0; 9057#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9055#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9053#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9051#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9048#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9046#L254-12 assume !(1 == ~t3_pc~0); 9044#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 9042#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9040#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9038#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9035#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9032#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9029#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9026#L466-3 assume !(1 == ~T2_E~0); 8986#L471-3 assume !(1 == ~T3_E~0); 8983#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8981#L481-3 assume !(1 == ~E_2~0); 8979#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8977#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8975#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8970#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8968#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 8965#L671 assume !(0 == start_simulation_~tmp~3#1); 8964#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8962#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8959#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8958#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 8957#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8956#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8951#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8950#L684 assume !(0 != start_simulation_~tmp___0~1#1); 8395#L652-2 [2024-10-15 01:00:28,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,094 INFO L85 PathProgramCache]: Analyzing trace with hash -286909970, now seen corresponding path program 1 times [2024-10-15 01:00:28,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449044682] [2024-10-15 01:00:28,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:28,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:28,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:28,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449044682] [2024-10-15 01:00:28,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449044682] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:28,141 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:28,141 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:28,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625647208] [2024-10-15 01:00:28,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:28,141 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:28,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,142 INFO L85 PathProgramCache]: Analyzing trace with hash -518044004, now seen corresponding path program 1 times [2024-10-15 01:00:28,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527028304] [2024-10-15 01:00:28,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:28,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:28,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:28,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [527028304] [2024-10-15 01:00:28,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [527028304] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:28,174 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:28,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:28,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366020979] [2024-10-15 01:00:28,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:28,175 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:28,175 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:28,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-15 01:00:28,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-15 01:00:28,176 INFO L87 Difference]: Start difference. First operand 1146 states and 1606 transitions. cyclomatic complexity: 464 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:28,208 INFO L93 Difference]: Finished difference Result 957 states and 1334 transitions. [2024-10-15 01:00:28,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957 states and 1334 transitions. [2024-10-15 01:00:28,215 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-10-15 01:00:28,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957 states to 957 states and 1334 transitions. [2024-10-15 01:00:28,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957 [2024-10-15 01:00:28,220 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957 [2024-10-15 01:00:28,220 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957 states and 1334 transitions. [2024-10-15 01:00:28,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:28,221 INFO L218 hiAutomatonCegarLoop]: Abstraction has 957 states and 1334 transitions. [2024-10-15 01:00:28,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states and 1334 transitions. [2024-10-15 01:00:28,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 957. [2024-10-15 01:00:28,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.393939393939394) internal successors, (1334), 956 states have internal predecessors, (1334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1334 transitions. [2024-10-15 01:00:28,238 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1334 transitions. [2024-10-15 01:00:28,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:28,239 INFO L425 stractBuchiCegarLoop]: Abstraction has 957 states and 1334 transitions. [2024-10-15 01:00:28,240 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-15 01:00:28,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1334 transitions. [2024-10-15 01:00:28,245 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-10-15 01:00:28,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:28,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:28,246 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,246 INFO L745 eck$LassoCheckResult]: Stem: 10668#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 10669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 10684#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10679#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10649#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 10650#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10460#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10461#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10695#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10426#L418 assume !(0 == ~M_E~0); 10427#L418-2 assume !(0 == ~T1_E~0); 10648#L423-1 assume !(0 == ~T2_E~0); 10701#L428-1 assume !(0 == ~T3_E~0); 10699#L433-1 assume !(0 == ~E_1~0); 10686#L438-1 assume !(0 == ~E_2~0); 10605#L443-1 assume !(0 == ~E_3~0); 10597#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10561#L197 assume !(1 == ~m_pc~0); 10558#L197-2 is_master_triggered_~__retres1~0#1 := 0; 10720#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10641#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10642#L510 assume !(0 != activate_threads_~tmp~1#1); 10405#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10406#L216 assume !(1 == ~t1_pc~0); 10456#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10457#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10487#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10407#L518 assume !(0 != activate_threads_~tmp___0~0#1); 10408#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10614#L235 assume !(1 == ~t2_pc~0); 10691#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10546#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10547#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10711#L526 assume !(0 != activate_threads_~tmp___1~0#1); 10712#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10529#L254 assume !(1 == ~t3_pc~0); 10464#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10465#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10418#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10419#L534 assume !(0 != activate_threads_~tmp___2~0#1); 10540#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10397#L461 assume !(1 == ~M_E~0); 10398#L461-2 assume !(1 == ~T1_E~0); 10462#L466-1 assume !(1 == ~T2_E~0); 10704#L471-1 assume !(1 == ~T3_E~0); 10488#L476-1 assume !(1 == ~E_1~0); 10489#L481-1 assume !(1 == ~E_2~0); 10630#L486-1 assume !(1 == ~E_3~0); 10505#L491-1 assume { :end_inline_reset_delta_events } true; 10414#L652-2 [2024-10-15 01:00:28,247 INFO L747 eck$LassoCheckResult]: Loop: 10414#L652-2 assume !false; 10415#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10482#L393-1 assume !false; 10479#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 10480#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 10454#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 10420#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10421#L346 assume !(0 != eval_~tmp~0#1); 10510#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11351#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11348#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10611#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10612#L423-3 assume !(0 == ~T2_E~0); 10606#L428-3 assume !(0 == ~T3_E~0); 10559#L433-3 assume !(0 == ~E_1~0); 10560#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10662#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10399#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10400#L197-12 assume 1 == ~m_pc~0; 10670#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10680#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11353#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11352#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10413#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10523#L216-12 assume !(1 == ~t1_pc~0); 10524#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 11317#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11315#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11313#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11311#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11309#L235-12 assume 1 == ~t2_pc~0; 11306#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11243#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11242#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11241#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11240#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10707#L254-12 assume !(1 == ~t3_pc~0); 10708#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 11290#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11289#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11288#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11287#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11286#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11284#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11282#L466-3 assume !(1 == ~T2_E~0); 11280#L471-3 assume !(1 == ~T3_E~0); 11278#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11276#L481-3 assume !(1 == ~E_2~0); 11274#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11272#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11270#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11265#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11263#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 11259#L671 assume !(0 == start_simulation_~tmp~3#1); 11258#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11256#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 10629#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 10485#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 10486#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 10636#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10637#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 10639#L684 assume !(0 != start_simulation_~tmp___0~1#1); 10414#L652-2 [2024-10-15 01:00:28,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,247 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2024-10-15 01:00:28,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259704093] [2024-10-15 01:00:28,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:28,258 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:28,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:28,290 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:28,292 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,292 INFO L85 PathProgramCache]: Analyzing trace with hash 2128865983, now seen corresponding path program 1 times [2024-10-15 01:00:28,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437196623] [2024-10-15 01:00:28,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:28,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:28,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:28,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437196623] [2024-10-15 01:00:28,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437196623] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:28,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:28,325 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:28,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982444105] [2024-10-15 01:00:28,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:28,325 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:28,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:28,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:28,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:28,326 INFO L87 Difference]: Start difference. First operand 957 states and 1334 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:28,381 INFO L93 Difference]: Finished difference Result 1656 states and 2278 transitions. [2024-10-15 01:00:28,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1656 states and 2278 transitions. [2024-10-15 01:00:28,390 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1553 [2024-10-15 01:00:28,398 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1656 states to 1656 states and 2278 transitions. [2024-10-15 01:00:28,398 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1656 [2024-10-15 01:00:28,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1656 [2024-10-15 01:00:28,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1656 states and 2278 transitions. [2024-10-15 01:00:28,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:28,402 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1656 states and 2278 transitions. [2024-10-15 01:00:28,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states and 2278 transitions. [2024-10-15 01:00:28,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 1654. [2024-10-15 01:00:28,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1654 states, 1654 states have (on average 1.3760580411124546) internal successors, (2276), 1653 states have internal predecessors, (2276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1654 states to 1654 states and 2276 transitions. [2024-10-15 01:00:28,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1654 states and 2276 transitions. [2024-10-15 01:00:28,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:28,427 INFO L425 stractBuchiCegarLoop]: Abstraction has 1654 states and 2276 transitions. [2024-10-15 01:00:28,427 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-15 01:00:28,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1654 states and 2276 transitions. [2024-10-15 01:00:28,434 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1551 [2024-10-15 01:00:28,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:28,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:28,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,436 INFO L745 eck$LassoCheckResult]: Stem: 13292#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 13293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 13305#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13304#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13277#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 13278#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13079#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13080#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13317#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13049#L418 assume !(0 == ~M_E~0); 13050#L418-2 assume !(0 == ~T1_E~0); 13276#L423-1 assume !(0 == ~T2_E~0); 13322#L428-1 assume !(0 == ~T3_E~0); 13319#L433-1 assume !(0 == ~E_1~0); 13307#L438-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13231#L443-1 assume !(0 == ~E_3~0); 13222#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13223#L197 assume !(1 == ~m_pc~0); 13179#L197-2 is_master_triggered_~__retres1~0#1 := 0; 13351#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13407#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13404#L510 assume !(0 != activate_threads_~tmp~1#1); 13024#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13025#L216 assume !(1 == ~t1_pc~0); 13403#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13402#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13107#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13108#L518 assume !(0 != activate_threads_~tmp___0~0#1); 13240#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13241#L235 assume !(1 == ~t2_pc~0); 13400#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13321#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13363#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13340#L526 assume !(0 != activate_threads_~tmp___1~0#1); 13341#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13398#L254 assume !(1 == ~t3_pc~0); 13084#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13085#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13039#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13040#L534 assume !(0 != activate_threads_~tmp___2~0#1); 13386#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13383#L461 assume !(1 == ~M_E~0); 13081#L461-2 assume !(1 == ~T1_E~0); 13082#L466-1 assume !(1 == ~T2_E~0); 13328#L471-1 assume !(1 == ~T3_E~0); 13111#L476-1 assume !(1 == ~E_1~0); 13112#L481-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13256#L486-1 assume !(1 == ~E_3~0); 13128#L491-1 assume { :end_inline_reset_delta_events } true; 13035#L652-2 [2024-10-15 01:00:28,436 INFO L747 eck$LassoCheckResult]: Loop: 13035#L652-2 assume !false; 13036#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13104#L393-1 assume !false; 14533#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13334#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13073#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13037#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13038#L346 assume !(0 != eval_~tmp~0#1); 13131#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14609#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14608#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14607#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14605#L423-3 assume !(0 == ~T2_E~0); 14604#L428-3 assume !(0 == ~T3_E~0); 14603#L433-3 assume !(0 == ~E_1~0); 14601#L438-3 assume !(0 == ~E_2~0); 14600#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14599#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14598#L197-12 assume !(1 == ~m_pc~0); 14595#L197-14 is_master_triggered_~__retres1~0#1 := 0; 14593#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14589#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14587#L510-12 assume !(0 != activate_threads_~tmp~1#1); 14584#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14582#L216-12 assume !(1 == ~t1_pc~0); 14579#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 14577#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14575#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14572#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14570#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14568#L235-12 assume !(1 == ~t2_pc~0); 14565#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 14563#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14561#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14559#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14558#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14556#L254-12 assume !(1 == ~t3_pc~0); 14554#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 14552#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14550#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14547#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14545#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14543#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14508#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14507#L466-3 assume !(1 == ~T2_E~0); 14506#L471-3 assume !(1 == ~T3_E~0); 14504#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14503#L481-3 assume !(1 == ~E_2~0); 13172#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13173#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13056#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13057#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13083#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 13246#L671 assume !(0 == start_simulation_~tmp~3#1); 13044#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13283#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13138#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13105#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 13106#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13261#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13262#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 13264#L684 assume !(0 != start_simulation_~tmp___0~1#1); 13035#L652-2 [2024-10-15 01:00:28,437 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1218472174, now seen corresponding path program 1 times [2024-10-15 01:00:28,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842800012] [2024-10-15 01:00:28,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:28,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:28,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:28,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842800012] [2024-10-15 01:00:28,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842800012] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:28,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:28,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 01:00:28,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036708877] [2024-10-15 01:00:28,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:28,468 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:28,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,468 INFO L85 PathProgramCache]: Analyzing trace with hash 47842237, now seen corresponding path program 1 times [2024-10-15 01:00:28,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956080059] [2024-10-15 01:00:28,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:28,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:28,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:28,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956080059] [2024-10-15 01:00:28,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956080059] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:28,517 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:28,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 01:00:28,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144365849] [2024-10-15 01:00:28,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:28,517 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:28,518 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:28,518 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:28,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:28,519 INFO L87 Difference]: Start difference. First operand 1654 states and 2276 transitions. cyclomatic complexity: 626 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:28,553 INFO L93 Difference]: Finished difference Result 957 states and 1301 transitions. [2024-10-15 01:00:28,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957 states and 1301 transitions. [2024-10-15 01:00:28,559 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-10-15 01:00:28,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957 states to 957 states and 1301 transitions. [2024-10-15 01:00:28,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957 [2024-10-15 01:00:28,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957 [2024-10-15 01:00:28,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957 states and 1301 transitions. [2024-10-15 01:00:28,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:28,567 INFO L218 hiAutomatonCegarLoop]: Abstraction has 957 states and 1301 transitions. [2024-10-15 01:00:28,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states and 1301 transitions. [2024-10-15 01:00:28,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 957. [2024-10-15 01:00:28,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.3594566353187043) internal successors, (1301), 956 states have internal predecessors, (1301), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1301 transitions. [2024-10-15 01:00:28,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1301 transitions. [2024-10-15 01:00:28,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:28,583 INFO L425 stractBuchiCegarLoop]: Abstraction has 957 states and 1301 transitions. [2024-10-15 01:00:28,583 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-15 01:00:28,583 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1301 transitions. [2024-10-15 01:00:28,587 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-10-15 01:00:28,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:28,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:28,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,588 INFO L745 eck$LassoCheckResult]: Stem: 15907#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 15908#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 15921#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15918#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15891#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 15892#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15700#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15701#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15931#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15665#L418 assume !(0 == ~M_E~0); 15666#L418-2 assume !(0 == ~T1_E~0); 15890#L423-1 assume !(0 == ~T2_E~0); 15935#L428-1 assume !(0 == ~T3_E~0); 15933#L433-1 assume !(0 == ~E_1~0); 15923#L438-1 assume !(0 == ~E_2~0); 15848#L443-1 assume !(0 == ~E_3~0); 15841#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15804#L197 assume !(1 == ~m_pc~0); 15801#L197-2 is_master_triggered_~__retres1~0#1 := 0; 15955#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15883#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15884#L510 assume !(0 != activate_threads_~tmp~1#1); 15644#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15645#L216 assume !(1 == ~t1_pc~0); 15696#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15697#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15727#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15646#L518 assume !(0 != activate_threads_~tmp___0~0#1); 15647#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15857#L235 assume !(1 == ~t2_pc~0); 15928#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15787#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15788#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15945#L526 assume !(0 != activate_threads_~tmp___1~0#1); 15946#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15770#L254 assume !(1 == ~t3_pc~0); 15704#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15705#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15657#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15658#L534 assume !(0 != activate_threads_~tmp___2~0#1); 15781#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15636#L461 assume !(1 == ~M_E~0); 15637#L461-2 assume !(1 == ~T1_E~0); 15702#L466-1 assume !(1 == ~T2_E~0); 15938#L471-1 assume !(1 == ~T3_E~0); 15728#L476-1 assume !(1 == ~E_1~0); 15729#L481-1 assume !(1 == ~E_2~0); 15874#L486-1 assume !(1 == ~E_3~0); 15744#L491-1 assume { :end_inline_reset_delta_events } true; 15745#L652-2 [2024-10-15 01:00:28,588 INFO L747 eck$LassoCheckResult]: Loop: 15745#L652-2 assume !false; 16418#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15879#L393-1 assume !false; 15719#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15720#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16089#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16086#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16084#L346 assume !(0 != eval_~tmp~0#1); 15824#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15825#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15862#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15855#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15856#L423-3 assume !(0 == ~T2_E~0); 15850#L428-3 assume !(0 == ~T3_E~0); 15802#L433-3 assume !(0 == ~E_1~0); 15803#L438-3 assume !(0 == ~E_2~0); 15901#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15638#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15639#L197-12 assume 1 == ~m_pc~0; 15909#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15919#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16379#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16378#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15652#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15764#L216-12 assume !(1 == ~t1_pc~0); 15765#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 16236#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16234#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16233#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16232#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16228#L235-12 assume !(1 == ~t2_pc~0); 16225#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 16223#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16222#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16219#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16218#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16216#L254-12 assume !(1 == ~t3_pc~0); 16148#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 16146#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16144#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16143#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16140#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16139#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16138#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16137#L466-3 assume !(1 == ~T2_E~0); 16136#L471-3 assume !(1 == ~T3_E~0); 16135#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16134#L481-3 assume !(1 == ~E_2~0); 16133#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16132#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16130#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16126#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16125#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 16122#L671 assume !(0 == start_simulation_~tmp~3#1); 16123#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16427#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16424#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 16422#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16421#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16420#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 16419#L684 assume !(0 != start_simulation_~tmp___0~1#1); 15745#L652-2 [2024-10-15 01:00:28,589 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,589 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2024-10-15 01:00:28,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,589 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156202356] [2024-10-15 01:00:28,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:28,600 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:28,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:28,612 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:28,613 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,613 INFO L85 PathProgramCache]: Analyzing trace with hash -1600215072, now seen corresponding path program 1 times [2024-10-15 01:00:28,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336722395] [2024-10-15 01:00:28,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:28,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:28,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:28,664 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336722395] [2024-10-15 01:00:28,664 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336722395] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:28,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:28,665 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 01:00:28,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674634222] [2024-10-15 01:00:28,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:28,665 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:28,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:28,665 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 01:00:28,665 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-15 01:00:28,666 INFO L87 Difference]: Start difference. First operand 957 states and 1301 transitions. cyclomatic complexity: 348 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:28,724 INFO L93 Difference]: Finished difference Result 985 states and 1329 transitions. [2024-10-15 01:00:28,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 985 states and 1329 transitions. [2024-10-15 01:00:28,730 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 925 [2024-10-15 01:00:28,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 985 states to 985 states and 1329 transitions. [2024-10-15 01:00:28,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 985 [2024-10-15 01:00:28,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 985 [2024-10-15 01:00:28,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 985 states and 1329 transitions. [2024-10-15 01:00:28,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:28,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 985 states and 1329 transitions. [2024-10-15 01:00:28,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 985 states and 1329 transitions. [2024-10-15 01:00:28,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 985 to 969. [2024-10-15 01:00:28,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.3550051599587203) internal successors, (1313), 968 states have internal predecessors, (1313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1313 transitions. [2024-10-15 01:00:28,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 969 states and 1313 transitions. [2024-10-15 01:00:28,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 01:00:28,756 INFO L425 stractBuchiCegarLoop]: Abstraction has 969 states and 1313 transitions. [2024-10-15 01:00:28,756 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-15 01:00:28,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1313 transitions. [2024-10-15 01:00:28,763 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 909 [2024-10-15 01:00:28,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:28,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:28,764 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,764 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,765 INFO L745 eck$LassoCheckResult]: Stem: 17856#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 17857#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 17871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17868#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17838#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 17839#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17650#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17651#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17885#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17615#L418 assume !(0 == ~M_E~0); 17616#L418-2 assume !(0 == ~T1_E~0); 17837#L423-1 assume !(0 == ~T2_E~0); 17893#L428-1 assume !(0 == ~T3_E~0); 17889#L433-1 assume !(0 == ~E_1~0); 17874#L438-1 assume !(0 == ~E_2~0); 17797#L443-1 assume !(0 == ~E_3~0); 17790#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17750#L197 assume !(1 == ~m_pc~0); 17747#L197-2 is_master_triggered_~__retres1~0#1 := 0; 17915#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17830#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17831#L510 assume !(0 != activate_threads_~tmp~1#1); 17594#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17595#L216 assume !(1 == ~t1_pc~0); 17646#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17647#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17677#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17596#L518 assume !(0 != activate_threads_~tmp___0~0#1); 17597#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17805#L235 assume !(1 == ~t2_pc~0); 17881#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17733#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17734#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17906#L526 assume !(0 != activate_threads_~tmp___1~0#1); 17907#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17717#L254 assume !(1 == ~t3_pc~0); 17654#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17655#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17607#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17608#L534 assume !(0 != activate_threads_~tmp___2~0#1); 17728#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17586#L461 assume !(1 == ~M_E~0); 17587#L461-2 assume !(1 == ~T1_E~0); 17652#L466-1 assume !(1 == ~T2_E~0); 17898#L471-1 assume !(1 == ~T3_E~0); 17678#L476-1 assume !(1 == ~E_1~0); 17679#L481-1 assume !(1 == ~E_2~0); 17823#L486-1 assume !(1 == ~E_3~0); 17694#L491-1 assume { :end_inline_reset_delta_events } true; 17603#L652-2 [2024-10-15 01:00:28,765 INFO L747 eck$LassoCheckResult]: Loop: 17603#L652-2 assume !false; 17604#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17672#L393-1 assume !false; 17669#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17670#L309 assume !(0 == ~m_st~0); 17643#L313 assume !(0 == ~t1_st~0); 17645#L317 assume !(0 == ~t2_st~0); 17829#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 17895#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 18527#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18526#L346 assume !(0 != eval_~tmp~0#1); 18525#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18524#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18523#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18522#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18521#L423-3 assume !(0 == ~T2_E~0); 18520#L428-3 assume !(0 == ~T3_E~0); 18519#L433-3 assume !(0 == ~E_1~0); 18518#L438-3 assume !(0 == ~E_2~0); 18517#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18516#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18515#L197-12 assume !(1 == ~m_pc~0); 18513#L197-14 is_master_triggered_~__retres1~0#1 := 0; 18511#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18509#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18508#L510-12 assume !(0 != activate_threads_~tmp~1#1); 18506#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17711#L216-12 assume !(1 == ~t1_pc~0); 17712#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 18390#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18388#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18386#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18384#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18381#L235-12 assume !(1 == ~t2_pc~0); 18378#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 18376#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18374#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18372#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17791#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17792#L254-12 assume !(1 == ~t3_pc~0); 17901#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 17796#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17680#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17681#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17770#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17715#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17716#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17810#L466-3 assume !(1 == ~T2_E~0); 17811#L471-3 assume !(1 == ~T3_E~0); 17708#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17709#L481-3 assume !(1 == ~E_2~0); 17740#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17741#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17627#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17628#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17653#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17812#L671 assume !(0 == start_simulation_~tmp~3#1); 17813#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 18461#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 18458#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 17676#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17825#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17826#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 17828#L684 assume !(0 != start_simulation_~tmp___0~1#1); 17603#L652-2 [2024-10-15 01:00:28,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,766 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2024-10-15 01:00:28,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137684741] [2024-10-15 01:00:28,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:28,775 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:28,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:28,816 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:28,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,817 INFO L85 PathProgramCache]: Analyzing trace with hash -182477129, now seen corresponding path program 1 times [2024-10-15 01:00:28,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295219452] [2024-10-15 01:00:28,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:28,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:28,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:28,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295219452] [2024-10-15 01:00:28,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295219452] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:28,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:28,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:28,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848493654] [2024-10-15 01:00:28,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:28,850 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:28,850 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:28,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:28,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:28,852 INFO L87 Difference]: Start difference. First operand 969 states and 1313 transitions. cyclomatic complexity: 348 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:28,901 INFO L93 Difference]: Finished difference Result 1700 states and 2264 transitions. [2024-10-15 01:00:28,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1700 states and 2264 transitions. [2024-10-15 01:00:28,908 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1634 [2024-10-15 01:00:28,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1700 states to 1700 states and 2264 transitions. [2024-10-15 01:00:28,916 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1700 [2024-10-15 01:00:28,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1700 [2024-10-15 01:00:28,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1700 states and 2264 transitions. [2024-10-15 01:00:28,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:28,920 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1700 states and 2264 transitions. [2024-10-15 01:00:28,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1700 states and 2264 transitions. [2024-10-15 01:00:28,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1700 to 1604. [2024-10-15 01:00:28,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1604 states, 1604 states have (on average 1.3366583541147132) internal successors, (2144), 1603 states have internal predecessors, (2144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:28,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1604 states to 1604 states and 2144 transitions. [2024-10-15 01:00:28,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1604 states and 2144 transitions. [2024-10-15 01:00:28,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:28,948 INFO L425 stractBuchiCegarLoop]: Abstraction has 1604 states and 2144 transitions. [2024-10-15 01:00:28,948 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-15 01:00:28,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1604 states and 2144 transitions. [2024-10-15 01:00:28,953 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1538 [2024-10-15 01:00:28,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:28,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:28,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,954 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:28,955 INFO L745 eck$LassoCheckResult]: Stem: 20537#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 20538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20552#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20550#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20521#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 20522#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20324#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20325#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20561#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20290#L418 assume !(0 == ~M_E~0); 20291#L418-2 assume !(0 == ~T1_E~0); 20520#L423-1 assume !(0 == ~T2_E~0); 20567#L428-1 assume !(0 == ~T3_E~0); 20565#L433-1 assume !(0 == ~E_1~0); 20554#L438-1 assume !(0 == ~E_2~0); 20474#L443-1 assume !(0 == ~E_3~0); 20468#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20430#L197 assume !(1 == ~m_pc~0); 20427#L197-2 is_master_triggered_~__retres1~0#1 := 0; 20595#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20511#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20512#L510 assume !(0 != activate_threads_~tmp~1#1); 20269#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20270#L216 assume !(1 == ~t1_pc~0); 20320#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20321#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20352#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20271#L518 assume !(0 != activate_threads_~tmp___0~0#1); 20272#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20482#L235 assume !(1 == ~t2_pc~0); 20557#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20410#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20411#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20583#L526 assume !(0 != activate_threads_~tmp___1~0#1); 20584#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20393#L254 assume !(1 == ~t3_pc~0); 20329#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20330#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20282#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20283#L534 assume !(0 != activate_threads_~tmp___2~0#1); 20405#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20261#L461 assume !(1 == ~M_E~0); 20262#L461-2 assume !(1 == ~T1_E~0); 20326#L466-1 assume !(1 == ~T2_E~0); 20572#L471-1 assume !(1 == ~T3_E~0); 20353#L476-1 assume !(1 == ~E_1~0); 20354#L481-1 assume !(1 == ~E_2~0); 20503#L486-1 assume !(1 == ~E_3~0); 20369#L491-1 assume { :end_inline_reset_delta_events } true; 20370#L652-2 [2024-10-15 01:00:28,955 INFO L747 eck$LassoCheckResult]: Loop: 20370#L652-2 assume !false; 21092#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20873#L393-1 assume !false; 21089#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21087#L309 assume !(0 == ~m_st~0); 20317#L313 assume !(0 == ~t1_st~0); 20319#L317 assume !(0 == ~t2_st~0); 20510#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 20569#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20284#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20285#L346 assume !(0 != eval_~tmp~0#1); 20451#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20452#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21390#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21387#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21385#L423-3 assume !(0 == ~T2_E~0); 21383#L428-3 assume !(0 == ~T3_E~0); 21381#L433-3 assume !(0 == ~E_1~0); 21379#L438-3 assume !(0 == ~E_2~0); 21377#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21375#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21370#L197-12 assume 1 == ~m_pc~0; 21362#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21357#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21353#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21351#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21350#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21349#L216-12 assume !(1 == ~t1_pc~0); 21348#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 21345#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21343#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21341#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21339#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21337#L235-12 assume !(1 == ~t2_pc~0); 21334#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 21168#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21164#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21161#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21158#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21155#L254-12 assume !(1 == ~t3_pc~0); 21153#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 21151#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21149#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21147#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21145#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21143#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21141#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21139#L466-3 assume !(1 == ~T2_E~0); 21137#L471-3 assume !(1 == ~T3_E~0); 21135#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21133#L481-3 assume !(1 == ~E_2~0); 21131#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21129#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21126#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21124#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21122#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21115#L671 assume !(0 == start_simulation_~tmp~3#1); 21113#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21110#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21108#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21106#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 21104#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21102#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21100#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 21096#L684 assume !(0 != start_simulation_~tmp___0~1#1); 20370#L652-2 [2024-10-15 01:00:28,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,955 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 4 times [2024-10-15 01:00:28,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143862468] [2024-10-15 01:00:28,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:28,963 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:28,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:28,974 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:28,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:28,975 INFO L85 PathProgramCache]: Analyzing trace with hash -1830534438, now seen corresponding path program 1 times [2024-10-15 01:00:28,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:28,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933763702] [2024-10-15 01:00:28,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:28,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:28,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:29,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:29,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:29,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933763702] [2024-10-15 01:00:29,038 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1933763702] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:29,038 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:29,038 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 01:00:29,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924162420] [2024-10-15 01:00:29,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:29,039 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:29,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:29,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 01:00:29,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-15 01:00:29,039 INFO L87 Difference]: Start difference. First operand 1604 states and 2144 transitions. cyclomatic complexity: 544 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:29,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:29,099 INFO L93 Difference]: Finished difference Result 1624 states and 2160 transitions. [2024-10-15 01:00:29,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1624 states and 2160 transitions. [2024-10-15 01:00:29,106 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1558 [2024-10-15 01:00:29,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1624 states to 1624 states and 2160 transitions. [2024-10-15 01:00:29,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1624 [2024-10-15 01:00:29,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1624 [2024-10-15 01:00:29,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1624 states and 2160 transitions. [2024-10-15 01:00:29,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:29,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1624 states and 2160 transitions. [2024-10-15 01:00:29,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1624 states and 2160 transitions. [2024-10-15 01:00:29,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1624 to 1616. [2024-10-15 01:00:29,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1616 states, 1616 states have (on average 1.3316831683168318) internal successors, (2152), 1615 states have internal predecessors, (2152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:29,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1616 states to 1616 states and 2152 transitions. [2024-10-15 01:00:29,145 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1616 states and 2152 transitions. [2024-10-15 01:00:29,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 01:00:29,146 INFO L425 stractBuchiCegarLoop]: Abstraction has 1616 states and 2152 transitions. [2024-10-15 01:00:29,146 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-15 01:00:29,146 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1616 states and 2152 transitions. [2024-10-15 01:00:29,151 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1550 [2024-10-15 01:00:29,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:29,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:29,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:29,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:29,153 INFO L745 eck$LassoCheckResult]: Stem: 23775#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 23776#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 23789#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23786#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23756#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 23757#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23560#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23561#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23802#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23526#L418 assume !(0 == ~M_E~0); 23527#L418-2 assume !(0 == ~T1_E~0); 23755#L423-1 assume !(0 == ~T2_E~0); 23808#L428-1 assume !(0 == ~T3_E~0); 23806#L433-1 assume !(0 == ~E_1~0); 23792#L438-1 assume !(0 == ~E_2~0); 23713#L443-1 assume !(0 == ~E_3~0); 23707#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23664#L197 assume !(1 == ~m_pc~0); 23661#L197-2 is_master_triggered_~__retres1~0#1 := 0; 23833#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23747#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 23748#L510 assume !(0 != activate_threads_~tmp~1#1); 23505#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23506#L216 assume !(1 == ~t1_pc~0); 23556#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23557#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23589#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23507#L518 assume !(0 != activate_threads_~tmp___0~0#1); 23508#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23720#L235 assume !(1 == ~t2_pc~0); 23797#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23647#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23648#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23823#L526 assume !(0 != activate_threads_~tmp___1~0#1); 23824#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23631#L254 assume !(1 == ~t3_pc~0); 23565#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23566#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23518#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23519#L534 assume !(0 != activate_threads_~tmp___2~0#1); 23642#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23497#L461 assume !(1 == ~M_E~0); 23498#L461-2 assume !(1 == ~T1_E~0); 23562#L466-1 assume !(1 == ~T2_E~0); 23814#L471-1 assume !(1 == ~T3_E~0); 23590#L476-1 assume !(1 == ~E_1~0); 23591#L481-1 assume !(1 == ~E_2~0); 23737#L486-1 assume !(1 == ~E_3~0); 23606#L491-1 assume { :end_inline_reset_delta_events } true; 23607#L652-2 [2024-10-15 01:00:29,153 INFO L747 eck$LassoCheckResult]: Loop: 23607#L652-2 assume !false; 24392#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24388#L393-1 assume !false; 24383#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24380#L309 assume !(0 == ~m_st~0); 24381#L313 assume !(0 == ~t1_st~0); 24517#L317 assume !(0 == ~t2_st~0); 24515#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 24513#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24512#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24510#L346 assume !(0 != eval_~tmp~0#1); 24511#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24653#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24652#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24651#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24650#L423-3 assume !(0 == ~T2_E~0); 24649#L428-3 assume !(0 == ~T3_E~0); 24648#L433-3 assume !(0 == ~E_1~0); 24647#L438-3 assume !(0 == ~E_2~0); 24643#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24641#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24639#L197-12 assume 1 == ~m_pc~0; 24636#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24631#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24629#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24626#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24624#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24622#L216-12 assume !(1 == ~t1_pc~0); 24620#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 24618#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24616#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24613#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24611#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24609#L235-12 assume !(1 == ~t2_pc~0); 24606#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 24604#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24602#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24600#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24597#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24595#L254-12 assume !(1 == ~t3_pc~0); 24593#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 24591#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24589#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24588#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24587#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24583#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24581#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24579#L466-3 assume !(1 == ~T2_E~0); 24578#L471-3 assume !(1 == ~T3_E~0); 24575#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24574#L481-3 assume !(1 == ~E_2~0); 24572#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24569#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24566#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24564#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24561#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 24429#L671 assume !(0 == start_simulation_~tmp~3#1); 24427#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24424#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24422#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24420#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 24418#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24416#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24414#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 24413#L684 assume !(0 != start_simulation_~tmp___0~1#1); 23607#L652-2 [2024-10-15 01:00:29,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,154 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 5 times [2024-10-15 01:00:29,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188525727] [2024-10-15 01:00:29,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,163 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:29,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,173 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:29,174 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,174 INFO L85 PathProgramCache]: Analyzing trace with hash -1830594020, now seen corresponding path program 1 times [2024-10-15 01:00:29,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660340541] [2024-10-15 01:00:29,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:29,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:29,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:29,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660340541] [2024-10-15 01:00:29,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [660340541] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:29,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:29,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 01:00:29,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209301232] [2024-10-15 01:00:29,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:29,248 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:29,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:29,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 01:00:29,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-15 01:00:29,248 INFO L87 Difference]: Start difference. First operand 1616 states and 2152 transitions. cyclomatic complexity: 540 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:29,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:29,354 INFO L93 Difference]: Finished difference Result 1670 states and 2191 transitions. [2024-10-15 01:00:29,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1670 states and 2191 transitions. [2024-10-15 01:00:29,360 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1604 [2024-10-15 01:00:29,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1670 states to 1670 states and 2191 transitions. [2024-10-15 01:00:29,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1670 [2024-10-15 01:00:29,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1670 [2024-10-15 01:00:29,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1670 states and 2191 transitions. [2024-10-15 01:00:29,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:29,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1670 states and 2191 transitions. [2024-10-15 01:00:29,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1670 states and 2191 transitions. [2024-10-15 01:00:29,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1670 to 1670. [2024-10-15 01:00:29,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1670 states, 1670 states have (on average 1.3119760479041915) internal successors, (2191), 1669 states have internal predecessors, (2191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:29,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1670 states to 1670 states and 2191 transitions. [2024-10-15 01:00:29,398 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1670 states and 2191 transitions. [2024-10-15 01:00:29,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 01:00:29,399 INFO L425 stractBuchiCegarLoop]: Abstraction has 1670 states and 2191 transitions. [2024-10-15 01:00:29,399 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-15 01:00:29,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1670 states and 2191 transitions. [2024-10-15 01:00:29,404 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1604 [2024-10-15 01:00:29,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:29,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:29,405 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:29,405 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:29,405 INFO L745 eck$LassoCheckResult]: Stem: 27068#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 27069#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27081#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27079#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27050#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 27051#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26854#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26855#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27095#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26820#L418 assume !(0 == ~M_E~0); 26821#L418-2 assume !(0 == ~T1_E~0); 27049#L423-1 assume !(0 == ~T2_E~0); 27103#L428-1 assume !(0 == ~T3_E~0); 27101#L433-1 assume !(0 == ~E_1~0); 27084#L438-1 assume !(0 == ~E_2~0); 27002#L443-1 assume !(0 == ~E_3~0); 26996#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26958#L197 assume !(1 == ~m_pc~0); 26955#L197-2 is_master_triggered_~__retres1~0#1 := 0; 27130#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27038#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 27039#L510 assume !(0 != activate_threads_~tmp~1#1); 26799#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26800#L216 assume !(1 == ~t1_pc~0); 26850#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26851#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26882#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26801#L518 assume !(0 != activate_threads_~tmp___0~0#1); 26802#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27011#L235 assume !(1 == ~t2_pc~0); 27090#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26941#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26942#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27119#L526 assume !(0 != activate_threads_~tmp___1~0#1); 27120#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26925#L254 assume !(1 == ~t3_pc~0); 26859#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26860#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26812#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26813#L534 assume !(0 != activate_threads_~tmp___2~0#1); 26936#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26791#L461 assume !(1 == ~M_E~0); 26792#L461-2 assume !(1 == ~T1_E~0); 26856#L466-1 assume !(1 == ~T2_E~0); 27107#L471-1 assume !(1 == ~T3_E~0); 26883#L476-1 assume !(1 == ~E_1~0); 26884#L481-1 assume !(1 == ~E_2~0); 27032#L486-1 assume !(1 == ~E_3~0); 26900#L491-1 assume { :end_inline_reset_delta_events } true; 26901#L652-2 [2024-10-15 01:00:29,406 INFO L747 eck$LassoCheckResult]: Loop: 26901#L652-2 assume !false; 28087#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27470#L393-1 assume !false; 28085#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28083#L309 assume !(0 == ~m_st~0); 27290#L313 assume !(0 == ~t1_st~0); 27287#L317 assume !(0 == ~t2_st~0); 27283#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 27280#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27277#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27268#L346 assume !(0 != eval_~tmp~0#1); 27269#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28288#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28287#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28286#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28285#L423-3 assume !(0 == ~T2_E~0); 28284#L428-3 assume !(0 == ~T3_E~0); 28283#L433-3 assume !(0 == ~E_1~0); 28282#L438-3 assume !(0 == ~E_2~0); 28281#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28280#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28279#L197-12 assume 1 == ~m_pc~0; 28276#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28274#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28273#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28271#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28269#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28266#L216-12 assume !(1 == ~t1_pc~0); 28264#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 28261#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28260#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28259#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 28257#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28255#L235-12 assume !(1 == ~t2_pc~0); 28252#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 28250#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28249#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28248#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28247#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28246#L254-12 assume !(1 == ~t3_pc~0); 28245#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 28243#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28242#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28241#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28240#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28238#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28237#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28235#L466-3 assume !(1 == ~T2_E~0); 28233#L471-3 assume !(1 == ~T3_E~0); 28232#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27226#L481-3 assume !(1 == ~E_2~0); 27224#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27225#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27219#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27220#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28133#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 28109#L671 assume !(0 == start_simulation_~tmp~3#1); 28107#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28104#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28102#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28100#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 28098#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28095#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28093#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 28091#L684 assume !(0 != start_simulation_~tmp___0~1#1); 26901#L652-2 [2024-10-15 01:00:29,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,406 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 6 times [2024-10-15 01:00:29,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698894994] [2024-10-15 01:00:29,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,414 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:29,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,424 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:29,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,425 INFO L85 PathProgramCache]: Analyzing trace with hash 220389978, now seen corresponding path program 1 times [2024-10-15 01:00:29,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433917404] [2024-10-15 01:00:29,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:29,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:29,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:29,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433917404] [2024-10-15 01:00:29,477 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1433917404] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:29,477 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:29,477 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 01:00:29,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137141210] [2024-10-15 01:00:29,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:29,478 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:29,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:29,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 01:00:29,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-15 01:00:29,479 INFO L87 Difference]: Start difference. First operand 1670 states and 2191 transitions. cyclomatic complexity: 525 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:29,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:29,558 INFO L93 Difference]: Finished difference Result 1682 states and 2174 transitions. [2024-10-15 01:00:29,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1682 states and 2174 transitions. [2024-10-15 01:00:29,564 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1616 [2024-10-15 01:00:29,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1682 states to 1682 states and 2174 transitions. [2024-10-15 01:00:29,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1682 [2024-10-15 01:00:29,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1682 [2024-10-15 01:00:29,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1682 states and 2174 transitions. [2024-10-15 01:00:29,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:29,575 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1682 states and 2174 transitions. [2024-10-15 01:00:29,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1682 states and 2174 transitions. [2024-10-15 01:00:29,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1682 to 1682. [2024-10-15 01:00:29,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1682 states, 1682 states have (on average 1.2925089179548157) internal successors, (2174), 1681 states have internal predecessors, (2174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:29,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1682 states to 1682 states and 2174 transitions. [2024-10-15 01:00:29,643 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1682 states and 2174 transitions. [2024-10-15 01:00:29,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 01:00:29,645 INFO L425 stractBuchiCegarLoop]: Abstraction has 1682 states and 2174 transitions. [2024-10-15 01:00:29,645 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-15 01:00:29,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1682 states and 2174 transitions. [2024-10-15 01:00:29,650 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1616 [2024-10-15 01:00:29,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:29,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:29,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:29,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:29,651 INFO L745 eck$LassoCheckResult]: Stem: 30440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 30441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 30455#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30452#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30419#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 30420#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30213#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30214#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30466#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30185#L418 assume !(0 == ~M_E~0); 30186#L418-2 assume !(0 == ~T1_E~0); 30418#L423-1 assume !(0 == ~T2_E~0); 30472#L428-1 assume !(0 == ~T3_E~0); 30470#L433-1 assume !(0 == ~E_1~0); 30459#L438-1 assume !(0 == ~E_2~0); 30370#L443-1 assume !(0 == ~E_3~0); 30363#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30320#L197 assume !(1 == ~m_pc~0); 30317#L197-2 is_master_triggered_~__retres1~0#1 := 0; 30496#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30410#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 30411#L510 assume !(0 != activate_threads_~tmp~1#1); 30159#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30160#L216 assume !(1 == ~t1_pc~0); 30211#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30212#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30242#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30164#L518 assume !(0 != activate_threads_~tmp___0~0#1); 30165#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30379#L235 assume !(1 == ~t2_pc~0); 30464#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30303#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30304#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30490#L526 assume !(0 != activate_threads_~tmp___1~0#1); 30491#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30287#L254 assume !(1 == ~t3_pc~0); 30218#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30219#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30174#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30175#L534 assume !(0 != activate_threads_~tmp___2~0#1); 30295#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30151#L461 assume !(1 == ~M_E~0); 30152#L461-2 assume !(1 == ~T1_E~0); 30215#L466-1 assume !(1 == ~T2_E~0); 30478#L471-1 assume !(1 == ~T3_E~0); 30245#L476-1 assume !(1 == ~E_1~0); 30246#L481-1 assume !(1 == ~E_2~0); 30398#L486-1 assume !(1 == ~E_3~0); 30263#L491-1 assume { :end_inline_reset_delta_events } true; 30264#L652-2 [2024-10-15 01:00:29,651 INFO L747 eck$LassoCheckResult]: Loop: 30264#L652-2 assume !false; 30754#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30751#L393-1 assume !false; 30749#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30746#L309 assume !(0 == ~m_st~0); 30747#L313 assume !(0 == ~t1_st~0); 30856#L317 assume !(0 == ~t2_st~0); 30857#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 30858#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30850#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30851#L346 assume !(0 != eval_~tmp~0#1); 31040#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31038#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31035#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31033#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31031#L423-3 assume !(0 == ~T2_E~0); 31026#L428-3 assume !(0 == ~T3_E~0); 31024#L433-3 assume !(0 == ~E_1~0); 31022#L438-3 assume !(0 == ~E_2~0); 31019#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31017#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31015#L197-12 assume 1 == ~m_pc~0; 31010#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31008#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31006#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 31004#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31001#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31000#L216-12 assume !(1 == ~t1_pc~0); 30999#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 30996#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30995#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30990#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 30988#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30986#L235-12 assume !(1 == ~t2_pc~0); 30983#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 30981#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30979#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30977#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 30975#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30972#L254-12 assume !(1 == ~t3_pc~0); 30970#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 30968#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30966#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30964#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30962#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30960#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30958#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30956#L466-3 assume !(1 == ~T2_E~0); 30954#L471-3 assume !(1 == ~T3_E~0); 30952#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30950#L481-3 assume !(1 == ~E_2~0); 30948#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30946#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30943#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30941#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30939#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 30933#L671 assume !(0 == start_simulation_~tmp~3#1); 30931#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30929#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30927#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 30923#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30921#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30919#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 30916#L684 assume !(0 != start_simulation_~tmp___0~1#1); 30264#L652-2 [2024-10-15 01:00:29,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,651 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 7 times [2024-10-15 01:00:29,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405785422] [2024-10-15 01:00:29,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,660 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:29,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:29,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,669 INFO L85 PathProgramCache]: Analyzing trace with hash -289083112, now seen corresponding path program 1 times [2024-10-15 01:00:29,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666435921] [2024-10-15 01:00:29,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:29,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:29,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:29,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666435921] [2024-10-15 01:00:29,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666435921] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:29,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:29,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-15 01:00:29,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791557807] [2024-10-15 01:00:29,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:29,727 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-15 01:00:29,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:29,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-15 01:00:29,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-15 01:00:29,728 INFO L87 Difference]: Start difference. First operand 1682 states and 2174 transitions. cyclomatic complexity: 496 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:29,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:29,825 INFO L93 Difference]: Finished difference Result 1730 states and 2205 transitions. [2024-10-15 01:00:29,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1730 states and 2205 transitions. [2024-10-15 01:00:29,831 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1664 [2024-10-15 01:00:29,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1730 states to 1730 states and 2205 transitions. [2024-10-15 01:00:29,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1730 [2024-10-15 01:00:29,839 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1730 [2024-10-15 01:00:29,839 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1730 states and 2205 transitions. [2024-10-15 01:00:29,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-15 01:00:29,841 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1730 states and 2205 transitions. [2024-10-15 01:00:29,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1730 states and 2205 transitions. [2024-10-15 01:00:29,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1730 to 1730. [2024-10-15 01:00:29,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1730 states, 1730 states have (on average 1.2745664739884393) internal successors, (2205), 1729 states have internal predecessors, (2205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:29,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1730 states to 1730 states and 2205 transitions. [2024-10-15 01:00:29,865 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1730 states and 2205 transitions. [2024-10-15 01:00:29,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-15 01:00:29,866 INFO L425 stractBuchiCegarLoop]: Abstraction has 1730 states and 2205 transitions. [2024-10-15 01:00:29,866 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-15 01:00:29,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1730 states and 2205 transitions. [2024-10-15 01:00:29,871 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1664 [2024-10-15 01:00:29,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:29,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:29,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:29,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:29,872 INFO L745 eck$LassoCheckResult]: Stem: 33852#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 33853#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 33867#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33865#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33835#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 33836#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33632#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33633#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33879#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33602#L418 assume !(0 == ~M_E~0); 33603#L418-2 assume !(0 == ~T1_E~0); 33834#L423-1 assume !(0 == ~T2_E~0); 33884#L428-1 assume !(0 == ~T3_E~0); 33882#L433-1 assume !(0 == ~E_1~0); 33869#L438-1 assume !(0 == ~E_2~0); 33791#L443-1 assume !(0 == ~E_3~0); 33782#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33739#L197 assume !(1 == ~m_pc~0); 33736#L197-2 is_master_triggered_~__retres1~0#1 := 0; 33908#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33826#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 33827#L510 assume !(0 != activate_threads_~tmp~1#1); 33579#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33580#L216 assume !(1 == ~t1_pc~0); 33630#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33631#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33661#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33581#L518 assume !(0 != activate_threads_~tmp___0~0#1); 33582#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33799#L235 assume !(1 == ~t2_pc~0); 33876#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33724#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33725#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33897#L526 assume !(0 != activate_threads_~tmp___1~0#1); 33898#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33705#L254 assume !(1 == ~t3_pc~0); 33637#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33638#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33592#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33593#L534 assume !(0 != activate_threads_~tmp___2~0#1); 33716#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33571#L461 assume !(1 == ~M_E~0); 33572#L461-2 assume !(1 == ~T1_E~0); 33634#L466-1 assume !(1 == ~T2_E~0); 33890#L471-1 assume !(1 == ~T3_E~0); 33664#L476-1 assume !(1 == ~E_1~0); 33665#L481-1 assume !(1 == ~E_2~0); 33816#L486-1 assume !(1 == ~E_3~0); 33683#L491-1 assume { :end_inline_reset_delta_events } true; 33684#L652-2 [2024-10-15 01:00:29,873 INFO L747 eck$LassoCheckResult]: Loop: 33684#L652-2 assume !false; 33966#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33965#L393-1 assume !false; 33964#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 33962#L309 assume !(0 == ~m_st~0); 33963#L313 assume !(0 == ~t1_st~0); 34377#L317 assume !(0 == ~t2_st~0); 34375#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 34374#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34371#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34369#L346 assume !(0 != eval_~tmp~0#1); 34367#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34364#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34362#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34360#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34357#L423-3 assume !(0 == ~T2_E~0); 34355#L428-3 assume !(0 == ~T3_E~0); 34319#L433-3 assume !(0 == ~E_1~0); 34317#L438-3 assume !(0 == ~E_2~0); 34315#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34313#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34311#L197-12 assume 1 == ~m_pc~0; 34308#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34306#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34304#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 34301#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34299#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34296#L216-12 assume !(1 == ~t1_pc~0); 34294#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 34292#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34289#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 34287#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 34285#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34283#L235-12 assume !(1 == ~t2_pc~0); 34280#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 34237#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34236#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34235#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 34234#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34219#L254-12 assume !(1 == ~t3_pc~0); 34194#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 34188#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34177#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34171#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 34166#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34127#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34120#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34113#L466-3 assume !(1 == ~T2_E~0); 34106#L471-3 assume !(1 == ~T3_E~0); 34098#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34092#L481-3 assume !(1 == ~E_2~0); 34086#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34079#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34071#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34064#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34056#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 34050#L671 assume !(0 == start_simulation_~tmp~3#1); 34046#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34040#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34036#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34029#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 34024#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34020#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34016#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 34009#L684 assume !(0 != start_simulation_~tmp___0~1#1); 33684#L652-2 [2024-10-15 01:00:29,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,873 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 8 times [2024-10-15 01:00:29,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240765963] [2024-10-15 01:00:29,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,881 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:29,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:29,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,890 INFO L85 PathProgramCache]: Analyzing trace with hash -70228394, now seen corresponding path program 1 times [2024-10-15 01:00:29,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429738286] [2024-10-15 01:00:29,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,899 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:29,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:29,909 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:29,910 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:29,910 INFO L85 PathProgramCache]: Analyzing trace with hash 242449541, now seen corresponding path program 1 times [2024-10-15 01:00:29,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:29,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539734123] [2024-10-15 01:00:29,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:29,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:29,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:29,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:29,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:29,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539734123] [2024-10-15 01:00:29,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539734123] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:29,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:29,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:29,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870633565] [2024-10-15 01:00:29,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:30,621 INFO L204 LassoAnalysis]: Preferences: [2024-10-15 01:00:30,622 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-15 01:00:30,622 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-15 01:00:30,622 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-15 01:00:30,622 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-15 01:00:30,622 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:30,622 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-15 01:00:30,623 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-15 01:00:30,623 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration18_Loop [2024-10-15 01:00:30,623 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-15 01:00:30,623 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-15 01:00:30,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,675 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,682 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,718 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,766 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,795 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:30,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,184 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-15 01:00:31,185 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-15 01:00:31,187 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,188 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,190 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,191 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-15 01:00:31,192 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,192 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,213 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,214 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,252 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-10-15 01:00:31,254 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,254 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,256 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,257 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-15 01:00:31,259 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,260 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,282 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,283 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=4} Honda state: {~t2_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,298 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-10-15 01:00:31,299 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,299 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,301 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,302 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-15 01:00:31,304 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,304 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,320 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,321 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,336 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-10-15 01:00:31,337 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,337 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,338 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,340 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-15 01:00:31,342 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,342 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,360 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,360 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret10#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,376 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:31,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,377 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,378 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,380 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-10-15 01:00:31,383 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,384 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,398 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,398 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,414 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-10-15 01:00:31,415 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,415 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,417 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,419 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-10-15 01:00:31,420 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,420 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,436 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,436 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,452 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:31,453 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,453 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,455 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,457 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-10-15 01:00:31,458 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,458 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,476 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,476 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,492 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-10-15 01:00:31,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,493 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,494 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,497 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-10-15 01:00:31,500 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,500 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,515 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,516 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,532 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-10-15 01:00:31,533 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,533 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,535 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,537 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-10-15 01:00:31,538 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,539 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,557 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,557 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret12#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret12#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,573 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-10-15 01:00:31,574 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,574 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,576 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,578 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-10-15 01:00:31,580 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,580 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,603 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,603 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,619 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-10-15 01:00:31,619 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,619 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,621 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,623 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-10-15 01:00:31,624 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,624 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,638 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,638 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,654 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-10-15 01:00:31,654 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,654 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,656 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,657 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-10-15 01:00:31,659 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,659 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,682 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:31,682 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:31,698 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:31,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,699 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,701 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,702 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-10-15 01:00:31,704 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:31,704 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,734 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-10-15 01:00:31,735 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,736 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:31,738 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:31,740 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-10-15 01:00:31,742 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-15 01:00:31,742 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:31,757 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-15 01:00:31,768 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-10-15 01:00:31,768 INFO L204 LassoAnalysis]: Preferences: [2024-10-15 01:00:31,768 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-15 01:00:31,768 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-15 01:00:31,768 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-15 01:00:31,769 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-15 01:00:31,769 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:31,769 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-15 01:00:31,769 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-15 01:00:31,769 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration18_Loop [2024-10-15 01:00:31,769 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-15 01:00:31,769 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-15 01:00:31,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,779 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,808 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,816 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,842 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,867 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,899 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,903 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,905 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,907 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,911 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,917 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,918 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,920 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,923 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,933 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:31,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:32,234 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-15 01:00:32,241 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-15 01:00:32,242 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,242 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,244 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,245 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-10-15 01:00:32,246 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,258 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,258 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,259 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,259 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,259 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,261 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,261 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,263 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,278 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-10-15 01:00:32,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,279 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,281 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,282 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-10-15 01:00:32,284 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,296 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,297 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,297 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,297 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,297 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,298 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,298 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,300 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,312 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:32,313 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,313 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,314 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,315 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-10-15 01:00:32,317 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,328 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,328 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,328 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,328 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-15 01:00:32,328 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,329 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-15 01:00:32,329 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,331 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,347 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-10-15 01:00:32,347 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,347 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,349 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,351 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-10-15 01:00:32,352 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,365 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,365 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,365 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,365 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,365 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,366 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,366 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,368 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,383 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-10-15 01:00:32,383 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,384 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,385 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,387 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-10-15 01:00:32,388 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,400 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,401 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,401 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,401 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,401 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,402 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,402 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,403 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,418 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-10-15 01:00:32,419 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,419 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,420 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,422 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-10-15 01:00:32,423 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,436 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,436 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,436 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,436 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,436 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,437 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,437 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,440 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,455 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:32,456 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,456 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,458 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,459 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-10-15 01:00:32,460 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,472 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,472 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,473 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,473 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,473 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,474 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,474 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,477 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,491 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:32,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,492 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,493 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,494 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-10-15 01:00:32,495 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,508 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,508 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,508 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,508 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,509 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,509 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,509 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,512 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,526 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-10-15 01:00:32,527 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,527 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,529 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,530 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-10-15 01:00:32,531 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,540 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,541 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,541 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,541 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,541 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,541 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,541 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,543 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,557 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-10-15 01:00:32,558 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,558 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,560 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,561 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-10-15 01:00:32,562 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,574 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,575 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,575 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,575 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,575 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,576 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,576 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,580 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,595 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-10-15 01:00:32,596 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,596 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,598 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,601 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-10-15 01:00:32,602 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,614 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,615 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,615 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,615 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-15 01:00:32,615 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,616 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-15 01:00:32,616 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,620 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,635 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-10-15 01:00:32,636 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,636 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,637 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,639 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-10-15 01:00:32,642 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,653 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,653 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,653 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,653 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-15 01:00:32,653 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,656 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-15 01:00:32,656 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,659 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:32,673 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:32,674 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,674 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,675 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,676 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-10-15 01:00:32,677 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:32,687 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:32,687 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:32,687 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:32,687 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:32,687 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:32,688 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:32,688 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:32,690 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-15 01:00:32,693 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-15 01:00:32,693 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-15 01:00:32,695 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:32,695 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:32,696 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:32,697 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-10-15 01:00:32,698 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-15 01:00:32,698 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-15 01:00:32,698 INFO L474 LassoAnalysis]: Proved termination. [2024-10-15 01:00:32,699 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2024-10-15 01:00:32,709 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2024-10-15 01:00:32,712 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-15 01:00:32,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:32,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:32,774 INFO L255 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-15 01:00:32,776 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 01:00:32,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:32,871 INFO L255 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-15 01:00:32,874 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 01:00:33,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:33,064 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-10-15 01:00:33,065 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1730 states and 2205 transitions. cyclomatic complexity: 479 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:33,193 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1730 states and 2205 transitions. cyclomatic complexity: 479. Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 4580 states and 5868 transitions. Complement of second has 5 states. [2024-10-15 01:00:33,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-15 01:00:33,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:33,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 356 transitions. [2024-10-15 01:00:33,199 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 356 transitions. Stem has 49 letters. Loop has 65 letters. [2024-10-15 01:00:33,201 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 01:00:33,202 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 356 transitions. Stem has 114 letters. Loop has 65 letters. [2024-10-15 01:00:33,203 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 01:00:33,203 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 356 transitions. Stem has 49 letters. Loop has 130 letters. [2024-10-15 01:00:33,207 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 01:00:33,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4580 states and 5868 transitions. [2024-10-15 01:00:33,230 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3048 [2024-10-15 01:00:33,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4580 states to 4572 states and 5860 transitions. [2024-10-15 01:00:33,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3135 [2024-10-15 01:00:33,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3156 [2024-10-15 01:00:33,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4572 states and 5860 transitions. [2024-10-15 01:00:33,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-15 01:00:33,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4572 states and 5860 transitions. [2024-10-15 01:00:33,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4572 states and 5860 transitions. [2024-10-15 01:00:33,325 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2024-10-15 01:00:33,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4572 to 4543. [2024-10-15 01:00:33,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4543 states, 4543 states have (on average 1.2817521461589259) internal successors, (5823), 4542 states have internal predecessors, (5823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:33,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4543 states to 4543 states and 5823 transitions. [2024-10-15 01:00:33,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4543 states and 5823 transitions. [2024-10-15 01:00:33,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:33,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:33,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:33,374 INFO L87 Difference]: Start difference. First operand 4543 states and 5823 transitions. Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:33,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:33,425 INFO L93 Difference]: Finished difference Result 4867 states and 6147 transitions. [2024-10-15 01:00:33,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4867 states and 6147 transitions. [2024-10-15 01:00:33,446 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3264 [2024-10-15 01:00:33,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4867 states to 4867 states and 6147 transitions. [2024-10-15 01:00:33,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3343 [2024-10-15 01:00:33,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3343 [2024-10-15 01:00:33,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4867 states and 6147 transitions. [2024-10-15 01:00:33,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-15 01:00:33,478 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4867 states and 6147 transitions. [2024-10-15 01:00:33,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4867 states and 6147 transitions. [2024-10-15 01:00:33,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4867 to 4543. [2024-10-15 01:00:33,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4543 states, 4543 states have (on average 1.271186440677966) internal successors, (5775), 4542 states have internal predecessors, (5775), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:33,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4543 states to 4543 states and 5775 transitions. [2024-10-15 01:00:33,567 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4543 states and 5775 transitions. [2024-10-15 01:00:33,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:33,568 INFO L425 stractBuchiCegarLoop]: Abstraction has 4543 states and 5775 transitions. [2024-10-15 01:00:33,568 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-15 01:00:33,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4543 states and 5775 transitions. [2024-10-15 01:00:33,584 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3048 [2024-10-15 01:00:33,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:33,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:33,585 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:33,585 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:33,585 INFO L745 eck$LassoCheckResult]: Stem: 50172#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 50173#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 50200#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50194#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50142#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 50143#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49762#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49763#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50225#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49703#L418 assume !(0 == ~M_E~0); 49704#L418-2 assume !(0 == ~T1_E~0); 50141#L423-1 assume !(0 == ~T2_E~0); 50235#L428-1 assume !(0 == ~T3_E~0); 50233#L433-1 assume !(0 == ~E_1~0); 50206#L438-1 assume !(0 == ~E_2~0); 50058#L443-1 assume !(0 == ~E_3~0); 50043#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49960#L197 assume !(1 == ~m_pc~0); 49955#L197-2 is_master_triggered_~__retres1~0#1 := 0; 50280#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50302#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 50258#L510 assume !(0 != activate_threads_~tmp~1#1); 49667#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49668#L216 assume !(1 == ~t1_pc~0); 49756#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49757#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49813#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 49669#L518 assume !(0 != activate_threads_~tmp___0~0#1); 49670#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50073#L235 assume !(1 == ~t2_pc~0); 50219#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49931#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49932#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50268#L526 assume !(0 != activate_threads_~tmp___1~0#1); 50269#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49896#L254 assume !(1 == ~t3_pc~0); 49768#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49769#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49689#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 49690#L534 assume !(0 != activate_threads_~tmp___2~0#1); 49917#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49655#L461 assume !(1 == ~M_E~0); 49656#L461-2 assume !(1 == ~T1_E~0); 49764#L466-1 assume !(1 == ~T2_E~0); 50246#L471-1 assume !(1 == ~T3_E~0); 49814#L476-1 assume !(1 == ~E_1~0); 49815#L481-1 assume !(1 == ~E_2~0); 50111#L486-1 assume !(1 == ~E_3~0); 49846#L491-1 assume { :end_inline_reset_delta_events } true; 49847#L652-2 assume !false; 51012#L653 [2024-10-15 01:00:33,586 INFO L747 eck$LassoCheckResult]: Loop: 51012#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52478#L393-1 assume !false; 52476#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52474#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 52472#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52471#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 52470#L346 assume 0 != eval_~tmp~0#1; 52469#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 52467#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 52463#L53 assume !(0 == ~m_pc~0); 52459#L56 assume 1 == ~m_pc~0; 52455#$Ultimate##157 assume !false; 52373#L73 ~m_pc~0 := 1;~m_st~0 := 2; 52368#master_returnLabel#1 assume { :end_inline_master } true; 52362#L354-2 havoc eval_~tmp_ndt_1~0#1; 52358#L351-1 assume !(0 == ~t1_st~0); 52352#L365-1 assume !(0 == ~t2_st~0); 52347#L379-1 assume !(0 == ~t3_st~0); 52348#L393-1 assume !false; 52607#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52605#L309 assume !(0 == ~m_st~0); 52596#L313 assume !(0 == ~t1_st~0); 52597#L317 assume !(0 == ~t2_st~0); 52598#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 52599#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 53072#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53070#L346 assume !(0 != eval_~tmp~0#1); 53068#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53066#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53065#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53064#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53063#L423-3 assume !(0 == ~T2_E~0); 53062#L428-3 assume !(0 == ~T3_E~0); 53061#L433-3 assume !(0 == ~E_1~0); 53060#L438-3 assume !(0 == ~E_2~0); 53059#L443-3 assume !(0 == ~E_3~0); 53058#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53056#L197-12 assume 1 == ~m_pc~0; 53053#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 53051#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53049#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 53048#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53047#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53046#L216-12 assume !(1 == ~t1_pc~0); 53044#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 53041#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53039#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 53037#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 53033#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53031#L235-12 assume !(1 == ~t2_pc~0); 53028#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 53026#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53024#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53022#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 53020#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53018#L254-12 assume !(1 == ~t3_pc~0); 53015#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 53013#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53011#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53009#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 53007#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53005#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53003#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53001#L466-3 assume !(1 == ~T2_E~0); 52999#L471-3 assume !(1 == ~T3_E~0); 52997#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52995#L481-3 assume !(1 == ~E_2~0); 52993#L486-3 assume !(1 == ~E_3~0); 52991#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52989#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 52987#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52985#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 52979#L671 assume !(0 == start_simulation_~tmp~3#1); 52976#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52975#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 52974#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52973#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 52972#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52971#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52970#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 52969#L684 assume !(0 != start_simulation_~tmp___0~1#1); 52968#L652-2 assume !false; 51012#L653 [2024-10-15 01:00:33,586 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:33,586 INFO L85 PathProgramCache]: Analyzing trace with hash -1276375252, now seen corresponding path program 1 times [2024-10-15 01:00:33,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:33,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989036000] [2024-10-15 01:00:33,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:33,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:33,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:33,595 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:33,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:33,613 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:33,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:33,614 INFO L85 PathProgramCache]: Analyzing trace with hash -211325414, now seen corresponding path program 1 times [2024-10-15 01:00:33,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:33,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157044270] [2024-10-15 01:00:33,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:33,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:33,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:33,626 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:33,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:33,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:33,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:33,642 INFO L85 PathProgramCache]: Analyzing trace with hash 132337797, now seen corresponding path program 1 times [2024-10-15 01:00:33,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:33,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347364648] [2024-10-15 01:00:33,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:33,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:33,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:33,713 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:33,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:33,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347364648] [2024-10-15 01:00:33,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347364648] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:33,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:33,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 01:00:33,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503652040] [2024-10-15 01:00:33,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:34,350 INFO L204 LassoAnalysis]: Preferences: [2024-10-15 01:00:34,350 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-15 01:00:34,350 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-15 01:00:34,351 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-15 01:00:34,351 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-15 01:00:34,351 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:34,351 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-15 01:00:34,351 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-15 01:00:34,351 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration19_Loop [2024-10-15 01:00:34,351 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-15 01:00:34,351 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-15 01:00:34,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,358 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,360 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,362 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,369 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,374 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,376 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,381 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,383 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,385 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,392 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,395 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,398 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,408 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,415 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,420 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,429 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,438 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,442 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,449 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,456 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,463 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,467 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,471 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,474 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,478 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,481 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,512 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,517 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,519 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,521 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,523 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,527 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:34,812 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-15 01:00:34,812 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-15 01:00:34,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:34,812 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:34,814 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:34,820 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:34,820 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:34,824 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-10-15 01:00:34,835 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:34,836 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:34,851 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:34,851 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:34,852 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:34,853 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:34,854 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-10-15 01:00:34,856 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:34,856 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:34,870 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:34,871 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:34,885 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:34,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:34,886 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:34,888 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:34,889 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-10-15 01:00:34,891 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:34,891 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:34,906 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:34,906 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet8#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:34,921 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:34,922 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:34,922 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:34,924 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:34,925 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-10-15 01:00:34,926 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:34,926 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:34,942 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:34,942 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:34,957 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:34,958 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:34,958 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:34,960 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:34,961 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-10-15 01:00:34,962 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:34,962 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:34,981 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:34,981 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~4#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:34,996 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2024-10-15 01:00:34,997 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:34,997 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:34,999 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,000 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2024-10-15 01:00:35,001 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,001 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,020 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:35,020 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-1} Honda state: {~E_3~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:35,031 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,031 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,032 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,033 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,034 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2024-10-15 01:00:35,035 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,035 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,046 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:35,046 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:35,056 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2024-10-15 01:00:35,057 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,057 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,058 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,060 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2024-10-15 01:00:35,060 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,060 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,078 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:35,078 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=4} Honda state: {~t2_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:35,089 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,089 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,089 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,090 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,091 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2024-10-15 01:00:35,092 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,092 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,103 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:35,103 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet5#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet5#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:35,114 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2024-10-15 01:00:35,115 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,115 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,116 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,117 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2024-10-15 01:00:35,117 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,117 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,128 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:35,128 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:35,140 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,140 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,141 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,142 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2024-10-15 01:00:35,143 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,143 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,162 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:35,162 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:35,174 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,174 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,174 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,175 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,176 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2024-10-15 01:00:35,177 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,177 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,192 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:35,192 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret4#1=0} Honda state: {ULTIMATE.start_eval_#t~ret4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:35,207 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Ended with exit code 0 [2024-10-15 01:00:35,208 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,208 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,210 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,212 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2024-10-15 01:00:35,213 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,213 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,226 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-15 01:00:35,226 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-15 01:00:35,236 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,237 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,237 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,238 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,239 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2024-10-15 01:00:35,240 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-15 01:00:35,240 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,261 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2024-10-15 01:00:35,262 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,262 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,263 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,264 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2024-10-15 01:00:35,265 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-15 01:00:35,265 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-15 01:00:35,280 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-15 01:00:35,291 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2024-10-15 01:00:35,292 INFO L204 LassoAnalysis]: Preferences: [2024-10-15 01:00:35,292 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-15 01:00:35,292 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-15 01:00:35,292 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-15 01:00:35,292 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-15 01:00:35,292 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,292 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-15 01:00:35,292 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-15 01:00:35,292 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration19_Loop [2024-10-15 01:00:35,292 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-15 01:00:35,292 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-15 01:00:35,294 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,300 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,304 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,309 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,311 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,313 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,315 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,316 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,327 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,331 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,333 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,335 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,343 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,348 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,350 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,352 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,360 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,365 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,367 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,369 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,373 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,376 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,381 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,383 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,385 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,391 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,395 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,400 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,402 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,404 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,406 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,408 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,418 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,420 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-15 01:00:35,701 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-15 01:00:35,701 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-15 01:00:35,701 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,701 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,703 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,705 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2024-10-15 01:00:35,706 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,716 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,716 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,716 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,716 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:35,717 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,717 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:35,717 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,718 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,729 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,729 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,729 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,730 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,731 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2024-10-15 01:00:35,732 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,742 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,742 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,743 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,743 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:35,743 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,743 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:35,743 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,745 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,755 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2024-10-15 01:00:35,756 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,756 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,757 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,758 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2024-10-15 01:00:35,758 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,769 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,769 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,769 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,769 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:35,769 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,770 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:35,770 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,772 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,784 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2024-10-15 01:00:35,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,784 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,785 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,786 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2024-10-15 01:00:35,787 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,796 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,797 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,797 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,797 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:35,797 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,797 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:35,797 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,800 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,812 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,813 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,813 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,815 INFO L229 MonitoredProcess]: Starting monitored process 49 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,817 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2024-10-15 01:00:35,817 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,830 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,830 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,830 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,830 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:35,830 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,831 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:35,831 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,833 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,849 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Ended with exit code 0 [2024-10-15 01:00:35,849 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,849 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,851 INFO L229 MonitoredProcess]: Starting monitored process 50 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,853 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2024-10-15 01:00:35,854 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,866 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,867 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,867 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,867 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-15 01:00:35,867 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,868 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-15 01:00:35,868 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,872 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,883 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,884 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,884 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,885 INFO L229 MonitoredProcess]: Starting monitored process 51 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,885 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2024-10-15 01:00:35,886 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,896 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,896 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,896 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,896 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:35,896 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,896 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:35,897 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,898 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,908 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,909 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,910 INFO L229 MonitoredProcess]: Starting monitored process 52 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,911 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2024-10-15 01:00:35,912 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,922 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,922 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,922 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,922 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-15 01:00:35,922 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,922 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-15 01:00:35,923 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,924 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,935 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Forceful destruction successful, exit code 0 [2024-10-15 01:00:35,935 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,936 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,937 INFO L229 MonitoredProcess]: Starting monitored process 53 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,937 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2024-10-15 01:00:35,938 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,948 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,948 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,948 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,948 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:35,948 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,949 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:35,949 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,950 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,961 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Ended with exit code 0 [2024-10-15 01:00:35,961 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,961 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,962 INFO L229 MonitoredProcess]: Starting monitored process 54 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,963 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2024-10-15 01:00:35,964 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,973 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:35,974 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:35,974 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:35,974 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:35,974 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:35,974 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:35,974 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:35,976 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:35,986 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Ended with exit code 0 [2024-10-15 01:00:35,986 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:35,987 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:35,988 INFO L229 MonitoredProcess]: Starting monitored process 55 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:35,989 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2024-10-15 01:00:35,990 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:35,999 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:36,000 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:36,000 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:36,000 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:36,000 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:36,000 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:36,001 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:36,002 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:36,017 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Ended with exit code 0 [2024-10-15 01:00:36,017 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:36,017 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:36,018 INFO L229 MonitoredProcess]: Starting monitored process 56 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:36,019 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2024-10-15 01:00:36,020 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:36,029 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:36,030 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:36,030 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:36,030 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:36,030 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:36,030 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:36,030 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:36,031 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:36,042 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Ended with exit code 0 [2024-10-15 01:00:36,042 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:36,042 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:36,044 INFO L229 MonitoredProcess]: Starting monitored process 57 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:36,044 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2024-10-15 01:00:36,045 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:36,055 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:36,055 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:36,055 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:36,056 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-15 01:00:36,056 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:36,056 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-15 01:00:36,056 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:36,058 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:36,069 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Ended with exit code 0 [2024-10-15 01:00:36,069 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:36,070 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:36,071 INFO L229 MonitoredProcess]: Starting monitored process 58 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:36,071 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Waiting until timeout for monitored process [2024-10-15 01:00:36,072 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:36,082 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:36,082 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:36,083 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:36,083 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:36,083 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:36,083 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:36,083 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:36,084 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-15 01:00:36,095 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Ended with exit code 0 [2024-10-15 01:00:36,095 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:36,096 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:36,097 INFO L229 MonitoredProcess]: Starting monitored process 59 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:36,097 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Waiting until timeout for monitored process [2024-10-15 01:00:36,098 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-15 01:00:36,108 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-15 01:00:36,108 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-15 01:00:36,108 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-15 01:00:36,108 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-15 01:00:36,108 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-15 01:00:36,109 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-15 01:00:36,109 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-15 01:00:36,111 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-15 01:00:36,113 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-15 01:00:36,113 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-15 01:00:36,113 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-15 01:00:36,113 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-15 01:00:36,114 INFO L229 MonitoredProcess]: Starting monitored process 60 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-15 01:00:36,115 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Waiting until timeout for monitored process [2024-10-15 01:00:36,116 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-15 01:00:36,116 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-15 01:00:36,116 INFO L474 LassoAnalysis]: Proved termination. [2024-10-15 01:00:36,116 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T1_E~0) = -1*~T1_E~0 + 1 Supporting invariants [] [2024-10-15 01:00:36,126 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Ended with exit code 0 [2024-10-15 01:00:36,127 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-15 01:00:36,140 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:36,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:36,168 INFO L255 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-15 01:00:36,169 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 01:00:36,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:36,254 INFO L255 TraceCheckSpWp]: Trace formula consists of 154 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-15 01:00:36,256 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-15 01:00:36,439 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-10-15 01:00:36,440 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-10-15 01:00:36,440 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 4543 states and 5775 transitions. cyclomatic complexity: 1244 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:36,517 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 4543 states and 5775 transitions. cyclomatic complexity: 1244. Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 9154 states and 11610 transitions. Complement of second has 4 states. [2024-10-15 01:00:36,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-15 01:00:36,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:36,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 397 transitions. [2024-10-15 01:00:36,519 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 397 transitions. Stem has 50 letters. Loop has 82 letters. [2024-10-15 01:00:36,520 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 01:00:36,520 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 397 transitions. Stem has 132 letters. Loop has 82 letters. [2024-10-15 01:00:36,520 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 01:00:36,520 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 397 transitions. Stem has 50 letters. Loop has 164 letters. [2024-10-15 01:00:36,521 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-15 01:00:36,521 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9154 states and 11610 transitions. [2024-10-15 01:00:36,558 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3048 [2024-10-15 01:00:36,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9154 states to 9154 states and 11610 transitions. [2024-10-15 01:00:36,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3148 [2024-10-15 01:00:36,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3189 [2024-10-15 01:00:36,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9154 states and 11610 transitions. [2024-10-15 01:00:36,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-15 01:00:36,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9154 states and 11610 transitions. [2024-10-15 01:00:36,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9154 states and 11610 transitions. [2024-10-15 01:00:36,647 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Ended with exit code 0 [2024-10-15 01:00:36,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9154 to 9113. [2024-10-15 01:00:36,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9113 states, 9113 states have (on average 1.2695051026006803) internal successors, (11569), 9112 states have internal predecessors, (11569), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:36,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9113 states to 9113 states and 11569 transitions. [2024-10-15 01:00:36,760 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9113 states and 11569 transitions. [2024-10-15 01:00:36,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:36,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:36,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:36,762 INFO L87 Difference]: Start difference. First operand 9113 states and 11569 transitions. Second operand has 3 states, 3 states have (on average 44.0) internal successors, (132), 2 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:36,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:36,826 INFO L93 Difference]: Finished difference Result 11337 states and 14252 transitions. [2024-10-15 01:00:36,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11337 states and 14252 transitions. [2024-10-15 01:00:36,868 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3812 [2024-10-15 01:00:36,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11337 states to 11337 states and 14252 transitions. [2024-10-15 01:00:36,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3928 [2024-10-15 01:00:36,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3928 [2024-10-15 01:00:36,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11337 states and 14252 transitions. [2024-10-15 01:00:36,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-15 01:00:36,906 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11337 states and 14252 transitions. [2024-10-15 01:00:36,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11337 states and 14252 transitions. [2024-10-15 01:00:37,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11337 to 10593. [2024-10-15 01:00:37,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10593 states, 10593 states have (on average 1.2661191352780137) internal successors, (13412), 10592 states have internal predecessors, (13412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:37,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10593 states to 10593 states and 13412 transitions. [2024-10-15 01:00:37,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10593 states and 13412 transitions. [2024-10-15 01:00:37,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:37,058 INFO L425 stractBuchiCegarLoop]: Abstraction has 10593 states and 13412 transitions. [2024-10-15 01:00:37,058 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-15 01:00:37,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10593 states and 13412 transitions. [2024-10-15 01:00:37,089 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3564 [2024-10-15 01:00:37,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:37,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:37,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:37,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:37,090 INFO L745 eck$LassoCheckResult]: Stem: 84757#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 84758#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 84787#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84779#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84722#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 84723#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84331#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84332#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84814#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84269#L418 assume !(0 == ~M_E~0); 84270#L418-2 assume !(0 == ~T1_E~0); 84721#L423-1 assume !(0 == ~T2_E~0); 84823#L428-1 assume !(0 == ~T3_E~0); 84821#L433-1 assume !(0 == ~E_1~0); 84794#L438-1 assume !(0 == ~E_2~0); 84622#L443-1 assume !(0 == ~E_3~0); 84607#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84524#L197 assume !(1 == ~m_pc~0); 84525#L197-2 is_master_triggered_~__retres1~0#1 := 0; 84875#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84702#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 84703#L510 assume !(0 != activate_threads_~tmp~1#1); 84233#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84234#L216 assume !(1 == ~t1_pc~0); 84325#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84326#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84380#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 84241#L518 assume !(0 != activate_threads_~tmp___0~0#1); 84242#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84638#L235 assume !(1 == ~t2_pc~0); 84807#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84496#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 84855#L526 assume !(0 != activate_threads_~tmp___1~0#1); 84856#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84468#L254 assume !(1 == ~t3_pc~0); 84337#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84338#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84255#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 84256#L534 assume !(0 != activate_threads_~tmp___2~0#1); 84483#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84219#L461 assume !(1 == ~M_E~0); 84220#L461-2 assume !(1 == ~T1_E~0); 84333#L466-1 assume !(1 == ~T2_E~0); 84837#L471-1 assume !(1 == ~T3_E~0); 84385#L476-1 assume !(1 == ~E_1~0); 84386#L481-1 assume !(1 == ~E_2~0); 84679#L486-1 assume !(1 == ~E_3~0); 84418#L491-1 assume { :end_inline_reset_delta_events } true; 84419#L652-2 assume !false; 85151#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85152#L393-1 [2024-10-15 01:00:37,090 INFO L747 eck$LassoCheckResult]: Loop: 85152#L393-1 assume !false; 85142#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 85138#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 85135#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 85130#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 85127#L346 assume 0 != eval_~tmp~0#1; 85123#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 85117#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 85118#L354-2 havoc eval_~tmp_ndt_1~0#1; 91258#L351-1 assume !(0 == ~t1_st~0); 91253#L365-1 assume !(0 == ~t2_st~0); 91250#L379-1 assume !(0 == ~t3_st~0); 85152#L393-1 [2024-10-15 01:00:37,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:37,091 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 1 times [2024-10-15 01:00:37,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:37,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391456772] [2024-10-15 01:00:37,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:37,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:37,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:37,101 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:37,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:37,114 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:37,115 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:37,115 INFO L85 PathProgramCache]: Analyzing trace with hash -1356345121, now seen corresponding path program 1 times [2024-10-15 01:00:37,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:37,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006953308] [2024-10-15 01:00:37,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:37,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:37,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:37,120 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:37,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:37,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:37,125 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:37,125 INFO L85 PathProgramCache]: Analyzing trace with hash 1338864530, now seen corresponding path program 1 times [2024-10-15 01:00:37,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:37,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669888400] [2024-10-15 01:00:37,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:37,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:37,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:37,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:37,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:37,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669888400] [2024-10-15 01:00:37,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669888400] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:37,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:37,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:37,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1023681893] [2024-10-15 01:00:37,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:37,201 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:37,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:37,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:37,202 INFO L87 Difference]: Start difference. First operand 10593 states and 13412 transitions. cyclomatic complexity: 2867 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:37,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:37,352 INFO L93 Difference]: Finished difference Result 18276 states and 22769 transitions. [2024-10-15 01:00:37,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18276 states and 22769 transitions. [2024-10-15 01:00:37,437 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 5738 [2024-10-15 01:00:37,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18276 states to 18276 states and 22769 transitions. [2024-10-15 01:00:37,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6394 [2024-10-15 01:00:37,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6394 [2024-10-15 01:00:37,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18276 states and 22769 transitions. [2024-10-15 01:00:37,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-15 01:00:37,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18276 states and 22769 transitions. [2024-10-15 01:00:37,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18276 states and 22769 transitions. [2024-10-15 01:00:37,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18276 to 17484. [2024-10-15 01:00:37,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17484 states, 17484 states have (on average 1.2497712194005948) internal successors, (21851), 17483 states have internal predecessors, (21851), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:37,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17484 states to 17484 states and 21851 transitions. [2024-10-15 01:00:37,785 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17484 states and 21851 transitions. [2024-10-15 01:00:37,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:37,786 INFO L425 stractBuchiCegarLoop]: Abstraction has 17484 states and 21851 transitions. [2024-10-15 01:00:37,786 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-15 01:00:37,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17484 states and 21851 transitions. [2024-10-15 01:00:37,831 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 5474 [2024-10-15 01:00:37,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:37,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:37,832 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:37,832 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:37,832 INFO L745 eck$LassoCheckResult]: Stem: 113631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 113632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 113658#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113599#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 113600#L281-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 113712#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118440#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118439#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118438#L418 assume !(0 == ~M_E~0); 118437#L418-2 assume !(0 == ~T1_E~0); 118436#L423-1 assume !(0 == ~T2_E~0); 118435#L428-1 assume !(0 == ~T3_E~0); 118434#L433-1 assume !(0 == ~E_1~0); 118433#L438-1 assume !(0 == ~E_2~0); 118432#L443-1 assume !(0 == ~E_3~0); 118431#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118430#L197 assume !(1 == ~m_pc~0); 118429#L197-2 is_master_triggered_~__retres1~0#1 := 0; 118428#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118427#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 118426#L510 assume !(0 != activate_threads_~tmp~1#1); 118425#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118424#L216 assume !(1 == ~t1_pc~0); 118423#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118422#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118421#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 118420#L518 assume !(0 != activate_threads_~tmp___0~0#1); 118419#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118418#L235 assume !(1 == ~t2_pc~0); 118416#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118415#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118414#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 118413#L526 assume !(0 != activate_threads_~tmp___1~0#1); 118412#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118411#L254 assume !(1 == ~t3_pc~0); 118410#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118409#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118408#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118407#L534 assume !(0 != activate_threads_~tmp___2~0#1); 118406#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118405#L461 assume !(1 == ~M_E~0); 118404#L461-2 assume !(1 == ~T1_E~0); 118403#L466-1 assume !(1 == ~T2_E~0); 118402#L471-1 assume !(1 == ~T3_E~0); 118401#L476-1 assume !(1 == ~E_1~0); 118400#L481-1 assume !(1 == ~E_2~0); 118399#L486-1 assume !(1 == ~E_3~0); 118398#L491-1 assume { :end_inline_reset_delta_events } true; 118396#L652-2 assume !false; 118383#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118381#L393-1 [2024-10-15 01:00:37,832 INFO L747 eck$LassoCheckResult]: Loop: 118381#L393-1 assume !false; 118379#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 118378#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 118376#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 118375#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 118374#L346 assume 0 != eval_~tmp~0#1; 118372#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 118369#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 118367#L354-2 havoc eval_~tmp_ndt_1~0#1; 118365#L351-1 assume !(0 == ~t1_st~0); 118361#L365-1 assume !(0 == ~t2_st~0); 118362#L379-1 assume !(0 == ~t3_st~0); 118381#L393-1 [2024-10-15 01:00:37,833 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:37,833 INFO L85 PathProgramCache]: Analyzing trace with hash 1015345778, now seen corresponding path program 1 times [2024-10-15 01:00:37,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:37,833 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652088305] [2024-10-15 01:00:37,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:37,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:37,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:37,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:37,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:37,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652088305] [2024-10-15 01:00:37,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652088305] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:37,859 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:37,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:37,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814109721] [2024-10-15 01:00:37,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:37,859 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-15 01:00:37,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:37,860 INFO L85 PathProgramCache]: Analyzing trace with hash -1356345121, now seen corresponding path program 2 times [2024-10-15 01:00:37,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:37,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839393269] [2024-10-15 01:00:37,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:37,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:37,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:37,864 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:37,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:37,866 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:37,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:37,906 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:37,907 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:37,907 INFO L87 Difference]: Start difference. First operand 17484 states and 21851 transitions. cyclomatic complexity: 4447 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:37,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:37,943 INFO L93 Difference]: Finished difference Result 11757 states and 14743 transitions. [2024-10-15 01:00:37,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11757 states and 14743 transitions. [2024-10-15 01:00:37,987 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3979 [2024-10-15 01:00:38,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11757 states to 11757 states and 14743 transitions. [2024-10-15 01:00:38,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4166 [2024-10-15 01:00:38,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4166 [2024-10-15 01:00:38,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11757 states and 14743 transitions. [2024-10-15 01:00:38,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-15 01:00:38,031 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11757 states and 14743 transitions. [2024-10-15 01:00:38,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11757 states and 14743 transitions. [2024-10-15 01:00:38,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11757 to 11757. [2024-10-15 01:00:38,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11757 states, 11757 states have (on average 1.2539763545122056) internal successors, (14743), 11756 states have internal predecessors, (14743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:38,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11757 states to 11757 states and 14743 transitions. [2024-10-15 01:00:38,295 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11757 states and 14743 transitions. [2024-10-15 01:00:38,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:38,398 INFO L425 stractBuchiCegarLoop]: Abstraction has 11757 states and 14743 transitions. [2024-10-15 01:00:38,399 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-15 01:00:38,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11757 states and 14743 transitions. [2024-10-15 01:00:38,433 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3979 [2024-10-15 01:00:38,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:38,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:38,434 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:38,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:38,435 INFO L745 eck$LassoCheckResult]: Stem: 142885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 142886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 142909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 142904#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 142849#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 142850#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 142454#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 142455#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 142930#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 142402#L418 assume !(0 == ~M_E~0); 142403#L418-2 assume !(0 == ~T1_E~0); 142848#L423-1 assume !(0 == ~T2_E~0); 142939#L428-1 assume !(0 == ~T3_E~0); 142937#L433-1 assume !(0 == ~E_1~0); 142913#L438-1 assume !(0 == ~E_2~0); 142752#L443-1 assume !(0 == ~E_3~0); 142734#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 142652#L197 assume !(1 == ~m_pc~0); 142653#L197-2 is_master_triggered_~__retres1~0#1 := 0; 142991#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 142830#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 142831#L510 assume !(0 != activate_threads_~tmp~1#1); 142357#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 142358#L216 assume !(1 == ~t1_pc~0); 142452#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 142453#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 142503#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 142365#L518 assume !(0 != activate_threads_~tmp___0~0#1); 142366#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 142771#L235 assume !(1 == ~t2_pc~0); 142928#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 142623#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 142624#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 142973#L526 assume !(0 != activate_threads_~tmp___1~0#1); 142974#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 142594#L254 assume !(1 == ~t3_pc~0); 142461#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 142462#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 142383#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 142384#L534 assume !(0 != activate_threads_~tmp___2~0#1); 142609#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 142343#L461 assume !(1 == ~M_E~0); 142344#L461-2 assume !(1 == ~T1_E~0); 142456#L466-1 assume !(1 == ~T2_E~0); 142951#L471-1 assume !(1 == ~T3_E~0); 142508#L476-1 assume !(1 == ~E_1~0); 142509#L481-1 assume !(1 == ~E_2~0); 142808#L486-1 assume !(1 == ~E_3~0); 142545#L491-1 assume { :end_inline_reset_delta_events } true; 142546#L652-2 assume !false; 148495#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 148494#L393-1 [2024-10-15 01:00:38,436 INFO L747 eck$LassoCheckResult]: Loop: 148494#L393-1 assume !false; 148493#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 148491#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 148489#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 148487#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 148486#L346 assume 0 != eval_~tmp~0#1; 148482#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 148479#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 148480#L354-2 havoc eval_~tmp_ndt_1~0#1; 148561#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 148556#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 148549#L368-2 havoc eval_~tmp_ndt_2~0#1; 148541#L365-1 assume !(0 == ~t2_st~0); 148497#L379-1 assume !(0 == ~t3_st~0); 148494#L393-1 [2024-10-15 01:00:38,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:38,436 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 2 times [2024-10-15 01:00:38,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:38,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255442228] [2024-10-15 01:00:38,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:38,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:38,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:38,444 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:38,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:38,455 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:38,457 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:38,457 INFO L85 PathProgramCache]: Analyzing trace with hash 2096165373, now seen corresponding path program 1 times [2024-10-15 01:00:38,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:38,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833868583] [2024-10-15 01:00:38,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:38,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:38,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:38,464 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:38,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:38,467 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:38,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:38,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1967606800, now seen corresponding path program 1 times [2024-10-15 01:00:38,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:38,467 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529496520] [2024-10-15 01:00:38,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:38,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:38,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:38,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:38,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:38,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529496520] [2024-10-15 01:00:38,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529496520] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:38,500 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:38,500 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-15 01:00:38,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170666877] [2024-10-15 01:00:38,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:38,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:38,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:38,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:38,548 INFO L87 Difference]: Start difference. First operand 11757 states and 14743 transitions. cyclomatic complexity: 3034 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:38,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:38,614 INFO L93 Difference]: Finished difference Result 19045 states and 23609 transitions. [2024-10-15 01:00:38,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19045 states and 23609 transitions. [2024-10-15 01:00:38,686 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6296 [2024-10-15 01:00:38,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19045 states to 19045 states and 23609 transitions. [2024-10-15 01:00:38,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6608 [2024-10-15 01:00:38,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6608 [2024-10-15 01:00:38,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19045 states and 23609 transitions. [2024-10-15 01:00:38,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-15 01:00:38,906 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19045 states and 23609 transitions. [2024-10-15 01:00:38,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19045 states and 23609 transitions. [2024-10-15 01:00:39,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19045 to 19045. [2024-10-15 01:00:39,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19045 states, 19045 states have (on average 1.2396429509057496) internal successors, (23609), 19044 states have internal predecessors, (23609), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:39,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19045 states to 19045 states and 23609 transitions. [2024-10-15 01:00:39,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19045 states and 23609 transitions. [2024-10-15 01:00:39,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:39,241 INFO L425 stractBuchiCegarLoop]: Abstraction has 19045 states and 23609 transitions. [2024-10-15 01:00:39,243 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-15 01:00:39,243 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19045 states and 23609 transitions. [2024-10-15 01:00:39,395 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6296 [2024-10-15 01:00:39,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:39,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:39,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:39,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:39,401 INFO L745 eck$LassoCheckResult]: Stem: 173712#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 173713#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 173741#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 173734#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 173675#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 173676#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173266#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 173267#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 173762#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173209#L418 assume !(0 == ~M_E~0); 173210#L418-2 assume !(0 == ~T1_E~0); 173674#L423-1 assume !(0 == ~T2_E~0); 173773#L428-1 assume !(0 == ~T3_E~0); 173771#L433-1 assume !(0 == ~E_1~0); 173747#L438-1 assume !(0 == ~E_2~0); 173579#L443-1 assume !(0 == ~E_3~0); 173560#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173467#L197 assume !(1 == ~m_pc~0); 173468#L197-2 is_master_triggered_~__retres1~0#1 := 0; 173826#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173656#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 173657#L510 assume !(0 != activate_threads_~tmp~1#1); 173167#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173168#L216 assume !(1 == ~t1_pc~0); 173264#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 173265#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173315#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 173173#L518 assume !(0 != activate_threads_~tmp___0~0#1); 173174#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 173599#L235 assume !(1 == ~t2_pc~0); 173755#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 173438#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 173439#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 173807#L526 assume !(0 != activate_threads_~tmp___1~0#1); 173808#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173405#L254 assume !(1 == ~t3_pc~0); 173273#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 173274#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 173191#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 173192#L534 assume !(0 != activate_threads_~tmp___2~0#1); 173422#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173153#L461 assume !(1 == ~M_E~0); 173154#L461-2 assume !(1 == ~T1_E~0); 173268#L466-1 assume !(1 == ~T2_E~0); 173786#L471-1 assume !(1 == ~T3_E~0); 173320#L476-1 assume !(1 == ~E_1~0); 173321#L481-1 assume !(1 == ~E_2~0); 173635#L486-1 assume !(1 == ~E_3~0); 173357#L491-1 assume { :end_inline_reset_delta_events } true; 173358#L652-2 assume !false; 176319#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 176825#L393-1 [2024-10-15 01:00:39,401 INFO L747 eck$LassoCheckResult]: Loop: 176825#L393-1 assume !false; 184236#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 184234#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 184232#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 184230#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 184228#L346 assume 0 != eval_~tmp~0#1; 184226#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 184223#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 184224#L354-2 havoc eval_~tmp_ndt_1~0#1; 184249#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 184247#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 184246#L368-2 havoc eval_~tmp_ndt_2~0#1; 184245#L365-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 184058#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 184242#L382-2 havoc eval_~tmp_ndt_3~0#1; 184240#L379-1 assume !(0 == ~t3_st~0); 176825#L393-1 [2024-10-15 01:00:39,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:39,401 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 3 times [2024-10-15 01:00:39,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:39,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218904679] [2024-10-15 01:00:39,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:39,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:39,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:39,416 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:39,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:39,435 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:39,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:39,436 INFO L85 PathProgramCache]: Analyzing trace with hash 71302111, now seen corresponding path program 1 times [2024-10-15 01:00:39,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:39,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73575927] [2024-10-15 01:00:39,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:39,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:39,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:39,440 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:39,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:39,444 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:39,444 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:39,444 INFO L85 PathProgramCache]: Analyzing trace with hash -1088484078, now seen corresponding path program 1 times [2024-10-15 01:00:39,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:39,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267291565] [2024-10-15 01:00:39,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:39,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:39,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-15 01:00:39,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-15 01:00:39,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-15 01:00:39,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267291565] [2024-10-15 01:00:39,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267291565] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-15 01:00:39,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-15 01:00:39,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-15 01:00:39,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960801717] [2024-10-15 01:00:39,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-15 01:00:39,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-15 01:00:39,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-15 01:00:39,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-15 01:00:39,524 INFO L87 Difference]: Start difference. First operand 19045 states and 23609 transitions. cyclomatic complexity: 4612 Second operand has 3 states, 2 states have (on average 33.5) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:39,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-15 01:00:39,653 INFO L93 Difference]: Finished difference Result 24493 states and 30294 transitions. [2024-10-15 01:00:39,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24493 states and 30294 transitions. [2024-10-15 01:00:39,743 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8139 [2024-10-15 01:00:39,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24493 states to 24493 states and 30294 transitions. [2024-10-15 01:00:39,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8554 [2024-10-15 01:00:39,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8554 [2024-10-15 01:00:39,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24493 states and 30294 transitions. [2024-10-15 01:00:39,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-15 01:00:39,841 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24493 states and 30294 transitions. [2024-10-15 01:00:39,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24493 states and 30294 transitions. [2024-10-15 01:00:40,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24493 to 24493. [2024-10-15 01:00:40,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24493 states, 24493 states have (on average 1.2368431796839914) internal successors, (30294), 24492 states have internal predecessors, (30294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-15 01:00:40,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24493 states to 24493 states and 30294 transitions. [2024-10-15 01:00:40,333 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24493 states and 30294 transitions. [2024-10-15 01:00:40,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-15 01:00:40,334 INFO L425 stractBuchiCegarLoop]: Abstraction has 24493 states and 30294 transitions. [2024-10-15 01:00:40,334 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-15 01:00:40,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24493 states and 30294 transitions. [2024-10-15 01:00:40,407 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8139 [2024-10-15 01:00:40,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-15 01:00:40,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-15 01:00:40,408 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:40,408 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-15 01:00:40,409 INFO L745 eck$LassoCheckResult]: Stem: 217251#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 217252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 217279#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 217270#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 217216#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 217217#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216811#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216812#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 217300#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 216761#L418 assume !(0 == ~M_E~0); 216762#L418-2 assume !(0 == ~T1_E~0); 217215#L423-1 assume !(0 == ~T2_E~0); 217312#L428-1 assume !(0 == ~T3_E~0); 217309#L433-1 assume !(0 == ~E_1~0); 217285#L438-1 assume !(0 == ~E_2~0); 217116#L443-1 assume !(0 == ~E_3~0); 217098#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 217008#L197 assume !(1 == ~m_pc~0); 217009#L197-2 is_master_triggered_~__retres1~0#1 := 0; 217371#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 217197#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 217198#L510 assume !(0 != activate_threads_~tmp~1#1); 216713#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216714#L216 assume !(1 == ~t1_pc~0); 216809#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 216810#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216859#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 216719#L518 assume !(0 != activate_threads_~tmp___0~0#1); 216720#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 217140#L235 assume !(1 == ~t2_pc~0); 217299#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 216978#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216979#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 217354#L526 assume !(0 != activate_threads_~tmp___1~0#1); 217355#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216948#L254 assume !(1 == ~t3_pc~0); 216818#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216819#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216737#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216738#L534 assume !(0 != activate_threads_~tmp___2~0#1); 216964#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216699#L461 assume !(1 == ~M_E~0); 216700#L461-2 assume !(1 == ~T1_E~0); 216813#L466-1 assume !(1 == ~T2_E~0); 217323#L471-1 assume !(1 == ~T3_E~0); 216864#L476-1 assume !(1 == ~E_1~0); 216865#L481-1 assume !(1 == ~E_2~0); 217175#L486-1 assume !(1 == ~E_3~0); 216902#L491-1 assume { :end_inline_reset_delta_events } true; 216903#L652-2 assume !false; 218686#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 218684#L393-1 [2024-10-15 01:00:40,410 INFO L747 eck$LassoCheckResult]: Loop: 218684#L393-1 assume !false; 218682#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 218680#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 218678#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 218676#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 218674#L346 assume 0 != eval_~tmp~0#1; 218672#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 218669#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 218667#L354-2 havoc eval_~tmp_ndt_1~0#1; 218665#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 218662#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 218663#L368-2 havoc eval_~tmp_ndt_2~0#1; 218701#L365-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 218698#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 218696#L382-2 havoc eval_~tmp_ndt_3~0#1; 218694#L379-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 218690#L396 assume !(0 != eval_~tmp_ndt_4~0#1); 218688#L396-2 havoc eval_~tmp_ndt_4~0#1; 218684#L393-1 [2024-10-15 01:00:40,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:40,410 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 4 times [2024-10-15 01:00:40,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:40,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088956491] [2024-10-15 01:00:40,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:40,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:40,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:40,419 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:40,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:40,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:40,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:40,432 INFO L85 PathProgramCache]: Analyzing trace with hash -198166090, now seen corresponding path program 1 times [2024-10-15 01:00:40,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:40,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643997379] [2024-10-15 01:00:40,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:40,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:40,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:40,438 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:40,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:40,442 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:40,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-15 01:00:40,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1938803241, now seen corresponding path program 1 times [2024-10-15 01:00:40,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-15 01:00:40,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790595858] [2024-10-15 01:00:40,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-15 01:00:40,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-15 01:00:40,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:40,452 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:40,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:40,469 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-15 01:00:41,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:41,332 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-15 01:00:41,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-15 01:00:41,470 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 15.10 01:00:41 BoogieIcfgContainer [2024-10-15 01:00:41,470 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-10-15 01:00:41,471 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-10-15 01:00:41,471 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-10-15 01:00:41,471 INFO L274 PluginConnector]: Witness Printer initialized [2024-10-15 01:00:41,472 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 01:00:25" (3/4) ... [2024-10-15 01:00:41,473 INFO L136 WitnessPrinter]: Generating witness for non-termination counterexample [2024-10-15 01:00:41,554 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-10-15 01:00:41,554 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-10-15 01:00:41,555 INFO L158 Benchmark]: Toolchain (without parser) took 17594.48ms. Allocated memory was 174.1MB in the beginning and 1.7GB in the end (delta: 1.6GB). Free memory was 120.0MB in the beginning and 1.4GB in the end (delta: -1.3GB). Peak memory consumption was 250.2MB. Max. memory is 16.1GB. [2024-10-15 01:00:41,555 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 174.1MB. Free memory is still 139.1MB. There was no memory consumed. Max. memory is 16.1GB. [2024-10-15 01:00:41,555 INFO L158 Benchmark]: CACSL2BoogieTranslator took 332.82ms. Allocated memory is still 174.1MB. Free memory was 119.6MB in the beginning and 104.5MB in the end (delta: 15.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-10-15 01:00:41,556 INFO L158 Benchmark]: Boogie Procedure Inliner took 85.33ms. Allocated memory is still 174.1MB. Free memory was 104.5MB in the beginning and 100.8MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-10-15 01:00:41,556 INFO L158 Benchmark]: Boogie Preprocessor took 128.22ms. Allocated memory is still 174.1MB. Free memory was 100.8MB in the beginning and 96.6MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-10-15 01:00:41,556 INFO L158 Benchmark]: RCFGBuilder took 1020.55ms. Allocated memory is still 174.1MB. Free memory was 96.6MB in the beginning and 54.7MB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2024-10-15 01:00:41,556 INFO L158 Benchmark]: BuchiAutomizer took 15936.86ms. Allocated memory was 174.1MB in the beginning and 1.7GB in the end (delta: 1.6GB). Free memory was 54.7MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 176.8MB. Max. memory is 16.1GB. [2024-10-15 01:00:41,557 INFO L158 Benchmark]: Witness Printer took 83.80ms. Allocated memory is still 1.7GB. Free memory was 1.5GB in the beginning and 1.4GB in the end (delta: 7.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-10-15 01:00:41,558 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 174.1MB. Free memory is still 139.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 332.82ms. Allocated memory is still 174.1MB. Free memory was 119.6MB in the beginning and 104.5MB in the end (delta: 15.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 85.33ms. Allocated memory is still 174.1MB. Free memory was 104.5MB in the beginning and 100.8MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 128.22ms. Allocated memory is still 174.1MB. Free memory was 100.8MB in the beginning and 96.6MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1020.55ms. Allocated memory is still 174.1MB. Free memory was 96.6MB in the beginning and 54.7MB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 15936.86ms. Allocated memory was 174.1MB in the beginning and 1.7GB in the end (delta: 1.6GB). Free memory was 54.7MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 176.8MB. Max. memory is 16.1GB. * Witness Printer took 83.80ms. Allocated memory is still 1.7GB. Free memory was 1.5GB in the beginning and 1.4GB in the end (delta: 7.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 25 terminating modules (23 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * E_3) + 1) and consists of 3 locations. One deterministic module has affine ranking function (((long long) -1 * T1_E) + 1) and consists of 3 locations. 23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 24493 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 15.7s and 24 iterations. TraceHistogramMax:2. Analysis of lassos took 8.9s. Construction of modules took 0.7s. Büchi inclusion checks took 4.9s. Highest rank in rank-based complementation 3. Minimization of det autom 17. Minimization of nondet autom 8. Automata minimization 2.2s AutomataMinimizationTime, 25 MinimizatonAttempts, 2965 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 1.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 6/6 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 7108 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 7106 mSDsluCounter, 22449 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 11471 mSDsCounter, 226 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 763 IncrementalHoareTripleChecker+Invalid, 989 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 226 mSolverCounterUnsat, 10978 mSDtfsCounter, 763 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc3 concLT2 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital86 mio100 ax100 hnf100 lsp11 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp60 tf111 neg100 sie108 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 18ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 25 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.6s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 341]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 341]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-10-15 01:00:41,598 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)