./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4a390ef5 Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4a390ef-m [2024-10-24 23:53:20,385 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-24 23:53:20,474 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf [2024-10-24 23:53:20,480 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-24 23:53:20,480 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-24 23:53:20,509 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-24 23:53:20,510 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-24 23:53:20,510 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-24 23:53:20,511 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-24 23:53:20,511 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-24 23:53:20,512 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-24 23:53:20,512 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-24 23:53:20,512 INFO L153 SettingsManager]: * Use SBE=true [2024-10-24 23:53:20,513 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-24 23:53:20,513 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-24 23:53:20,513 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-24 23:53:20,514 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-24 23:53:20,514 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-24 23:53:20,514 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-24 23:53:20,515 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-24 23:53:20,515 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-24 23:53:20,516 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-24 23:53:20,516 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-24 23:53:20,516 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-24 23:53:20,516 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-24 23:53:20,517 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-24 23:53:20,517 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-24 23:53:20,517 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-24 23:53:20,518 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-24 23:53:20,518 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-24 23:53:20,518 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-24 23:53:20,519 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-24 23:53:20,519 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-24 23:53:20,519 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-24 23:53:20,519 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-24 23:53:20,520 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-24 23:53:20,520 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe [2024-10-24 23:53:20,756 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-24 23:53:20,778 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-24 23:53:20,781 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-24 23:53:20,782 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-24 23:53:20,782 INFO L274 PluginConnector]: CDTParser initialized [2024-10-24 23:53:20,783 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2024-10-24 23:53:22,192 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-24 23:53:22,425 INFO L384 CDTParser]: Found 1 translation units. [2024-10-24 23:53:22,425 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2024-10-24 23:53:22,438 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ff29c614/920d0609456b47cbb71a7af8d8f46511/FLAGc366a6fc6 [2024-10-24 23:53:22,766 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ff29c614/920d0609456b47cbb71a7af8d8f46511 [2024-10-24 23:53:22,768 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-24 23:53:22,769 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-24 23:53:22,773 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-24 23:53:22,773 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-24 23:53:22,779 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-24 23:53:22,780 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.10 11:53:22" (1/1) ... [2024-10-24 23:53:22,781 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5f4d3cfc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:22, skipping insertion in model container [2024-10-24 23:53:22,781 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.10 11:53:22" (1/1) ... [2024-10-24 23:53:22,825 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-24 23:53:23,217 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-24 23:53:23,228 INFO L200 MainTranslator]: Completed pre-run [2024-10-24 23:53:23,274 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-24 23:53:23,304 INFO L204 MainTranslator]: Completed translation [2024-10-24 23:53:23,304 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23 WrapperNode [2024-10-24 23:53:23,304 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-24 23:53:23,305 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-24 23:53:23,305 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-24 23:53:23,306 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-24 23:53:23,312 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,325 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,339 INFO L138 Inliner]: procedures = 109, calls = 13, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 33 [2024-10-24 23:53:23,340 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-24 23:53:23,340 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-24 23:53:23,340 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-24 23:53:23,341 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-24 23:53:23,350 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,350 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,352 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,363 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [3, 4]. 57 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0]. The 3 writes are split as follows [1, 2]. [2024-10-24 23:53:23,363 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,363 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,367 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,369 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,370 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,371 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,373 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-24 23:53:23,374 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-24 23:53:23,374 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-24 23:53:23,374 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-24 23:53:23,375 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (1/1) ... [2024-10-24 23:53:23,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-24 23:53:23,392 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-24 23:53:23,408 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-24 23:53:23,415 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-24 23:53:23,458 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-10-24 23:53:23,459 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-10-24 23:53:23,460 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-10-24 23:53:23,460 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-10-24 23:53:23,461 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-10-24 23:53:23,461 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-10-24 23:53:23,461 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-24 23:53:23,461 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-24 23:53:23,577 INFO L238 CfgBuilder]: Building ICFG [2024-10-24 23:53:23,579 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-24 23:53:23,668 INFO L? ?]: Removed 4 outVars from TransFormulas that were not future-live. [2024-10-24 23:53:23,668 INFO L287 CfgBuilder]: Performing block encoding [2024-10-24 23:53:23,681 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-24 23:53:23,682 INFO L314 CfgBuilder]: Removed 2 assume(true) statements. [2024-10-24 23:53:23,682 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.10 11:53:23 BoogieIcfgContainer [2024-10-24 23:53:23,682 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-24 23:53:23,683 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-24 23:53:23,683 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-24 23:53:23,687 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-24 23:53:23,688 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-24 23:53:23,688 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 24.10 11:53:22" (1/3) ... [2024-10-24 23:53:23,689 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45e02973 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 24.10 11:53:23, skipping insertion in model container [2024-10-24 23:53:23,689 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-24 23:53:23,689 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.10 11:53:23" (2/3) ... [2024-10-24 23:53:23,689 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45e02973 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 24.10 11:53:23, skipping insertion in model container [2024-10-24 23:53:23,689 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-24 23:53:23,689 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.10 11:53:23" (3/3) ... [2024-10-24 23:53:23,691 INFO L332 chiAutomizerObserver]: Analyzing ICFG Urban-2013WST-Fig2-modified1000-alloca.i [2024-10-24 23:53:23,732 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-24 23:53:23,732 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-24 23:53:23,732 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-24 23:53:23,732 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-24 23:53:23,732 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-24 23:53:23,732 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-24 23:53:23,732 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-24 23:53:23,733 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-24 23:53:23,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:23,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2024-10-24 23:53:23,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:53:23,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:53:23,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:53:23,760 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2024-10-24 23:53:23,761 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-24 23:53:23,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:23,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2024-10-24 23:53:23,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:53:23,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:53:23,764 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:53:23,764 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2024-10-24 23:53:23,771 INFO L745 eck$LassoCheckResult]: Stem: 6#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 5#L549-3true [2024-10-24 23:53:23,771 INFO L747 eck$LassoCheckResult]: Loop: 5#L549-3true call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 2#L549-1true assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 7#L551-3true assume !true; 11#L551-4true call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 5#L549-3true [2024-10-24 23:53:23,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:23,777 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-10-24 23:53:23,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:23,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049277260] [2024-10-24 23:53:23,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:23,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:23,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:23,910 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-24 23:53:23,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:23,943 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-24 23:53:23,945 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:23,945 INFO L85 PathProgramCache]: Analyzing trace with hash 1144360, now seen corresponding path program 1 times [2024-10-24 23:53:23,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:23,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898077325] [2024-10-24 23:53:23,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:23,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:23,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:53:23,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:23,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-24 23:53:23,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898077325] [2024-10-24 23:53:23,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898077325] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-24 23:53:23,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-24 23:53:23,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-24 23:53:23,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526410397] [2024-10-24 23:53:23,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-24 23:53:23,999 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-24 23:53:23,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-24 23:53:24,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-10-24 23:53:24,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-10-24 23:53:24,025 INFO L87 Difference]: Start difference. First operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:24,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-24 23:53:24,029 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions. [2024-10-24 23:53:24,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions. [2024-10-24 23:53:24,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2024-10-24 23:53:24,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 7 states and 8 transitions. [2024-10-24 23:53:24,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2024-10-24 23:53:24,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2024-10-24 23:53:24,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 8 transitions. [2024-10-24 23:53:24,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-24 23:53:24,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2024-10-24 23:53:24,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 8 transitions. [2024-10-24 23:53:24,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2024-10-24 23:53:24,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:24,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions. [2024-10-24 23:53:24,054 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2024-10-24 23:53:24,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-10-24 23:53:24,058 INFO L425 stractBuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2024-10-24 23:53:24,058 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-24 23:53:24,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions. [2024-10-24 23:53:24,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2024-10-24 23:53:24,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:53:24,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:53:24,059 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:53:24,059 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2024-10-24 23:53:24,060 INFO L745 eck$LassoCheckResult]: Stem: 33#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 34#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 32#L549-3 [2024-10-24 23:53:24,060 INFO L747 eck$LassoCheckResult]: Loop: 32#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 30#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 31#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 35#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 36#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 32#L549-3 [2024-10-24 23:53:24,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:24,060 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2024-10-24 23:53:24,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:24,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62331148] [2024-10-24 23:53:24,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:24,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:24,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:24,080 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-24 23:53:24,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:24,090 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-24 23:53:24,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:24,091 INFO L85 PathProgramCache]: Analyzing trace with hash 35468273, now seen corresponding path program 1 times [2024-10-24 23:53:24,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:24,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190427194] [2024-10-24 23:53:24,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:24,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:24,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:53:24,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:24,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-24 23:53:24,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190427194] [2024-10-24 23:53:24,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190427194] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-24 23:53:24,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-24 23:53:24,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-24 23:53:24,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192493106] [2024-10-24 23:53:24,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-24 23:53:24,272 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-24 23:53:24,273 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-24 23:53:24,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-24 23:53:24,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-24 23:53:24,275 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:24,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-24 23:53:24,317 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2024-10-24 23:53:24,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2024-10-24 23:53:24,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2024-10-24 23:53:24,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 9 states and 10 transitions. [2024-10-24 23:53:24,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-10-24 23:53:24,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-10-24 23:53:24,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2024-10-24 23:53:24,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-24 23:53:24,322 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2024-10-24 23:53:24,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2024-10-24 23:53:24,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2024-10-24 23:53:24,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:24,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2024-10-24 23:53:24,324 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2024-10-24 23:53:24,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-24 23:53:24,325 INFO L425 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2024-10-24 23:53:24,326 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-24 23:53:24,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2024-10-24 23:53:24,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2024-10-24 23:53:24,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:53:24,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:53:24,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:53:24,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1] [2024-10-24 23:53:24,329 INFO L745 eck$LassoCheckResult]: Stem: 60#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 61#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 57#L549-3 [2024-10-24 23:53:24,329 INFO L747 eck$LassoCheckResult]: Loop: 57#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 55#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 56#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 58#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 59#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 63#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 62#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 57#L549-3 [2024-10-24 23:53:24,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:24,330 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times [2024-10-24 23:53:24,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:24,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610127298] [2024-10-24 23:53:24,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:24,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:24,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:24,355 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-24 23:53:24,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:24,369 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-24 23:53:24,370 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:24,370 INFO L85 PathProgramCache]: Analyzing trace with hash -274676436, now seen corresponding path program 1 times [2024-10-24 23:53:24,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:24,371 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618452908] [2024-10-24 23:53:24,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:24,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:24,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:53:24,618 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:24,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-24 23:53:24,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618452908] [2024-10-24 23:53:24,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618452908] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-24 23:53:24,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [166718534] [2024-10-24 23:53:24,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:24,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-24 23:53:24,621 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-24 23:53:24,623 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-24 23:53:24,625 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-10-24 23:53:24,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:53:24,711 INFO L255 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-10-24 23:53:24,717 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-24 23:53:24,776 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-10-24 23:53:24,813 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-10-24 23:53:24,824 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-10-24 23:53:24,831 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:24,833 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-24 23:53:24,893 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:24,893 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [166718534] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-24 23:53:24,893 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-24 23:53:24,893 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 9 [2024-10-24 23:53:24,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [768397865] [2024-10-24 23:53:24,894 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-24 23:53:24,894 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-24 23:53:24,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-24 23:53:24,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-10-24 23:53:24,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2024-10-24 23:53:24,896 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 9 states, 9 states have (on average 1.5555555555555556) internal successors, (14), 9 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:24,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-24 23:53:24,965 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2024-10-24 23:53:24,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2024-10-24 23:53:24,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2024-10-24 23:53:24,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2024-10-24 23:53:24,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2024-10-24 23:53:24,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2024-10-24 23:53:24,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2024-10-24 23:53:24,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-24 23:53:24,969 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2024-10-24 23:53:24,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2024-10-24 23:53:24,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2024-10-24 23:53:24,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:24,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2024-10-24 23:53:24,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2024-10-24 23:53:24,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-10-24 23:53:24,973 INFO L425 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2024-10-24 23:53:24,973 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-24 23:53:24,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2024-10-24 23:53:24,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2024-10-24 23:53:24,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:53:24,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:53:24,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:53:24,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [5, 4, 1, 1, 1, 1] [2024-10-24 23:53:24,977 INFO L745 eck$LassoCheckResult]: Stem: 139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 135#L549-3 [2024-10-24 23:53:24,977 INFO L747 eck$LassoCheckResult]: Loop: 135#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 133#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 134#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 136#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 137#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 138#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 147#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 146#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 145#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 144#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 143#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 142#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 141#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 135#L549-3 [2024-10-24 23:53:24,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:24,977 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times [2024-10-24 23:53:24,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:24,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877692291] [2024-10-24 23:53:24,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:24,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:24,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:24,992 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-24 23:53:24,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:25,001 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-24 23:53:25,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:25,004 INFO L85 PathProgramCache]: Analyzing trace with hash 351922269, now seen corresponding path program 2 times [2024-10-24 23:53:25,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:25,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335897656] [2024-10-24 23:53:25,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:25,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:25,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:53:25,454 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:25,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-24 23:53:25,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335897656] [2024-10-24 23:53:25,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335897656] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-24 23:53:25,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [171210033] [2024-10-24 23:53:25,455 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-10-24 23:53:25,455 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-24 23:53:25,455 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-24 23:53:25,479 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-24 23:53:25,480 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-10-24 23:53:25,547 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-10-24 23:53:25,547 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-24 23:53:25,548 INFO L255 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-10-24 23:53:25,552 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-24 23:53:25,560 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-10-24 23:53:25,580 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-10-24 23:53:25,596 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:25,610 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:25,630 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:25,641 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-10-24 23:53:25,645 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:25,646 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-24 23:53:25,764 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:25,765 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [171210033] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-24 23:53:25,765 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-24 23:53:25,765 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 18 [2024-10-24 23:53:25,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802352414] [2024-10-24 23:53:25,765 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-24 23:53:25,766 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-24 23:53:25,766 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-24 23:53:25,766 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-10-24 23:53:25,767 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=179, Unknown=0, NotChecked=0, Total=306 [2024-10-24 23:53:25,767 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 2 Second operand has 18 states, 18 states have (on average 1.7777777777777777) internal successors, (32), 18 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:25,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-24 23:53:25,910 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2024-10-24 23:53:25,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2024-10-24 23:53:25,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2024-10-24 23:53:25,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2024-10-24 23:53:25,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-10-24 23:53:25,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2024-10-24 23:53:25,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2024-10-24 23:53:25,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-24 23:53:25,913 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2024-10-24 23:53:25,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2024-10-24 23:53:25,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2024-10-24 23:53:25,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:25,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2024-10-24 23:53:25,916 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2024-10-24 23:53:25,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2024-10-24 23:53:25,917 INFO L425 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2024-10-24 23:53:25,917 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-24 23:53:25,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2024-10-24 23:53:25,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2024-10-24 23:53:25,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:53:25,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:53:25,919 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:53:25,919 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [11, 10, 1, 1, 1, 1] [2024-10-24 23:53:25,919 INFO L745 eck$LassoCheckResult]: Stem: 286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 282#L549-3 [2024-10-24 23:53:25,919 INFO L747 eck$LassoCheckResult]: Loop: 282#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 280#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 281#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 283#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 284#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 285#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 306#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 305#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 304#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 303#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 302#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 301#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 300#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 299#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 298#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 297#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 296#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 295#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 294#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 293#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 292#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 291#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 290#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 289#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 288#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 282#L549-3 [2024-10-24 23:53:25,919 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:25,920 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times [2024-10-24 23:53:25,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:25,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936013900] [2024-10-24 23:53:25,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:25,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:25,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:25,929 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-24 23:53:25,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:25,935 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-24 23:53:25,936 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:25,936 INFO L85 PathProgramCache]: Analyzing trace with hash 646907007, now seen corresponding path program 3 times [2024-10-24 23:53:25,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:25,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292172121] [2024-10-24 23:53:25,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:25,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:25,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:53:27,068 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:27,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-24 23:53:27,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [292172121] [2024-10-24 23:53:27,069 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [292172121] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-24 23:53:27,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [388509252] [2024-10-24 23:53:27,070 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-24 23:53:27,070 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-24 23:53:27,070 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-24 23:53:27,103 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-24 23:53:27,104 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-10-24 23:53:27,224 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-10-24 23:53:27,224 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-24 23:53:27,226 INFO L255 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 34 conjuncts are in the unsatisfiable core [2024-10-24 23:53:27,230 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-24 23:53:27,239 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-10-24 23:53:27,250 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-10-24 23:53:27,258 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,277 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,291 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,302 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,316 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,330 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,345 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,367 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,383 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:27,391 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-10-24 23:53:27,395 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:27,395 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-24 23:53:27,701 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:27,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [388509252] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-24 23:53:27,703 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-24 23:53:27,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 14, 14] total 36 [2024-10-24 23:53:27,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [629090405] [2024-10-24 23:53:27,703 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-24 23:53:27,704 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-24 23:53:27,704 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-24 23:53:27,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2024-10-24 23:53:27,708 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=541, Invalid=719, Unknown=0, NotChecked=0, Total=1260 [2024-10-24 23:53:27,709 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 2 Second operand has 36 states, 36 states have (on average 1.8888888888888888) internal successors, (68), 36 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:28,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-24 23:53:28,062 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2024-10-24 23:53:28,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2024-10-24 23:53:28,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2024-10-24 23:53:28,063 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2024-10-24 23:53:28,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2024-10-24 23:53:28,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2024-10-24 23:53:28,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2024-10-24 23:53:28,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-24 23:53:28,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2024-10-24 23:53:28,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2024-10-24 23:53:28,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2024-10-24 23:53:28,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:28,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2024-10-24 23:53:28,071 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2024-10-24 23:53:28,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2024-10-24 23:53:28,072 INFO L425 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2024-10-24 23:53:28,074 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-24 23:53:28,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2024-10-24 23:53:28,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2024-10-24 23:53:28,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:53:28,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:53:28,076 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:53:28,076 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [23, 22, 1, 1, 1, 1] [2024-10-24 23:53:28,076 INFO L745 eck$LassoCheckResult]: Stem: 571#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 567#L549-3 [2024-10-24 23:53:28,077 INFO L747 eck$LassoCheckResult]: Loop: 567#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 565#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 566#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 570#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 568#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 569#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 615#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 614#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 613#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 612#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 611#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 610#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 609#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 608#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 607#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 606#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 605#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 604#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 603#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 602#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 601#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 600#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 599#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 598#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 597#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 596#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 595#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 594#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 593#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 592#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 591#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 590#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 589#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 588#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 587#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 586#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 585#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 584#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 583#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 582#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 581#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 580#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 579#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 578#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 577#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 576#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 575#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 574#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 573#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 567#L549-3 [2024-10-24 23:53:28,077 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:28,077 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times [2024-10-24 23:53:28,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:28,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254669244] [2024-10-24 23:53:28,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:28,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:28,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:28,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-24 23:53:28,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:28,086 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-24 23:53:28,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:28,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1009537987, now seen corresponding path program 4 times [2024-10-24 23:53:28,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:28,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915122904] [2024-10-24 23:53:28,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:28,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:28,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:53:31,074 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:31,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-24 23:53:31,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915122904] [2024-10-24 23:53:31,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [915122904] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-24 23:53:31,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [48183638] [2024-10-24 23:53:31,075 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-10-24 23:53:31,075 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-24 23:53:31,076 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-24 23:53:31,081 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-24 23:53:31,082 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-10-24 23:53:31,489 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-10-24 23:53:31,489 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-24 23:53:31,496 INFO L255 TraceCheckSpWp]: Trace formula consists of 362 conjuncts, 70 conjuncts are in the unsatisfiable core [2024-10-24 23:53:31,504 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-24 23:53:31,511 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-10-24 23:53:31,528 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-10-24 23:53:31,537 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,546 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,558 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,570 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,584 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,595 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,605 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,616 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,632 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,641 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,649 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,657 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,671 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,684 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,693 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,702 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,711 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,734 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,742 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,750 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,758 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:53:31,763 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-10-24 23:53:31,766 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:31,766 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-24 23:53:32,722 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:32,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [48183638] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-24 23:53:32,723 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-24 23:53:32,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 26, 26] total 72 [2024-10-24 23:53:32,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570049024] [2024-10-24 23:53:32,723 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-24 23:53:32,724 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-24 23:53:32,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-24 23:53:32,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2024-10-24 23:53:32,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2233, Invalid=2879, Unknown=0, NotChecked=0, Total=5112 [2024-10-24 23:53:32,729 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 2 Second operand has 72 states, 72 states have (on average 1.9444444444444444) internal successors, (140), 72 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:33,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-24 23:53:33,712 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2024-10-24 23:53:33,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2024-10-24 23:53:33,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2024-10-24 23:53:33,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2024-10-24 23:53:33,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2024-10-24 23:53:33,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2024-10-24 23:53:33,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2024-10-24 23:53:33,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-24 23:53:33,722 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2024-10-24 23:53:33,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2024-10-24 23:53:33,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2024-10-24 23:53:33,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:53:33,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2024-10-24 23:53:33,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2024-10-24 23:53:33,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-10-24 23:53:33,730 INFO L425 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2024-10-24 23:53:33,730 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-24 23:53:33,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2024-10-24 23:53:33,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2024-10-24 23:53:33,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:53:33,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:53:33,733 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:53:33,733 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [47, 46, 1, 1, 1, 1] [2024-10-24 23:53:33,733 INFO L745 eck$LassoCheckResult]: Stem: 1132#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 1128#L549-3 [2024-10-24 23:53:33,734 INFO L747 eck$LassoCheckResult]: Loop: 1128#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 1126#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1127#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1129#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1130#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1131#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1224#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1223#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1222#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1221#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1220#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1219#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1218#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1217#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1216#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1215#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1214#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1213#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1212#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1211#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1210#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1209#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1208#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1207#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1206#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1205#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1204#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1203#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1202#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1201#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1200#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1199#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1198#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1197#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1196#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1195#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1194#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1193#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1192#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1191#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1190#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1189#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1188#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1187#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1186#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1185#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1184#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1183#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1182#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1181#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1180#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1179#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1178#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1177#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1176#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1175#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1174#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1173#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1172#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1171#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1170#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1169#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1168#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1167#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1166#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1165#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1164#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1163#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1162#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1161#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1160#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1159#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1158#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1157#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1156#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1155#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1154#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1153#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1152#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1151#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1150#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1149#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1148#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1147#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1146#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1145#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1144#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1143#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1142#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1141#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1140#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1139#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1138#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1137#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1136#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1135#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 1134#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 1128#L549-3 [2024-10-24 23:53:33,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:33,735 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 7 times [2024-10-24 23:53:33,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:33,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147164428] [2024-10-24 23:53:33,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:33,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:33,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:33,744 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-24 23:53:33,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:53:33,747 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-24 23:53:33,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:53:33,750 INFO L85 PathProgramCache]: Analyzing trace with hash 1846627915, now seen corresponding path program 5 times [2024-10-24 23:53:33,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:53:33,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847616714] [2024-10-24 23:53:33,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:53:33,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:53:33,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:53:40,982 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:53:40,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-24 23:53:40,983 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847616714] [2024-10-24 23:53:40,983 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847616714] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-24 23:53:40,983 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [685337226] [2024-10-24 23:53:40,983 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-24 23:53:40,983 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-24 23:53:40,984 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-24 23:53:40,985 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-24 23:53:40,986 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-10-24 23:54:00,022 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-10-24 23:54:00,022 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-24 23:54:00,039 INFO L255 TraceCheckSpWp]: Trace formula consists of 722 conjuncts, 142 conjuncts are in the unsatisfiable core [2024-10-24 23:54:00,057 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-24 23:54:00,060 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-10-24 23:54:00,070 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-10-24 23:54:00,075 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,081 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,086 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,101 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,109 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,122 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,131 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,138 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,146 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,156 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,163 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,172 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,178 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,184 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,191 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,198 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,204 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,212 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,219 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,227 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,236 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,248 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,256 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,264 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,272 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,280 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,287 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,292 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,301 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,308 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,315 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,322 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,334 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,345 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,355 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,361 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,378 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,385 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,392 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,399 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,406 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,413 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,420 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,426 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-10-24 23:54:00,430 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-10-24 23:54:00,433 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:54:00,434 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-24 23:54:03,221 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:54:03,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [685337226] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-24 23:54:03,221 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-24 23:54:03,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 50, 50] total 144 [2024-10-24 23:54:03,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819877177] [2024-10-24 23:54:03,222 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-24 23:54:03,223 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-24 23:54:03,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-24 23:54:03,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 144 interpolants. [2024-10-24 23:54:03,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9073, Invalid=11519, Unknown=0, NotChecked=0, Total=20592 [2024-10-24 23:54:03,233 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 2 Second operand has 144 states, 144 states have (on average 1.9722222222222223) internal successors, (284), 144 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:54:05,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-24 23:54:05,943 INFO L93 Difference]: Finished difference Result 195 states and 196 transitions. [2024-10-24 23:54:05,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 196 transitions. [2024-10-24 23:54:05,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2024-10-24 23:54:05,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 196 transitions. [2024-10-24 23:54:05,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2024-10-24 23:54:05,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2024-10-24 23:54:05,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 196 transitions. [2024-10-24 23:54:05,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-24 23:54:05,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2024-10-24 23:54:05,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 196 transitions. [2024-10-24 23:54:05,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2024-10-24 23:54:05,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-24 23:54:05,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions. [2024-10-24 23:54:05,962 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2024-10-24 23:54:05,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2024-10-24 23:54:05,963 INFO L425 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions. [2024-10-24 23:54:05,963 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-24 23:54:05,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions. [2024-10-24 23:54:05,964 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2024-10-24 23:54:05,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-24 23:54:05,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-24 23:54:05,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-24 23:54:05,967 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [95, 94, 1, 1, 1, 1] [2024-10-24 23:54:05,967 INFO L745 eck$LassoCheckResult]: Stem: 2245#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 2241#L549-3 [2024-10-24 23:54:05,967 INFO L747 eck$LassoCheckResult]: Loop: 2241#L549-3 call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 2239#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2240#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2244#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2242#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2243#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2433#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2432#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2431#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2430#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2429#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2428#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2427#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2426#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2425#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2424#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2423#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2422#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2421#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2420#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2419#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2418#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2417#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2416#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2415#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2414#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2413#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2412#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2411#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2410#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2409#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2408#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2407#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2406#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2405#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2404#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2403#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2402#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2401#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2400#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2399#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2398#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2397#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2396#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2395#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2394#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2393#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2392#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2391#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2390#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2389#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2388#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2387#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2386#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2385#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2384#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2383#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2382#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2381#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2380#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2379#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2378#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2377#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2376#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2375#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2374#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2373#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2372#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2371#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2370#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2369#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2368#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2367#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2366#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2365#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2364#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2363#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2362#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2361#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2360#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2359#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2358#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2357#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2356#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2355#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2354#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2353#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2352#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2351#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2350#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2349#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2348#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2347#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2346#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2345#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2344#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2343#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2342#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2341#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2340#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2339#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2338#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2337#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2336#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2335#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2334#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2333#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2332#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2331#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2330#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2329#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2328#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2327#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2326#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2325#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2324#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2323#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2322#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2321#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2320#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2319#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2318#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2317#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2316#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2315#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2314#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2313#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2312#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2311#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2310#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2309#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2308#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2307#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2306#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2305#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2304#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2303#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2302#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2301#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2300#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2299#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2298#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2297#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2296#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2295#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2294#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2293#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2292#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2291#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2290#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2289#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2288#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2287#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2286#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2285#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2284#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2283#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2282#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2281#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2280#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2279#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2278#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2277#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2276#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2275#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2274#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2273#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2272#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2271#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2270#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2269#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2268#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2267#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2266#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2265#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2264#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2263#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2262#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2261#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2260#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2259#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2258#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2257#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2256#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2255#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2254#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2253#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2252#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2251#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2250#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2249#L551-3 call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2248#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 2247#L551-4 call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 2241#L549-3 [2024-10-24 23:54:05,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:54:05,968 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 8 times [2024-10-24 23:54:05,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:54:05,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367407167] [2024-10-24 23:54:05,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:54:05,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:54:05,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:54:05,974 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-24 23:54:05,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-24 23:54:05,978 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-24 23:54:05,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-24 23:54:05,980 INFO L85 PathProgramCache]: Analyzing trace with hash -1384860837, now seen corresponding path program 6 times [2024-10-24 23:54:05,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-24 23:54:05,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1041476378] [2024-10-24 23:54:05,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-24 23:54:05,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-24 23:54:06,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-24 23:54:31,083 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-24 23:54:31,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-24 23:54:31,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1041476378] [2024-10-24 23:54:31,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1041476378] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-24 23:54:31,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1820403135] [2024-10-24 23:54:31,083 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-10-24 23:54:31,083 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-24 23:54:31,084 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-24 23:54:31,086 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-24 23:54:31,086 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process